Microchip Technology Inc. ATSAMA5D41 2024.06.03 Atmel ATSAMA5D41 Microcontroller false 8 32 ADC Analog-to-Digital Converter ADC 0x0 0x0 0x50 registers n ADC 44 ACR Analog Control Register 0x94 32 read-write n 0x0 0x0 PENDETSENS Pen Detection Sensitivity 0 2 read-write CDR0 Channel Data Register 0x50 32 read-only n DATA Converted Data 0 12 read-only CDR1 Channel Data Register 0x54 32 read-only n DATA Converted Data 0 12 read-only CDR2 Channel Data Register 0x58 32 read-only n DATA Converted Data 0 12 read-only CDR3 Channel Data Register 0x5C 32 read-only n DATA Converted Data 0 12 read-only CDR4 Channel Data Register 0x60 32 read-only n DATA Converted Data 0 12 read-only CDR[0] Channel Data Register 0xA0 32 read-only n 0x0 0x0 DATA Converted Data 0 12 read-only CDR[1] Channel Data Register 0xF4 32 read-only n 0x0 0x0 DATA Converted Data 0 12 read-only CDR[2] Channel Data Register 0x14C 32 read-only n 0x0 0x0 DATA Converted Data 0 12 read-only CDR[3] Channel Data Register 0x1A8 32 read-only n 0x0 0x0 DATA Converted Data 0 12 read-only CDR[4] Channel Data Register 0x208 32 read-only n 0x0 0x0 DATA Converted Data 0 12 read-only CHDR Channel Disable Register 0x14 32 write-only n 0x0 0x0 CH0 Channel 0 Disable 0 1 write-only CH1 Channel 1 Disable 1 1 write-only CH2 Channel 2 Disable 2 1 write-only CH3 Channel 3 Disable 3 1 write-only CH4 Channel 4 Disable 4 1 write-only CHER Channel Enable Register 0x10 32 write-only n 0x0 0x0 CH0 Channel 0 Enable 0 1 write-only CH1 Channel 1 Enable 1 1 write-only CH2 Channel 2 Enable 2 1 write-only CH3 Channel 3 Enable 3 1 write-only CH4 Channel 4 Enable 4 1 write-only CHSR Channel Status Register 0x18 32 read-only n 0x0 0x0 CH0 Channel 0 Status 0 1 read-only CH1 Channel 1 Status 1 1 read-only CH2 Channel 2 Status 2 1 read-only CH3 Channel 3 Status 3 1 read-only CH4 Channel 4 Status 4 1 read-only CR Control Register 0x0 32 write-only n 0x0 0x0 START Start Conversion 1 1 write-only SWRST Software Reset 0 1 write-only TSCALIB Touchscreen Calibration 2 1 write-only CWR Compare Window Register 0x44 32 read-write n 0x0 0x0 HIGHTHRES High Threshold 16 12 read-write LOWTHRES Low Threshold 0 12 read-write EMR Extended Mode Register 0x40 32 read-write n 0x0 0x0 ASTE Averaging on Single Trigger Event 20 1 read-write MULTI_TRIG_AVERAGE The average requests several trigger events. 0 SINGLE_TRIG_AVERAGE The average requests only one trigger event. 1 CMPALL Compare All Channels 9 1 read-write CMPFILTER Compare Event Filtering 12 2 read-write CMPMODE Comparison Mode 0 2 read-write LOW When the converted data is lower than the low threshold of the window, generates the COMPE flag in ADC_ISR. 0x0 HIGH When the converted data is higher than the high threshold of the window, generates the COMPE flag in ADC_ISR. 0x1 IN When the converted data is in the comparison window, generates the COMPE flag in ADC_ISR. 0x2 OUT When the converted data is out of the comparison window, generates the COMPE flag in ADC_ISR. 0x3 CMPSEL Comparison Selected Channel 4 4 read-write OSR Oversampling Rate 16 2 read-write NO_AVERAGE No averaging. ADC sample rate is maximum. 0x0 OSR4 1-bit enhanced resolution by averaging. ADC sample rate divided by 4. 0x1 OSR16 2-bit enhanced resolution by averaging. ADC sample rate divided by 16. 0x2 TAG Tag of ADC_LCDR 24 1 read-write IDR Interrupt Disable Register 0x28 32 write-only n 0x0 0x0 COMPE Comparison Event Interrupt Disable 26 1 write-only DRDY Data Ready Interrupt Disable 24 1 write-only EOC0 End of Conversion Interrupt Disable 0 0 1 write-only EOC1 End of Conversion Interrupt Disable 1 1 1 write-only EOC2 End of Conversion Interrupt Disable 2 2 1 write-only EOC3 End of Conversion Interrupt Disable 3 3 1 write-only EOC4 End of Conversion Interrupt Disable 4 4 1 write-only GOVRE General Overrun Error Interrupt Disable 25 1 write-only NOPEN No Pen Contact Interrupt Disable 30 1 write-only PEN Pen Contact Interrupt Disable 29 1 write-only PRDY Touchscreen Measure Pressure Ready Interrupt Disable 22 1 write-only XRDY Touchscreen Measure XPOS Ready Interrupt Disable 20 1 write-only YRDY Touchscreen Measure YPOS Ready Interrupt Disable 21 1 write-only IER Interrupt Enable Register 0x24 32 write-only n 0x0 0x0 COMPE Comparison Event Interrupt Enable 26 1 write-only DRDY Data Ready Interrupt Enable 24 1 write-only EOC0 End of Conversion Interrupt Enable 0 0 1 write-only EOC1 End of Conversion Interrupt Enable 1 1 1 write-only EOC2 End of Conversion Interrupt Enable 2 2 1 write-only EOC3 End of Conversion Interrupt Enable 3 3 1 write-only EOC4 End of Conversion Interrupt Enable 4 4 1 write-only GOVRE General Overrun Error Interrupt Enable 25 1 write-only NOPEN No Pen Contact Interrupt Enable 30 1 write-only PEN Pen Contact Interrupt Enable 29 1 write-only PRDY Touchscreen Measure Pressure Ready Interrupt Enable 22 1 write-only XRDY Touchscreen Measure XPOS Ready Interrupt Enable 20 1 write-only YRDY Touchscreen Measure YPOS Ready Interrupt Enable 21 1 write-only IMR Interrupt Mask Register 0x2C 32 read-only n 0x0 0x0 COMPE Comparison Event Interrupt Mask 26 1 read-only DRDY Data Ready Interrupt Mask 24 1 read-only EOC0 End of Conversion Interrupt Mask 0 0 1 read-only EOC1 End of Conversion Interrupt Mask 1 1 1 read-only EOC2 End of Conversion Interrupt Mask 2 2 1 read-only EOC3 End of Conversion Interrupt Mask 3 3 1 read-only EOC4 End of Conversion Interrupt Mask 4 4 1 read-only GOVRE General Overrun Error Interrupt Mask 25 1 read-only NOPEN No Pen Contact Interrupt Mask 30 1 read-only PEN Pen Contact Interrupt Mask 29 1 read-only PRDY Touchscreen Measure Pressure Ready Interrupt Mask 22 1 read-only XRDY Touchscreen Measure XPOS Ready Interrupt Mask 20 1 read-only YRDY Touchscreen Measure YPOS Ready Interrupt Mask 21 1 read-only ISR Interrupt Status Register 0x30 32 read-only n 0x0 0x0 COMPE Comparison Event (cleared on read) 26 1 read-only DRDY Data Ready (automatically set / cleared) 24 1 read-only EOC0 End of Conversion 0 (automatically set / cleared) 0 1 read-only EOC1 End of Conversion 1 (automatically set / cleared) 1 1 read-only EOC2 End of Conversion 2 (automatically set / cleared) 2 1 read-only EOC3 End of Conversion 3 (automatically set / cleared) 3 1 read-only EOC4 End of Conversion 4 (automatically set / cleared) 4 1 read-only GOVRE General Overrun Error (cleared on read) 25 1 read-only NOPEN No Pen Contact (cleared on read) 30 1 read-only PEN Pen contact (cleared on read) 29 1 read-only PENS Pen Detect Status 31 1 read-only PRDY Touchscreen Pressure Measure Ready (cleared on read) 22 1 read-only XRDY Touchscreen XPOS Measure Ready (cleared on read) 20 1 read-only YRDY Touchscreen YPOS Measure Ready (cleared on read) 21 1 read-only LCDR Last Converted Data Register 0x20 32 read-only n 0x0 0x0 CHNB Channel Number 12 4 read-only LDATA Last Data Converted 0 12 read-only MR Mode Register 0x4 32 read-write n 0x0 0x0 LOWRES Resolution 4 1 read-write BITS_10 10-bit resolution. For higher resolution by averaging, refer to Section 8.18 "ADC Extended Mode Register". 0 BITS_8 8-bit resolution 1 PRESCAL Prescaler Rate Selection 8 8 read-write SLEEP Sleep Mode 5 1 read-write NORMAL Normal Mode: The ADC core and reference voltage circuitry are kept ON between conversions. 0 SLEEP Sleep Mode: The ADC core and reference voltage circuitry are OFF between conversions. 1 STARTUP Startup Time 16 4 read-write SUT0 0 periods of ADCCLK 0x0 SUT8 8 periods of ADCCLK 0x1 SUT16 16 periods of ADCCLK 0x2 SUT24 24 periods of ADCCLK 0x3 SUT64 64 periods of ADCCLK 0x4 SUT80 80 periods of ADCCLK 0x5 SUT96 96 periods of ADCCLK 0x6 SUT112 112 periods of ADCCLK 0x7 SUT512 512 periods of ADCCLK 0x8 SUT576 576 periods of ADCCLK 0x9 SUT640 640 periods of ADCCLK 0xA SUT704 704 periods of ADCCLK 0xB SUT768 768 periods of ADCCLK 0xC SUT832 832 periods of ADCCLK 0xD SUT896 896 periods of ADCCLK 0xE SUT960 960 periods of ADCCLK 0xF TRACKTIM Tracking Time 24 4 read-write TRGSEL Trigger Selection 1 3 read-write ADC_TRIG0 ADTRG 0x0 ADC_TRIG1 TIOA0 0x1 ADC_TRIG2 TIOA1 0x2 ADC_TRIG3 TIOA2 0x3 ADC_TRIG4 PWM event line 0 0x4 ADC_TRIG5 PWM_even line 1 0x5 ADC_TRIG7 - 0x7 USEQ Use Sequence Enable 31 1 read-write NUM_ORDER Normal Mode: The controller converts channels in a simple numeric order depending only on the channel index. 0 REG_ORDER User Sequence Mode: The sequence respects what is defined in ADC_SEQR1 register and can be used to convert the same channel several times. 1 OVER Overrun Status Register 0x3C 32 read-only n 0x0 0x0 OVRE0 Overrun Error 0 0 1 read-only OVRE1 Overrun Error 1 1 1 read-only OVRE2 Overrun Error 2 2 1 read-only OVRE3 Overrun Error 3 3 1 read-only OVRE4 Overrun Error 4 4 1 read-only PRESSR Touchscreen Pressure Register 0xBC 32 read-only n 0x0 0x0 Z1 Data of Z1 Measurement 0 12 read-only Z2 Data of Z2 Measurement 16 12 read-only SEQR1 Channel Sequence Register 1 0x8 32 read-write n 0x0 0x0 USCH1 User Sequence Number 1 0 4 read-write USCH2 User Sequence Number 2 4 4 read-write USCH3 User Sequence Number 3 8 4 read-write USCH4 User Sequence Number 4 12 4 read-write TRGR Trigger Register 0xC0 32 read-write n 0x0 0x0 TRGMOD Trigger Mode 0 3 read-write NO_TRIGGER No trigger, only software trigger can start conversions 0x0 EXT_TRIG_RISE External trigger rising edge 0x1 EXT_TRIG_FALL External trigger falling edge 0x2 EXT_TRIG_ANY External trigger any edge 0x3 PEN_TRIG Pen Detect Trigger (shall be selected only if PENDET is set and TSAMOD = Touchscreen only mode) 0x4 PERIOD_TRIG ADC internal periodic trigger (see field TRGPER) 0x5 CONTINUOUS Continuous Mode 0x6 TRGPER Trigger Period 16 16 read-write TSMR Touchscreen Mode Register 0xB0 32 read-write n 0x0 0x0 NOTSDMA No TouchScreen DMA 22 1 read-write PENDBC Pen Detect Debouncing Period 28 4 read-write PENDET Pen Contact Detection Enable 24 1 read-write TSAV Touchscreen Average 4 2 read-write NO_FILTER No Filtering. Only one ADC conversion per measure 0x0 AVG2CONV Averages 2 ADC conversions 0x1 AVG4CONV Averages 4 ADC conversions 0x2 AVG8CONV Averages 8 ADC conversions 0x3 TSFREQ Touchscreen Frequency 8 4 read-write TSMODE Touchscreen Mode 0 2 read-write NONE No Touchscreen 0x0 4_WIRE_NO_PM 4-wire Touchscreen without pressure measurement 0x1 4_WIRE 4-wire Touchscreen with pressure measurement 0x2 5_WIRE 5-wire Touchscreen 0x3 TSSCTIM Touchscreen Switches Closure Time 16 4 read-write WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 read-write WPKEY Write Protection Key 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 0x414443 WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 read-only WPVSRC Write Protection Violation Source 8 16 read-only XPOSR Touchscreen X Position Register 0xB4 32 read-only n 0x0 0x0 XPOS X Position 0 12 read-only XSCALE Scale of XPOS 16 12 read-only YPOSR Touchscreen Y Position Register 0xB8 32 read-only n 0x0 0x0 YPOS Y Position 0 12 read-only YSCALE Scale of YPOS 16 12 read-only AES Advanced Encryption Standard AES 0x0 0x0 0x50 registers n AES 12 AADLENR Additional Authenticated Data Length Register 0x70 32 read-write n 0x0 0x0 AADLEN Additional Authenticated Data Length 0 32 read-write CLENR Plaintext/Ciphertext Length Register 0x74 32 read-write n 0x0 0x0 CLEN Plaintext/Ciphertext Length 0 32 read-write CR Control Register 0x0 32 write-only n 0x0 0x0 START Start Processing 0 1 write-only SWRST Software Reset 8 1 write-only CTRR GCM Encryption Counter Value Register 0x98 32 read-only n 0x0 0x0 CTR GCM Encryption Counter 0 32 read-only GCMHR0 GCM H Word Register 0x9C 32 read-write n H GCM H Word x 0 32 read-write GCMHR1 GCM H Word Register 0xA0 32 read-write n H GCM H Word x 0 32 read-write GCMHR2 GCM H Word Register 0xA4 32 read-write n H GCM H Word x 0 32 read-write GCMHR3 GCM H Word Register 0xA8 32 read-write n H GCM H Word x 0 32 read-write GCMHR[0] GCM H Word Register 0x138 32 read-write n 0x0 0x0 H GCM H Word x 0 32 read-write GCMHR[1] GCM H Word Register 0x1D8 32 read-write n 0x0 0x0 H GCM H Word x 0 32 read-write GCMHR[2] GCM H Word Register 0x27C 32 read-write n 0x0 0x0 H GCM H Word x 0 32 read-write GCMHR[3] GCM H Word Register 0x324 32 read-write n 0x0 0x0 H GCM H Word x 0 32 read-write GHASHR0 GCM Intermediate Hash Word Register 0x78 32 read-write n GHASH Intermediate GCM Hash Word x 0 32 read-write GHASHR1 GCM Intermediate Hash Word Register 0x7C 32 read-write n GHASH Intermediate GCM Hash Word x 0 32 read-write GHASHR2 GCM Intermediate Hash Word Register 0x80 32 read-write n GHASH Intermediate GCM Hash Word x 0 32 read-write GHASHR3 GCM Intermediate Hash Word Register 0x84 32 read-write n GHASH Intermediate GCM Hash Word x 0 32 read-write GHASHR[0] GCM Intermediate Hash Word Register 0xF0 32 read-write n 0x0 0x0 GHASH Intermediate GCM Hash Word x 0 32 read-write GHASHR[1] GCM Intermediate Hash Word Register 0x16C 32 read-write n 0x0 0x0 GHASH Intermediate GCM Hash Word x 0 32 read-write GHASHR[2] GCM Intermediate Hash Word Register 0x1EC 32 read-write n 0x0 0x0 GHASH Intermediate GCM Hash Word x 0 32 read-write GHASHR[3] GCM Intermediate Hash Word Register 0x270 32 read-write n 0x0 0x0 GHASH Intermediate GCM Hash Word x 0 32 read-write IDATAR0 Input Data Register 0x40 32 write-only n IDATA Input Data Word 0 32 write-only IDATAR1 Input Data Register 0x44 32 write-only n IDATA Input Data Word 0 32 write-only IDATAR2 Input Data Register 0x48 32 write-only n IDATA Input Data Word 0 32 write-only IDATAR3 Input Data Register 0x4C 32 write-only n IDATA Input Data Word 0 32 write-only IDATAR[0] Input Data Register 0x80 32 write-only n 0x0 0x0 IDATA Input Data Word 0 32 write-only IDATAR[1] Input Data Register 0xC4 32 write-only n 0x0 0x0 IDATA Input Data Word 0 32 write-only IDATAR[2] Input Data Register 0x10C 32 write-only n 0x0 0x0 IDATA Input Data Word 0 32 write-only IDATAR[3] Input Data Register 0x158 32 write-only n 0x0 0x0 IDATA Input Data Word 0 32 write-only IDR Interrupt Disable Register 0x14 32 write-only n 0x0 0x0 DATRDY Data Ready Interrupt Disable 0 1 write-only TAGRDY GCM Tag Ready Interrupt Disable 16 1 write-only URAD Unspecified Register Access Detection Interrupt Disable 8 1 write-only IER Interrupt Enable Register 0x10 32 write-only n 0x0 0x0 DATRDY Data Ready Interrupt Enable 0 1 write-only TAGRDY GCM Tag Ready Interrupt Enable 16 1 write-only URAD Unspecified Register Access Detection Interrupt Enable 8 1 write-only IMR Interrupt Mask Register 0x18 32 read-only n 0x0 0x0 DATRDY Data Ready Interrupt Mask 0 1 read-only TAGRDY GCM Tag Ready Interrupt Mask 16 1 read-only URAD Unspecified Register Access Detection Interrupt Mask 8 1 read-only ISR Interrupt Status Register 0x1C 32 read-only n 0x0 0x0 DATRDY Data Ready (cleared by setting bit START or bit SWRST in AES_CR or by reading AES_ODATARx) 0 1 read-only TAGRDY GCM Tag Ready 16 1 read-only URAD Unspecified Register Access Detection Status (cleared by writing SWRST in AES_CR) 8 1 read-only URAT Unspecified Register Access (cleared by writing SWRST in AES_CR) 12 4 read-only IDR_WR_PROCESSING Input Data register written during the data processing when SMOD = 2 mode. 0x0 ODR_RD_PROCESSING Output Data register read during the data processing. 0x1 MR_WR_PROCESSING Mode register written during the data processing. 0x2 ODR_RD_SUBKGEN Output Data register read during the sub-keys generation. 0x3 MR_WR_SUBKGEN Mode register written during the sub-keys generation. 0x4 WOR_RD_ACCESS Write-only register read access. 0x5 IVR0 Initialization Vector Register 0x60 32 write-only n IV Initialization Vector 0 32 write-only IVR1 Initialization Vector Register 0x64 32 write-only n IV Initialization Vector 0 32 write-only IVR2 Initialization Vector Register 0x68 32 write-only n IV Initialization Vector 0 32 write-only IVR3 Initialization Vector Register 0x6C 32 write-only n IV Initialization Vector 0 32 write-only IVR[0] Initialization Vector Register 0xC0 32 write-only n 0x0 0x0 IV Initialization Vector 0 32 write-only IVR[1] Initialization Vector Register 0x124 32 write-only n 0x0 0x0 IV Initialization Vector 0 32 write-only IVR[2] Initialization Vector Register 0x18C 32 write-only n 0x0 0x0 IV Initialization Vector 0 32 write-only IVR[3] Initialization Vector Register 0x1F8 32 write-only n 0x0 0x0 IV Initialization Vector 0 32 write-only KEYWR0 Key Word Register 0x20 32 write-only n KEYW Key Word 0 32 write-only KEYWR1 Key Word Register 0x24 32 write-only n KEYW Key Word 0 32 write-only KEYWR2 Key Word Register 0x28 32 write-only n KEYW Key Word 0 32 write-only KEYWR3 Key Word Register 0x2C 32 write-only n KEYW Key Word 0 32 write-only KEYWR4 Key Word Register 0x30 32 write-only n KEYW Key Word 0 32 write-only KEYWR5 Key Word Register 0x34 32 write-only n KEYW Key Word 0 32 write-only KEYWR6 Key Word Register 0x38 32 write-only n KEYW Key Word 0 32 write-only KEYWR7 Key Word Register 0x3C 32 write-only n KEYW Key Word 0 32 write-only KEYWR[0] Key Word Register 0x40 32 write-only n 0x0 0x0 KEYW Key Word 0 32 write-only KEYWR[1] Key Word Register 0x64 32 write-only n 0x0 0x0 KEYW Key Word 0 32 write-only KEYWR[2] Key Word Register 0x8C 32 write-only n 0x0 0x0 KEYW Key Word 0 32 write-only KEYWR[3] Key Word Register 0xB8 32 write-only n 0x0 0x0 KEYW Key Word 0 32 write-only KEYWR[4] Key Word Register 0xE8 32 write-only n 0x0 0x0 KEYW Key Word 0 32 write-only KEYWR[5] Key Word Register 0x11C 32 write-only n 0x0 0x0 KEYW Key Word 0 32 write-only KEYWR[6] Key Word Register 0x154 32 write-only n 0x0 0x0 KEYW Key Word 0 32 write-only KEYWR[7] Key Word Register 0x190 32 write-only n 0x0 0x0 KEYW Key Word 0 32 write-only MR Mode Register 0x4 32 read-write n 0x0 0x0 CFBS Cipher Feedback Data Size 16 3 read-write SIZE_128BIT 128-bit 0x0 SIZE_64BIT 64-bit 0x1 SIZE_32BIT 32-bit 0x2 SIZE_16BIT 16-bit 0x3 SIZE_8BIT 8-bit 0x4 CIPHER Processing Mode 0 1 read-write CKEY Key 20 4 read-write PASSWD This field must be written with 0xE the first time AES_MR is programmed. For subsequent programming of AES_MR, any value can be written, including that of 0xE.Always reads as 0. 0xE DUALBUFF Dual Input Buffer 3 1 read-write INACTIVE AES_IDATARx cannot be written during processing of previous block. 0 ACTIVE AES_IDATARx can be written during processing of previous block when SMOD = 2. It speeds up the overall runtime of large files. 1 GTAGEN GCM Automatic Tag Generation Enable 1 1 read-write KEYSIZE Key Size 10 2 read-write AES128 AES Key Size is 128 bits 0x0 AES192 AES Key Size is 192 bits 0x1 AES256 AES Key Size is 256 bits 0x2 LOD Last Output Data Mode 15 1 read-write OPMOD Operating Mode 12 3 read-write ECB ECB: Electronic Codebook mode 0x0 CBC CBC: Cipher Block Chaining mode 0x1 OFB OFB: Output Feedback mode 0x2 CFB CFB: Cipher Feedback mode 0x3 CTR CTR: Counter mode (16-bit internal counter) 0x4 GCM GCM: Galois/Counter mode 0x5 PROCDLY Processing Delay 4 4 read-write SMOD Start Mode 8 2 read-write MANUAL_START Manual Mode 0x0 AUTO_START Auto Mode 0x1 IDATAR0_START AES_IDATAR0 access only Auto Mode (DMA) 0x2 ODATAR0 Output Data Register 0x50 32 read-only n ODATA Output Data 0 32 read-only ODATAR1 Output Data Register 0x54 32 read-only n ODATA Output Data 0 32 read-only ODATAR2 Output Data Register 0x58 32 read-only n ODATA Output Data 0 32 read-only ODATAR3 Output Data Register 0x5C 32 read-only n ODATA Output Data 0 32 read-only ODATAR[0] Output Data Register 0xA0 32 read-only n 0x0 0x0 ODATA Output Data 0 32 read-only ODATAR[1] Output Data Register 0xF4 32 read-only n 0x0 0x0 ODATA Output Data 0 32 read-only ODATAR[2] Output Data Register 0x14C 32 read-only n 0x0 0x0 ODATA Output Data 0 32 read-only ODATAR[3] Output Data Register 0x1A8 32 read-only n 0x0 0x0 ODATA Output Data 0 32 read-only TAGR0 GCM Authentication Tag Word Register 0x88 32 read-only n TAG GCM Authentication Tag x 0 32 read-only TAGR1 GCM Authentication Tag Word Register 0x8C 32 read-only n TAG GCM Authentication Tag x 0 32 read-only TAGR2 GCM Authentication Tag Word Register 0x90 32 read-only n TAG GCM Authentication Tag x 0 32 read-only TAGR3 GCM Authentication Tag Word Register 0x94 32 read-only n TAG GCM Authentication Tag x 0 32 read-only TAGR[0] GCM Authentication Tag Word Register 0x110 32 read-only n 0x0 0x0 TAG GCM Authentication Tag x 0 32 read-only TAGR[1] GCM Authentication Tag Word Register 0x19C 32 read-only n 0x0 0x0 TAG GCM Authentication Tag x 0 32 read-only TAGR[2] GCM Authentication Tag Word Register 0x22C 32 read-only n 0x0 0x0 TAG GCM Authentication Tag x 0 32 read-only TAGR[3] GCM Authentication Tag Word Register 0x2C0 32 read-only n 0x0 0x0 TAG GCM Authentication Tag x 0 32 read-only AESB Advanced Encryption Standard Bridge AESB 0x0 0x0 0x50 registers n AESB 13 CR Control Register 0x0 32 write-only n 0x0 0x0 START Start Processing 0 1 write-only SWRST Software Reset 8 1 write-only IDATAR0 Input Data Register 0x40 32 write-only n IDATA Input Data Word 0 32 write-only IDATAR1 Input Data Register 0x44 32 write-only n IDATA Input Data Word 0 32 write-only IDATAR2 Input Data Register 0x48 32 write-only n IDATA Input Data Word 0 32 write-only IDATAR3 Input Data Register 0x4C 32 write-only n IDATA Input Data Word 0 32 write-only IDATAR[0] Input Data Register 0x80 32 write-only n 0x0 0x0 IDATA Input Data Word 0 32 write-only IDATAR[1] Input Data Register 0xC4 32 write-only n 0x0 0x0 IDATA Input Data Word 0 32 write-only IDATAR[2] Input Data Register 0x10C 32 write-only n 0x0 0x0 IDATA Input Data Word 0 32 write-only IDATAR[3] Input Data Register 0x158 32 write-only n 0x0 0x0 IDATA Input Data Word 0 32 write-only IDR Interrupt Disable Register 0x14 32 write-only n 0x0 0x0 DATRDY Data Ready Interrupt Disable 0 1 write-only URAD Unspecified Register Access Detection Interrupt Disable 8 1 write-only IER Interrupt Enable Register 0x10 32 write-only n 0x0 0x0 DATRDY Data Ready Interrupt Enable 0 1 write-only URAD Unspecified Register Access Detection Interrupt Enable 8 1 write-only IMR Interrupt Mask Register 0x18 32 read-only n 0x0 0x0 DATRDY Data Ready Interrupt Mask 0 1 read-only URAD Unspecified Register Access Detection Interrupt Mask 8 1 read-only ISR Interrupt Status Register 0x1C 32 read-only n 0x0 0x0 DATRDY Data Ready 0 1 read-only URAD Unspecified Register Access Detection Status 8 1 read-only URAT Unspecified Register Access 12 4 read-only IDR_WR_PROCESSING Input Data Register written during the data processing when SMOD = 0x2 mode 0x0 ODR_RD_PROCESSING Output Data Register read during the data processing 0x1 MR_WR_PROCESSING Mode Register written during the data processing 0x2 ODR_RD_SUBKGEN Output Data Register read during the sub-keys generation 0x3 MR_WR_SUBKGEN Mode Register written during the sub-keys generation 0x4 WOR_RD_ACCESS Write-only register read access 0x5 IVR0 Initialization Vector Register 0x60 32 write-only n IV Initialization Vector 0 32 write-only IVR1 Initialization Vector Register 0x64 32 write-only n IV Initialization Vector 0 32 write-only IVR2 Initialization Vector Register 0x68 32 write-only n IV Initialization Vector 0 32 write-only IVR3 Initialization Vector Register 0x6C 32 write-only n IV Initialization Vector 0 32 write-only IVR[0] Initialization Vector Register 0xC0 32 write-only n 0x0 0x0 IV Initialization Vector 0 32 write-only IVR[1] Initialization Vector Register 0x124 32 write-only n 0x0 0x0 IV Initialization Vector 0 32 write-only IVR[2] Initialization Vector Register 0x18C 32 write-only n 0x0 0x0 IV Initialization Vector 0 32 write-only IVR[3] Initialization Vector Register 0x1F8 32 write-only n 0x0 0x0 IV Initialization Vector 0 32 write-only KEYWR0 Key Word Register 0x20 32 write-only n KEYW Key Word 0 32 write-only KEYWR1 Key Word Register 0x24 32 write-only n KEYW Key Word 0 32 write-only KEYWR2 Key Word Register 0x28 32 write-only n KEYW Key Word 0 32 write-only KEYWR3 Key Word Register 0x2C 32 write-only n KEYW Key Word 0 32 write-only KEYWR[0] Key Word Register 0x40 32 write-only n 0x0 0x0 KEYW Key Word 0 32 write-only KEYWR[1] Key Word Register 0x64 32 write-only n 0x0 0x0 KEYW Key Word 0 32 write-only KEYWR[2] Key Word Register 0x8C 32 write-only n 0x0 0x0 KEYW Key Word 0 32 write-only KEYWR[3] Key Word Register 0xB8 32 write-only n 0x0 0x0 KEYW Key Word 0 32 write-only MR Mode Register 0x4 32 read-write n 0x0 0x0 AAHB Automatic Bridge Mode 2 1 read-write CIPHER Processing Mode 0 1 read-write CKEY Key 20 4 read-write PASSWD This field must be written with 0xE the first time that AES_MR is programmed. For subsequent programming of the AES_MR register, any value can be written, including that of 0xE.Always reads as 0. 0xE DUALBUFF Dual Input Buffer 3 1 read-write INACTIVE AESB_IDATARx cannot be written during processing of previous block. 0x0 ACTIVE AESB_IDATARx can be written during processing of previous block when SMOD = 0x2. It speeds up the overall runtime of large files. 0x1 LOD Last Output Data Mode 15 1 read-write OPMOD Operating Mode 12 3 read-write ECB Electronic Code Book mode 0x0 CBC Cipher Block Chaining mode 0x1 CTR Counter mode (16-bit internal counter) 0x4 PROCDLY Processing Delay 4 4 read-write SMOD Start Mode 8 2 read-write MANUAL_START Manual mode 0x0 AUTO_START Auto mode 0x1 IDATAR0_START AESB_IDATAR0 access only Auto mode 0x2 ODATAR0 Output Data Register 0x50 32 read-only n ODATA Output Data 0 32 read-only ODATAR1 Output Data Register 0x54 32 read-only n ODATA Output Data 0 32 read-only ODATAR2 Output Data Register 0x58 32 read-only n ODATA Output Data 0 32 read-only ODATAR3 Output Data Register 0x5C 32 read-only n ODATA Output Data 0 32 read-only ODATAR[0] Output Data Register 0xA0 32 read-only n 0x0 0x0 ODATA Output Data 0 32 read-only ODATAR[1] Output Data Register 0xF4 32 read-only n 0x0 0x0 ODATA Output Data 0 32 read-only ODATAR[2] Output Data Register 0x14C 32 read-only n 0x0 0x0 ODATA Output Data 0 32 read-only ODATAR[3] Output Data Register 0x1A8 32 read-only n 0x0 0x0 ODATA Output Data 0 32 read-only AIC Advanced Interrupt Controller AIC 0x0 0x0 0x1000 registers n IRQ 56 AIC 65 CISR Core Interrupt Status Register 0x34 32 read-only n 0x0 0x0 NFIQ NFIQ Status 0 1 read-only NIRQ NIRQ Status 1 1 read-only DCR Debug Control Register 0x6C 32 read-write n 0x0 0x0 GMSK General Interrupt Mask 1 1 read-write PROT Protection Mode 0 1 read-write EOICR End of Interrupt Command Register 0x38 32 write-only n 0x0 0x0 ENDIT Interrupt Processing Complete Command 0 1 write-only FVR FIQ Vector Register 0x14 32 read-only n 0x0 0x0 FIQV FIQ Vector Register 0 32 read-only ICCR Interrupt Clear Command Register 0x48 32 write-only n 0x0 0x0 INTCLR Interrupt Clear 0 1 write-only IDCR Interrupt Disable Command Register 0x44 32 write-only n 0x0 0x0 INTD Interrupt Disable 0 1 write-only IECR Interrupt Enable Command Register 0x40 32 write-only n 0x0 0x0 INTEN Interrupt Enable 0 1 write-only IMR Interrupt Mask Register 0x30 32 read-only n 0x0 0x0 INTM Interrupt Mask 0 1 read-only IPR0 Interrupt Pending Register 0 0x20 32 read-only n 0x0 0x0 FIQ Interrupt Pending 0 1 read-only PID10 Interrupt Pending 10 1 read-only PID11 Interrupt Pending 11 1 read-only PID12 Interrupt Pending 12 1 read-only PID13 Interrupt Pending 13 1 read-only PID14 Interrupt Pending 14 1 read-only PID15 Interrupt Pending 15 1 read-only PID16 Interrupt Pending 16 1 read-only PID17 Interrupt Pending 17 1 read-only PID18 Interrupt Pending 18 1 read-only PID19 Interrupt Pending 19 1 read-only PID2 Interrupt Pending 2 1 read-only PID20 Interrupt Pending 20 1 read-only PID21 Interrupt Pending 21 1 read-only PID22 Interrupt Pending 22 1 read-only PID23 Interrupt Pending 23 1 read-only PID24 Interrupt Pending 24 1 read-only PID25 Interrupt Pending 25 1 read-only PID26 Interrupt Pending 26 1 read-only PID27 Interrupt Pending 27 1 read-only PID28 Interrupt Pending 28 1 read-only PID29 Interrupt Pending 29 1 read-only PID3 Interrupt Pending 3 1 read-only PID30 Interrupt Pending 30 1 read-only PID31 Interrupt Pending 31 1 read-only PID4 Interrupt Pending 4 1 read-only PID5 Interrupt Pending 5 1 read-only PID6 Interrupt Pending 6 1 read-only PID7 Interrupt Pending 7 1 read-only PID8 Interrupt Pending 8 1 read-only PID9 Interrupt Pending 9 1 read-only SYS Interrupt Pending 1 1 read-only IPR1 Interrupt Pending Register 1 0x24 32 read-only n 0x0 0x0 PID32 Interrupt Pending 0 1 read-only PID33 Interrupt Pending 1 1 read-only PID34 Interrupt Pending 2 1 read-only PID35 Interrupt Pending 3 1 read-only PID36 Interrupt Pending 4 1 read-only PID37 Interrupt Pending 5 1 read-only PID38 Interrupt Pending 6 1 read-only PID39 Interrupt Pending 7 1 read-only PID40 Interrupt Pending 8 1 read-only PID41 Interrupt Pending 9 1 read-only PID42 Interrupt Pending 10 1 read-only PID43 Interrupt Pending 11 1 read-only PID44 Interrupt Pending 12 1 read-only PID45 Interrupt Pending 13 1 read-only PID46 Interrupt Pending 14 1 read-only PID47 Interrupt Pending 15 1 read-only PID48 Interrupt Pending 16 1 read-only PID49 Interrupt Pending 17 1 read-only PID50 Interrupt Pending 18 1 read-only PID51 Interrupt Pending 19 1 read-only PID52 Interrupt Pending 20 1 read-only PID53 Interrupt Pending 21 1 read-only PID54 Interrupt Pending 22 1 read-only PID55 Interrupt Pending 23 1 read-only PID56 Interrupt Pending 24 1 read-only PID57 Interrupt Pending 25 1 read-only PID58 Interrupt Pending 26 1 read-only PID59 Interrupt Pending 27 1 read-only PID60 Interrupt Pending 28 1 read-only PID61 Interrupt Pending 29 1 read-only PID62 Interrupt Pending 30 1 read-only PID63 Interrupt Pending 31 1 read-only IPR2 Interrupt Pending Register 2 0x28 32 read-only n 0x0 0x0 PID64 Interrupt Pending 0 1 read-only PID65 Interrupt Pending 1 1 read-only PID66 Interrupt Pending 2 1 read-only PID67 Interrupt Pending 3 1 read-only PID68 Interrupt Pending 4 1 read-only PID69 Interrupt Pending 5 1 read-only PID70 Interrupt Pending 6 1 read-only PID71 Interrupt Pending 7 1 read-only PID72 Interrupt Pending 8 1 read-only PID73 Interrupt Pending 9 1 read-only PID74 Interrupt Pending 10 1 read-only PID75 Interrupt Pending 11 1 read-only PID76 Interrupt Pending 12 1 read-only PID77 Interrupt Pending 13 1 read-only PID78 Interrupt Pending 14 1 read-only PID79 Interrupt Pending 15 1 read-only PID80 Interrupt Pending 16 1 read-only PID81 Interrupt Pending 17 1 read-only PID82 Interrupt Pending 18 1 read-only PID83 Interrupt Pending 19 1 read-only PID84 Interrupt Pending 20 1 read-only PID85 Interrupt Pending 21 1 read-only PID86 Interrupt Pending 22 1 read-only PID87 Interrupt Pending 23 1 read-only PID88 Interrupt Pending 24 1 read-only PID89 Interrupt Pending 25 1 read-only PID90 Interrupt Pending 26 1 read-only PID91 Interrupt Pending 27 1 read-only PID92 Interrupt Pending 28 1 read-only PID93 Interrupt Pending 29 1 read-only PID94 Interrupt Pending 30 1 read-only PID95 Interrupt Pending 31 1 read-only IPR3 Interrupt Pending Register 3 0x2C 32 read-only n 0x0 0x0 PID100 Interrupt Pending 4 1 read-only PID101 Interrupt Pending 5 1 read-only PID102 Interrupt Pending 6 1 read-only PID103 Interrupt Pending 7 1 read-only PID104 Interrupt Pending 8 1 read-only PID105 Interrupt Pending 9 1 read-only PID106 Interrupt Pending 10 1 read-only PID107 Interrupt Pending 11 1 read-only PID108 Interrupt Pending 12 1 read-only PID109 Interrupt Pending 13 1 read-only PID110 Interrupt Pending 14 1 read-only PID111 Interrupt Pending 15 1 read-only PID112 Interrupt Pending 16 1 read-only PID113 Interrupt Pending 17 1 read-only PID114 Interrupt Pending 18 1 read-only PID115 Interrupt Pending 19 1 read-only PID116 Interrupt Pending 20 1 read-only PID117 Interrupt Pending 21 1 read-only PID118 Interrupt Pending 22 1 read-only PID119 Interrupt Pending 23 1 read-only PID120 Interrupt Pending 24 1 read-only PID121 Interrupt Pending 25 1 read-only PID122 Interrupt Pending 26 1 read-only PID123 Interrupt Pending 27 1 read-only PID124 Interrupt Pending 28 1 read-only PID125 Interrupt Pending 29 1 read-only PID126 Interrupt Pending 30 1 read-only PID127 Interrupt Pending 31 1 read-only PID96 Interrupt Pending 0 1 read-only PID97 Interrupt Pending 1 1 read-only PID98 Interrupt Pending 2 1 read-only PID99 Interrupt Pending 3 1 read-only ISCR Interrupt Set Command Register 0x4C 32 write-only n 0x0 0x0 INTSET Interrupt Set 0 1 write-only ISR Interrupt Status Register 0x18 32 read-only n 0x0 0x0 IRQID Current Interrupt Identifier 0 7 read-only IVR Interrupt Vector Register 0x10 32 read-only n 0x0 0x0 IRQV Interrupt Vector Register 0 32 read-only SMR Source Mode Register 0x4 32 read-write n 0x0 0x0 PRIOR Priority Level 0 3 read-write SRCTYPE Interrupt Source Type 5 2 read-write INT_LEVEL_SENSITIVE High level Sensitive for internal sourceLow level Sensitive for external source 0x0 INT_EDGE_TRIGGERED Positive edge triggered for internal sourceNegative edge triggered for external source 0x1 EXT_HIGH_LEVEL High level Sensitive for internal sourceHigh level Sensitive for external source 0x2 EXT_POSITIVE_EDGE Positive edge triggered for internal sourcePositive edge triggered for external source 0x3 SPU Spurious Interrupt Vector Register 0x3C 32 read-write n 0x0 0x0 SIVR Spurious Interrupt Vector Register 0 32 read-write SSR Source Select Register 0x0 32 read-write n 0x0 0x0 INTSEL Interrupt Line Selection 0 7 read-write SVR Source Vector Register 0x8 32 read-write n 0x0 0x0 VECTOR Source Vector 0 32 read-write WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 read-write WPKEY Write Protection Key 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 0x414943 WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 read-only WPVSRC Write Protection Violation Source 8 16 read-only AXIMX AXI Matrix AXIMX 0x0 0x0 0x100000 registers n REMAP AXI Matrix Remap Register 0x0 32 write-only n 0x0 0x0 REMAP0 Remap State 0 0 1 write-only DBGU Debug Unit DBGU 0x0 0x0 0x1000 registers n DBGU 45 BRGR Baud Rate Generator Register 0x20 32 read-write n 0x0 0x0 CD Clock Divisor 0 16 read-write DISABLED DBGU Disabled 0 MCK Peripheral clock 1 CIDR Chip ID Register 0x40 32 read-only n 0x0 0x0 ARCH Architecture Identifier 20 8 read-only AT91SAM9xx AT91SAM9xx Series 0x19 AT91SAM9XExx AT91SAM9XExx Series 0x29 AT91x34 AT91x34 Series 0x34 CAP7 CAP7 Series 0x37 CAP9 CAP9 Series 0x39 CAP11 CAP11 Series 0x3B AT91x40 AT91x40 Series 0x40 AT91x42 AT91x42 Series 0x42 AT91x55 AT91x55 Series 0x55 AT91SAM7Axx AT91SAM7Axx Series 0x60 AT91SAM7AQxx AT91SAM7AQxx Series 0x61 AT91x63 AT91x63 Series 0x63 AT91SAM7Sxx AT91SAM7Sxx Series 0x70 AT91SAM7XCxx AT91SAM7XCxx Series 0x71 AT91SAM7SExx AT91SAM7SExx Series 0x72 AT91SAM7Lxx AT91SAM7Lxx Series 0x73 AT91SAM7Xxx AT91SAM7Xxx Series 0x75 AT91SAM7SLxx AT91SAM7SLxx Series 0x76 ATSAM3UxC ATSAM3UxC Series (100-pin version) 0x80 ATSAM3UxE ATSAM3UxE Series (144-pin version) 0x81 ATSAM3AxC ATSAM3AxC Series (100-pin version) 0x83 ATSAM3XxC ATSAM3XxC Series (100-pin version) 0x84 ATSAM3XxE ATSAM3XxE Series (144-pin version) 0x85 ATSAM3XxG ATSAM3XxG Series (208/217-pin version) 0x86 ATSAM3SxA ATSAM3SxA Series (48-pin version) 0x88 ATSAM3SxB ATSAM3SxB Series (64-pin version) 0x89 ATSAM3SxC ATSAM3SxC Series (100-pin version) 0x8A AT91x92 AT91x92 Series 0x92 ATSAM3NxA ATSAM3NxA Series (48-pin version) 0x93 ATSAM3NxB ATSAM3NxB Series (64-pin version) 0x94 ATSAM3NxC ATSAM3NxC Series (100-pin version) 0x95 ATSAM3SDxA ATSAM3SDxA Series (48-pin version) 0x98 ATSAM3SDxB ATSAM3SDxB Series (64-pin version) 0x99 ATSAM3SDxC ATSAM3SDxC Series (100-pin version) 0x9A ATSAMA5xx ATSAMA5xx Series 0xA5 AT75Cxx AT75Cxx Series 0xF0 EPROC Embedded Processor 5 3 read-only ARM946ES ARM946ES 0x1 ARM7TDMI ARM7TDMI 0x2 CM3 Cortex-M3 0x3 ARM920T ARM920T 0x4 ARM926EJS ARM926EJ-S 0x5 CA5 Cortex-A5 0x6 EXT Extension Flag 31 1 read-only NVPSIZ Nonvolatile Program Memory Size 8 4 read-only NONE None 0x0 8K 8 Kbytes 0x1 16K 16 Kbytes 0x2 32K 32 Kbytes 0x3 64K 64 Kbytes 0x5 128K 128 Kbytes 0x7 256K 256 Kbytes 0x9 512K 512 Kbytes 0xA 1024K 1024 Kbytes 0xC 2048K 2048 Kbytes 0xE NVPSIZ2 Second Nonvolatile Program Memory Size 12 4 read-only NONE None 0x0 8K 8 Kbytes 0x1 16K 16 Kbytes 0x2 32K 32 Kbytes 0x3 64K 64 Kbytes 0x5 128K 128 Kbytes 0x7 256K 256 Kbytes 0x9 512K 512 Kbytes 0xA 1024K 1024 Kbytes 0xC 2048K 2048 Kbytes 0xE NVPTYP Nonvolatile Program Memory Type 28 3 read-only ROM ROM 0x0 ROMLESS ROMless or on-chip Flash 0x1 FLASH Embedded Flash Memory 0x2 ROM_FLASH ROM and Embedded Flash MemoryNVPSIZ is ROM size NVPSIZ2 is Flash size 0x3 SRAM SRAM emulating ROM 0x4 SRAMSIZ Internal SRAM Size 16 4 read-only 1K 1 Kbytes 0x1 2K 2 Kbytes 0x2 6K 6 Kbytes 0x3 112K 112 Kbytes 0x4 4K 4 Kbytes 0x5 80K 80 Kbytes 0x6 160K 160 Kbytes 0x7 8K 8 Kbytes 0x8 16K 16 Kbytes 0x9 32K 32 Kbytes 0xA 64K 64 Kbytes 0xB 128K 128 Kbytes 0xC 256K 256 Kbytes 0xD 96K 96 Kbytes 0xE 512K 512 Kbytes 0xF VERSION Version of the Device 0 5 read-only CR Control Register 0x0 32 write-only n 0x0 0x0 RSTRX Reset Receiver 2 1 write-only RSTSTA Reset Status Bits 8 1 write-only RSTTX Reset Transmitter 3 1 write-only RXDIS Receiver Disable 5 1 write-only RXEN Receiver Enable 4 1 write-only TXDIS Transmitter Disable 7 1 write-only TXEN Transmitter Enable 6 1 write-only EXID Chip ID Extension Register 0x44 32 read-only n 0x0 0x0 EXID Chip ID Extension 0 32 read-only FNR Force NTRST Register 0x48 32 read-write n 0x0 0x0 FNTRST Force NTRST 0 1 read-write IDR Interrupt Disable Register 0xC 32 write-only n 0x0 0x0 COMMRX Disable COMMRX (from ARM) Interrupt 31 1 write-only COMMTX Disable COMMTX (from ARM) Interrupt 30 1 write-only FRAME Disable Framing Error Interrupt 6 1 write-only OVRE Disable Overrun Error Interrupt 5 1 write-only PARE Disable Parity Error Interrupt 7 1 write-only RXRDY Disable RXRDY Interrupt 0 1 write-only TXEMPTY Disable TXEMPTY Interrupt 9 1 write-only TXRDY Disable TXRDY Interrupt 1 1 write-only IER Interrupt Enable Register 0x8 32 write-only n 0x0 0x0 COMMRX Enable COMMRX (from ARM) Interrupt 31 1 write-only COMMTX Enable COMMTX (from ARM) Interrupt 30 1 write-only FRAME Enable Framing Error Interrupt 6 1 write-only OVRE Enable Overrun Error Interrupt 5 1 write-only PARE Enable Parity Error Interrupt 7 1 write-only RXRDY Enable RXRDY Interrupt 0 1 write-only TXEMPTY Enable TXEMPTY Interrupt 9 1 write-only TXRDY Enable TXRDY Interrupt 1 1 write-only IMR Interrupt Mask Register 0x10 32 read-only n 0x0 0x0 COMMRX Mask COMMRX Interrupt 31 1 read-only COMMTX Mask COMMTX Interrupt 30 1 read-only FRAME Mask Framing Error Interrupt 6 1 read-only OVRE Mask Overrun Error Interrupt 5 1 read-only PARE Mask Parity Error Interrupt 7 1 read-only RXRDY Mask RXRDY Interrupt 0 1 read-only TXEMPTY Mask TXEMPTY Interrupt 9 1 read-only TXRDY Disable TXRDY Interrupt 1 1 read-only MR Mode Register 0x4 32 read-write n 0x0 0x0 CHMODE Channel Mode 14 2 read-write NORM Normal Mode 0x0 AUTO Automatic Echo 0x1 LOCLOOP Local Loopback 0x2 REMLOOP Remote Loopback 0x3 FILTER Receiver Digital Filter 4 1 read-write DISABLED DBGU does not filter the receive line. 0 ENABLED DBGU filters the receive line using a three-sample filter (16x-bit clock) (2 over 3 majority). 1 PAR Parity Type 9 3 read-write EVEN Even Parity 0x0 ODD Odd Parity 0x1 SPACE Space: Parity forced to 0 0x2 MARK Mark: Parity forced to 1 0x3 NONE No Parity 0x4 RHR Receive Holding Register 0x18 32 read-only n 0x0 0x0 RXCHR Received Character 0 8 read-only SR Status Register 0x14 32 read-only n 0x0 0x0 COMMRX Debug Communication Channel Read Status 31 1 read-only COMMTX Debug Communication Channel Write Status 30 1 read-only FRAME Framing Error 6 1 read-only OVRE Overrun Error 5 1 read-only PARE Parity Error 7 1 read-only RXRDY Receiver Ready 0 1 read-only TXEMPTY Transmitter Empty 9 1 read-only TXRDY Transmitter Ready 1 1 read-only THR Transmit Holding Register 0x1C 32 write-only n 0x0 0x0 TXCHR Character to be Transmitted 0 8 write-only GMAC0 Gigabit Ethernet MAC 0 GMAC 0x0 0x0 0x50 registers n GMAC0 54 AE Alignment Errors Register 0x19C 32 read-only n 0x0 0x0 AER Alignment Errors 0 10 read-only BCFR Broadcast Frames Received Register 0x15C 32 read-only n 0x0 0x0 BFRX Broadcast Frames Received without Error 0 32 read-only BCFT Broadcast Frames Transmitted Register 0x10C 32 read-only n 0x0 0x0 BFTX Broadcast Frames Transmitted without Error 0 32 read-only BFR64 64 Byte Frames Received Register 0x168 32 read-only n 0x0 0x0 NFRX 64 Byte Frames Received without Error 0 32 read-only BFT64 64 Byte Frames Transmitted Register 0x118 32 read-only n 0x0 0x0 NFTX 64 Byte Frames Transmitted without Error 0 32 read-only CSE Carrier Sense Errors Register 0x14C 32 read-only n 0x0 0x0 CSR Carrier Sense Error 0 10 read-only DCFGR DMA Configuration Register 0x10 32 read-write n 0x0 0x0 DRBS DMA Receive Buffer Size 16 8 read-write ESMA Endian Swap Mode Enable for Management Descriptor Accesses 6 1 read-write ESPA Endian Swap Mode Enable for Packet Data Accesses 7 1 read-write FBLDO Fixed Burst Length for DMA Data Operations: 0 5 read-write SINGLE 00001: Always use SINGLE AHB bursts 0x1 INCR16 1xxxx: Attempt to use INCR16 AHB bursts 0x10 INCR4 001xx: Attempt to use INCR4 AHB bursts (Default) 0x4 INCR8 01xxx: Attempt to use INCR8 AHB bursts 0x8 DTF Deferred Transmission Frames Register 0x148 32 read-only n 0x0 0x0 DEFT Deferred Transmission 0 18 read-only EC Excessive Collisions Register 0x140 32 read-only n 0x0 0x0 XCOL Excessive Collisions 0 10 read-only EFRN PTP Event Frame Received Nanoseconds Register 0x1EC 32 read-only n 0x0 0x0 RUD Register Update 0 30 read-only EFRSH PTP Event Frame Received Seconds High Register 0xEC 32 read-only n 0x0 0x0 RUD Register Update 0 16 read-only EFRSL PTP Event Frame Received Seconds Low Register 0x1E8 32 read-only n 0x0 0x0 RUD Register Update 0 32 read-only EFTN PTP Event Frame Transmitted Nanoseconds Register 0x1E4 32 read-only n 0x0 0x0 RUD Register Update 0 30 read-only EFTSH PTP Event Frame Transmitted Seconds High Register 0xE8 32 read-only n 0x0 0x0 RUD Register Update 0 16 read-only EFTSL PTP Event Frame Transmitted Seconds Low Register 0x1E0 32 read-only n 0x0 0x0 RUD Register Update 0 32 read-only FCSE Frame Check Sequence Errors Register 0x190 32 read-only n 0x0 0x0 FCKR Frame Check Sequence Errors 0 10 read-only FR Frames Received Register 0x158 32 read-only n 0x0 0x0 FRX Frames Received without Error 0 32 read-only FT Frames Transmitted Register 0x108 32 read-only n 0x0 0x0 FTX Frames Transmitted without Error 0 32 read-only GTBFT1518 Greater Than 1518 Byte Frames Transmitted Register 0x130 32 read-only n 0x0 0x0 NFTX Greater than 1518 Byte Frames Transmitted without Error 0 32 read-only HRB Hash Register Bottom 0x80 32 read-write n 0x0 0x0 ADDR Hash Address 0 32 read-write HRT Hash Register Top 0x84 32 read-write n 0x0 0x0 ADDR Hash Address 0 32 read-write IDR Interrupt Disable Register 0x2C 32 write-only n 0x0 0x0 DRQFR PTP Delay Request Frame Received 18 1 write-only DRQFT PTP Delay Request Frame Transmitted 20 1 write-only EXINT External Interrupt 15 1 write-only HRESP HRESP Not OK 11 1 write-only MFS Management Frame Sent 0 1 write-only PDRQFR PDelay Request Frame Received 22 1 write-only PDRQFT PDelay Request Frame Transmitted 24 1 write-only PDRSFR PDelay Response Frame Received 23 1 write-only PDRSFT PDelay Response Frame Transmitted 25 1 write-only PFNZ Pause Frame with Non-zero Pause Quantum Received 12 1 write-only PFTR Pause Frame Transmitted 14 1 write-only PTZ Pause Time Zero 13 1 write-only RCOMP Receive Complete 1 1 write-only RLEX Retry Limit Exceeded or Late Collision 5 1 write-only ROVR Receive Overrun 10 1 write-only RXLPISBC Enable RX LPI Indication 27 1 write-only RXUBR RX Used Bit Read 2 1 write-only SFR PTP Sync Frame Received 19 1 write-only SFT PTP Sync Frame Transmitted 21 1 write-only SRI TSU Seconds Register Increment 26 1 write-only TCOMP Transmit Complete 7 1 write-only TFC Transmit Frame Corruption Due to AHB Error 6 1 write-only TSUTIMCOMP TSU Timer Comparison 29 1 write-only TUR Transmit Underrun 4 1 write-only TXUBR TX Used Bit Read 3 1 write-only WOL Wake On LAN 28 1 write-only IER Interrupt Enable Register 0x28 32 write-only n 0x0 0x0 DRQFR PTP Delay Request Frame Received 18 1 write-only DRQFT PTP Delay Request Frame Transmitted 20 1 write-only EXINT External Interrupt 15 1 write-only HRESP HRESP Not OK 11 1 write-only MFS Management Frame Sent 0 1 write-only PDRQFR PDelay Request Frame Received 22 1 write-only PDRQFT PDelay Request Frame Transmitted 24 1 write-only PDRSFR PDelay Response Frame Received 23 1 write-only PDRSFT PDelay Response Frame Transmitted 25 1 write-only PFNZ Pause Frame with Non-zero Pause Quantum Received 12 1 write-only PFTR Pause Frame Transmitted 14 1 write-only PTZ Pause Time Zero 13 1 write-only RCOMP Receive Complete 1 1 write-only RLEX Retry Limit Exceeded or Late Collision 5 1 write-only ROVR Receive Overrun 10 1 write-only RXLPISBC Enable RX LPI Indication 27 1 write-only RXUBR RX Used Bit Read 2 1 write-only SFR PTP Sync Frame Received 19 1 write-only SFT PTP Sync Frame Transmitted 21 1 write-only SRI TSU Seconds Register Increment 26 1 write-only TCOMP Transmit Complete 7 1 write-only TFC Transmit Frame Corruption Due to AHB Error 6 1 write-only TSUTIMCOMP TSU Timer Comparison 29 1 write-only TUR Transmit Underrun 4 1 write-only TXUBR TX Used Bit Read 3 1 write-only WOL Wake On LAN 28 1 write-only IHCE IP Header Checksum Errors Register 0x1A8 32 read-only n 0x0 0x0 HCKER IP Header Checksum Errors 0 8 read-only IMR Interrupt Mask Register 0x30 32 read-write n 0x0 0x0 DRQFR PTP Delay Request Frame Received 18 1 read-write DRQFT PTP Delay Request Frame Transmitted 20 1 read-write EXINT External Interrupt 15 1 read-write HRESP HRESP Not OK 11 1 read-write MFS Management Frame Sent 0 1 read-write PDRQFR PDelay Request Frame Received 22 1 read-write PDRQFT PDelay Request Frame Transmitted 24 1 read-write PDRSFR PDelay Response Frame Received 23 1 read-write PDRSFT PDelay Response Frame Transmitted 25 1 read-write PFNZ Pause Frame with Non-zero Pause Quantum Received 12 1 read-write PFTR Pause Frame Transmitted 14 1 read-write PTZ Pause Time Zero 13 1 read-write RCOMP Receive Complete 1 1 read-write RLEX Retry Limit Exceeded 5 1 read-write ROVR Receive Overrun 10 1 read-write RXLPISBC Enable RX LPI Indication 27 1 read-write RXUBR RX Used Bit Read 2 1 read-write SFR PTP Sync Frame Received 19 1 read-write SFT PTP Sync Frame Transmitted 21 1 read-write SRI TSU Seconds Register Increment 26 1 read-write TCOMP Transmit Complete 7 1 read-write TFC Transmit Frame Corruption Due to AHB Error 6 1 read-write TSUTIMCOMP TSU Timer Comparison 29 1 read-write TUR Transmit Underrun 4 1 read-write TXUBR TX Used Bit Read 3 1 read-write WOL Wake On LAN 28 1 read-write IPGS IPG Stretch Register 0xBC 32 read-write n 0x0 0x0 FL Frame Length 0 16 read-write ISR Interrupt Status Register 0x24 32 read-only n 0x0 0x0 DRQFR PTP Delay Request Frame Received 18 1 read-only DRQFT PTP Delay Request Frame Transmitted 20 1 read-only HRESP HRESP Not OK 11 1 read-only MFS Management Frame Sent 0 1 read-only PDRQFR PDelay Request Frame Received 22 1 read-only PDRQFT PDelay Request Frame Transmitted 24 1 read-only PDRSFR PDelay Response Frame Received 23 1 read-only PDRSFT PDelay Response Frame Transmitted 25 1 read-only PFNZ Pause Frame with Non-zero Pause Quantum Received 12 1 read-only PFTR Pause Frame Transmitted 14 1 read-only PTZ Pause Time Zero 13 1 read-only RCOMP Receive Complete 1 1 read-only RLEX Retry Limit Exceeded 5 1 read-only ROVR Receive Overrun 10 1 read-only RXLPISBC Receive LPI indication Status Bit Change 27 1 read-only RXUBR RX Used Bit Read 2 1 read-only SFR PTP Sync Frame Received 19 1 read-only SFT PTP Sync Frame Transmitted 21 1 read-only SRI TSU Seconds Register Increment 26 1 read-only TCOMP Transmit Complete 7 1 read-only TFC Transmit Frame Corruption Due to AHB Error 6 1 read-only TSUTIMCOMP TSU Timer Comparison 29 1 read-only TUR Transmit Underrun 4 1 read-only TXUBR TX Used Bit Read 3 1 read-only WOL Wake On LAN 28 1 read-only JR Jabbers Received Register 0x18C 32 read-only n 0x0 0x0 JRX Jabbers Received 0 10 read-only LC Late Collisions Register 0x144 32 read-only n 0x0 0x0 LCOL Late Collisions 0 10 read-only LFFE Length Field Frame Errors Register 0x194 32 read-only n 0x0 0x0 LFER Length Field Frame Errors 0 10 read-only MAN PHY Maintenance Register 0x34 32 read-write n 0x0 0x0 CLTTO Clause 22 Operation 30 1 read-write DATA PHY Data 0 16 read-write OP Operation 28 2 read-write PHYA PHY Address 23 5 read-write REGA Register Address 18 5 read-write WTN Write Ten 16 2 read-write WZO Write ZERO 31 1 read-write MCF Multiple Collision Frames Register 0x13C 32 read-only n 0x0 0x0 MCOL Multiple Collision 0 18 read-only MFR Multicast Frames Received Register 0x160 32 read-only n 0x0 0x0 MFRX Multicast Frames Received without Error 0 32 read-only MFT Multicast Frames Transmitted Register 0x110 32 read-only n 0x0 0x0 MFTX Multicast Frames Transmitted without Error 0 32 read-only NCFGR Network Configuration Register 0x4 32 read-write n 0x0 0x0 CAF Copy All Frames 4 1 read-write CLK MDC CLock Division 18 3 read-write MCK_8 MCK divided by 8 (MCK up to 20 MHz) 0x0 MCK_16 MCK divided by 16 (MCK up to 40 MHz) 0x1 MCK_32 MCK divided by 32 (MCK up to 80 MHz) 0x2 MCK_48 MCK divided by 48 (MCK up to 120 MHz) 0x3 MCK_64 MCK divided by 64 (MCK up to 160 MHz) 0x4 MCK_96 MCK divided by 96 (MCK up to 240 MHz) 0x5 DBW Data Bus Width 21 2 read-write DCPF Disable Copy of Pause Frames 23 1 read-write DNVLAN Discard Non-VLAN FRAMES 2 1 read-write EFRHD Enable Frames Received in Half Duplex 25 1 read-write FD Full Duplex 1 1 read-write IPGSEN IP Stretch Enable 28 1 read-write IRXER Ignore IPG GRXER 30 1 read-write IRXFCS Ignore RX FCS 26 1 read-write JFRAME Jumbo Frame Size 3 1 read-write LFERD Length Field Error Frame Discard 16 1 read-write MAXFS 1536 Maximum Frame Size 8 1 read-write MTIHEN Multicast Hash Enable 6 1 read-write NBC No Broadcast 5 1 read-write PEN Pause Enable 13 1 read-write RFCS Remove FCS 17 1 read-write RTY Retry Test 12 1 read-write RXBP Receive Bad Preamble 29 1 read-write RXBUFO Receive Buffer Offset 14 2 read-write RXCOEN Receive Checksum Offload Enable 24 1 read-write SPD Speed 0 1 read-write UNIHEN Unicast Hash Enable 7 1 read-write NCR Network Control Register 0x0 32 read-write n 0x0 0x0 BP Back pressure 8 1 read-write CLRSTAT Clear Statistics Registers 5 1 read-write ENPBPR Enable PFC Priority-based Pause Reception 16 1 read-write FNP Flush Next Packet 18 1 read-write INCSTAT Increment Statistics Registers 6 1 read-write LBL Loop Back Local 1 1 read-write MPE Management Port Enable 4 1 read-write RXEN Receive Enable 2 1 read-write SRTSM Store Receive Time Stamp to Memory 15 1 read-write THALT Transmit Halt 10 1 read-write TSTART Start Transmission 9 1 read-write TXEN Transmit Enable 3 1 read-write TXLPIEN Enable LPI Transmission 19 1 read-write TXPBPF Transmit PFC Priority-based Pause Frame 17 1 read-write TXPF Transmit Pause Frame 11 1 read-write TXZQPF Transmit Zero Quantum Pause Frame 12 1 read-write WESTAT Write Enable for Statistics Registers 7 1 read-write NSC 1588 Timer Nanosecond Comparison Register 0xDC 32 read-write n 0x0 0x0 NANOSEC 1588 Timer Nanosecond Comparison Value 0 22 read-write NSR Network Status Register 0x8 32 read-only n 0x0 0x0 IDLE PHY Management Logic Idle 2 1 read-only MDIO MDIO Input Status 1 1 read-only RXLPIS LPI Indication 7 1 read-only OFR Oversize Frames Received Register 0x188 32 read-only n 0x0 0x0 OFRX Oversized Frames Received 0 10 read-only ORHI Octets Received High Received Register 0x154 32 read-only n 0x0 0x0 RXO Received Octets 0 16 read-only ORLO Octets Received Low Received Register 0x150 32 read-only n 0x0 0x0 RXO Received Octets 0 32 read-only OTHI Octets Transmitted High Register 0x104 32 read-only n 0x0 0x0 TXO Transmitted Octets 0 16 read-only OTLO Octets Transmitted Low Register 0x100 32 read-only n 0x0 0x0 TXO Transmitted Octets 0 32 read-only PEFRN PTP Peer Event Frame Received Nanoseconds Register 0x1FC 32 read-only n 0x0 0x0 RUD Register Update 0 30 read-only PEFRSH PTP Peer Event Frame Received Seconds High Register 0xF4 32 read-only n 0x0 0x0 RUD Register Update 0 16 read-only PEFRSL PTP Peer Event Frame Received Seconds Low Register 0x1F8 32 read-only n 0x0 0x0 RUD Register Update 0 32 read-only PEFTN PTP Peer Event Frame Transmitted Nanoseconds Register 0x1F4 32 read-only n 0x0 0x0 RUD Register Update 0 30 read-only PEFTSH PTP Peer Event Frame Transmitted Seconds High Register 0xF0 32 read-only n 0x0 0x0 RUD Register Update 0 16 read-only PEFTSL PTP Peer Event Frame Transmitted Seconds Low Register 0x1F0 32 read-only n 0x0 0x0 RUD Register Update 0 32 read-only PFR Pause Frames Received Register 0x164 32 read-only n 0x0 0x0 PFRX Pause Frames Received Register 0 16 read-only PFT Pause Frames Transmitted Register 0x114 32 read-only n 0x0 0x0 PFTX Pause Frames Transmitted Register 0 16 read-only RBQB Receive Buffer Queue Base Address Register 0x18 32 read-write n 0x0 0x0 ADDR Receive Buffer Queue Base Address 2 30 read-write RJFML RX Jumbo Frame Max Length Register 0x48 32 read-write n 0x0 0x0 FML Frame Max Length 0 14 read-write ROE Receive Overrun Register 0x1A4 32 read-only n 0x0 0x0 RXOVR Receive Overruns 0 10 read-only RPQ Received Pause Quantum Register 0x38 32 read-only n 0x0 0x0 RPQ Received Pause Quantum 0 16 read-only RRE Receive Resource Errors Register 0x1A0 32 read-only n 0x0 0x0 RXRER Receive Resource Errors 0 18 read-only RSE Receive Symbol Errors Register 0x198 32 read-only n 0x0 0x0 RXSE Receive Symbol Errors 0 10 read-only RSR Receive Status Register 0x20 32 read-write n 0x0 0x0 BNA Buffer Not Available 0 1 read-write HNO HRESP Not OK 3 1 read-write REC Frame Received 1 1 read-write RXOVR Receive Overrun 2 1 read-write RXLPI Received LPI Transitions 0x270 32 read-only n 0x0 0x0 COUNT Count of RX LPI transitions (cleared on read) 0 16 read-only RXLPITIME Received LPI Time 0x274 32 read-only n 0x0 0x0 LPITIME Time in LPI (cleared on read) 0 24 read-only SAB1 Specific Address 1 Bottom Register 0x88 32 read-write n 0x0 0x0 ADDR Specific Address 1 0 32 read-write SAB2 Specific Address 2 Bottom Register 0x90 32 read-write n 0x0 0x0 ADDR Specific Address 2 0 32 read-write SAB3 Specific Address 3 Bottom Register 0x98 32 read-write n 0x0 0x0 ADDR Specific Address 3 0 32 read-write SAB4 Specific Address 4 Bottom Register 0xA0 32 read-write n 0x0 0x0 ADDR Specific Address 4 0 32 read-write SAMB1 Specific Address 1 Mask Bottom Register 0xC8 32 read-write n 0x0 0x0 ADDR Specific Address 1 Mask 0 32 read-write SAMT1 Specific Address 1 Mask Top Register 0xCC 32 read-write n 0x0 0x0 ADDR Specific Address 1 Mask 0 16 read-write SAT1 Specific Address 1 Top Register 0x8C 32 read-write n 0x0 0x0 ADDR Specific Address 1 0 16 read-write SAT2 Specific Address 2 Top Register 0x94 32 read-write n 0x0 0x0 ADDR Specific Address 2 0 16 read-write SAT3 Specific Address 3 Top Register 0x9C 32 read-write n 0x0 0x0 ADDR Specific Address 3 0 16 read-write SAT4 Specific Address 4 Top Register 0xA4 32 read-write n 0x0 0x0 ADDR Specific Address 4 0 16 read-write SCF Single Collision Frames Register 0x138 32 read-only n 0x0 0x0 SCOL Single Collision 0 18 read-only SCH 1588 Timer Second Comparison High Register 0xE4 32 read-write n 0x0 0x0 SEC 1588 Timer Second Comparison Value 0 16 read-write SCL 1588 Timer Second Comparison Low Register 0xE0 32 read-write n 0x0 0x0 SEC 1588 Timer Second Comparison Value 0 32 read-write SVLAN Stacked VLAN Register 0xC0 32 read-write n 0x0 0x0 ESVLAN Enable Stacked VLAN Processing Mode 31 1 read-write VLAN_TYPE User Defined VLAN_TYPE Field 0 16 read-write TA 1588 Timer Adjust Register 0x1D8 32 write-only n 0x0 0x0 ADJ Adjust 1588 Timer 31 1 write-only ITDT Increment/Decrement 0 30 write-only TBFR1023 512 to 1023 Byte Frames Received Register 0x178 32 read-only n 0x0 0x0 NFRX 512 to 1023 Byte Frames Received without Error 0 32 read-only TBFR127 65 to 127 Byte Frames Received Register 0x16C 32 read-only n 0x0 0x0 NFRX 65 to 127 Byte Frames Received without Error 0 32 read-only TBFR1518 1024 to 1518 Byte Frames Received Register 0x17C 32 read-only n 0x0 0x0 NFRX 1024 to 1518 Byte Frames Received without Error 0 32 read-only TBFR255 128 to 255 Byte Frames Received Register 0x170 32 read-only n 0x0 0x0 NFRX 128 to 255 Byte Frames Received without Error 0 32 read-only TBFR511 256 to 511 Byte Frames Received Register 0x174 32 read-only n 0x0 0x0 NFRX 256 to 511 Byte Frames Received without Error 0 32 read-only TBFT1023 512 to 1023 Byte Frames Transmitted Register 0x128 32 read-only n 0x0 0x0 NFTX 512 to 1023 Byte Frames Transmitted without Error 0 32 read-only TBFT127 65 to 127 Byte Frames Transmitted Register 0x11C 32 read-only n 0x0 0x0 NFTX 65 to 127 Byte Frames Transmitted without Error 0 32 read-only TBFT1518 1024 to 1518 Byte Frames Transmitted Register 0x12C 32 read-only n 0x0 0x0 NFTX 1024 to 1518 Byte Frames Transmitted without Error 0 32 read-only TBFT255 128 to 255 Byte Frames Transmitted Register 0x120 32 read-only n 0x0 0x0 NFTX 128 to 255 Byte Frames Transmitted without Error 0 32 read-only TBFT511 256 to 511 Byte Frames Transmitted Register 0x124 32 read-only n 0x0 0x0 NFTX 256 to 511 Byte Frames Transmitted without Error 0 32 read-only TBQB Transmit Buffer Queue Base Address Register 0x1C 32 read-write n 0x0 0x0 ADDR Transmit Buffer Queue Base Address 2 30 read-write TCE TCP Checksum Errors Register 0x1AC 32 read-only n 0x0 0x0 TCKER TCP Checksum Errors 0 8 read-only TI 1588 Timer Increment Register 0x1DC 32 read-write n 0x0 0x0 ACNS Alternative Count Nanoseconds 8 8 read-write CNS Count Nanoseconds 0 8 read-write NIT Number of Increments 16 8 read-write TIDM1 Type ID Match 1 Register 0xA8 32 read-write n 0x0 0x0 ENID1 Enable Copying of TID Matched Frames 31 1 read-write TID Type ID Match 1 0 16 read-write TIDM2 Type ID Match 2 Register 0xAC 32 read-write n 0x0 0x0 ENID2 Enable Copying of TID Matched Frames 31 1 read-write TID Type ID Match 2 0 16 read-write TIDM3 Type ID Match 3 Register 0xB0 32 read-write n 0x0 0x0 ENID3 Enable Copying of TID Matched Frames 31 1 read-write TID Type ID Match 3 0 16 read-write TIDM4 Type ID Match 4 Register 0xB4 32 read-write n 0x0 0x0 ENID4 Enable Copying of TID Matched Frames 31 1 read-write TID Type ID Match 4 0 16 read-write TISUBN 1588 Timer Increment Sub-nanoseconds Register 0x1BC 32 read-write n 0x0 0x0 LSBTIR Lower Significant Bits of Timer Increment Register 0 16 read-write TMXBFR 1519 to Maximum Byte Frames Received Register 0x180 32 read-only n 0x0 0x0 NFRX 1519 to Maximum Byte Frames Received without Error 0 32 read-only TN 1588 Timer Nanoseconds Register 0x1D4 32 read-write n 0x0 0x0 TNS Timer Count in Nanoseconds 0 30 read-write TPFCP Transmit PFC Pause Register 0xC4 32 read-write n 0x0 0x0 PEV Priority Enable Vector 0 8 read-write PQ Pause Quantum 8 8 read-write TPQ Transmit Pause Quantum Register 0x3C 32 read-write n 0x0 0x0 TPQ Transmit Pause Quantum 0 16 read-write TSH 1588 Timer Seconds High Register 0x1C0 32 read-write n 0x0 0x0 TCS Timer Count in Seconds 0 16 read-write TSL 1588 Timer Seconds Low Register 0x1D0 32 read-write n 0x0 0x0 TCS Timer Count in Seconds 0 32 read-write TSR Transmit Status Register 0x14 32 read-write n 0x0 0x0 COL Collision Occurred 1 1 read-write HRESP HRESP Not OK 8 1 read-write RLE Retry Limit Exceeded 2 1 read-write TFC Transmit Frame Corruption Due to AHB Error 4 1 read-write TXCOMP Transmit Complete 5 1 read-write TXGO Transmit Go 3 1 read-write UBR Used Bit Read 0 1 read-write UND Transmit Underrun 6 1 read-write TUR Transmit Underruns Register 0x134 32 read-only n 0x0 0x0 TXUNR Transmit Underruns 0 10 read-only TXLPI Transmit LPI Transitions 0x278 32 read-only n 0x0 0x0 COUNT Count of LPI transitions (cleared on read) 0 16 read-only TXLPITIME Transmit LPI Time 0x27C 32 read-only n 0x0 0x0 LPITIME Time in LPI (cleared on read) 0 24 read-only UCE UDP Checksum Errors Register 0x1B0 32 read-only n 0x0 0x0 UCKER UDP Checksum Errors 0 8 read-only UFR Undersize Frames Received Register 0x184 32 read-only n 0x0 0x0 UFRX Undersize Frames Received 0 10 read-only UR User Register 0xC 32 read-write n 0x0 0x0 RMII Reduced MII Mode 0 1 read-write WOL Wake on LAN Register 0xB8 32 read-write n 0x0 0x0 ARP ARP Request IP Address 17 1 read-write IP ARP Request IP Address 0 16 read-write MAG Magic Packet Event Enable 16 1 read-write MTI Multicast Hash Event Enable 19 1 read-write SA1 Specific Address Register 1 Event Enable 18 1 read-write GMAC1 Gigabit Ethernet MAC 1 GMAC 0x0 0x0 0x50 registers n GMAC1 55 AE Alignment Errors Register 0x19C 32 read-only n 0x0 0x0 AER Alignment Errors 0 10 read-only BCFR Broadcast Frames Received Register 0x15C 32 read-only n 0x0 0x0 BFRX Broadcast Frames Received without Error 0 32 read-only BCFT Broadcast Frames Transmitted Register 0x10C 32 read-only n 0x0 0x0 BFTX Broadcast Frames Transmitted without Error 0 32 read-only BFR64 64 Byte Frames Received Register 0x168 32 read-only n 0x0 0x0 NFRX 64 Byte Frames Received without Error 0 32 read-only BFT64 64 Byte Frames Transmitted Register 0x118 32 read-only n 0x0 0x0 NFTX 64 Byte Frames Transmitted without Error 0 32 read-only CSE Carrier Sense Errors Register 0x14C 32 read-only n 0x0 0x0 CSR Carrier Sense Error 0 10 read-only DCFGR DMA Configuration Register 0x10 32 read-write n 0x0 0x0 DRBS DMA Receive Buffer Size 16 8 read-write ESMA Endian Swap Mode Enable for Management Descriptor Accesses 6 1 read-write ESPA Endian Swap Mode Enable for Packet Data Accesses 7 1 read-write FBLDO Fixed Burst Length for DMA Data Operations: 0 5 read-write SINGLE 00001: Always use SINGLE AHB bursts 0x1 INCR16 1xxxx: Attempt to use INCR16 AHB bursts 0x10 INCR4 001xx: Attempt to use INCR4 AHB bursts (Default) 0x4 INCR8 01xxx: Attempt to use INCR8 AHB bursts 0x8 DTF Deferred Transmission Frames Register 0x148 32 read-only n 0x0 0x0 DEFT Deferred Transmission 0 18 read-only EC Excessive Collisions Register 0x140 32 read-only n 0x0 0x0 XCOL Excessive Collisions 0 10 read-only EFRN PTP Event Frame Received Nanoseconds Register 0x1EC 32 read-only n 0x0 0x0 RUD Register Update 0 30 read-only EFRSH PTP Event Frame Received Seconds High Register 0xEC 32 read-only n 0x0 0x0 RUD Register Update 0 16 read-only EFRSL PTP Event Frame Received Seconds Low Register 0x1E8 32 read-only n 0x0 0x0 RUD Register Update 0 32 read-only EFTN PTP Event Frame Transmitted Nanoseconds Register 0x1E4 32 read-only n 0x0 0x0 RUD Register Update 0 30 read-only EFTSH PTP Event Frame Transmitted Seconds High Register 0xE8 32 read-only n 0x0 0x0 RUD Register Update 0 16 read-only EFTSL PTP Event Frame Transmitted Seconds Low Register 0x1E0 32 read-only n 0x0 0x0 RUD Register Update 0 32 read-only FCSE Frame Check Sequence Errors Register 0x190 32 read-only n 0x0 0x0 FCKR Frame Check Sequence Errors 0 10 read-only FR Frames Received Register 0x158 32 read-only n 0x0 0x0 FRX Frames Received without Error 0 32 read-only FT Frames Transmitted Register 0x108 32 read-only n 0x0 0x0 FTX Frames Transmitted without Error 0 32 read-only GTBFT1518 Greater Than 1518 Byte Frames Transmitted Register 0x130 32 read-only n 0x0 0x0 NFTX Greater than 1518 Byte Frames Transmitted without Error 0 32 read-only HRB Hash Register Bottom 0x80 32 read-write n 0x0 0x0 ADDR Hash Address 0 32 read-write HRT Hash Register Top 0x84 32 read-write n 0x0 0x0 ADDR Hash Address 0 32 read-write IDR Interrupt Disable Register 0x2C 32 write-only n 0x0 0x0 DRQFR PTP Delay Request Frame Received 18 1 write-only DRQFT PTP Delay Request Frame Transmitted 20 1 write-only EXINT External Interrupt 15 1 write-only HRESP HRESP Not OK 11 1 write-only MFS Management Frame Sent 0 1 write-only PDRQFR PDelay Request Frame Received 22 1 write-only PDRQFT PDelay Request Frame Transmitted 24 1 write-only PDRSFR PDelay Response Frame Received 23 1 write-only PDRSFT PDelay Response Frame Transmitted 25 1 write-only PFNZ Pause Frame with Non-zero Pause Quantum Received 12 1 write-only PFTR Pause Frame Transmitted 14 1 write-only PTZ Pause Time Zero 13 1 write-only RCOMP Receive Complete 1 1 write-only RLEX Retry Limit Exceeded or Late Collision 5 1 write-only ROVR Receive Overrun 10 1 write-only RXLPISBC Enable RX LPI Indication 27 1 write-only RXUBR RX Used Bit Read 2 1 write-only SFR PTP Sync Frame Received 19 1 write-only SFT PTP Sync Frame Transmitted 21 1 write-only SRI TSU Seconds Register Increment 26 1 write-only TCOMP Transmit Complete 7 1 write-only TFC Transmit Frame Corruption Due to AHB Error 6 1 write-only TSUTIMCOMP TSU Timer Comparison 29 1 write-only TUR Transmit Underrun 4 1 write-only TXUBR TX Used Bit Read 3 1 write-only WOL Wake On LAN 28 1 write-only IER Interrupt Enable Register 0x28 32 write-only n 0x0 0x0 DRQFR PTP Delay Request Frame Received 18 1 write-only DRQFT PTP Delay Request Frame Transmitted 20 1 write-only EXINT External Interrupt 15 1 write-only HRESP HRESP Not OK 11 1 write-only MFS Management Frame Sent 0 1 write-only PDRQFR PDelay Request Frame Received 22 1 write-only PDRQFT PDelay Request Frame Transmitted 24 1 write-only PDRSFR PDelay Response Frame Received 23 1 write-only PDRSFT PDelay Response Frame Transmitted 25 1 write-only PFNZ Pause Frame with Non-zero Pause Quantum Received 12 1 write-only PFTR Pause Frame Transmitted 14 1 write-only PTZ Pause Time Zero 13 1 write-only RCOMP Receive Complete 1 1 write-only RLEX Retry Limit Exceeded or Late Collision 5 1 write-only ROVR Receive Overrun 10 1 write-only RXLPISBC Enable RX LPI Indication 27 1 write-only RXUBR RX Used Bit Read 2 1 write-only SFR PTP Sync Frame Received 19 1 write-only SFT PTP Sync Frame Transmitted 21 1 write-only SRI TSU Seconds Register Increment 26 1 write-only TCOMP Transmit Complete 7 1 write-only TFC Transmit Frame Corruption Due to AHB Error 6 1 write-only TSUTIMCOMP TSU Timer Comparison 29 1 write-only TUR Transmit Underrun 4 1 write-only TXUBR TX Used Bit Read 3 1 write-only WOL Wake On LAN 28 1 write-only IHCE IP Header Checksum Errors Register 0x1A8 32 read-only n 0x0 0x0 HCKER IP Header Checksum Errors 0 8 read-only IMR Interrupt Mask Register 0x30 32 read-write n 0x0 0x0 DRQFR PTP Delay Request Frame Received 18 1 read-write DRQFT PTP Delay Request Frame Transmitted 20 1 read-write EXINT External Interrupt 15 1 read-write HRESP HRESP Not OK 11 1 read-write MFS Management Frame Sent 0 1 read-write PDRQFR PDelay Request Frame Received 22 1 read-write PDRQFT PDelay Request Frame Transmitted 24 1 read-write PDRSFR PDelay Response Frame Received 23 1 read-write PDRSFT PDelay Response Frame Transmitted 25 1 read-write PFNZ Pause Frame with Non-zero Pause Quantum Received 12 1 read-write PFTR Pause Frame Transmitted 14 1 read-write PTZ Pause Time Zero 13 1 read-write RCOMP Receive Complete 1 1 read-write RLEX Retry Limit Exceeded 5 1 read-write ROVR Receive Overrun 10 1 read-write RXLPISBC Enable RX LPI Indication 27 1 read-write RXUBR RX Used Bit Read 2 1 read-write SFR PTP Sync Frame Received 19 1 read-write SFT PTP Sync Frame Transmitted 21 1 read-write SRI TSU Seconds Register Increment 26 1 read-write TCOMP Transmit Complete 7 1 read-write TFC Transmit Frame Corruption Due to AHB Error 6 1 read-write TSUTIMCOMP TSU Timer Comparison 29 1 read-write TUR Transmit Underrun 4 1 read-write TXUBR TX Used Bit Read 3 1 read-write WOL Wake On LAN 28 1 read-write IPGS IPG Stretch Register 0xBC 32 read-write n 0x0 0x0 FL Frame Length 0 16 read-write ISR Interrupt Status Register 0x24 32 read-only n 0x0 0x0 DRQFR PTP Delay Request Frame Received 18 1 read-only DRQFT PTP Delay Request Frame Transmitted 20 1 read-only HRESP HRESP Not OK 11 1 read-only MFS Management Frame Sent 0 1 read-only PDRQFR PDelay Request Frame Received 22 1 read-only PDRQFT PDelay Request Frame Transmitted 24 1 read-only PDRSFR PDelay Response Frame Received 23 1 read-only PDRSFT PDelay Response Frame Transmitted 25 1 read-only PFNZ Pause Frame with Non-zero Pause Quantum Received 12 1 read-only PFTR Pause Frame Transmitted 14 1 read-only PTZ Pause Time Zero 13 1 read-only RCOMP Receive Complete 1 1 read-only RLEX Retry Limit Exceeded 5 1 read-only ROVR Receive Overrun 10 1 read-only RXLPISBC Receive LPI indication Status Bit Change 27 1 read-only RXUBR RX Used Bit Read 2 1 read-only SFR PTP Sync Frame Received 19 1 read-only SFT PTP Sync Frame Transmitted 21 1 read-only SRI TSU Seconds Register Increment 26 1 read-only TCOMP Transmit Complete 7 1 read-only TFC Transmit Frame Corruption Due to AHB Error 6 1 read-only TSUTIMCOMP TSU Timer Comparison 29 1 read-only TUR Transmit Underrun 4 1 read-only TXUBR TX Used Bit Read 3 1 read-only WOL Wake On LAN 28 1 read-only JR Jabbers Received Register 0x18C 32 read-only n 0x0 0x0 JRX Jabbers Received 0 10 read-only LC Late Collisions Register 0x144 32 read-only n 0x0 0x0 LCOL Late Collisions 0 10 read-only LFFE Length Field Frame Errors Register 0x194 32 read-only n 0x0 0x0 LFER Length Field Frame Errors 0 10 read-only MAN PHY Maintenance Register 0x34 32 read-write n 0x0 0x0 CLTTO Clause 22 Operation 30 1 read-write DATA PHY Data 0 16 read-write OP Operation 28 2 read-write PHYA PHY Address 23 5 read-write REGA Register Address 18 5 read-write WTN Write Ten 16 2 read-write WZO Write ZERO 31 1 read-write MCF Multiple Collision Frames Register 0x13C 32 read-only n 0x0 0x0 MCOL Multiple Collision 0 18 read-only MFR Multicast Frames Received Register 0x160 32 read-only n 0x0 0x0 MFRX Multicast Frames Received without Error 0 32 read-only MFT Multicast Frames Transmitted Register 0x110 32 read-only n 0x0 0x0 MFTX Multicast Frames Transmitted without Error 0 32 read-only NCFGR Network Configuration Register 0x4 32 read-write n 0x0 0x0 CAF Copy All Frames 4 1 read-write CLK MDC CLock Division 18 3 read-write MCK_8 MCK divided by 8 (MCK up to 20 MHz) 0x0 MCK_16 MCK divided by 16 (MCK up to 40 MHz) 0x1 MCK_32 MCK divided by 32 (MCK up to 80 MHz) 0x2 MCK_48 MCK divided by 48 (MCK up to 120 MHz) 0x3 MCK_64 MCK divided by 64 (MCK up to 160 MHz) 0x4 MCK_96 MCK divided by 96 (MCK up to 240 MHz) 0x5 DBW Data Bus Width 21 2 read-write DCPF Disable Copy of Pause Frames 23 1 read-write DNVLAN Discard Non-VLAN FRAMES 2 1 read-write EFRHD Enable Frames Received in Half Duplex 25 1 read-write FD Full Duplex 1 1 read-write IPGSEN IP Stretch Enable 28 1 read-write IRXER Ignore IPG GRXER 30 1 read-write IRXFCS Ignore RX FCS 26 1 read-write JFRAME Jumbo Frame Size 3 1 read-write LFERD Length Field Error Frame Discard 16 1 read-write MAXFS 1536 Maximum Frame Size 8 1 read-write MTIHEN Multicast Hash Enable 6 1 read-write NBC No Broadcast 5 1 read-write PEN Pause Enable 13 1 read-write RFCS Remove FCS 17 1 read-write RTY Retry Test 12 1 read-write RXBP Receive Bad Preamble 29 1 read-write RXBUFO Receive Buffer Offset 14 2 read-write RXCOEN Receive Checksum Offload Enable 24 1 read-write SPD Speed 0 1 read-write UNIHEN Unicast Hash Enable 7 1 read-write NCR Network Control Register 0x0 32 read-write n 0x0 0x0 BP Back pressure 8 1 read-write CLRSTAT Clear Statistics Registers 5 1 read-write ENPBPR Enable PFC Priority-based Pause Reception 16 1 read-write FNP Flush Next Packet 18 1 read-write INCSTAT Increment Statistics Registers 6 1 read-write LBL Loop Back Local 1 1 read-write MPE Management Port Enable 4 1 read-write RXEN Receive Enable 2 1 read-write SRTSM Store Receive Time Stamp to Memory 15 1 read-write THALT Transmit Halt 10 1 read-write TSTART Start Transmission 9 1 read-write TXEN Transmit Enable 3 1 read-write TXLPIEN Enable LPI Transmission 19 1 read-write TXPBPF Transmit PFC Priority-based Pause Frame 17 1 read-write TXPF Transmit Pause Frame 11 1 read-write TXZQPF Transmit Zero Quantum Pause Frame 12 1 read-write WESTAT Write Enable for Statistics Registers 7 1 read-write NSC 1588 Timer Nanosecond Comparison Register 0xDC 32 read-write n 0x0 0x0 NANOSEC 1588 Timer Nanosecond Comparison Value 0 22 read-write NSR Network Status Register 0x8 32 read-only n 0x0 0x0 IDLE PHY Management Logic Idle 2 1 read-only MDIO MDIO Input Status 1 1 read-only RXLPIS LPI Indication 7 1 read-only OFR Oversize Frames Received Register 0x188 32 read-only n 0x0 0x0 OFRX Oversized Frames Received 0 10 read-only ORHI Octets Received High Received Register 0x154 32 read-only n 0x0 0x0 RXO Received Octets 0 16 read-only ORLO Octets Received Low Received Register 0x150 32 read-only n 0x0 0x0 RXO Received Octets 0 32 read-only OTHI Octets Transmitted High Register 0x104 32 read-only n 0x0 0x0 TXO Transmitted Octets 0 16 read-only OTLO Octets Transmitted Low Register 0x100 32 read-only n 0x0 0x0 TXO Transmitted Octets 0 32 read-only PEFRN PTP Peer Event Frame Received Nanoseconds Register 0x1FC 32 read-only n 0x0 0x0 RUD Register Update 0 30 read-only PEFRSH PTP Peer Event Frame Received Seconds High Register 0xF4 32 read-only n 0x0 0x0 RUD Register Update 0 16 read-only PEFRSL PTP Peer Event Frame Received Seconds Low Register 0x1F8 32 read-only n 0x0 0x0 RUD Register Update 0 32 read-only PEFTN PTP Peer Event Frame Transmitted Nanoseconds Register 0x1F4 32 read-only n 0x0 0x0 RUD Register Update 0 30 read-only PEFTSH PTP Peer Event Frame Transmitted Seconds High Register 0xF0 32 read-only n 0x0 0x0 RUD Register Update 0 16 read-only PEFTSL PTP Peer Event Frame Transmitted Seconds Low Register 0x1F0 32 read-only n 0x0 0x0 RUD Register Update 0 32 read-only PFR Pause Frames Received Register 0x164 32 read-only n 0x0 0x0 PFRX Pause Frames Received Register 0 16 read-only PFT Pause Frames Transmitted Register 0x114 32 read-only n 0x0 0x0 PFTX Pause Frames Transmitted Register 0 16 read-only RBQB Receive Buffer Queue Base Address Register 0x18 32 read-write n 0x0 0x0 ADDR Receive Buffer Queue Base Address 2 30 read-write RJFML RX Jumbo Frame Max Length Register 0x48 32 read-write n 0x0 0x0 FML Frame Max Length 0 14 read-write ROE Receive Overrun Register 0x1A4 32 read-only n 0x0 0x0 RXOVR Receive Overruns 0 10 read-only RPQ Received Pause Quantum Register 0x38 32 read-only n 0x0 0x0 RPQ Received Pause Quantum 0 16 read-only RRE Receive Resource Errors Register 0x1A0 32 read-only n 0x0 0x0 RXRER Receive Resource Errors 0 18 read-only RSE Receive Symbol Errors Register 0x198 32 read-only n 0x0 0x0 RXSE Receive Symbol Errors 0 10 read-only RSR Receive Status Register 0x20 32 read-write n 0x0 0x0 BNA Buffer Not Available 0 1 read-write HNO HRESP Not OK 3 1 read-write REC Frame Received 1 1 read-write RXOVR Receive Overrun 2 1 read-write RXLPI Received LPI Transitions 0x270 32 read-only n 0x0 0x0 COUNT Count of RX LPI transitions (cleared on read) 0 16 read-only RXLPITIME Received LPI Time 0x274 32 read-only n 0x0 0x0 LPITIME Time in LPI (cleared on read) 0 24 read-only SAB1 Specific Address 1 Bottom Register 0x88 32 read-write n 0x0 0x0 ADDR Specific Address 1 0 32 read-write SAB2 Specific Address 2 Bottom Register 0x90 32 read-write n 0x0 0x0 ADDR Specific Address 2 0 32 read-write SAB3 Specific Address 3 Bottom Register 0x98 32 read-write n 0x0 0x0 ADDR Specific Address 3 0 32 read-write SAB4 Specific Address 4 Bottom Register 0xA0 32 read-write n 0x0 0x0 ADDR Specific Address 4 0 32 read-write SAMB1 Specific Address 1 Mask Bottom Register 0xC8 32 read-write n 0x0 0x0 ADDR Specific Address 1 Mask 0 32 read-write SAMT1 Specific Address 1 Mask Top Register 0xCC 32 read-write n 0x0 0x0 ADDR Specific Address 1 Mask 0 16 read-write SAT1 Specific Address 1 Top Register 0x8C 32 read-write n 0x0 0x0 ADDR Specific Address 1 0 16 read-write SAT2 Specific Address 2 Top Register 0x94 32 read-write n 0x0 0x0 ADDR Specific Address 2 0 16 read-write SAT3 Specific Address 3 Top Register 0x9C 32 read-write n 0x0 0x0 ADDR Specific Address 3 0 16 read-write SAT4 Specific Address 4 Top Register 0xA4 32 read-write n 0x0 0x0 ADDR Specific Address 4 0 16 read-write SCF Single Collision Frames Register 0x138 32 read-only n 0x0 0x0 SCOL Single Collision 0 18 read-only SCH 1588 Timer Second Comparison High Register 0xE4 32 read-write n 0x0 0x0 SEC 1588 Timer Second Comparison Value 0 16 read-write SCL 1588 Timer Second Comparison Low Register 0xE0 32 read-write n 0x0 0x0 SEC 1588 Timer Second Comparison Value 0 32 read-write SVLAN Stacked VLAN Register 0xC0 32 read-write n 0x0 0x0 ESVLAN Enable Stacked VLAN Processing Mode 31 1 read-write VLAN_TYPE User Defined VLAN_TYPE Field 0 16 read-write TA 1588 Timer Adjust Register 0x1D8 32 write-only n 0x0 0x0 ADJ Adjust 1588 Timer 31 1 write-only ITDT Increment/Decrement 0 30 write-only TBFR1023 512 to 1023 Byte Frames Received Register 0x178 32 read-only n 0x0 0x0 NFRX 512 to 1023 Byte Frames Received without Error 0 32 read-only TBFR127 65 to 127 Byte Frames Received Register 0x16C 32 read-only n 0x0 0x0 NFRX 65 to 127 Byte Frames Received without Error 0 32 read-only TBFR1518 1024 to 1518 Byte Frames Received Register 0x17C 32 read-only n 0x0 0x0 NFRX 1024 to 1518 Byte Frames Received without Error 0 32 read-only TBFR255 128 to 255 Byte Frames Received Register 0x170 32 read-only n 0x0 0x0 NFRX 128 to 255 Byte Frames Received without Error 0 32 read-only TBFR511 256 to 511 Byte Frames Received Register 0x174 32 read-only n 0x0 0x0 NFRX 256 to 511 Byte Frames Received without Error 0 32 read-only TBFT1023 512 to 1023 Byte Frames Transmitted Register 0x128 32 read-only n 0x0 0x0 NFTX 512 to 1023 Byte Frames Transmitted without Error 0 32 read-only TBFT127 65 to 127 Byte Frames Transmitted Register 0x11C 32 read-only n 0x0 0x0 NFTX 65 to 127 Byte Frames Transmitted without Error 0 32 read-only TBFT1518 1024 to 1518 Byte Frames Transmitted Register 0x12C 32 read-only n 0x0 0x0 NFTX 1024 to 1518 Byte Frames Transmitted without Error 0 32 read-only TBFT255 128 to 255 Byte Frames Transmitted Register 0x120 32 read-only n 0x0 0x0 NFTX 128 to 255 Byte Frames Transmitted without Error 0 32 read-only TBFT511 256 to 511 Byte Frames Transmitted Register 0x124 32 read-only n 0x0 0x0 NFTX 256 to 511 Byte Frames Transmitted without Error 0 32 read-only TBQB Transmit Buffer Queue Base Address Register 0x1C 32 read-write n 0x0 0x0 ADDR Transmit Buffer Queue Base Address 2 30 read-write TCE TCP Checksum Errors Register 0x1AC 32 read-only n 0x0 0x0 TCKER TCP Checksum Errors 0 8 read-only TI 1588 Timer Increment Register 0x1DC 32 read-write n 0x0 0x0 ACNS Alternative Count Nanoseconds 8 8 read-write CNS Count Nanoseconds 0 8 read-write NIT Number of Increments 16 8 read-write TIDM1 Type ID Match 1 Register 0xA8 32 read-write n 0x0 0x0 ENID1 Enable Copying of TID Matched Frames 31 1 read-write TID Type ID Match 1 0 16 read-write TIDM2 Type ID Match 2 Register 0xAC 32 read-write n 0x0 0x0 ENID2 Enable Copying of TID Matched Frames 31 1 read-write TID Type ID Match 2 0 16 read-write TIDM3 Type ID Match 3 Register 0xB0 32 read-write n 0x0 0x0 ENID3 Enable Copying of TID Matched Frames 31 1 read-write TID Type ID Match 3 0 16 read-write TIDM4 Type ID Match 4 Register 0xB4 32 read-write n 0x0 0x0 ENID4 Enable Copying of TID Matched Frames 31 1 read-write TID Type ID Match 4 0 16 read-write TISUBN 1588 Timer Increment Sub-nanoseconds Register 0x1BC 32 read-write n 0x0 0x0 LSBTIR Lower Significant Bits of Timer Increment Register 0 16 read-write TMXBFR 1519 to Maximum Byte Frames Received Register 0x180 32 read-only n 0x0 0x0 NFRX 1519 to Maximum Byte Frames Received without Error 0 32 read-only TN 1588 Timer Nanoseconds Register 0x1D4 32 read-write n 0x0 0x0 TNS Timer Count in Nanoseconds 0 30 read-write TPFCP Transmit PFC Pause Register 0xC4 32 read-write n 0x0 0x0 PEV Priority Enable Vector 0 8 read-write PQ Pause Quantum 8 8 read-write TPQ Transmit Pause Quantum Register 0x3C 32 read-write n 0x0 0x0 TPQ Transmit Pause Quantum 0 16 read-write TSH 1588 Timer Seconds High Register 0x1C0 32 read-write n 0x0 0x0 TCS Timer Count in Seconds 0 16 read-write TSL 1588 Timer Seconds Low Register 0x1D0 32 read-write n 0x0 0x0 TCS Timer Count in Seconds 0 32 read-write TSR Transmit Status Register 0x14 32 read-write n 0x0 0x0 COL Collision Occurred 1 1 read-write HRESP HRESP Not OK 8 1 read-write RLE Retry Limit Exceeded 2 1 read-write TFC Transmit Frame Corruption Due to AHB Error 4 1 read-write TXCOMP Transmit Complete 5 1 read-write TXGO Transmit Go 3 1 read-write UBR Used Bit Read 0 1 read-write UND Transmit Underrun 6 1 read-write TUR Transmit Underruns Register 0x134 32 read-only n 0x0 0x0 TXUNR Transmit Underruns 0 10 read-only TXLPI Transmit LPI Transitions 0x278 32 read-only n 0x0 0x0 COUNT Count of LPI transitions (cleared on read) 0 16 read-only TXLPITIME Transmit LPI Time 0x27C 32 read-only n 0x0 0x0 LPITIME Time in LPI (cleared on read) 0 24 read-only UCE UDP Checksum Errors Register 0x1B0 32 read-only n 0x0 0x0 UCKER UDP Checksum Errors 0 8 read-only UFR Undersize Frames Received Register 0x184 32 read-only n 0x0 0x0 UFRX Undersize Frames Received 0 10 read-only UR User Register 0xC 32 read-write n 0x0 0x0 RMII Reduced MII Mode 0 1 read-write WOL Wake on LAN Register 0xB8 32 read-write n 0x0 0x0 ARP ARP Request IP Address 17 1 read-write IP ARP Request IP Address 0 16 read-write MAG Magic Packet Event Enable 16 1 read-write MTI Multicast Hash Event Enable 19 1 read-write SA1 Specific Address Register 1 Event Enable 18 1 read-write HSMC Static Memory Controller EBI 0x0 0x0 0x50 registers n ADDR NFC Address Cycle Zero Register 0x18 32 read-write n 0x0 0x0 ADDR_CYCLE0 NAND Flash Array Address Cycle 0 0 8 read-write BANK Bank Address Register 0x1C 32 read-write n 0x0 0x0 BANK Bank Identifier 0 1 read-write CFG NFC Configuration Register 0x0 32 read-write n 0x0 0x0 DTOCYC Data Timeout Cycle Number 16 4 read-write DTOMUL Data Timeout Multiplier 20 3 read-write X1 DTOCYC 0x0 X16 DTOCYC x 16 0x1 X128 DTOCYC x 128 0x2 X256 DTOCYC x 256 0x3 X1024 DTOCYC x 1024 0x4 X4096 DTOCYC x 4096 0x5 X65536 DTOCYC x 65536 0x6 X1048576 DTOCYC x 1048576 0x7 EDGECTRL Rising/Falling Edge Detection Control 12 1 read-write NFCSPARESIZE NAND Flash Spare Area Size Retrieved by the Host Controller 24 7 read-write PAGESIZE Page Size of the NAND Flash Device 0 3 read-write PS512 Main area 512 bytes 0x0 PS1024 Main area 1024 bytes 0x1 PS2048 Main area 2048 bytes 0x2 PS4096 Main area 4096 bytes 0x3 PS8192 Main area 8192 bytes 0x4 RBEDGE Ready/Busy Signal Edge Detection 13 1 read-write RSPARE Read Spare Area 9 1 read-write WSPARE Write Spare Area 8 1 read-write CTRL NFC Control Register 0x4 32 write-only n 0x0 0x0 NFCDIS NAND Flash Controller Disable 1 1 write-only NFCEN NAND Flash Controller Enable 0 1 write-only CYCLE0 Cycle Register (CS_number = 0) 0x608 32 read-write n 0x0 0x0 NRD_CYCLE Total Read Cycle Length 16 9 read-write NWE_CYCLE Total Write Cycle Length 0 9 read-write CYCLE1 Cycle Register (CS_number = 1) 0x61C 32 read-write n 0x0 0x0 NRD_CYCLE Total Read Cycle Length 16 9 read-write NWE_CYCLE Total Write Cycle Length 0 9 read-write CYCLE2 Cycle Register (CS_number = 2) 0x630 32 read-write n 0x0 0x0 NRD_CYCLE Total Read Cycle Length 16 9 read-write NWE_CYCLE Total Write Cycle Length 0 9 read-write CYCLE3 Cycle Register (CS_number = 3) 0x644 32 read-write n 0x0 0x0 NRD_CYCLE Total Read Cycle Length 16 9 read-write NWE_CYCLE Total Write Cycle Length 0 9 read-write ELCFG PMECC Error Location Configuration Register 0x500 32 read-write n 0x0 0x0 ERRNUM Number of Errors 16 5 read-write SECTORSZ Sector Size 0 1 read-write ELDIS PMECC Error Location Disable Register 0x50C 32 write-only n 0x0 0x0 DIS Disable Error Location Engine 0 1 write-only ELEN PMECC Error Location Enable Register 0x508 32 write-only n 0x0 0x0 ENINIT Error Location Enable 0 14 write-only ELIDR PMECC Error Location Interrupt Disable Register 0x518 32 write-only n 0x0 0x0 DONE Computation Terminated Interrupt Disable 0 1 write-only ELIER PMECC Error Location Interrupt Enable register 0x514 32 write-only n 0x0 0x0 DONE Computation Terminated Interrupt Enable 0 1 write-only ELIMR PMECC Error Location Interrupt Mask Register 0x51C 32 read-only n 0x0 0x0 DONE Computation Terminated Interrupt Mask 0 1 read-only ELISR PMECC Error Location Interrupt Status Register 0x520 32 read-only n 0x0 0x0 DONE Computation Terminated Interrupt Status 0 1 read-only ERR_CNT Error Counter value 8 5 read-only ELPRIM PMECC Error Location Primitive Register 0x504 32 read-only n 0x0 0x0 PRIMITIV Primitive Polynomial 0 16 read-only ELSR PMECC Error Location Status Register 0x510 32 read-only n 0x0 0x0 BUSY Error Location Engine Busy 0 1 read-only ERRLOC0 PMECC Error Location 0 Register 0x58C 32 read-only n ERRLOCN Error Position within the Set {sector area, spare area} 0 14 read-only ERRLOC1 PMECC Error Location 0 Register 0x590 32 read-only n ERRLOCN Error Position within the Set {sector area, spare area} 0 14 read-only ERRLOC10 PMECC Error Location 0 Register 0x5B4 32 read-only n ERRLOCN Error Position within the Set {sector area, spare area} 0 14 read-only ERRLOC11 PMECC Error Location 0 Register 0x5B8 32 read-only n ERRLOCN Error Position within the Set {sector area, spare area} 0 14 read-only ERRLOC12 PMECC Error Location 0 Register 0x5BC 32 read-only n ERRLOCN Error Position within the Set {sector area, spare area} 0 14 read-only ERRLOC13 PMECC Error Location 0 Register 0x5C0 32 read-only n ERRLOCN Error Position within the Set {sector area, spare area} 0 14 read-only ERRLOC14 PMECC Error Location 0 Register 0x5C4 32 read-only n ERRLOCN Error Position within the Set {sector area, spare area} 0 14 read-only ERRLOC15 PMECC Error Location 0 Register 0x5C8 32 read-only n ERRLOCN Error Position within the Set {sector area, spare area} 0 14 read-only ERRLOC16 PMECC Error Location 0 Register 0x5CC 32 read-only n ERRLOCN Error Position within the Set {sector area, spare area} 0 14 read-only ERRLOC17 PMECC Error Location 0 Register 0x5D0 32 read-only n ERRLOCN Error Position within the Set {sector area, spare area} 0 14 read-only ERRLOC18 PMECC Error Location 0 Register 0x5D4 32 read-only n ERRLOCN Error Position within the Set {sector area, spare area} 0 14 read-only ERRLOC19 PMECC Error Location 0 Register 0x5D8 32 read-only n ERRLOCN Error Position within the Set {sector area, spare area} 0 14 read-only ERRLOC2 PMECC Error Location 0 Register 0x594 32 read-only n ERRLOCN Error Position within the Set {sector area, spare area} 0 14 read-only ERRLOC20 PMECC Error Location 0 Register 0x5DC 32 read-only n ERRLOCN Error Position within the Set {sector area, spare area} 0 14 read-only ERRLOC21 PMECC Error Location 0 Register 0x5E0 32 read-only n ERRLOCN Error Position within the Set {sector area, spare area} 0 14 read-only ERRLOC22 PMECC Error Location 0 Register 0x5E4 32 read-only n ERRLOCN Error Position within the Set {sector area, spare area} 0 14 read-only ERRLOC23 PMECC Error Location 0 Register 0x5E8 32 read-only n ERRLOCN Error Position within the Set {sector area, spare area} 0 14 read-only ERRLOC3 PMECC Error Location 0 Register 0x598 32 read-only n ERRLOCN Error Position within the Set {sector area, spare area} 0 14 read-only ERRLOC4 PMECC Error Location 0 Register 0x59C 32 read-only n ERRLOCN Error Position within the Set {sector area, spare area} 0 14 read-only ERRLOC5 PMECC Error Location 0 Register 0x5A0 32 read-only n ERRLOCN Error Position within the Set {sector area, spare area} 0 14 read-only ERRLOC6 PMECC Error Location 0 Register 0x5A4 32 read-only n ERRLOCN Error Position within the Set {sector area, spare area} 0 14 read-only ERRLOC7 PMECC Error Location 0 Register 0x5A8 32 read-only n ERRLOCN Error Position within the Set {sector area, spare area} 0 14 read-only ERRLOC8 PMECC Error Location 0 Register 0x5AC 32 read-only n ERRLOCN Error Position within the Set {sector area, spare area} 0 14 read-only ERRLOC9 PMECC Error Location 0 Register 0x5B0 32 read-only n ERRLOCN Error Position within the Set {sector area, spare area} 0 14 read-only ERRLOC[0] PMECC Error Location 0 Register 0xB18 32 read-only n 0x0 0x0 ERRLOCN Error Position within the Set {sector area, spare area} 0 14 read-only ERRLOC[10] PMECC Error Location 0 Register 0x436C 32 read-only n 0x0 0x0 ERRLOCN Error Position within the Set {sector area, spare area} 0 14 read-only ERRLOC[11] PMECC Error Location 0 Register 0x4924 32 read-only n 0x0 0x0 ERRLOCN Error Position within the Set {sector area, spare area} 0 14 read-only ERRLOC[12] PMECC Error Location 0 Register 0x4EE0 32 read-only n 0x0 0x0 ERRLOCN Error Position within the Set {sector area, spare area} 0 14 read-only ERRLOC[13] PMECC Error Location 0 Register 0x54A0 32 read-only n 0x0 0x0 ERRLOCN Error Position within the Set {sector area, spare area} 0 14 read-only ERRLOC[14] PMECC Error Location 0 Register 0x5A64 32 read-only n 0x0 0x0 ERRLOCN Error Position within the Set {sector area, spare area} 0 14 read-only ERRLOC[15] PMECC Error Location 0 Register 0x602C 32 read-only n 0x0 0x0 ERRLOCN Error Position within the Set {sector area, spare area} 0 14 read-only ERRLOC[16] PMECC Error Location 0 Register 0x65F8 32 read-only n 0x0 0x0 ERRLOCN Error Position within the Set {sector area, spare area} 0 14 read-only ERRLOC[17] PMECC Error Location 0 Register 0x6BC8 32 read-only n 0x0 0x0 ERRLOCN Error Position within the Set {sector area, spare area} 0 14 read-only ERRLOC[18] PMECC Error Location 0 Register 0x719C 32 read-only n 0x0 0x0 ERRLOCN Error Position within the Set {sector area, spare area} 0 14 read-only ERRLOC[19] PMECC Error Location 0 Register 0x7774 32 read-only n 0x0 0x0 ERRLOCN Error Position within the Set {sector area, spare area} 0 14 read-only ERRLOC[1] PMECC Error Location 0 Register 0x10A8 32 read-only n 0x0 0x0 ERRLOCN Error Position within the Set {sector area, spare area} 0 14 read-only ERRLOC[20] PMECC Error Location 0 Register 0x7D50 32 read-only n 0x0 0x0 ERRLOCN Error Position within the Set {sector area, spare area} 0 14 read-only ERRLOC[21] PMECC Error Location 0 Register 0x8330 32 read-only n 0x0 0x0 ERRLOCN Error Position within the Set {sector area, spare area} 0 14 read-only ERRLOC[22] PMECC Error Location 0 Register 0x8914 32 read-only n 0x0 0x0 ERRLOCN Error Position within the Set {sector area, spare area} 0 14 read-only ERRLOC[23] PMECC Error Location 0 Register 0x8EFC 32 read-only n 0x0 0x0 ERRLOCN Error Position within the Set {sector area, spare area} 0 14 read-only ERRLOC[2] PMECC Error Location 0 Register 0x163C 32 read-only n 0x0 0x0 ERRLOCN Error Position within the Set {sector area, spare area} 0 14 read-only ERRLOC[3] PMECC Error Location 0 Register 0x1BD4 32 read-only n 0x0 0x0 ERRLOCN Error Position within the Set {sector area, spare area} 0 14 read-only ERRLOC[4] PMECC Error Location 0 Register 0x2170 32 read-only n 0x0 0x0 ERRLOCN Error Position within the Set {sector area, spare area} 0 14 read-only ERRLOC[5] PMECC Error Location 0 Register 0x2710 32 read-only n 0x0 0x0 ERRLOCN Error Position within the Set {sector area, spare area} 0 14 read-only ERRLOC[6] PMECC Error Location 0 Register 0x2CB4 32 read-only n 0x0 0x0 ERRLOCN Error Position within the Set {sector area, spare area} 0 14 read-only ERRLOC[7] PMECC Error Location 0 Register 0x325C 32 read-only n 0x0 0x0 ERRLOCN Error Position within the Set {sector area, spare area} 0 14 read-only ERRLOC[8] PMECC Error Location 0 Register 0x3808 32 read-only n 0x0 0x0 ERRLOCN Error Position within the Set {sector area, spare area} 0 14 read-only ERRLOC[9] PMECC Error Location 0 Register 0x3DB8 32 read-only n 0x0 0x0 ERRLOCN Error Position within the Set {sector area, spare area} 0 14 read-only IDR NFC Interrupt Disable Register 0x10 32 write-only n 0x0 0x0 AWB Accessing While Busy Interrupt Disable 22 1 write-only CMDDONE Command Done Interrupt Disable 17 1 write-only DTOE Data Timeout Error Interrupt Disable 20 1 write-only NFCASE NFC Access Size Error Interrupt Disable 23 1 write-only RB_EDGE0 Ready/Busy Line 0 Interrupt Disable 24 1 write-only RB_FALL Ready Busy Falling Edge Detection Interrupt Disable 5 1 write-only RB_RISE Ready Busy Rising Edge Detection Interrupt Disable 4 1 write-only UNDEF Undefined Area Access Interrupt Disable 21 1 write-only XFRDONE Transfer Done Interrupt Disable 16 1 write-only IER NFC Interrupt Enable Register 0xC 32 write-only n 0x0 0x0 AWB Accessing While Busy Interrupt Enable 22 1 write-only CMDDONE Command Done Interrupt Enable 17 1 write-only DTOE Data Timeout Error Interrupt Enable 20 1 write-only NFCASE NFC Access Size Error Interrupt Enable 23 1 write-only RB_EDGE0 Ready/Busy Line 0 Interrupt Enable 24 1 write-only RB_FALL Ready Busy Falling Edge Detection Interrupt Enable 5 1 write-only RB_RISE Ready Busy Rising Edge Detection Interrupt Enable 4 1 write-only UNDEF Undefined Area Access Interrupt Enable 21 1 write-only XFRDONE Transfer Done Interrupt Enable 16 1 write-only IMR NFC Interrupt Mask Register 0x14 32 read-only n 0x0 0x0 AWB Accessing While Busy Interrupt Mask 22 1 read-only CMDDONE Command Done Interrupt Mask 17 1 read-only DTOE Data Timeout Error Interrupt Mask 20 1 read-only NFCASE NFC Access Size Error Interrupt Mask 23 1 read-only RB_EDGE0 Ready/Busy Line 0 Interrupt Mask 24 1 read-only RB_FALL Ready Busy Falling Edge Detection Interrupt Mask 5 1 read-only RB_RISE Ready Busy Rising Edge Detection Interrupt Mask 4 1 read-only UNDEF Undefined Area Access Interrupt Mask5 21 1 read-only XFRDONE Transfer Done Interrupt Mask 16 1 read-only KEY1 Off Chip Memory Scrambling KEY1 Register 0x6A4 32 write-only n 0x0 0x0 KEY1 Off Chip Memory Scrambling (OCMS) Key Part 1 0 32 write-only KEY2 Off Chip Memory Scrambling KEY2 Register 0x6A8 32 write-only n 0x0 0x0 KEY2 Off Chip Memory Scrambling (OCMS) Key Part 2 0 32 write-only MODE0 Mode Register (CS_number = 0) 0x610 32 read-write n 0x0 0x0 BAT Byte Access Type 8 1 read-write BYTE_SELECT Byte select access type:- Write operation is controlled using NCS, NWE, NBS0, NBS1.- Read operation is controlled using NCS, NRD, NBS0, NBS1. 0 BYTE_WRITE Byte write access type:- Write operation is controlled using NCS, NWR0, NWR1.- Read operation is controlled using NCS and NRD. 1 DBW Data Bus Width 12 1 read-write BIT_8 8-bit bus 0 BIT_16 16-bit bus 1 EXNW_MODE NWAIT Mode 4 2 read-write DISABLED Disabled-The NWAIT input signal is ignored on the corresponding Chip Select. 0x0 FROZEN Frozen Mode-If asserted, the NWAIT signal freezes the current read or write cycle. After deassertion, the read/write cycle is resumed from the point where it was stopped. 0x2 READY Ready Mode-The NWAIT signal indicates the availability of the external device at the end of the pulse of the controlling read or write signal, to complete the access. If high, the access normally completes. If low, the access is extended until NWAIT returns high. 0x3 READ_MODE Selection of the Control Signal for Read Operation 0 1 read-write NCS_CTRL The Read operation is controlled by the NCS signal. 0 NRD_CTRL The Read operation is controlled by the NRD signal. 1 TDF_CYCLES Data Float Time 16 4 read-write TDF_MODE TDF Optimization 20 1 read-write WRITE_MODE Selection of the Control Signal for Write Operation 1 1 read-write NCS_CTRL The Write operation is controller by the NCS signal. 0 NWE_CTRL The Write operation is controlled by the NWE signal 1 MODE1 Mode Register (CS_number = 1) 0x624 32 read-write n 0x0 0x0 BAT Byte Access Type 8 1 read-write BYTE_SELECT Byte select access type:- Write operation is controlled using NCS, NWE, NBS0, NBS1.- Read operation is controlled using NCS, NRD, NBS0, NBS1. 0 BYTE_WRITE Byte write access type:- Write operation is controlled using NCS, NWR0, NWR1.- Read operation is controlled using NCS and NRD. 1 DBW Data Bus Width 12 1 read-write BIT_8 8-bit bus 0 BIT_16 16-bit bus 1 EXNW_MODE NWAIT Mode 4 2 read-write DISABLED Disabled-The NWAIT input signal is ignored on the corresponding Chip Select. 0x0 FROZEN Frozen Mode-If asserted, the NWAIT signal freezes the current read or write cycle. After deassertion, the read/write cycle is resumed from the point where it was stopped. 0x2 READY Ready Mode-The NWAIT signal indicates the availability of the external device at the end of the pulse of the controlling read or write signal, to complete the access. If high, the access normally completes. If low, the access is extended until NWAIT returns high. 0x3 READ_MODE Selection of the Control Signal for Read Operation 0 1 read-write NCS_CTRL The Read operation is controlled by the NCS signal. 0 NRD_CTRL The Read operation is controlled by the NRD signal. 1 TDF_CYCLES Data Float Time 16 4 read-write TDF_MODE TDF Optimization 20 1 read-write WRITE_MODE Selection of the Control Signal for Write Operation 1 1 read-write NCS_CTRL The Write operation is controller by the NCS signal. 0 NWE_CTRL The Write operation is controlled by the NWE signal 1 MODE2 Mode Register (CS_number = 2) 0x638 32 read-write n 0x0 0x0 BAT Byte Access Type 8 1 read-write BYTE_SELECT Byte select access type:- Write operation is controlled using NCS, NWE, NBS0, NBS1.- Read operation is controlled using NCS, NRD, NBS0, NBS1. 0 BYTE_WRITE Byte write access type:- Write operation is controlled using NCS, NWR0, NWR1.- Read operation is controlled using NCS and NRD. 1 DBW Data Bus Width 12 1 read-write BIT_8 8-bit bus 0 BIT_16 16-bit bus 1 EXNW_MODE NWAIT Mode 4 2 read-write DISABLED Disabled-The NWAIT input signal is ignored on the corresponding Chip Select. 0x0 FROZEN Frozen Mode-If asserted, the NWAIT signal freezes the current read or write cycle. After deassertion, the read/write cycle is resumed from the point where it was stopped. 0x2 READY Ready Mode-The NWAIT signal indicates the availability of the external device at the end of the pulse of the controlling read or write signal, to complete the access. If high, the access normally completes. If low, the access is extended until NWAIT returns high. 0x3 READ_MODE Selection of the Control Signal for Read Operation 0 1 read-write NCS_CTRL The Read operation is controlled by the NCS signal. 0 NRD_CTRL The Read operation is controlled by the NRD signal. 1 TDF_CYCLES Data Float Time 16 4 read-write TDF_MODE TDF Optimization 20 1 read-write WRITE_MODE Selection of the Control Signal for Write Operation 1 1 read-write NCS_CTRL The Write operation is controller by the NCS signal. 0 NWE_CTRL The Write operation is controlled by the NWE signal 1 MODE3 Mode Register (CS_number = 3) 0x64C 32 read-write n 0x0 0x0 BAT Byte Access Type 8 1 read-write BYTE_SELECT Byte select access type:- Write operation is controlled using NCS, NWE, NBS0, NBS1.- Read operation is controlled using NCS, NRD, NBS0, NBS1. 0 BYTE_WRITE Byte write access type:- Write operation is controlled using NCS, NWR0, NWR1.- Read operation is controlled using NCS and NRD. 1 DBW Data Bus Width 12 1 read-write BIT_8 8-bit bus 0 BIT_16 16-bit bus 1 EXNW_MODE NWAIT Mode 4 2 read-write DISABLED Disabled-The NWAIT input signal is ignored on the corresponding Chip Select. 0x0 FROZEN Frozen Mode-If asserted, the NWAIT signal freezes the current read or write cycle. After deassertion, the read/write cycle is resumed from the point where it was stopped. 0x2 READY Ready Mode-The NWAIT signal indicates the availability of the external device at the end of the pulse of the controlling read or write signal, to complete the access. If high, the access normally completes. If low, the access is extended until NWAIT returns high. 0x3 READ_MODE Selection of the Control Signal for Read Operation 0 1 read-write NCS_CTRL The Read operation is controlled by the NCS signal. 0 NRD_CTRL The Read operation is controlled by the NRD signal. 1 TDF_CYCLES Data Float Time 16 4 read-write TDF_MODE TDF Optimization 20 1 read-write WRITE_MODE Selection of the Control Signal for Write Operation 1 1 read-write NCS_CTRL The Write operation is controller by the NCS signal. 0 NWE_CTRL The Write operation is controlled by the NWE signal 1 OCMS Off Chip Memory Scrambling Register 0x6A0 32 read-write n 0x0 0x0 SMSE Static Memory Controller Scrambling Enable 0 1 read-write SRSE NFC Internal SRAM Scrambling Enable 1 1 read-write PMECC0_0 PMECC Redundancy 0 Register (sec_num = 0) 0xB0 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC0_1 PMECC Redundancy 0 Register (sec_num = 1) 0xF0 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC0_2 PMECC Redundancy 0 Register (sec_num = 2) 0x130 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC0_3 PMECC Redundancy 0 Register (sec_num = 3) 0x170 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC0_4 PMECC Redundancy 0 Register (sec_num = 4) 0x1B0 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC0_5 PMECC Redundancy 0 Register (sec_num = 5) 0x1F0 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC0_6 PMECC Redundancy 0 Register (sec_num = 6) 0x230 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC0_7 PMECC Redundancy 0 Register (sec_num = 7) 0x270 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC10_0 PMECC Redundancy 10 Register (sec_num = 0) 0xD8 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC10_1 PMECC Redundancy 10 Register (sec_num = 1) 0x118 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC10_2 PMECC Redundancy 10 Register (sec_num = 2) 0x158 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC10_3 PMECC Redundancy 10 Register (sec_num = 3) 0x198 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC10_4 PMECC Redundancy 10 Register (sec_num = 4) 0x1D8 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC10_5 PMECC Redundancy 10 Register (sec_num = 5) 0x218 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC10_6 PMECC Redundancy 10 Register (sec_num = 6) 0x258 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC10_7 PMECC Redundancy 10 Register (sec_num = 7) 0x298 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC1_0 PMECC Redundancy 1 Register (sec_num = 0) 0xB4 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC1_1 PMECC Redundancy 1 Register (sec_num = 1) 0xF4 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC1_2 PMECC Redundancy 1 Register (sec_num = 2) 0x134 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC1_3 PMECC Redundancy 1 Register (sec_num = 3) 0x174 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC1_4 PMECC Redundancy 1 Register (sec_num = 4) 0x1B4 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC1_5 PMECC Redundancy 1 Register (sec_num = 5) 0x1F4 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC1_6 PMECC Redundancy 1 Register (sec_num = 6) 0x234 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC1_7 PMECC Redundancy 1 Register (sec_num = 7) 0x274 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC2_0 PMECC Redundancy 2 Register (sec_num = 0) 0xB8 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC2_1 PMECC Redundancy 2 Register (sec_num = 1) 0xF8 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC2_2 PMECC Redundancy 2 Register (sec_num = 2) 0x138 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC2_3 PMECC Redundancy 2 Register (sec_num = 3) 0x178 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC2_4 PMECC Redundancy 2 Register (sec_num = 4) 0x1B8 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC2_5 PMECC Redundancy 2 Register (sec_num = 5) 0x1F8 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC2_6 PMECC Redundancy 2 Register (sec_num = 6) 0x238 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC2_7 PMECC Redundancy 2 Register (sec_num = 7) 0x278 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC3_0 PMECC Redundancy 3 Register (sec_num = 0) 0xBC 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC3_1 PMECC Redundancy 3 Register (sec_num = 1) 0xFC 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC3_2 PMECC Redundancy 3 Register (sec_num = 2) 0x13C 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC3_3 PMECC Redundancy 3 Register (sec_num = 3) 0x17C 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC3_4 PMECC Redundancy 3 Register (sec_num = 4) 0x1BC 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC3_5 PMECC Redundancy 3 Register (sec_num = 5) 0x1FC 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC3_6 PMECC Redundancy 3 Register (sec_num = 6) 0x23C 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC3_7 PMECC Redundancy 3 Register (sec_num = 7) 0x27C 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC4_0 PMECC Redundancy 4 Register (sec_num = 0) 0xC0 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC4_1 PMECC Redundancy 4 Register (sec_num = 1) 0x100 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC4_2 PMECC Redundancy 4 Register (sec_num = 2) 0x140 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC4_3 PMECC Redundancy 4 Register (sec_num = 3) 0x180 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC4_4 PMECC Redundancy 4 Register (sec_num = 4) 0x1C0 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC4_5 PMECC Redundancy 4 Register (sec_num = 5) 0x200 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC4_6 PMECC Redundancy 4 Register (sec_num = 6) 0x240 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC4_7 PMECC Redundancy 4 Register (sec_num = 7) 0x280 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC5_0 PMECC Redundancy 5 Register (sec_num = 0) 0xC4 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC5_1 PMECC Redundancy 5 Register (sec_num = 1) 0x104 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC5_2 PMECC Redundancy 5 Register (sec_num = 2) 0x144 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC5_3 PMECC Redundancy 5 Register (sec_num = 3) 0x184 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC5_4 PMECC Redundancy 5 Register (sec_num = 4) 0x1C4 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC5_5 PMECC Redundancy 5 Register (sec_num = 5) 0x204 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC5_6 PMECC Redundancy 5 Register (sec_num = 6) 0x244 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC5_7 PMECC Redundancy 5 Register (sec_num = 7) 0x284 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC6_0 PMECC Redundancy 6 Register (sec_num = 0) 0xC8 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC6_1 PMECC Redundancy 6 Register (sec_num = 1) 0x108 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC6_2 PMECC Redundancy 6 Register (sec_num = 2) 0x148 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC6_3 PMECC Redundancy 6 Register (sec_num = 3) 0x188 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC6_4 PMECC Redundancy 6 Register (sec_num = 4) 0x1C8 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC6_5 PMECC Redundancy 6 Register (sec_num = 5) 0x208 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC6_6 PMECC Redundancy 6 Register (sec_num = 6) 0x248 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC6_7 PMECC Redundancy 6 Register (sec_num = 7) 0x288 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC7_0 PMECC Redundancy 7 Register (sec_num = 0) 0xCC 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC7_1 PMECC Redundancy 7 Register (sec_num = 1) 0x10C 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC7_2 PMECC Redundancy 7 Register (sec_num = 2) 0x14C 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC7_3 PMECC Redundancy 7 Register (sec_num = 3) 0x18C 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC7_4 PMECC Redundancy 7 Register (sec_num = 4) 0x1CC 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC7_5 PMECC Redundancy 7 Register (sec_num = 5) 0x20C 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC7_6 PMECC Redundancy 7 Register (sec_num = 6) 0x24C 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC7_7 PMECC Redundancy 7 Register (sec_num = 7) 0x28C 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC8_0 PMECC Redundancy 8 Register (sec_num = 0) 0xD0 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC8_1 PMECC Redundancy 8 Register (sec_num = 1) 0x110 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC8_2 PMECC Redundancy 8 Register (sec_num = 2) 0x150 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC8_3 PMECC Redundancy 8 Register (sec_num = 3) 0x190 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC8_4 PMECC Redundancy 8 Register (sec_num = 4) 0x1D0 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC8_5 PMECC Redundancy 8 Register (sec_num = 5) 0x210 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC8_6 PMECC Redundancy 8 Register (sec_num = 6) 0x250 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC8_7 PMECC Redundancy 8 Register (sec_num = 7) 0x290 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC9_0 PMECC Redundancy 9 Register (sec_num = 0) 0xD4 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC9_1 PMECC Redundancy 9 Register (sec_num = 1) 0x114 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC9_2 PMECC Redundancy 9 Register (sec_num = 2) 0x154 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC9_3 PMECC Redundancy 9 Register (sec_num = 3) 0x194 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC9_4 PMECC Redundancy 9 Register (sec_num = 4) 0x1D4 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC9_5 PMECC Redundancy 9 Register (sec_num = 5) 0x214 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC9_6 PMECC Redundancy 9 Register (sec_num = 6) 0x254 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECC9_7 PMECC Redundancy 9 Register (sec_num = 7) 0x294 32 read-only n 0x0 0x0 ECC BCH Redundancy 0 32 read-only PMECCEADDR PMECC End Address Register 0x7C 32 read-write n 0x0 0x0 ENDADDR ECC Area End Address 0 9 read-write PMECCFG PMECC Configuration Register 0x70 32 read-write n 0x0 0x0 AUTO Automatic Mode Enable 20 1 read-write BCH_ERR Error Correcting Capability 0 3 read-write BCH_ERR2 2 errors 0x0 BCH_ERR4 4 errors 0x1 BCH_ERR8 8 errors 0x2 BCH_ERR12 12 errors 0x3 BCH_ERR24 24 errors 0x4 NANDWR NAND Write Access 12 1 read-write PAGESIZE Number of Sectors in the Page 8 2 read-write PAGESIZE_1SEC 1 sector for main area (512 or 1024 bytes) 0x0 PAGESIZE_2SEC 2 sectors for main area (1024 or 2048 bytes) 0x1 PAGESIZE_4SEC 4 sectors for main area (2048 or 4096 bytes) 0x2 PAGESIZE_8SEC 8 sectors for main area (4096 or 8192 bytes) 0x3 SECTORSZ Sector Size 4 1 read-write SPAREEN Spare Enable 16 1 read-write PMECCIDR PMECC Interrupt Disable Register 0x90 32 write-only n 0x0 0x0 ERRID Error Interrupt Disable 0 1 write-only PMECCIER PMECC Interrupt Enable register 0x8C 32 write-only n 0x0 0x0 ERRIE Error Interrupt Enable 0 1 write-only PMECCIMR PMECC Interrupt Mask Register 0x94 32 read-only n 0x0 0x0 ERRIM Error Interrupt Mask 0 1 read-only PMECCISR PMECC Interrupt Status Register 0x98 32 read-only n 0x0 0x0 ERRIS Error Interrupt Status Register 0 8 read-only PMECCSADDR PMECC Start Address Register 0x78 32 read-write n 0x0 0x0 STARTADDR ECC Area Start Address 0 9 read-write PMECCSAREA PMECC Spare Area Size Register 0x74 32 read-write n 0x0 0x0 SPARESIZE Spare Area Size 0 9 read-write PMECCSR PMECC Status Register 0x88 32 read-only n 0x0 0x0 BUSY The kernel of the PMECC is busy 0 1 read-only ENABLE PMECC Enable bit 4 1 read-only PMECCTRL PMECC Control Register 0x84 32 write-only n 0x0 0x0 DATA Start a Data Phase 1 1 write-only DISABLE PMECC Enable 5 1 write-only ENABLE PMECC Enable 4 1 write-only RST Reset the PMECC Module 0 1 write-only USER Start a User Mode Phase 2 1 write-only PULSE0 Pulse Register (CS_number = 0) 0x604 32 read-write n 0x0 0x0 NCS_RD_PULSE NCS Pulse Length in READ Access 24 7 read-write NCS_WR_PULSE NCS Pulse Length in WRITE Access 8 7 read-write NRD_PULSE NRD Pulse Length 16 7 read-write NWE_PULSE NWE Pulse Length 0 7 read-write PULSE1 Pulse Register (CS_number = 1) 0x618 32 read-write n 0x0 0x0 NCS_RD_PULSE NCS Pulse Length in READ Access 24 7 read-write NCS_WR_PULSE NCS Pulse Length in WRITE Access 8 7 read-write NRD_PULSE NRD Pulse Length 16 7 read-write NWE_PULSE NWE Pulse Length 0 7 read-write PULSE2 Pulse Register (CS_number = 2) 0x62C 32 read-write n 0x0 0x0 NCS_RD_PULSE NCS Pulse Length in READ Access 24 7 read-write NCS_WR_PULSE NCS Pulse Length in WRITE Access 8 7 read-write NRD_PULSE NRD Pulse Length 16 7 read-write NWE_PULSE NWE Pulse Length 0 7 read-write PULSE3 Pulse Register (CS_number = 3) 0x640 32 read-write n 0x0 0x0 NCS_RD_PULSE NCS Pulse Length in READ Access 24 7 read-write NCS_WR_PULSE NCS Pulse Length in WRITE Access 8 7 read-write NRD_PULSE NRD Pulse Length 16 7 read-write NWE_PULSE NWE Pulse Length 0 7 read-write REM0_0 PMECC Remainder 0 Register (sec_num = 0) 0x2B0 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM0_1 PMECC Remainder 0 Register (sec_num = 1) 0x2F0 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM0_2 PMECC Remainder 0 Register (sec_num = 2) 0x330 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM0_3 PMECC Remainder 0 Register (sec_num = 3) 0x370 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM0_4 PMECC Remainder 0 Register (sec_num = 4) 0x3B0 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM0_5 PMECC Remainder 0 Register (sec_num = 5) 0x3F0 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM0_6 PMECC Remainder 0 Register (sec_num = 6) 0x430 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM0_7 PMECC Remainder 0 Register (sec_num = 7) 0x470 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM10_0 PMECC Remainder 10 Register (sec_num = 0) 0x2D8 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM10_1 PMECC Remainder 10 Register (sec_num = 1) 0x318 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM10_2 PMECC Remainder 10 Register (sec_num = 2) 0x358 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM10_3 PMECC Remainder 10 Register (sec_num = 3) 0x398 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM10_4 PMECC Remainder 10 Register (sec_num = 4) 0x3D8 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM10_5 PMECC Remainder 10 Register (sec_num = 5) 0x418 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM10_6 PMECC Remainder 10 Register (sec_num = 6) 0x458 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM10_7 PMECC Remainder 10 Register (sec_num = 7) 0x498 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM11_0 PMECC Remainder 11 Register (sec_num = 0) 0x2DC 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM11_1 PMECC Remainder 11 Register (sec_num = 1) 0x31C 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM11_2 PMECC Remainder 11 Register (sec_num = 2) 0x35C 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM11_3 PMECC Remainder 11 Register (sec_num = 3) 0x39C 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM11_4 PMECC Remainder 11 Register (sec_num = 4) 0x3DC 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM11_5 PMECC Remainder 11 Register (sec_num = 5) 0x41C 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM11_6 PMECC Remainder 11 Register (sec_num = 6) 0x45C 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM11_7 PMECC Remainder 11 Register (sec_num = 7) 0x49C 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM1_0 PMECC Remainder 1 Register (sec_num = 0) 0x2B4 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM1_1 PMECC Remainder 1 Register (sec_num = 1) 0x2F4 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM1_2 PMECC Remainder 1 Register (sec_num = 2) 0x334 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM1_3 PMECC Remainder 1 Register (sec_num = 3) 0x374 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM1_4 PMECC Remainder 1 Register (sec_num = 4) 0x3B4 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM1_5 PMECC Remainder 1 Register (sec_num = 5) 0x3F4 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM1_6 PMECC Remainder 1 Register (sec_num = 6) 0x434 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM1_7 PMECC Remainder 1 Register (sec_num = 7) 0x474 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM2_0 PMECC Remainder 2 Register (sec_num = 0) 0x2B8 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM2_1 PMECC Remainder 2 Register (sec_num = 1) 0x2F8 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM2_2 PMECC Remainder 2 Register (sec_num = 2) 0x338 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM2_3 PMECC Remainder 2 Register (sec_num = 3) 0x378 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM2_4 PMECC Remainder 2 Register (sec_num = 4) 0x3B8 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM2_5 PMECC Remainder 2 Register (sec_num = 5) 0x3F8 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM2_6 PMECC Remainder 2 Register (sec_num = 6) 0x438 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM2_7 PMECC Remainder 2 Register (sec_num = 7) 0x478 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM3_0 PMECC Remainder 3 Register (sec_num = 0) 0x2BC 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM3_1 PMECC Remainder 3 Register (sec_num = 1) 0x2FC 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM3_2 PMECC Remainder 3 Register (sec_num = 2) 0x33C 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM3_3 PMECC Remainder 3 Register (sec_num = 3) 0x37C 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM3_4 PMECC Remainder 3 Register (sec_num = 4) 0x3BC 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM3_5 PMECC Remainder 3 Register (sec_num = 5) 0x3FC 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM3_6 PMECC Remainder 3 Register (sec_num = 6) 0x43C 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM3_7 PMECC Remainder 3 Register (sec_num = 7) 0x47C 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM4_0 PMECC Remainder 4 Register (sec_num = 0) 0x2C0 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM4_1 PMECC Remainder 4 Register (sec_num = 1) 0x300 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM4_2 PMECC Remainder 4 Register (sec_num = 2) 0x340 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM4_3 PMECC Remainder 4 Register (sec_num = 3) 0x380 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM4_4 PMECC Remainder 4 Register (sec_num = 4) 0x3C0 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM4_5 PMECC Remainder 4 Register (sec_num = 5) 0x400 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM4_6 PMECC Remainder 4 Register (sec_num = 6) 0x440 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM4_7 PMECC Remainder 4 Register (sec_num = 7) 0x480 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM5_0 PMECC Remainder 5 Register (sec_num = 0) 0x2C4 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM5_1 PMECC Remainder 5 Register (sec_num = 1) 0x304 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM5_2 PMECC Remainder 5 Register (sec_num = 2) 0x344 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM5_3 PMECC Remainder 5 Register (sec_num = 3) 0x384 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM5_4 PMECC Remainder 5 Register (sec_num = 4) 0x3C4 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM5_5 PMECC Remainder 5 Register (sec_num = 5) 0x404 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM5_6 PMECC Remainder 5 Register (sec_num = 6) 0x444 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM5_7 PMECC Remainder 5 Register (sec_num = 7) 0x484 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM6_0 PMECC Remainder 6 Register (sec_num = 0) 0x2C8 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM6_1 PMECC Remainder 6 Register (sec_num = 1) 0x308 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM6_2 PMECC Remainder 6 Register (sec_num = 2) 0x348 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM6_3 PMECC Remainder 6 Register (sec_num = 3) 0x388 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM6_4 PMECC Remainder 6 Register (sec_num = 4) 0x3C8 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM6_5 PMECC Remainder 6 Register (sec_num = 5) 0x408 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM6_6 PMECC Remainder 6 Register (sec_num = 6) 0x448 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM6_7 PMECC Remainder 6 Register (sec_num = 7) 0x488 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM7_0 PMECC Remainder 7 Register (sec_num = 0) 0x2CC 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM7_1 PMECC Remainder 7 Register (sec_num = 1) 0x30C 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM7_2 PMECC Remainder 7 Register (sec_num = 2) 0x34C 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM7_3 PMECC Remainder 7 Register (sec_num = 3) 0x38C 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM7_4 PMECC Remainder 7 Register (sec_num = 4) 0x3CC 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM7_5 PMECC Remainder 7 Register (sec_num = 5) 0x40C 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM7_6 PMECC Remainder 7 Register (sec_num = 6) 0x44C 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM7_7 PMECC Remainder 7 Register (sec_num = 7) 0x48C 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM8_0 PMECC Remainder 8 Register (sec_num = 0) 0x2D0 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM8_1 PMECC Remainder 8 Register (sec_num = 1) 0x310 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM8_2 PMECC Remainder 8 Register (sec_num = 2) 0x350 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM8_3 PMECC Remainder 8 Register (sec_num = 3) 0x390 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM8_4 PMECC Remainder 8 Register (sec_num = 4) 0x3D0 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM8_5 PMECC Remainder 8 Register (sec_num = 5) 0x410 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM8_6 PMECC Remainder 8 Register (sec_num = 6) 0x450 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM8_7 PMECC Remainder 8 Register (sec_num = 7) 0x490 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM9_0 PMECC Remainder 9 Register (sec_num = 0) 0x2D4 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM9_1 PMECC Remainder 9 Register (sec_num = 1) 0x314 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM9_2 PMECC Remainder 9 Register (sec_num = 2) 0x354 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM9_3 PMECC Remainder 9 Register (sec_num = 3) 0x394 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM9_4 PMECC Remainder 9 Register (sec_num = 4) 0x3D4 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM9_5 PMECC Remainder 9 Register (sec_num = 5) 0x414 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM9_6 PMECC Remainder 9 Register (sec_num = 6) 0x454 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only REM9_7 PMECC Remainder 9 Register (sec_num = 7) 0x494 32 read-only n 0x0 0x0 REM2NP1 BCH Remainder 2 * N + 1 0 14 read-only REM2NP3 BCH Remainder 2 * N + 3 16 14 read-only SETUP0 Setup Register (CS_number = 0) 0x600 32 read-write n 0x0 0x0 NCS_RD_SETUP NCS Setup Length in Read Access 24 6 read-write NCS_WR_SETUP NCS Setup Length in Write Access 8 6 read-write NRD_SETUP NRD Setup Length 16 6 read-write NWE_SETUP NWE Setup Length 0 6 read-write SETUP1 Setup Register (CS_number = 1) 0x614 32 read-write n 0x0 0x0 NCS_RD_SETUP NCS Setup Length in Read Access 24 6 read-write NCS_WR_SETUP NCS Setup Length in Write Access 8 6 read-write NRD_SETUP NRD Setup Length 16 6 read-write NWE_SETUP NWE Setup Length 0 6 read-write SETUP2 Setup Register (CS_number = 2) 0x628 32 read-write n 0x0 0x0 NCS_RD_SETUP NCS Setup Length in Read Access 24 6 read-write NCS_WR_SETUP NCS Setup Length in Write Access 8 6 read-write NRD_SETUP NRD Setup Length 16 6 read-write NWE_SETUP NWE Setup Length 0 6 read-write SETUP3 Setup Register (CS_number = 3) 0x63C 32 read-write n 0x0 0x0 NCS_RD_SETUP NCS Setup Length in Read Access 24 6 read-write NCS_WR_SETUP NCS Setup Length in Write Access 8 6 read-write NRD_SETUP NRD Setup Length 16 6 read-write NWE_SETUP NWE Setup Length 0 6 read-write SIGMA0 PMECC Error Location SIGMA 0 Register 0x528 32 read-only n 0x0 0x0 SIGMA0 Coefficient of degree 0 in the SIGMA polynomial 0 14 read-only SIGMA1 PMECC Error Location SIGMA 1 Register 0x52C 32 read-write n 0x0 0x0 SIGMA1 Coefficient of degree x in the SIGMA polynomial 0 14 read-write SIGMA10 PMECC Error Location SIGMA 10 Register 0x550 32 read-write n 0x0 0x0 SIGMA10 Coefficient of degree x in the SIGMA polynomial 0 14 read-write SIGMA11 PMECC Error Location SIGMA 11 Register 0x554 32 read-write n 0x0 0x0 SIGMA11 Coefficient of degree x in the SIGMA polynomial 0 14 read-write SIGMA12 PMECC Error Location SIGMA 12 Register 0x558 32 read-write n 0x0 0x0 SIGMA12 Coefficient of degree x in the SIGMA polynomial 0 14 read-write SIGMA13 PMECC Error Location SIGMA 13 Register 0x55C 32 read-write n 0x0 0x0 SIGMA13 Coefficient of degree x in the SIGMA polynomial 0 14 read-write SIGMA14 PMECC Error Location SIGMA 14 Register 0x560 32 read-write n 0x0 0x0 SIGMA14 Coefficient of degree x in the SIGMA polynomial 0 14 read-write SIGMA15 PMECC Error Location SIGMA 15 Register 0x564 32 read-write n 0x0 0x0 SIGMA15 Coefficient of degree x in the SIGMA polynomial 0 14 read-write SIGMA16 PMECC Error Location SIGMA 16 Register 0x568 32 read-write n 0x0 0x0 SIGMA16 Coefficient of degree x in the SIGMA polynomial 0 14 read-write SIGMA17 PMECC Error Location SIGMA 17 Register 0x56C 32 read-write n 0x0 0x0 SIGMA17 Coefficient of degree x in the SIGMA polynomial 0 14 read-write SIGMA18 PMECC Error Location SIGMA 18 Register 0x570 32 read-write n 0x0 0x0 SIGMA18 Coefficient of degree x in the SIGMA polynomial 0 14 read-write SIGMA19 PMECC Error Location SIGMA 19 Register 0x574 32 read-write n 0x0 0x0 SIGMA19 Coefficient of degree x in the SIGMA polynomial 0 14 read-write SIGMA2 PMECC Error Location SIGMA 2 Register 0x530 32 read-write n 0x0 0x0 SIGMA2 Coefficient of degree x in the SIGMA polynomial 0 14 read-write SIGMA20 PMECC Error Location SIGMA 20 Register 0x578 32 read-write n 0x0 0x0 SIGMA20 Coefficient of degree x in the SIGMA polynomial 0 14 read-write SIGMA21 PMECC Error Location SIGMA 21 Register 0x57C 32 read-write n 0x0 0x0 SIGMA21 Coefficient of degree x in the SIGMA polynomial 0 14 read-write SIGMA22 PMECC Error Location SIGMA 22 Register 0x580 32 read-write n 0x0 0x0 SIGMA22 Coefficient of degree x in the SIGMA polynomial 0 14 read-write SIGMA23 PMECC Error Location SIGMA 23 Register 0x584 32 read-write n 0x0 0x0 SIGMA23 Coefficient of degree x in the SIGMA polynomial 0 14 read-write SIGMA24 PMECC Error Location SIGMA 24 Register 0x588 32 read-write n 0x0 0x0 SIGMA24 Coefficient of degree x in the SIGMA polynomial 0 14 read-write SIGMA3 PMECC Error Location SIGMA 3 Register 0x534 32 read-write n 0x0 0x0 SIGMA3 Coefficient of degree x in the SIGMA polynomial 0 14 read-write SIGMA4 PMECC Error Location SIGMA 4 Register 0x538 32 read-write n 0x0 0x0 SIGMA4 Coefficient of degree x in the SIGMA polynomial 0 14 read-write SIGMA5 PMECC Error Location SIGMA 5 Register 0x53C 32 read-write n 0x0 0x0 SIGMA5 Coefficient of degree x in the SIGMA polynomial 0 14 read-write SIGMA6 PMECC Error Location SIGMA 6 Register 0x540 32 read-write n 0x0 0x0 SIGMA6 Coefficient of degree x in the SIGMA polynomial 0 14 read-write SIGMA7 PMECC Error Location SIGMA 7 Register 0x544 32 read-write n 0x0 0x0 SIGMA7 Coefficient of degree x in the SIGMA polynomial 0 14 read-write SIGMA8 PMECC Error Location SIGMA 8 Register 0x548 32 read-write n 0x0 0x0 SIGMA8 Coefficient of degree x in the SIGMA polynomial 0 14 read-write SIGMA9 PMECC Error Location SIGMA 9 Register 0x54C 32 read-write n 0x0 0x0 SIGMA9 Coefficient of degree x in the SIGMA polynomial 0 14 read-write SR NFC Status Register 0x8 32 read-only n 0x0 0x0 AWB Accessing While Busy 22 1 read-only CMDDONE Command Done 17 1 read-only DTOE Data Timeout Error 20 1 read-only NFCASE NFC Access Size Error 23 1 read-only NFCBUSY NFC Busy (this field cannot be reset) 8 1 read-only NFCSID NFC Chip Select ID (this field cannot be reset) 12 3 read-only NFCWR NFC Write/Read Operation (this field cannot be reset) 11 1 read-only RB_EDGE0 Ready/Busy Line 0 Edge Detected 24 1 read-only RB_FALL Selected Ready Busy Falling Edge Detected 5 1 read-only RB_RISE Selected Ready Busy Rising Edge Detected 4 1 read-only SMCSTS NAND Flash Controller Status (this field cannot be reset) 0 1 read-only UNDEF Undefined Area Error 21 1 read-only XFRDONE NFC Data Transfer Terminated 16 1 read-only TIMINGS0 Timings Register (CS_number = 0) 0x60C 32 read-write n 0x0 0x0 NFSEL NAND Flash Selection 31 1 read-write OCMS Off Chip Memory Scrambling Enable 12 1 read-write TADL ALE to Data Start 4 4 read-write TAR ALE to REN Low Delay 8 4 read-write TCLR CLE to REN Low Delay 0 4 read-write TRR Ready to REN Low Delay 16 4 read-write TWB WEN High to REN to Busy 24 4 read-write TIMINGS1 Timings Register (CS_number = 1) 0x620 32 read-write n 0x0 0x0 NFSEL NAND Flash Selection 31 1 read-write OCMS Off Chip Memory Scrambling Enable 12 1 read-write TADL ALE to Data Start 4 4 read-write TAR ALE to REN Low Delay 8 4 read-write TCLR CLE to REN Low Delay 0 4 read-write TRR Ready to REN Low Delay 16 4 read-write TWB WEN High to REN to Busy 24 4 read-write TIMINGS2 Timings Register (CS_number = 2) 0x634 32 read-write n 0x0 0x0 NFSEL NAND Flash Selection 31 1 read-write OCMS Off Chip Memory Scrambling Enable 12 1 read-write TADL ALE to Data Start 4 4 read-write TAR ALE to REN Low Delay 8 4 read-write TCLR CLE to REN Low Delay 0 4 read-write TRR Ready to REN Low Delay 16 4 read-write TWB WEN High to REN to Busy 24 4 read-write TIMINGS3 Timings Register (CS_number = 3) 0x648 32 read-write n 0x0 0x0 NFSEL NAND Flash Selection 31 1 read-write OCMS Off Chip Memory Scrambling Enable 12 1 read-write TADL ALE to Data Start 4 4 read-write TAR ALE to REN Low Delay 8 4 read-write TCLR CLE to REN Low Delay 0 4 read-write TRR Ready to REN Low Delay 16 4 read-write TWB WEN High to REN to Busy 24 4 read-write WPMR Write Protection Mode Register 0x6E4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 read-write WPKEY Write Protection Key 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of bit WPEN.Always reads as 0. 0x534D43 WPSR Write Protection Status Register 0x6E8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 read-only WPVSRC Write Protection Violation Source 8 16 read-only HSMCI0 High Speed MultiMedia Card Interface 0 HSMCI 0x0 0x0 0x50 registers n HSMCI0 35 ARGR Argument Register 0x10 32 read-write n 0x0 0x0 ARG Command Argument 0 32 read-write BLKR Block Register 0x18 32 read-write n 0x0 0x0 BCNT MMC/SDIO Block Count - SDIO Byte Count 0 16 read-write BLKLEN Data Block Length 16 16 read-write CFG Configuration Register 0x54 32 read-write n 0x0 0x0 FERRCTRL Flow Error flag reset control mode 4 1 read-write FIFOMODE HSMCI Internal FIFO control mode 0 1 read-write HSMODE High Speed Mode 8 1 read-write LSYNC Synchronize on the last block 12 1 read-write CMDR Command Register 0x14 32 write-only n 0x0 0x0 ATACS ATA with Command Completion Signal 26 1 write-only NORMAL Normal operation mode. 0 COMPLETION This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR). 1 BOOT_ACK Boot Operation Acknowledge 27 1 write-only CMDNB Command Number 0 6 write-only IOSPCMD SDIO Special Command 24 2 write-only STD Not an SDIO Special Command 0x0 SUSPEND SDIO Suspend Command 0x1 RESUME SDIO Resume Command 0x2 MAXLAT Max Latency for Command to Response 12 1 write-only 5 5-cycle max latency. 0 64 64-cycle max latency. 1 OPDCMD Open Drain Command 11 1 write-only PUSHPULL Push pull command. 0 OPENDRAIN Open drain command. 1 RSPTYP Response Type 6 2 write-only NORESP No response 0x0 48_BIT 48-bit response 0x1 136_BIT 136-bit response 0x2 R1B R1b response type 0x3 SPCMD Special Command 8 3 write-only STD Not a special CMD. 0x0 INIT Initialization CMD: 74 clock cycles for initialization sequence. 0x1 SYNC Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command. 0x2 CE_ATA CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line. 0x3 IT_CMD Interrupt command: Corresponds to the Interrupt Mode (CMD40). 0x4 IT_RESP Interrupt response: Corresponds to the Interrupt Mode (CMD40). 0x5 BOR Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly. 0x6 EBO End Boot Operation. This command allows the host processor to terminate the boot operation mode. 0x7 TRCMD Transfer Command 16 2 write-only NO_DATA No data transfer 0x0 START_DATA Start data transfer 0x1 STOP_DATA Stop data transfer 0x2 TRDIR Transfer Direction 18 1 write-only WRITE Write. 0 READ Read. 1 TRTYP Transfer Type 19 3 write-only SINGLE MMC/SD Card Single Block 0x0 MULTIPLE MMC/SD Card Multiple Block 0x1 STREAM MMC Stream 0x2 BYTE SDIO Byte 0x4 BLOCK SDIO Block 0x5 CR Control Register 0x0 32 write-only n 0x0 0x0 MCIDIS Multi-Media Interface Disable 1 1 write-only MCIEN Multi-Media Interface Enable 0 1 write-only PWSDIS Power Save Mode Disable 3 1 write-only PWSEN Power Save Mode Enable 2 1 write-only SWRST Software Reset 7 1 write-only CSTOR Completion Signal Timeout Register 0x1C 32 read-write n 0x0 0x0 CSTOCYC Completion Signal Timeout Cycle Number 0 4 read-write CSTOMUL Completion Signal Timeout Multiplier 4 3 read-write 1 CSTOCYC x 1 0x0 16 CSTOCYC x 16 0x1 128 CSTOCYC x 128 0x2 256 CSTOCYC x 256 0x3 1024 CSTOCYC x 1024 0x4 4096 CSTOCYC x 4096 0x5 65536 CSTOCYC x 65536 0x6 1048576 CSTOCYC x 1048576 0x7 DMA DMA Configuration Register 0x50 32 read-write n 0x0 0x0 CHKSIZE DMA Channel Read and Write Chunk Size 4 3 read-write 1 1 data available 0x0 2 2 data available 0x1 4 4 data available 0x2 8 8 data available 0x3 16 16 data available 0x4 DMAEN DMA Hardware Handshaking Enable 8 1 read-write DTOR Data Timeout Register 0x8 32 read-write n 0x0 0x0 DTOCYC Data Timeout Cycle Number 0 4 read-write DTOMUL Data Timeout Multiplier 4 3 read-write 1 DTOCYC 0x0 16 DTOCYC x 16 0x1 128 DTOCYC x 128 0x2 256 DTOCYC x 256 0x3 1024 DTOCYC x 1024 0x4 4096 DTOCYC x 4096 0x5 65536 DTOCYC x 65536 0x6 1048576 DTOCYC x 1048576 0x7 FIFO0 FIFO Memory Aperture0 0x200 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO1 FIFO Memory Aperture0 0x204 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO10 FIFO Memory Aperture0 0x228 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO100 FIFO Memory Aperture0 0x390 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO101 FIFO Memory Aperture0 0x394 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO102 FIFO Memory Aperture0 0x398 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO103 FIFO Memory Aperture0 0x39C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO104 FIFO Memory Aperture0 0x3A0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO105 FIFO Memory Aperture0 0x3A4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO106 FIFO Memory Aperture0 0x3A8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO107 FIFO Memory Aperture0 0x3AC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO108 FIFO Memory Aperture0 0x3B0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO109 FIFO Memory Aperture0 0x3B4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO11 FIFO Memory Aperture0 0x22C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO110 FIFO Memory Aperture0 0x3B8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO111 FIFO Memory Aperture0 0x3BC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO112 FIFO Memory Aperture0 0x3C0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO113 FIFO Memory Aperture0 0x3C4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO114 FIFO Memory Aperture0 0x3C8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO115 FIFO Memory Aperture0 0x3CC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO116 FIFO Memory Aperture0 0x3D0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO117 FIFO Memory Aperture0 0x3D4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO118 FIFO Memory Aperture0 0x3D8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO119 FIFO Memory Aperture0 0x3DC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO12 FIFO Memory Aperture0 0x230 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO120 FIFO Memory Aperture0 0x3E0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO121 FIFO Memory Aperture0 0x3E4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO122 FIFO Memory Aperture0 0x3E8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO123 FIFO Memory Aperture0 0x3EC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO124 FIFO Memory Aperture0 0x3F0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO125 FIFO Memory Aperture0 0x3F4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO126 FIFO Memory Aperture0 0x3F8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO127 FIFO Memory Aperture0 0x3FC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO128 FIFO Memory Aperture0 0x400 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO129 FIFO Memory Aperture0 0x404 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO13 FIFO Memory Aperture0 0x234 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO130 FIFO Memory Aperture0 0x408 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO131 FIFO Memory Aperture0 0x40C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO132 FIFO Memory Aperture0 0x410 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO133 FIFO Memory Aperture0 0x414 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO134 FIFO Memory Aperture0 0x418 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO135 FIFO Memory Aperture0 0x41C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO136 FIFO Memory Aperture0 0x420 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO137 FIFO Memory Aperture0 0x424 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO138 FIFO Memory Aperture0 0x428 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO139 FIFO Memory Aperture0 0x42C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO14 FIFO Memory Aperture0 0x238 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO140 FIFO Memory Aperture0 0x430 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO141 FIFO Memory Aperture0 0x434 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO142 FIFO Memory Aperture0 0x438 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO143 FIFO Memory Aperture0 0x43C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO144 FIFO Memory Aperture0 0x440 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO145 FIFO Memory Aperture0 0x444 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO146 FIFO Memory Aperture0 0x448 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO147 FIFO Memory Aperture0 0x44C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO148 FIFO Memory Aperture0 0x450 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO149 FIFO Memory Aperture0 0x454 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO15 FIFO Memory Aperture0 0x23C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO150 FIFO Memory Aperture0 0x458 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO151 FIFO Memory Aperture0 0x45C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO152 FIFO Memory Aperture0 0x460 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO153 FIFO Memory Aperture0 0x464 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO154 FIFO Memory Aperture0 0x468 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO155 FIFO Memory Aperture0 0x46C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO156 FIFO Memory Aperture0 0x470 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO157 FIFO Memory Aperture0 0x474 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO158 FIFO Memory Aperture0 0x478 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO159 FIFO Memory Aperture0 0x47C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO16 FIFO Memory Aperture0 0x240 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO160 FIFO Memory Aperture0 0x480 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO161 FIFO Memory Aperture0 0x484 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO162 FIFO Memory Aperture0 0x488 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO163 FIFO Memory Aperture0 0x48C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO164 FIFO Memory Aperture0 0x490 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO165 FIFO Memory Aperture0 0x494 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO166 FIFO Memory Aperture0 0x498 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO167 FIFO Memory Aperture0 0x49C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO168 FIFO Memory Aperture0 0x4A0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO169 FIFO Memory Aperture0 0x4A4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO17 FIFO Memory Aperture0 0x244 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO170 FIFO Memory Aperture0 0x4A8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO171 FIFO Memory Aperture0 0x4AC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO172 FIFO Memory Aperture0 0x4B0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO173 FIFO Memory Aperture0 0x4B4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO174 FIFO Memory Aperture0 0x4B8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO175 FIFO Memory Aperture0 0x4BC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO176 FIFO Memory Aperture0 0x4C0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO177 FIFO Memory Aperture0 0x4C4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO178 FIFO Memory Aperture0 0x4C8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO179 FIFO Memory Aperture0 0x4CC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO18 FIFO Memory Aperture0 0x248 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO180 FIFO Memory Aperture0 0x4D0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO181 FIFO Memory Aperture0 0x4D4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO182 FIFO Memory Aperture0 0x4D8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO183 FIFO Memory Aperture0 0x4DC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO184 FIFO Memory Aperture0 0x4E0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO185 FIFO Memory Aperture0 0x4E4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO186 FIFO Memory Aperture0 0x4E8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO187 FIFO Memory Aperture0 0x4EC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO188 FIFO Memory Aperture0 0x4F0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO189 FIFO Memory Aperture0 0x4F4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO19 FIFO Memory Aperture0 0x24C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO190 FIFO Memory Aperture0 0x4F8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO191 FIFO Memory Aperture0 0x4FC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO192 FIFO Memory Aperture0 0x500 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO193 FIFO Memory Aperture0 0x504 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO194 FIFO Memory Aperture0 0x508 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO195 FIFO Memory Aperture0 0x50C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO196 FIFO Memory Aperture0 0x510 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO197 FIFO Memory Aperture0 0x514 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO198 FIFO Memory Aperture0 0x518 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO199 FIFO Memory Aperture0 0x51C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO2 FIFO Memory Aperture0 0x208 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO20 FIFO Memory Aperture0 0x250 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO200 FIFO Memory Aperture0 0x520 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO201 FIFO Memory Aperture0 0x524 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO202 FIFO Memory Aperture0 0x528 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO203 FIFO Memory Aperture0 0x52C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO204 FIFO Memory Aperture0 0x530 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO205 FIFO Memory Aperture0 0x534 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO206 FIFO Memory Aperture0 0x538 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO207 FIFO Memory Aperture0 0x53C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO208 FIFO Memory Aperture0 0x540 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO209 FIFO Memory Aperture0 0x544 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO21 FIFO Memory Aperture0 0x254 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO210 FIFO Memory Aperture0 0x548 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO211 FIFO Memory Aperture0 0x54C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO212 FIFO Memory Aperture0 0x550 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO213 FIFO Memory Aperture0 0x554 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO214 FIFO Memory Aperture0 0x558 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO215 FIFO Memory Aperture0 0x55C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO216 FIFO Memory Aperture0 0x560 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO217 FIFO Memory Aperture0 0x564 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO218 FIFO Memory Aperture0 0x568 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO219 FIFO Memory Aperture0 0x56C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO22 FIFO Memory Aperture0 0x258 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO220 FIFO Memory Aperture0 0x570 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO221 FIFO Memory Aperture0 0x574 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO222 FIFO Memory Aperture0 0x578 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO223 FIFO Memory Aperture0 0x57C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO224 FIFO Memory Aperture0 0x580 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO225 FIFO Memory Aperture0 0x584 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO226 FIFO Memory Aperture0 0x588 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO227 FIFO Memory Aperture0 0x58C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO228 FIFO Memory Aperture0 0x590 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO229 FIFO Memory Aperture0 0x594 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO23 FIFO Memory Aperture0 0x25C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO230 FIFO Memory Aperture0 0x598 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO231 FIFO Memory Aperture0 0x59C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO232 FIFO Memory Aperture0 0x5A0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO233 FIFO Memory Aperture0 0x5A4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO234 FIFO Memory Aperture0 0x5A8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO235 FIFO Memory Aperture0 0x5AC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO236 FIFO Memory Aperture0 0x5B0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO237 FIFO Memory Aperture0 0x5B4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO238 FIFO Memory Aperture0 0x5B8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO239 FIFO Memory Aperture0 0x5BC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO24 FIFO Memory Aperture0 0x260 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO240 FIFO Memory Aperture0 0x5C0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO241 FIFO Memory Aperture0 0x5C4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO242 FIFO Memory Aperture0 0x5C8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO243 FIFO Memory Aperture0 0x5CC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO244 FIFO Memory Aperture0 0x5D0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO245 FIFO Memory Aperture0 0x5D4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO246 FIFO Memory Aperture0 0x5D8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO247 FIFO Memory Aperture0 0x5DC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO248 FIFO Memory Aperture0 0x5E0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO249 FIFO Memory Aperture0 0x5E4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO25 FIFO Memory Aperture0 0x264 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO250 FIFO Memory Aperture0 0x5E8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO251 FIFO Memory Aperture0 0x5EC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO252 FIFO Memory Aperture0 0x5F0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO253 FIFO Memory Aperture0 0x5F4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO254 FIFO Memory Aperture0 0x5F8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO255 FIFO Memory Aperture0 0x5FC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO26 FIFO Memory Aperture0 0x268 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO27 FIFO Memory Aperture0 0x26C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO28 FIFO Memory Aperture0 0x270 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO29 FIFO Memory Aperture0 0x274 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO3 FIFO Memory Aperture0 0x20C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO30 FIFO Memory Aperture0 0x278 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO31 FIFO Memory Aperture0 0x27C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO32 FIFO Memory Aperture0 0x280 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO33 FIFO Memory Aperture0 0x284 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO34 FIFO Memory Aperture0 0x288 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO35 FIFO Memory Aperture0 0x28C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO36 FIFO Memory Aperture0 0x290 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO37 FIFO Memory Aperture0 0x294 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO38 FIFO Memory Aperture0 0x298 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO39 FIFO Memory Aperture0 0x29C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO4 FIFO Memory Aperture0 0x210 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO40 FIFO Memory Aperture0 0x2A0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO41 FIFO Memory Aperture0 0x2A4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO42 FIFO Memory Aperture0 0x2A8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO43 FIFO Memory Aperture0 0x2AC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO44 FIFO Memory Aperture0 0x2B0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO45 FIFO Memory Aperture0 0x2B4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO46 FIFO Memory Aperture0 0x2B8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO47 FIFO Memory Aperture0 0x2BC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO48 FIFO Memory Aperture0 0x2C0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO49 FIFO Memory Aperture0 0x2C4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO5 FIFO Memory Aperture0 0x214 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO50 FIFO Memory Aperture0 0x2C8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO51 FIFO Memory Aperture0 0x2CC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO52 FIFO Memory Aperture0 0x2D0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO53 FIFO Memory Aperture0 0x2D4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO54 FIFO Memory Aperture0 0x2D8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO55 FIFO Memory Aperture0 0x2DC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO56 FIFO Memory Aperture0 0x2E0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO57 FIFO Memory Aperture0 0x2E4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO58 FIFO Memory Aperture0 0x2E8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO59 FIFO Memory Aperture0 0x2EC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO6 FIFO Memory Aperture0 0x218 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO60 FIFO Memory Aperture0 0x2F0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO61 FIFO Memory Aperture0 0x2F4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO62 FIFO Memory Aperture0 0x2F8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO63 FIFO Memory Aperture0 0x2FC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO64 FIFO Memory Aperture0 0x300 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO65 FIFO Memory Aperture0 0x304 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO66 FIFO Memory Aperture0 0x308 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO67 FIFO Memory Aperture0 0x30C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO68 FIFO Memory Aperture0 0x310 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO69 FIFO Memory Aperture0 0x314 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO7 FIFO Memory Aperture0 0x21C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO70 FIFO Memory Aperture0 0x318 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO71 FIFO Memory Aperture0 0x31C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO72 FIFO Memory Aperture0 0x320 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO73 FIFO Memory Aperture0 0x324 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO74 FIFO Memory Aperture0 0x328 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO75 FIFO Memory Aperture0 0x32C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO76 FIFO Memory Aperture0 0x330 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO77 FIFO Memory Aperture0 0x334 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO78 FIFO Memory Aperture0 0x338 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO79 FIFO Memory Aperture0 0x33C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO8 FIFO Memory Aperture0 0x220 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO80 FIFO Memory Aperture0 0x340 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO81 FIFO Memory Aperture0 0x344 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO82 FIFO Memory Aperture0 0x348 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO83 FIFO Memory Aperture0 0x34C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO84 FIFO Memory Aperture0 0x350 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO85 FIFO Memory Aperture0 0x354 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO86 FIFO Memory Aperture0 0x358 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO87 FIFO Memory Aperture0 0x35C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO88 FIFO Memory Aperture0 0x360 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO89 FIFO Memory Aperture0 0x364 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO9 FIFO Memory Aperture0 0x224 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO90 FIFO Memory Aperture0 0x368 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO91 FIFO Memory Aperture0 0x36C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO92 FIFO Memory Aperture0 0x370 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO93 FIFO Memory Aperture0 0x374 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO94 FIFO Memory Aperture0 0x378 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO95 FIFO Memory Aperture0 0x37C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO96 FIFO Memory Aperture0 0x380 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO97 FIFO Memory Aperture0 0x384 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO98 FIFO Memory Aperture0 0x388 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO99 FIFO Memory Aperture0 0x38C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO[0] FIFO Memory Aperture0 0x400 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[100] FIFO Memory Aperture0 0x11AE8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[101] FIFO Memory Aperture0 0x11E7C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[102] FIFO Memory Aperture0 0x12214 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[103] FIFO Memory Aperture0 0x125B0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[104] FIFO Memory Aperture0 0x12950 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[105] FIFO Memory Aperture0 0x12CF4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[106] FIFO Memory Aperture0 0x1309C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[107] FIFO Memory Aperture0 0x13448 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[108] FIFO Memory Aperture0 0x137F8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[109] FIFO Memory Aperture0 0x13BAC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[10] FIFO Memory Aperture0 0x18DC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[110] FIFO Memory Aperture0 0x13F64 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[111] FIFO Memory Aperture0 0x14320 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[112] FIFO Memory Aperture0 0x146E0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[113] FIFO Memory Aperture0 0x14AA4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[114] FIFO Memory Aperture0 0x14E6C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[115] FIFO Memory Aperture0 0x15238 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[116] FIFO Memory Aperture0 0x15608 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[117] FIFO Memory Aperture0 0x159DC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[118] FIFO Memory Aperture0 0x15DB4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[119] FIFO Memory Aperture0 0x16190 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[11] FIFO Memory Aperture0 0x1B08 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[120] FIFO Memory Aperture0 0x16570 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[121] FIFO Memory Aperture0 0x16954 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[122] FIFO Memory Aperture0 0x16D3C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[123] FIFO Memory Aperture0 0x17128 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[124] FIFO Memory Aperture0 0x17518 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[125] FIFO Memory Aperture0 0x1790C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[126] FIFO Memory Aperture0 0x17D04 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[127] FIFO Memory Aperture0 0x18100 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[128] FIFO Memory Aperture0 0x18500 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[129] FIFO Memory Aperture0 0x18904 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[12] FIFO Memory Aperture0 0x1D38 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[130] FIFO Memory Aperture0 0x18D0C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[131] FIFO Memory Aperture0 0x19118 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[132] FIFO Memory Aperture0 0x19528 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[133] FIFO Memory Aperture0 0x1993C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[134] FIFO Memory Aperture0 0x19D54 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[135] FIFO Memory Aperture0 0x1A170 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[136] FIFO Memory Aperture0 0x1A590 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[137] FIFO Memory Aperture0 0x1A9B4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[138] FIFO Memory Aperture0 0x1ADDC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[139] FIFO Memory Aperture0 0x1B208 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[13] FIFO Memory Aperture0 0x1F6C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[140] FIFO Memory Aperture0 0x1B638 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[141] FIFO Memory Aperture0 0x1BA6C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[142] FIFO Memory Aperture0 0x1BEA4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[143] FIFO Memory Aperture0 0x1C2E0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[144] FIFO Memory Aperture0 0x1C720 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[145] FIFO Memory Aperture0 0x1CB64 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[146] FIFO Memory Aperture0 0x1CFAC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[147] FIFO Memory Aperture0 0x1D3F8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[148] FIFO Memory Aperture0 0x1D848 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[149] FIFO Memory Aperture0 0x1DC9C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[14] FIFO Memory Aperture0 0x21A4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[150] FIFO Memory Aperture0 0x1E0F4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[151] FIFO Memory Aperture0 0x1E550 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[152] FIFO Memory Aperture0 0x1E9B0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[153] FIFO Memory Aperture0 0x1EE14 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[154] FIFO Memory Aperture0 0x1F27C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[155] FIFO Memory Aperture0 0x1F6E8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[156] FIFO Memory Aperture0 0x1FB58 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[157] FIFO Memory Aperture0 0x1FFCC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[158] FIFO Memory Aperture0 0x20444 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[159] FIFO Memory Aperture0 0x208C0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[15] FIFO Memory Aperture0 0x23E0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[160] FIFO Memory Aperture0 0x20D40 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[161] FIFO Memory Aperture0 0x211C4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[162] FIFO Memory Aperture0 0x2164C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[163] FIFO Memory Aperture0 0x21AD8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[164] FIFO Memory Aperture0 0x21F68 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[165] FIFO Memory Aperture0 0x223FC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[166] FIFO Memory Aperture0 0x22894 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[167] FIFO Memory Aperture0 0x22D30 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[168] FIFO Memory Aperture0 0x231D0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[169] FIFO Memory Aperture0 0x23674 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[16] FIFO Memory Aperture0 0x2620 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[170] FIFO Memory Aperture0 0x23B1C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[171] FIFO Memory Aperture0 0x23FC8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[172] FIFO Memory Aperture0 0x24478 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[173] FIFO Memory Aperture0 0x2492C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[174] FIFO Memory Aperture0 0x24DE4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[175] FIFO Memory Aperture0 0x252A0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[176] FIFO Memory Aperture0 0x25760 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[177] FIFO Memory Aperture0 0x25C24 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[178] FIFO Memory Aperture0 0x260EC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[179] FIFO Memory Aperture0 0x265B8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[17] FIFO Memory Aperture0 0x2864 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[180] FIFO Memory Aperture0 0x26A88 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[181] FIFO Memory Aperture0 0x26F5C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[182] FIFO Memory Aperture0 0x27434 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[183] FIFO Memory Aperture0 0x27910 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[184] FIFO Memory Aperture0 0x27DF0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[185] FIFO Memory Aperture0 0x282D4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[186] FIFO Memory Aperture0 0x287BC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[187] FIFO Memory Aperture0 0x28CA8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[188] FIFO Memory Aperture0 0x29198 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[189] FIFO Memory Aperture0 0x2968C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[18] FIFO Memory Aperture0 0x2AAC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[190] FIFO Memory Aperture0 0x29B84 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[191] FIFO Memory Aperture0 0x2A080 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[192] FIFO Memory Aperture0 0x2A580 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[193] FIFO Memory Aperture0 0x2AA84 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[194] FIFO Memory Aperture0 0x2AF8C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[195] FIFO Memory Aperture0 0x2B498 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[196] FIFO Memory Aperture0 0x2B9A8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[197] FIFO Memory Aperture0 0x2BEBC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[198] FIFO Memory Aperture0 0x2C3D4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[199] FIFO Memory Aperture0 0x2C8F0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[19] FIFO Memory Aperture0 0x2CF8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[1] FIFO Memory Aperture0 0x604 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[200] FIFO Memory Aperture0 0x2CE10 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[201] FIFO Memory Aperture0 0x2D334 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[202] FIFO Memory Aperture0 0x2D85C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[203] FIFO Memory Aperture0 0x2DD88 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[204] FIFO Memory Aperture0 0x2E2B8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[205] FIFO Memory Aperture0 0x2E7EC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[206] FIFO Memory Aperture0 0x2ED24 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[207] FIFO Memory Aperture0 0x2F260 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[208] FIFO Memory Aperture0 0x2F7A0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[209] FIFO Memory Aperture0 0x2FCE4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[20] FIFO Memory Aperture0 0x2F48 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[210] FIFO Memory Aperture0 0x3022C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[211] FIFO Memory Aperture0 0x30778 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[212] FIFO Memory Aperture0 0x30CC8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[213] FIFO Memory Aperture0 0x3121C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[214] FIFO Memory Aperture0 0x31774 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[215] FIFO Memory Aperture0 0x31CD0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[216] FIFO Memory Aperture0 0x32230 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[217] FIFO Memory Aperture0 0x32794 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[218] FIFO Memory Aperture0 0x32CFC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[219] FIFO Memory Aperture0 0x33268 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[21] FIFO Memory Aperture0 0x319C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[220] FIFO Memory Aperture0 0x337D8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[221] FIFO Memory Aperture0 0x33D4C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[222] FIFO Memory Aperture0 0x342C4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[223] FIFO Memory Aperture0 0x34840 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[224] FIFO Memory Aperture0 0x34DC0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[225] FIFO Memory Aperture0 0x35344 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[226] FIFO Memory Aperture0 0x358CC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[227] FIFO Memory Aperture0 0x35E58 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[228] FIFO Memory Aperture0 0x363E8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[229] FIFO Memory Aperture0 0x3697C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[22] FIFO Memory Aperture0 0x33F4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[230] FIFO Memory Aperture0 0x36F14 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[231] FIFO Memory Aperture0 0x374B0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[232] FIFO Memory Aperture0 0x37A50 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[233] FIFO Memory Aperture0 0x37FF4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[234] FIFO Memory Aperture0 0x3859C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[235] FIFO Memory Aperture0 0x38B48 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[236] FIFO Memory Aperture0 0x390F8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[237] FIFO Memory Aperture0 0x396AC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[238] FIFO Memory Aperture0 0x39C64 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[239] FIFO Memory Aperture0 0x3A220 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[23] FIFO Memory Aperture0 0x3650 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[240] FIFO Memory Aperture0 0x3A7E0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[241] FIFO Memory Aperture0 0x3ADA4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[242] FIFO Memory Aperture0 0x3B36C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[243] FIFO Memory Aperture0 0x3B938 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[244] FIFO Memory Aperture0 0x3BF08 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[245] FIFO Memory Aperture0 0x3C4DC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[246] FIFO Memory Aperture0 0x3CAB4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[247] FIFO Memory Aperture0 0x3D090 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[248] FIFO Memory Aperture0 0x3D670 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[249] FIFO Memory Aperture0 0x3DC54 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[24] FIFO Memory Aperture0 0x38B0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[250] FIFO Memory Aperture0 0x3E23C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[251] FIFO Memory Aperture0 0x3E828 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[252] FIFO Memory Aperture0 0x3EE18 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[253] FIFO Memory Aperture0 0x3F40C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[254] FIFO Memory Aperture0 0x3FA04 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[255] FIFO Memory Aperture0 0x40000 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[25] FIFO Memory Aperture0 0x3B14 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[26] FIFO Memory Aperture0 0x3D7C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[27] FIFO Memory Aperture0 0x3FE8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[28] FIFO Memory Aperture0 0x4258 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[29] FIFO Memory Aperture0 0x44CC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[2] FIFO Memory Aperture0 0x80C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[30] FIFO Memory Aperture0 0x4744 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[31] FIFO Memory Aperture0 0x49C0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[32] FIFO Memory Aperture0 0x4C40 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[33] FIFO Memory Aperture0 0x4EC4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[34] FIFO Memory Aperture0 0x514C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[35] FIFO Memory Aperture0 0x53D8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[36] FIFO Memory Aperture0 0x5668 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[37] FIFO Memory Aperture0 0x58FC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[38] FIFO Memory Aperture0 0x5B94 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[39] FIFO Memory Aperture0 0x5E30 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[3] FIFO Memory Aperture0 0xA18 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[40] FIFO Memory Aperture0 0x60D0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[41] FIFO Memory Aperture0 0x6374 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[42] FIFO Memory Aperture0 0x661C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[43] FIFO Memory Aperture0 0x68C8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[44] FIFO Memory Aperture0 0x6B78 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[45] FIFO Memory Aperture0 0x6E2C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[46] FIFO Memory Aperture0 0x70E4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[47] FIFO Memory Aperture0 0x73A0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[48] FIFO Memory Aperture0 0x7660 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[49] FIFO Memory Aperture0 0x7924 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[4] FIFO Memory Aperture0 0xC28 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[50] FIFO Memory Aperture0 0x7BEC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[51] FIFO Memory Aperture0 0x7EB8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[52] FIFO Memory Aperture0 0x8188 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[53] FIFO Memory Aperture0 0x845C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[54] FIFO Memory Aperture0 0x8734 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[55] FIFO Memory Aperture0 0x8A10 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[56] FIFO Memory Aperture0 0x8CF0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[57] FIFO Memory Aperture0 0x8FD4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[58] FIFO Memory Aperture0 0x92BC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[59] FIFO Memory Aperture0 0x95A8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[5] FIFO Memory Aperture0 0xE3C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[60] FIFO Memory Aperture0 0x9898 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[61] FIFO Memory Aperture0 0x9B8C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[62] FIFO Memory Aperture0 0x9E84 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[63] FIFO Memory Aperture0 0xA180 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[64] FIFO Memory Aperture0 0xA480 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[65] FIFO Memory Aperture0 0xA784 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[66] FIFO Memory Aperture0 0xAA8C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[67] FIFO Memory Aperture0 0xAD98 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[68] FIFO Memory Aperture0 0xB0A8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[69] FIFO Memory Aperture0 0xB3BC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[6] FIFO Memory Aperture0 0x1054 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[70] FIFO Memory Aperture0 0xB6D4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[71] FIFO Memory Aperture0 0xB9F0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[72] FIFO Memory Aperture0 0xBD10 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[73] FIFO Memory Aperture0 0xC034 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[74] FIFO Memory Aperture0 0xC35C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[75] FIFO Memory Aperture0 0xC688 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[76] FIFO Memory Aperture0 0xC9B8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[77] FIFO Memory Aperture0 0xCCEC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[78] FIFO Memory Aperture0 0xD024 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[79] FIFO Memory Aperture0 0xD360 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[7] FIFO Memory Aperture0 0x1270 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[80] FIFO Memory Aperture0 0xD6A0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[81] FIFO Memory Aperture0 0xD9E4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[82] FIFO Memory Aperture0 0xDD2C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[83] FIFO Memory Aperture0 0xE078 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[84] FIFO Memory Aperture0 0xE3C8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[85] FIFO Memory Aperture0 0xE71C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[86] FIFO Memory Aperture0 0xEA74 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[87] FIFO Memory Aperture0 0xEDD0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[88] FIFO Memory Aperture0 0xF130 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[89] FIFO Memory Aperture0 0xF494 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[8] FIFO Memory Aperture0 0x1490 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[90] FIFO Memory Aperture0 0xF7FC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[91] FIFO Memory Aperture0 0xFB68 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[92] FIFO Memory Aperture0 0xFED8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[93] FIFO Memory Aperture0 0x1024C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[94] FIFO Memory Aperture0 0x105C4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[95] FIFO Memory Aperture0 0x10940 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[96] FIFO Memory Aperture0 0x10CC0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[97] FIFO Memory Aperture0 0x11044 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[98] FIFO Memory Aperture0 0x113CC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[99] FIFO Memory Aperture0 0x11758 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[9] FIFO Memory Aperture0 0x16B4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write IDR Interrupt Disable Register 0x48 32 write-only n 0x0 0x0 ACKRCV Boot Acknowledge Interrupt Disable 28 1 write-only ACKRCVE Boot Acknowledge Error Interrupt Disable 29 1 write-only BLKE Data Block Ended Interrupt Disable 3 1 write-only BLKOVRE DMA Block Overrun Error Interrupt Disable 24 1 write-only CMDRDY Command Ready Interrupt Disable 0 1 write-only CSRCV Completion Signal received interrupt Disable 13 1 write-only CSTOE Completion Signal Time out Error Interrupt Disable 23 1 write-only DCRCE Data CRC Error Interrupt Disable 21 1 write-only DTIP Data Transfer in Progress Interrupt Disable 4 1 write-only DTOE Data Time-out Error Interrupt Disable 22 1 write-only FIFOEMPTY FIFO empty Interrupt Disable 26 1 write-only NOTBUSY Data Not Busy Interrupt Disable 5 1 write-only OVRE Overrun Interrupt Disable 30 1 write-only RCRCE Response CRC Error Interrupt Disable 18 1 write-only RDIRE Response Direction Error Interrupt Disable 17 1 write-only RENDE Response End Bit Error Interrupt Disable 19 1 write-only RINDE Response Index Error Interrupt Disable 16 1 write-only RTOE Response Time-out Error Interrupt Disable 20 1 write-only RXRDY Receiver Ready Interrupt Disable 1 1 write-only SDIOIRQA SDIO Interrupt for Slot A Interrupt Disable 8 1 write-only SDIOIRQB SDIO Interrupt for Slot B Interrupt Disable 9 1 write-only SDIOWAIT SDIO Read Wait Operation Status Interrupt Disable 12 1 write-only TXRDY Transmit Ready Interrupt Disable 2 1 write-only UNRE Underrun Interrupt Disable 31 1 write-only XFRDONE Transfer Done Interrupt Disable 27 1 write-only IER Interrupt Enable Register 0x44 32 write-only n 0x0 0x0 ACKRCV Boot Acknowledge Interrupt Enable 28 1 write-only ACKRCVE Boot Acknowledge Error Interrupt Enable 29 1 write-only BLKE Data Block Ended Interrupt Enable 3 1 write-only BLKOVRE DMA Block Overrun Error Interrupt Enable 24 1 write-only CMDRDY Command Ready Interrupt Enable 0 1 write-only CSRCV Completion Signal Received Interrupt Enable 13 1 write-only CSTOE Completion Signal Timeout Error Interrupt Enable 23 1 write-only DCRCE Data CRC Error Interrupt Enable 21 1 write-only DTIP Data Transfer in Progress Interrupt Enable 4 1 write-only DTOE Data Time-out Error Interrupt Enable 22 1 write-only FIFOEMPTY FIFO empty Interrupt enable 26 1 write-only NOTBUSY Data Not Busy Interrupt Enable 5 1 write-only OVRE Overrun Interrupt Enable 30 1 write-only RCRCE Response CRC Error Interrupt Enable 18 1 write-only RDIRE Response Direction Error Interrupt Enable 17 1 write-only RENDE Response End Bit Error Interrupt Enable 19 1 write-only RINDE Response Index Error Interrupt Enable 16 1 write-only RTOE Response Time-out Error Interrupt Enable 20 1 write-only RXRDY Receiver Ready Interrupt Enable 1 1 write-only SDIOIRQA SDIO Interrupt for Slot A Interrupt Enable 8 1 write-only SDIOIRQB SDIO Interrupt for Slot B Interrupt Enable 9 1 write-only SDIOWAIT SDIO Read Wait Operation Status Interrupt Enable 12 1 write-only TXRDY Transmit Ready Interrupt Enable 2 1 write-only UNRE Underrun Interrupt Enable 31 1 write-only XFRDONE Transfer Done Interrupt enable 27 1 write-only IMR Interrupt Mask Register 0x4C 32 read-only n 0x0 0x0 ACKRCV Boot Operation Acknowledge Received Interrupt Mask 28 1 read-only ACKRCVE Boot Operation Acknowledge Error Interrupt Mask 29 1 read-only BLKE Data Block Ended Interrupt Mask 3 1 read-only BLKOVRE DMA Block Overrun Error Interrupt Mask 24 1 read-only CMDRDY Command Ready Interrupt Mask 0 1 read-only CSRCV Completion Signal Received Interrupt Mask 13 1 read-only CSTOE Completion Signal Time-out Error Interrupt Mask 23 1 read-only DCRCE Data CRC Error Interrupt Mask 21 1 read-only DTIP Data Transfer in Progress Interrupt Mask 4 1 read-only DTOE Data Time-out Error Interrupt Mask 22 1 read-only FIFOEMPTY FIFO Empty Interrupt Mask 26 1 read-only NOTBUSY Data Not Busy Interrupt Mask 5 1 read-only OVRE Overrun Interrupt Mask 30 1 read-only RCRCE Response CRC Error Interrupt Mask 18 1 read-only RDIRE Response Direction Error Interrupt Mask 17 1 read-only RENDE Response End Bit Error Interrupt Mask 19 1 read-only RINDE Response Index Error Interrupt Mask 16 1 read-only RTOE Response Time-out Error Interrupt Mask 20 1 read-only RXRDY Receiver Ready Interrupt Mask 1 1 read-only SDIOIRQA SDIO Interrupt for Slot A Interrupt Mask 8 1 read-only SDIOIRQB SDIO Interrupt for Slot B Interrupt Mask 9 1 read-only SDIOWAIT SDIO Read Wait Operation Status Interrupt Mask 12 1 read-only TXRDY Transmit Ready Interrupt Mask 2 1 read-only UNRE Underrun Interrupt Mask 31 1 read-only XFRDONE Transfer Done Interrupt Mask 27 1 read-only MR Mode Register 0x4 32 read-write n 0x0 0x0 CLKDIV Clock Divider 0 8 read-write CLKODD Clock divider is odd 16 1 read-write FBYTE Force Byte Transfer 13 1 read-write PADV Padding Value 14 1 read-write PWSDIV Power Saving Divider 8 3 read-write RDPROOF Read Proof Enable 11 1 read-write WRPROOF Write Proof Enable 12 1 read-write RDR Receive Data Register 0x30 32 read-only n 0x0 0x0 DATA Data to Read 0 32 read-only RSPR0 Response Register 0x20 32 read-only n RSP Response 0 32 read-only RSPR1 Response Register 0x24 32 read-only n RSP Response 0 32 read-only RSPR2 Response Register 0x28 32 read-only n RSP Response 0 32 read-only RSPR3 Response Register 0x2C 32 read-only n RSP Response 0 32 read-only RSPR[0] Response Register 0x40 32 read-only n 0x0 0x0 RSP Response 0 32 read-only RSPR[1] Response Register 0x64 32 read-only n 0x0 0x0 RSP Response 0 32 read-only RSPR[2] Response Register 0x8C 32 read-only n 0x0 0x0 RSP Response 0 32 read-only RSPR[3] Response Register 0xB8 32 read-only n 0x0 0x0 RSP Response 0 32 read-only SDCR SD/SDIO Card Register 0xC 32 read-write n 0x0 0x0 SDCBUS SDCard/SDIO Bus Width 6 2 read-write 1 1 bit 0x0 4 4 bits 0x2 8 8 bits 0x3 SDCSEL SDCard/SDIO Slot 0 2 read-write SLOTA Slot A is selected. 0 SLOTB Slot B is selected. 1 SR Status Register 0x40 32 read-only n 0x0 0x0 ACKRCV Boot Operation Acknowledge Received (cleared on read) 28 1 read-only ACKRCVE Boot Operation Acknowledge Error (cleared on read) 29 1 read-only BLKE Data Block Ended (cleared on read) 3 1 read-only BLKOVRE DMA Block Overrun Error (cleared on read) 24 1 read-only CMDRDY Command Ready (cleared by writing in HSMCI_CMDR) 0 1 read-only CSRCV CE-ATA Completion Signal Received (cleared on read) 13 1 read-only CSTOE Completion Signal Time-out Error (cleared on read) 23 1 read-only DCRCE Data CRC Error (cleared on read) 21 1 read-only DTIP Data Transfer in Progress (cleared at the end of CRC16 calculation) 4 1 read-only DTOE Data Time-out Error (cleared on read) 22 1 read-only FIFOEMPTY FIFO empty flag 26 1 read-only NOTBUSY HSMCI Not Busy 5 1 read-only OVRE Overrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR or cleared on read if FERRCTRL = 0) 30 1 read-only RCRCE Response CRC Error (cleared by writing in HSMCI_CMDR) 18 1 read-only RDIRE Response Direction Error (cleared by writing in HSMCI_CMDR) 17 1 read-only RENDE Response End Bit Error (cleared by writing in HSMCI_CMDR) 19 1 read-only RINDE Response Index Error (cleared by writing in HSMCI_CMDR) 16 1 read-only RTOE Response Time-out Error (cleared by writing in HSMCI_CMDR) 20 1 read-only RXRDY Receiver Ready (cleared by reading HSMCI_RDR) 1 1 read-only SDIOIRQA SDIO Interrupt for Slot A (cleared on read) 8 1 read-only SDIOIRQB SDIO Interrupt for Slot B (cleared on read) 9 1 read-only SDIOWAIT SDIO Read Wait Operation Status 12 1 read-only TXRDY Transmit Ready (cleared by writing in HSMCI_TDR) 2 1 read-only UNRE Underrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR or cleared on read if FERRCTRL = 0) 31 1 read-only XFRDONE Transfer Done flag 27 1 read-only TDR Transmit Data Register 0x34 32 write-only n 0x0 0x0 DATA Data to Write 0 32 write-only WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protect Enable 0 1 read-write WPKEY Write Protect Key 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 0x4D4349 WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 read-only WPVSRC Write Protection Violation Source 8 16 read-only HSMCI1 High Speed MultiMedia Card Interface 1 HSMCI 0x0 0x0 0x50 registers n HSMCI1 36 ARGR Argument Register 0x10 32 read-write n 0x0 0x0 ARG Command Argument 0 32 read-write BLKR Block Register 0x18 32 read-write n 0x0 0x0 BCNT MMC/SDIO Block Count - SDIO Byte Count 0 16 read-write BLKLEN Data Block Length 16 16 read-write CFG Configuration Register 0x54 32 read-write n 0x0 0x0 FERRCTRL Flow Error flag reset control mode 4 1 read-write FIFOMODE HSMCI Internal FIFO control mode 0 1 read-write HSMODE High Speed Mode 8 1 read-write LSYNC Synchronize on the last block 12 1 read-write CMDR Command Register 0x14 32 write-only n 0x0 0x0 ATACS ATA with Command Completion Signal 26 1 write-only NORMAL Normal operation mode. 0 COMPLETION This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR). 1 BOOT_ACK Boot Operation Acknowledge 27 1 write-only CMDNB Command Number 0 6 write-only IOSPCMD SDIO Special Command 24 2 write-only STD Not an SDIO Special Command 0x0 SUSPEND SDIO Suspend Command 0x1 RESUME SDIO Resume Command 0x2 MAXLAT Max Latency for Command to Response 12 1 write-only 5 5-cycle max latency. 0 64 64-cycle max latency. 1 OPDCMD Open Drain Command 11 1 write-only PUSHPULL Push pull command. 0 OPENDRAIN Open drain command. 1 RSPTYP Response Type 6 2 write-only NORESP No response 0x0 48_BIT 48-bit response 0x1 136_BIT 136-bit response 0x2 R1B R1b response type 0x3 SPCMD Special Command 8 3 write-only STD Not a special CMD. 0x0 INIT Initialization CMD: 74 clock cycles for initialization sequence. 0x1 SYNC Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command. 0x2 CE_ATA CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line. 0x3 IT_CMD Interrupt command: Corresponds to the Interrupt Mode (CMD40). 0x4 IT_RESP Interrupt response: Corresponds to the Interrupt Mode (CMD40). 0x5 BOR Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly. 0x6 EBO End Boot Operation. This command allows the host processor to terminate the boot operation mode. 0x7 TRCMD Transfer Command 16 2 write-only NO_DATA No data transfer 0x0 START_DATA Start data transfer 0x1 STOP_DATA Stop data transfer 0x2 TRDIR Transfer Direction 18 1 write-only WRITE Write. 0 READ Read. 1 TRTYP Transfer Type 19 3 write-only SINGLE MMC/SD Card Single Block 0x0 MULTIPLE MMC/SD Card Multiple Block 0x1 STREAM MMC Stream 0x2 BYTE SDIO Byte 0x4 BLOCK SDIO Block 0x5 CR Control Register 0x0 32 write-only n 0x0 0x0 MCIDIS Multi-Media Interface Disable 1 1 write-only MCIEN Multi-Media Interface Enable 0 1 write-only PWSDIS Power Save Mode Disable 3 1 write-only PWSEN Power Save Mode Enable 2 1 write-only SWRST Software Reset 7 1 write-only CSTOR Completion Signal Timeout Register 0x1C 32 read-write n 0x0 0x0 CSTOCYC Completion Signal Timeout Cycle Number 0 4 read-write CSTOMUL Completion Signal Timeout Multiplier 4 3 read-write 1 CSTOCYC x 1 0x0 16 CSTOCYC x 16 0x1 128 CSTOCYC x 128 0x2 256 CSTOCYC x 256 0x3 1024 CSTOCYC x 1024 0x4 4096 CSTOCYC x 4096 0x5 65536 CSTOCYC x 65536 0x6 1048576 CSTOCYC x 1048576 0x7 DMA DMA Configuration Register 0x50 32 read-write n 0x0 0x0 CHKSIZE DMA Channel Read and Write Chunk Size 4 3 read-write 1 1 data available 0x0 2 2 data available 0x1 4 4 data available 0x2 8 8 data available 0x3 16 16 data available 0x4 DMAEN DMA Hardware Handshaking Enable 8 1 read-write DTOR Data Timeout Register 0x8 32 read-write n 0x0 0x0 DTOCYC Data Timeout Cycle Number 0 4 read-write DTOMUL Data Timeout Multiplier 4 3 read-write 1 DTOCYC 0x0 16 DTOCYC x 16 0x1 128 DTOCYC x 128 0x2 256 DTOCYC x 256 0x3 1024 DTOCYC x 1024 0x4 4096 DTOCYC x 4096 0x5 65536 DTOCYC x 65536 0x6 1048576 DTOCYC x 1048576 0x7 FIFO0 FIFO Memory Aperture0 0x200 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO1 FIFO Memory Aperture0 0x204 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO10 FIFO Memory Aperture0 0x228 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO100 FIFO Memory Aperture0 0x390 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO101 FIFO Memory Aperture0 0x394 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO102 FIFO Memory Aperture0 0x398 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO103 FIFO Memory Aperture0 0x39C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO104 FIFO Memory Aperture0 0x3A0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO105 FIFO Memory Aperture0 0x3A4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO106 FIFO Memory Aperture0 0x3A8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO107 FIFO Memory Aperture0 0x3AC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO108 FIFO Memory Aperture0 0x3B0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO109 FIFO Memory Aperture0 0x3B4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO11 FIFO Memory Aperture0 0x22C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO110 FIFO Memory Aperture0 0x3B8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO111 FIFO Memory Aperture0 0x3BC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO112 FIFO Memory Aperture0 0x3C0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO113 FIFO Memory Aperture0 0x3C4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO114 FIFO Memory Aperture0 0x3C8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO115 FIFO Memory Aperture0 0x3CC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO116 FIFO Memory Aperture0 0x3D0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO117 FIFO Memory Aperture0 0x3D4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO118 FIFO Memory Aperture0 0x3D8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO119 FIFO Memory Aperture0 0x3DC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO12 FIFO Memory Aperture0 0x230 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO120 FIFO Memory Aperture0 0x3E0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO121 FIFO Memory Aperture0 0x3E4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO122 FIFO Memory Aperture0 0x3E8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO123 FIFO Memory Aperture0 0x3EC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO124 FIFO Memory Aperture0 0x3F0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO125 FIFO Memory Aperture0 0x3F4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO126 FIFO Memory Aperture0 0x3F8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO127 FIFO Memory Aperture0 0x3FC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO128 FIFO Memory Aperture0 0x400 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO129 FIFO Memory Aperture0 0x404 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO13 FIFO Memory Aperture0 0x234 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO130 FIFO Memory Aperture0 0x408 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO131 FIFO Memory Aperture0 0x40C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO132 FIFO Memory Aperture0 0x410 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO133 FIFO Memory Aperture0 0x414 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO134 FIFO Memory Aperture0 0x418 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO135 FIFO Memory Aperture0 0x41C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO136 FIFO Memory Aperture0 0x420 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO137 FIFO Memory Aperture0 0x424 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO138 FIFO Memory Aperture0 0x428 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO139 FIFO Memory Aperture0 0x42C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO14 FIFO Memory Aperture0 0x238 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO140 FIFO Memory Aperture0 0x430 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO141 FIFO Memory Aperture0 0x434 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO142 FIFO Memory Aperture0 0x438 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO143 FIFO Memory Aperture0 0x43C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO144 FIFO Memory Aperture0 0x440 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO145 FIFO Memory Aperture0 0x444 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO146 FIFO Memory Aperture0 0x448 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO147 FIFO Memory Aperture0 0x44C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO148 FIFO Memory Aperture0 0x450 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO149 FIFO Memory Aperture0 0x454 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO15 FIFO Memory Aperture0 0x23C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO150 FIFO Memory Aperture0 0x458 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO151 FIFO Memory Aperture0 0x45C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO152 FIFO Memory Aperture0 0x460 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO153 FIFO Memory Aperture0 0x464 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO154 FIFO Memory Aperture0 0x468 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO155 FIFO Memory Aperture0 0x46C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO156 FIFO Memory Aperture0 0x470 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO157 FIFO Memory Aperture0 0x474 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO158 FIFO Memory Aperture0 0x478 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO159 FIFO Memory Aperture0 0x47C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO16 FIFO Memory Aperture0 0x240 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO160 FIFO Memory Aperture0 0x480 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO161 FIFO Memory Aperture0 0x484 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO162 FIFO Memory Aperture0 0x488 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO163 FIFO Memory Aperture0 0x48C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO164 FIFO Memory Aperture0 0x490 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO165 FIFO Memory Aperture0 0x494 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO166 FIFO Memory Aperture0 0x498 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO167 FIFO Memory Aperture0 0x49C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO168 FIFO Memory Aperture0 0x4A0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO169 FIFO Memory Aperture0 0x4A4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO17 FIFO Memory Aperture0 0x244 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO170 FIFO Memory Aperture0 0x4A8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO171 FIFO Memory Aperture0 0x4AC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO172 FIFO Memory Aperture0 0x4B0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO173 FIFO Memory Aperture0 0x4B4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO174 FIFO Memory Aperture0 0x4B8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO175 FIFO Memory Aperture0 0x4BC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO176 FIFO Memory Aperture0 0x4C0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO177 FIFO Memory Aperture0 0x4C4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO178 FIFO Memory Aperture0 0x4C8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO179 FIFO Memory Aperture0 0x4CC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO18 FIFO Memory Aperture0 0x248 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO180 FIFO Memory Aperture0 0x4D0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO181 FIFO Memory Aperture0 0x4D4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO182 FIFO Memory Aperture0 0x4D8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO183 FIFO Memory Aperture0 0x4DC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO184 FIFO Memory Aperture0 0x4E0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO185 FIFO Memory Aperture0 0x4E4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO186 FIFO Memory Aperture0 0x4E8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO187 FIFO Memory Aperture0 0x4EC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO188 FIFO Memory Aperture0 0x4F0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO189 FIFO Memory Aperture0 0x4F4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO19 FIFO Memory Aperture0 0x24C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO190 FIFO Memory Aperture0 0x4F8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO191 FIFO Memory Aperture0 0x4FC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO192 FIFO Memory Aperture0 0x500 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO193 FIFO Memory Aperture0 0x504 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO194 FIFO Memory Aperture0 0x508 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO195 FIFO Memory Aperture0 0x50C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO196 FIFO Memory Aperture0 0x510 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO197 FIFO Memory Aperture0 0x514 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO198 FIFO Memory Aperture0 0x518 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO199 FIFO Memory Aperture0 0x51C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO2 FIFO Memory Aperture0 0x208 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO20 FIFO Memory Aperture0 0x250 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO200 FIFO Memory Aperture0 0x520 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO201 FIFO Memory Aperture0 0x524 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO202 FIFO Memory Aperture0 0x528 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO203 FIFO Memory Aperture0 0x52C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO204 FIFO Memory Aperture0 0x530 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO205 FIFO Memory Aperture0 0x534 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO206 FIFO Memory Aperture0 0x538 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO207 FIFO Memory Aperture0 0x53C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO208 FIFO Memory Aperture0 0x540 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO209 FIFO Memory Aperture0 0x544 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO21 FIFO Memory Aperture0 0x254 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO210 FIFO Memory Aperture0 0x548 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO211 FIFO Memory Aperture0 0x54C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO212 FIFO Memory Aperture0 0x550 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO213 FIFO Memory Aperture0 0x554 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO214 FIFO Memory Aperture0 0x558 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO215 FIFO Memory Aperture0 0x55C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO216 FIFO Memory Aperture0 0x560 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO217 FIFO Memory Aperture0 0x564 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO218 FIFO Memory Aperture0 0x568 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO219 FIFO Memory Aperture0 0x56C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO22 FIFO Memory Aperture0 0x258 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO220 FIFO Memory Aperture0 0x570 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO221 FIFO Memory Aperture0 0x574 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO222 FIFO Memory Aperture0 0x578 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO223 FIFO Memory Aperture0 0x57C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO224 FIFO Memory Aperture0 0x580 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO225 FIFO Memory Aperture0 0x584 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO226 FIFO Memory Aperture0 0x588 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO227 FIFO Memory Aperture0 0x58C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO228 FIFO Memory Aperture0 0x590 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO229 FIFO Memory Aperture0 0x594 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO23 FIFO Memory Aperture0 0x25C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO230 FIFO Memory Aperture0 0x598 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO231 FIFO Memory Aperture0 0x59C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO232 FIFO Memory Aperture0 0x5A0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO233 FIFO Memory Aperture0 0x5A4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO234 FIFO Memory Aperture0 0x5A8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO235 FIFO Memory Aperture0 0x5AC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO236 FIFO Memory Aperture0 0x5B0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO237 FIFO Memory Aperture0 0x5B4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO238 FIFO Memory Aperture0 0x5B8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO239 FIFO Memory Aperture0 0x5BC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO24 FIFO Memory Aperture0 0x260 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO240 FIFO Memory Aperture0 0x5C0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO241 FIFO Memory Aperture0 0x5C4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO242 FIFO Memory Aperture0 0x5C8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO243 FIFO Memory Aperture0 0x5CC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO244 FIFO Memory Aperture0 0x5D0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO245 FIFO Memory Aperture0 0x5D4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO246 FIFO Memory Aperture0 0x5D8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO247 FIFO Memory Aperture0 0x5DC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO248 FIFO Memory Aperture0 0x5E0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO249 FIFO Memory Aperture0 0x5E4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO25 FIFO Memory Aperture0 0x264 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO250 FIFO Memory Aperture0 0x5E8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO251 FIFO Memory Aperture0 0x5EC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO252 FIFO Memory Aperture0 0x5F0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO253 FIFO Memory Aperture0 0x5F4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO254 FIFO Memory Aperture0 0x5F8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO255 FIFO Memory Aperture0 0x5FC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO26 FIFO Memory Aperture0 0x268 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO27 FIFO Memory Aperture0 0x26C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO28 FIFO Memory Aperture0 0x270 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO29 FIFO Memory Aperture0 0x274 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO3 FIFO Memory Aperture0 0x20C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO30 FIFO Memory Aperture0 0x278 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO31 FIFO Memory Aperture0 0x27C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO32 FIFO Memory Aperture0 0x280 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO33 FIFO Memory Aperture0 0x284 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO34 FIFO Memory Aperture0 0x288 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO35 FIFO Memory Aperture0 0x28C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO36 FIFO Memory Aperture0 0x290 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO37 FIFO Memory Aperture0 0x294 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO38 FIFO Memory Aperture0 0x298 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO39 FIFO Memory Aperture0 0x29C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO4 FIFO Memory Aperture0 0x210 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO40 FIFO Memory Aperture0 0x2A0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO41 FIFO Memory Aperture0 0x2A4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO42 FIFO Memory Aperture0 0x2A8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO43 FIFO Memory Aperture0 0x2AC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO44 FIFO Memory Aperture0 0x2B0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO45 FIFO Memory Aperture0 0x2B4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO46 FIFO Memory Aperture0 0x2B8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO47 FIFO Memory Aperture0 0x2BC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO48 FIFO Memory Aperture0 0x2C0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO49 FIFO Memory Aperture0 0x2C4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO5 FIFO Memory Aperture0 0x214 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO50 FIFO Memory Aperture0 0x2C8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO51 FIFO Memory Aperture0 0x2CC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO52 FIFO Memory Aperture0 0x2D0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO53 FIFO Memory Aperture0 0x2D4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO54 FIFO Memory Aperture0 0x2D8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO55 FIFO Memory Aperture0 0x2DC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO56 FIFO Memory Aperture0 0x2E0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO57 FIFO Memory Aperture0 0x2E4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO58 FIFO Memory Aperture0 0x2E8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO59 FIFO Memory Aperture0 0x2EC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO6 FIFO Memory Aperture0 0x218 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO60 FIFO Memory Aperture0 0x2F0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO61 FIFO Memory Aperture0 0x2F4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO62 FIFO Memory Aperture0 0x2F8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO63 FIFO Memory Aperture0 0x2FC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO64 FIFO Memory Aperture0 0x300 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO65 FIFO Memory Aperture0 0x304 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO66 FIFO Memory Aperture0 0x308 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO67 FIFO Memory Aperture0 0x30C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO68 FIFO Memory Aperture0 0x310 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO69 FIFO Memory Aperture0 0x314 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO7 FIFO Memory Aperture0 0x21C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO70 FIFO Memory Aperture0 0x318 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO71 FIFO Memory Aperture0 0x31C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO72 FIFO Memory Aperture0 0x320 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO73 FIFO Memory Aperture0 0x324 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO74 FIFO Memory Aperture0 0x328 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO75 FIFO Memory Aperture0 0x32C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO76 FIFO Memory Aperture0 0x330 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO77 FIFO Memory Aperture0 0x334 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO78 FIFO Memory Aperture0 0x338 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO79 FIFO Memory Aperture0 0x33C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO8 FIFO Memory Aperture0 0x220 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO80 FIFO Memory Aperture0 0x340 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO81 FIFO Memory Aperture0 0x344 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO82 FIFO Memory Aperture0 0x348 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO83 FIFO Memory Aperture0 0x34C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO84 FIFO Memory Aperture0 0x350 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO85 FIFO Memory Aperture0 0x354 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO86 FIFO Memory Aperture0 0x358 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO87 FIFO Memory Aperture0 0x35C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO88 FIFO Memory Aperture0 0x360 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO89 FIFO Memory Aperture0 0x364 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO9 FIFO Memory Aperture0 0x224 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO90 FIFO Memory Aperture0 0x368 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO91 FIFO Memory Aperture0 0x36C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO92 FIFO Memory Aperture0 0x370 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO93 FIFO Memory Aperture0 0x374 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO94 FIFO Memory Aperture0 0x378 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO95 FIFO Memory Aperture0 0x37C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO96 FIFO Memory Aperture0 0x380 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO97 FIFO Memory Aperture0 0x384 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO98 FIFO Memory Aperture0 0x388 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO99 FIFO Memory Aperture0 0x38C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO[0] FIFO Memory Aperture0 0x400 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[100] FIFO Memory Aperture0 0x11AE8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[101] FIFO Memory Aperture0 0x11E7C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[102] FIFO Memory Aperture0 0x12214 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[103] FIFO Memory Aperture0 0x125B0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[104] FIFO Memory Aperture0 0x12950 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[105] FIFO Memory Aperture0 0x12CF4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[106] FIFO Memory Aperture0 0x1309C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[107] FIFO Memory Aperture0 0x13448 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[108] FIFO Memory Aperture0 0x137F8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[109] FIFO Memory Aperture0 0x13BAC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[10] FIFO Memory Aperture0 0x18DC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[110] FIFO Memory Aperture0 0x13F64 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[111] FIFO Memory Aperture0 0x14320 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[112] FIFO Memory Aperture0 0x146E0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[113] FIFO Memory Aperture0 0x14AA4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[114] FIFO Memory Aperture0 0x14E6C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[115] FIFO Memory Aperture0 0x15238 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[116] FIFO Memory Aperture0 0x15608 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[117] FIFO Memory Aperture0 0x159DC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[118] FIFO Memory Aperture0 0x15DB4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[119] FIFO Memory Aperture0 0x16190 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[11] FIFO Memory Aperture0 0x1B08 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[120] FIFO Memory Aperture0 0x16570 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[121] FIFO Memory Aperture0 0x16954 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[122] FIFO Memory Aperture0 0x16D3C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[123] FIFO Memory Aperture0 0x17128 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[124] FIFO Memory Aperture0 0x17518 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[125] FIFO Memory Aperture0 0x1790C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[126] FIFO Memory Aperture0 0x17D04 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[127] FIFO Memory Aperture0 0x18100 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[128] FIFO Memory Aperture0 0x18500 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[129] FIFO Memory Aperture0 0x18904 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[12] FIFO Memory Aperture0 0x1D38 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[130] FIFO Memory Aperture0 0x18D0C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[131] FIFO Memory Aperture0 0x19118 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[132] FIFO Memory Aperture0 0x19528 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[133] FIFO Memory Aperture0 0x1993C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[134] FIFO Memory Aperture0 0x19D54 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[135] FIFO Memory Aperture0 0x1A170 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[136] FIFO Memory Aperture0 0x1A590 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[137] FIFO Memory Aperture0 0x1A9B4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[138] FIFO Memory Aperture0 0x1ADDC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[139] FIFO Memory Aperture0 0x1B208 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[13] FIFO Memory Aperture0 0x1F6C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[140] FIFO Memory Aperture0 0x1B638 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[141] FIFO Memory Aperture0 0x1BA6C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[142] FIFO Memory Aperture0 0x1BEA4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[143] FIFO Memory Aperture0 0x1C2E0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[144] FIFO Memory Aperture0 0x1C720 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[145] FIFO Memory Aperture0 0x1CB64 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[146] FIFO Memory Aperture0 0x1CFAC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[147] FIFO Memory Aperture0 0x1D3F8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[148] FIFO Memory Aperture0 0x1D848 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[149] FIFO Memory Aperture0 0x1DC9C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[14] FIFO Memory Aperture0 0x21A4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[150] FIFO Memory Aperture0 0x1E0F4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[151] FIFO Memory Aperture0 0x1E550 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[152] FIFO Memory Aperture0 0x1E9B0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[153] FIFO Memory Aperture0 0x1EE14 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[154] FIFO Memory Aperture0 0x1F27C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[155] FIFO Memory Aperture0 0x1F6E8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[156] FIFO Memory Aperture0 0x1FB58 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[157] FIFO Memory Aperture0 0x1FFCC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[158] FIFO Memory Aperture0 0x20444 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[159] FIFO Memory Aperture0 0x208C0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[15] FIFO Memory Aperture0 0x23E0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[160] FIFO Memory Aperture0 0x20D40 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[161] FIFO Memory Aperture0 0x211C4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[162] FIFO Memory Aperture0 0x2164C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[163] FIFO Memory Aperture0 0x21AD8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[164] FIFO Memory Aperture0 0x21F68 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[165] FIFO Memory Aperture0 0x223FC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[166] FIFO Memory Aperture0 0x22894 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[167] FIFO Memory Aperture0 0x22D30 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[168] FIFO Memory Aperture0 0x231D0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[169] FIFO Memory Aperture0 0x23674 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[16] FIFO Memory Aperture0 0x2620 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[170] FIFO Memory Aperture0 0x23B1C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[171] FIFO Memory Aperture0 0x23FC8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[172] FIFO Memory Aperture0 0x24478 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[173] FIFO Memory Aperture0 0x2492C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[174] FIFO Memory Aperture0 0x24DE4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[175] FIFO Memory Aperture0 0x252A0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[176] FIFO Memory Aperture0 0x25760 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[177] FIFO Memory Aperture0 0x25C24 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[178] FIFO Memory Aperture0 0x260EC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[179] FIFO Memory Aperture0 0x265B8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[17] FIFO Memory Aperture0 0x2864 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[180] FIFO Memory Aperture0 0x26A88 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[181] FIFO Memory Aperture0 0x26F5C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[182] FIFO Memory Aperture0 0x27434 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[183] FIFO Memory Aperture0 0x27910 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[184] FIFO Memory Aperture0 0x27DF0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[185] FIFO Memory Aperture0 0x282D4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[186] FIFO Memory Aperture0 0x287BC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[187] FIFO Memory Aperture0 0x28CA8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[188] FIFO Memory Aperture0 0x29198 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[189] FIFO Memory Aperture0 0x2968C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[18] FIFO Memory Aperture0 0x2AAC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[190] FIFO Memory Aperture0 0x29B84 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[191] FIFO Memory Aperture0 0x2A080 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[192] FIFO Memory Aperture0 0x2A580 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[193] FIFO Memory Aperture0 0x2AA84 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[194] FIFO Memory Aperture0 0x2AF8C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[195] FIFO Memory Aperture0 0x2B498 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[196] FIFO Memory Aperture0 0x2B9A8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[197] FIFO Memory Aperture0 0x2BEBC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[198] FIFO Memory Aperture0 0x2C3D4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[199] FIFO Memory Aperture0 0x2C8F0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[19] FIFO Memory Aperture0 0x2CF8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[1] FIFO Memory Aperture0 0x604 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[200] FIFO Memory Aperture0 0x2CE10 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[201] FIFO Memory Aperture0 0x2D334 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[202] FIFO Memory Aperture0 0x2D85C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[203] FIFO Memory Aperture0 0x2DD88 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[204] FIFO Memory Aperture0 0x2E2B8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[205] FIFO Memory Aperture0 0x2E7EC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[206] FIFO Memory Aperture0 0x2ED24 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[207] FIFO Memory Aperture0 0x2F260 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[208] FIFO Memory Aperture0 0x2F7A0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[209] FIFO Memory Aperture0 0x2FCE4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[20] FIFO Memory Aperture0 0x2F48 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[210] FIFO Memory Aperture0 0x3022C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[211] FIFO Memory Aperture0 0x30778 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[212] FIFO Memory Aperture0 0x30CC8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[213] FIFO Memory Aperture0 0x3121C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[214] FIFO Memory Aperture0 0x31774 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[215] FIFO Memory Aperture0 0x31CD0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[216] FIFO Memory Aperture0 0x32230 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[217] FIFO Memory Aperture0 0x32794 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[218] FIFO Memory Aperture0 0x32CFC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[219] FIFO Memory Aperture0 0x33268 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[21] FIFO Memory Aperture0 0x319C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[220] FIFO Memory Aperture0 0x337D8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[221] FIFO Memory Aperture0 0x33D4C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[222] FIFO Memory Aperture0 0x342C4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[223] FIFO Memory Aperture0 0x34840 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[224] FIFO Memory Aperture0 0x34DC0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[225] FIFO Memory Aperture0 0x35344 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[226] FIFO Memory Aperture0 0x358CC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[227] FIFO Memory Aperture0 0x35E58 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[228] FIFO Memory Aperture0 0x363E8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[229] FIFO Memory Aperture0 0x3697C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[22] FIFO Memory Aperture0 0x33F4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[230] FIFO Memory Aperture0 0x36F14 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[231] FIFO Memory Aperture0 0x374B0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[232] FIFO Memory Aperture0 0x37A50 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[233] FIFO Memory Aperture0 0x37FF4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[234] FIFO Memory Aperture0 0x3859C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[235] FIFO Memory Aperture0 0x38B48 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[236] FIFO Memory Aperture0 0x390F8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[237] FIFO Memory Aperture0 0x396AC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[238] FIFO Memory Aperture0 0x39C64 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[239] FIFO Memory Aperture0 0x3A220 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[23] FIFO Memory Aperture0 0x3650 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[240] FIFO Memory Aperture0 0x3A7E0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[241] FIFO Memory Aperture0 0x3ADA4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[242] FIFO Memory Aperture0 0x3B36C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[243] FIFO Memory Aperture0 0x3B938 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[244] FIFO Memory Aperture0 0x3BF08 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[245] FIFO Memory Aperture0 0x3C4DC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[246] FIFO Memory Aperture0 0x3CAB4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[247] FIFO Memory Aperture0 0x3D090 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[248] FIFO Memory Aperture0 0x3D670 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[249] FIFO Memory Aperture0 0x3DC54 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[24] FIFO Memory Aperture0 0x38B0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[250] FIFO Memory Aperture0 0x3E23C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[251] FIFO Memory Aperture0 0x3E828 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[252] FIFO Memory Aperture0 0x3EE18 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[253] FIFO Memory Aperture0 0x3F40C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[254] FIFO Memory Aperture0 0x3FA04 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[255] FIFO Memory Aperture0 0x40000 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[25] FIFO Memory Aperture0 0x3B14 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[26] FIFO Memory Aperture0 0x3D7C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[27] FIFO Memory Aperture0 0x3FE8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[28] FIFO Memory Aperture0 0x4258 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[29] FIFO Memory Aperture0 0x44CC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[2] FIFO Memory Aperture0 0x80C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[30] FIFO Memory Aperture0 0x4744 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[31] FIFO Memory Aperture0 0x49C0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[32] FIFO Memory Aperture0 0x4C40 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[33] FIFO Memory Aperture0 0x4EC4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[34] FIFO Memory Aperture0 0x514C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[35] FIFO Memory Aperture0 0x53D8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[36] FIFO Memory Aperture0 0x5668 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[37] FIFO Memory Aperture0 0x58FC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[38] FIFO Memory Aperture0 0x5B94 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[39] FIFO Memory Aperture0 0x5E30 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[3] FIFO Memory Aperture0 0xA18 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[40] FIFO Memory Aperture0 0x60D0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[41] FIFO Memory Aperture0 0x6374 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[42] FIFO Memory Aperture0 0x661C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[43] FIFO Memory Aperture0 0x68C8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[44] FIFO Memory Aperture0 0x6B78 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[45] FIFO Memory Aperture0 0x6E2C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[46] FIFO Memory Aperture0 0x70E4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[47] FIFO Memory Aperture0 0x73A0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[48] FIFO Memory Aperture0 0x7660 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[49] FIFO Memory Aperture0 0x7924 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[4] FIFO Memory Aperture0 0xC28 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[50] FIFO Memory Aperture0 0x7BEC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[51] FIFO Memory Aperture0 0x7EB8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[52] FIFO Memory Aperture0 0x8188 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[53] FIFO Memory Aperture0 0x845C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[54] FIFO Memory Aperture0 0x8734 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[55] FIFO Memory Aperture0 0x8A10 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[56] FIFO Memory Aperture0 0x8CF0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[57] FIFO Memory Aperture0 0x8FD4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[58] FIFO Memory Aperture0 0x92BC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[59] FIFO Memory Aperture0 0x95A8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[5] FIFO Memory Aperture0 0xE3C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[60] FIFO Memory Aperture0 0x9898 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[61] FIFO Memory Aperture0 0x9B8C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[62] FIFO Memory Aperture0 0x9E84 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[63] FIFO Memory Aperture0 0xA180 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[64] FIFO Memory Aperture0 0xA480 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[65] FIFO Memory Aperture0 0xA784 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[66] FIFO Memory Aperture0 0xAA8C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[67] FIFO Memory Aperture0 0xAD98 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[68] FIFO Memory Aperture0 0xB0A8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[69] FIFO Memory Aperture0 0xB3BC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[6] FIFO Memory Aperture0 0x1054 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[70] FIFO Memory Aperture0 0xB6D4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[71] FIFO Memory Aperture0 0xB9F0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[72] FIFO Memory Aperture0 0xBD10 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[73] FIFO Memory Aperture0 0xC034 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[74] FIFO Memory Aperture0 0xC35C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[75] FIFO Memory Aperture0 0xC688 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[76] FIFO Memory Aperture0 0xC9B8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[77] FIFO Memory Aperture0 0xCCEC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[78] FIFO Memory Aperture0 0xD024 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[79] FIFO Memory Aperture0 0xD360 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[7] FIFO Memory Aperture0 0x1270 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[80] FIFO Memory Aperture0 0xD6A0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[81] FIFO Memory Aperture0 0xD9E4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[82] FIFO Memory Aperture0 0xDD2C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[83] FIFO Memory Aperture0 0xE078 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[84] FIFO Memory Aperture0 0xE3C8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[85] FIFO Memory Aperture0 0xE71C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[86] FIFO Memory Aperture0 0xEA74 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[87] FIFO Memory Aperture0 0xEDD0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[88] FIFO Memory Aperture0 0xF130 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[89] FIFO Memory Aperture0 0xF494 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[8] FIFO Memory Aperture0 0x1490 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[90] FIFO Memory Aperture0 0xF7FC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[91] FIFO Memory Aperture0 0xFB68 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[92] FIFO Memory Aperture0 0xFED8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[93] FIFO Memory Aperture0 0x1024C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[94] FIFO Memory Aperture0 0x105C4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[95] FIFO Memory Aperture0 0x10940 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[96] FIFO Memory Aperture0 0x10CC0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[97] FIFO Memory Aperture0 0x11044 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[98] FIFO Memory Aperture0 0x113CC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[99] FIFO Memory Aperture0 0x11758 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write FIFO[9] FIFO Memory Aperture0 0x16B4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 read-write IDR Interrupt Disable Register 0x48 32 write-only n 0x0 0x0 ACKRCV Boot Acknowledge Interrupt Disable 28 1 write-only ACKRCVE Boot Acknowledge Error Interrupt Disable 29 1 write-only BLKE Data Block Ended Interrupt Disable 3 1 write-only BLKOVRE DMA Block Overrun Error Interrupt Disable 24 1 write-only CMDRDY Command Ready Interrupt Disable 0 1 write-only CSRCV Completion Signal received interrupt Disable 13 1 write-only CSTOE Completion Signal Time out Error Interrupt Disable 23 1 write-only DCRCE Data CRC Error Interrupt Disable 21 1 write-only DTIP Data Transfer in Progress Interrupt Disable 4 1 write-only DTOE Data Time-out Error Interrupt Disable 22 1 write-only FIFOEMPTY FIFO empty Interrupt Disable 26 1 write-only NOTBUSY Data Not Busy Interrupt Disable 5 1 write-only OVRE Overrun Interrupt Disable 30 1 write-only RCRCE Response CRC Error Interrupt Disable 18 1 write-only RDIRE Response Direction Error Interrupt Disable 17 1 write-only RENDE Response End Bit Error Interrupt Disable 19 1 write-only RINDE Response Index Error Interrupt Disable 16 1 write-only RTOE Response Time-out Error Interrupt Disable 20 1 write-only RXRDY Receiver Ready Interrupt Disable 1 1 write-only SDIOIRQA SDIO Interrupt for Slot A Interrupt Disable 8 1 write-only SDIOIRQB SDIO Interrupt for Slot B Interrupt Disable 9 1 write-only SDIOWAIT SDIO Read Wait Operation Status Interrupt Disable 12 1 write-only TXRDY Transmit Ready Interrupt Disable 2 1 write-only UNRE Underrun Interrupt Disable 31 1 write-only XFRDONE Transfer Done Interrupt Disable 27 1 write-only IER Interrupt Enable Register 0x44 32 write-only n 0x0 0x0 ACKRCV Boot Acknowledge Interrupt Enable 28 1 write-only ACKRCVE Boot Acknowledge Error Interrupt Enable 29 1 write-only BLKE Data Block Ended Interrupt Enable 3 1 write-only BLKOVRE DMA Block Overrun Error Interrupt Enable 24 1 write-only CMDRDY Command Ready Interrupt Enable 0 1 write-only CSRCV Completion Signal Received Interrupt Enable 13 1 write-only CSTOE Completion Signal Timeout Error Interrupt Enable 23 1 write-only DCRCE Data CRC Error Interrupt Enable 21 1 write-only DTIP Data Transfer in Progress Interrupt Enable 4 1 write-only DTOE Data Time-out Error Interrupt Enable 22 1 write-only FIFOEMPTY FIFO empty Interrupt enable 26 1 write-only NOTBUSY Data Not Busy Interrupt Enable 5 1 write-only OVRE Overrun Interrupt Enable 30 1 write-only RCRCE Response CRC Error Interrupt Enable 18 1 write-only RDIRE Response Direction Error Interrupt Enable 17 1 write-only RENDE Response End Bit Error Interrupt Enable 19 1 write-only RINDE Response Index Error Interrupt Enable 16 1 write-only RTOE Response Time-out Error Interrupt Enable 20 1 write-only RXRDY Receiver Ready Interrupt Enable 1 1 write-only SDIOIRQA SDIO Interrupt for Slot A Interrupt Enable 8 1 write-only SDIOIRQB SDIO Interrupt for Slot B Interrupt Enable 9 1 write-only SDIOWAIT SDIO Read Wait Operation Status Interrupt Enable 12 1 write-only TXRDY Transmit Ready Interrupt Enable 2 1 write-only UNRE Underrun Interrupt Enable 31 1 write-only XFRDONE Transfer Done Interrupt enable 27 1 write-only IMR Interrupt Mask Register 0x4C 32 read-only n 0x0 0x0 ACKRCV Boot Operation Acknowledge Received Interrupt Mask 28 1 read-only ACKRCVE Boot Operation Acknowledge Error Interrupt Mask 29 1 read-only BLKE Data Block Ended Interrupt Mask 3 1 read-only BLKOVRE DMA Block Overrun Error Interrupt Mask 24 1 read-only CMDRDY Command Ready Interrupt Mask 0 1 read-only CSRCV Completion Signal Received Interrupt Mask 13 1 read-only CSTOE Completion Signal Time-out Error Interrupt Mask 23 1 read-only DCRCE Data CRC Error Interrupt Mask 21 1 read-only DTIP Data Transfer in Progress Interrupt Mask 4 1 read-only DTOE Data Time-out Error Interrupt Mask 22 1 read-only FIFOEMPTY FIFO Empty Interrupt Mask 26 1 read-only NOTBUSY Data Not Busy Interrupt Mask 5 1 read-only OVRE Overrun Interrupt Mask 30 1 read-only RCRCE Response CRC Error Interrupt Mask 18 1 read-only RDIRE Response Direction Error Interrupt Mask 17 1 read-only RENDE Response End Bit Error Interrupt Mask 19 1 read-only RINDE Response Index Error Interrupt Mask 16 1 read-only RTOE Response Time-out Error Interrupt Mask 20 1 read-only RXRDY Receiver Ready Interrupt Mask 1 1 read-only SDIOIRQA SDIO Interrupt for Slot A Interrupt Mask 8 1 read-only SDIOIRQB SDIO Interrupt for Slot B Interrupt Mask 9 1 read-only SDIOWAIT SDIO Read Wait Operation Status Interrupt Mask 12 1 read-only TXRDY Transmit Ready Interrupt Mask 2 1 read-only UNRE Underrun Interrupt Mask 31 1 read-only XFRDONE Transfer Done Interrupt Mask 27 1 read-only MR Mode Register 0x4 32 read-write n 0x0 0x0 CLKDIV Clock Divider 0 8 read-write CLKODD Clock divider is odd 16 1 read-write FBYTE Force Byte Transfer 13 1 read-write PADV Padding Value 14 1 read-write PWSDIV Power Saving Divider 8 3 read-write RDPROOF Read Proof Enable 11 1 read-write WRPROOF Write Proof Enable 12 1 read-write RDR Receive Data Register 0x30 32 read-only n 0x0 0x0 DATA Data to Read 0 32 read-only RSPR0 Response Register 0x20 32 read-only n RSP Response 0 32 read-only RSPR1 Response Register 0x24 32 read-only n RSP Response 0 32 read-only RSPR2 Response Register 0x28 32 read-only n RSP Response 0 32 read-only RSPR3 Response Register 0x2C 32 read-only n RSP Response 0 32 read-only RSPR[0] Response Register 0x40 32 read-only n 0x0 0x0 RSP Response 0 32 read-only RSPR[1] Response Register 0x64 32 read-only n 0x0 0x0 RSP Response 0 32 read-only RSPR[2] Response Register 0x8C 32 read-only n 0x0 0x0 RSP Response 0 32 read-only RSPR[3] Response Register 0xB8 32 read-only n 0x0 0x0 RSP Response 0 32 read-only SDCR SD/SDIO Card Register 0xC 32 read-write n 0x0 0x0 SDCBUS SDCard/SDIO Bus Width 6 2 read-write 1 1 bit 0x0 4 4 bits 0x2 8 8 bits 0x3 SDCSEL SDCard/SDIO Slot 0 2 read-write SLOTA Slot A is selected. 0 SLOTB Slot B is selected. 1 SR Status Register 0x40 32 read-only n 0x0 0x0 ACKRCV Boot Operation Acknowledge Received (cleared on read) 28 1 read-only ACKRCVE Boot Operation Acknowledge Error (cleared on read) 29 1 read-only BLKE Data Block Ended (cleared on read) 3 1 read-only BLKOVRE DMA Block Overrun Error (cleared on read) 24 1 read-only CMDRDY Command Ready (cleared by writing in HSMCI_CMDR) 0 1 read-only CSRCV CE-ATA Completion Signal Received (cleared on read) 13 1 read-only CSTOE Completion Signal Time-out Error (cleared on read) 23 1 read-only DCRCE Data CRC Error (cleared on read) 21 1 read-only DTIP Data Transfer in Progress (cleared at the end of CRC16 calculation) 4 1 read-only DTOE Data Time-out Error (cleared on read) 22 1 read-only FIFOEMPTY FIFO empty flag 26 1 read-only NOTBUSY HSMCI Not Busy 5 1 read-only OVRE Overrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR or cleared on read if FERRCTRL = 0) 30 1 read-only RCRCE Response CRC Error (cleared by writing in HSMCI_CMDR) 18 1 read-only RDIRE Response Direction Error (cleared by writing in HSMCI_CMDR) 17 1 read-only RENDE Response End Bit Error (cleared by writing in HSMCI_CMDR) 19 1 read-only RINDE Response Index Error (cleared by writing in HSMCI_CMDR) 16 1 read-only RTOE Response Time-out Error (cleared by writing in HSMCI_CMDR) 20 1 read-only RXRDY Receiver Ready (cleared by reading HSMCI_RDR) 1 1 read-only SDIOIRQA SDIO Interrupt for Slot A (cleared on read) 8 1 read-only SDIOIRQB SDIO Interrupt for Slot B (cleared on read) 9 1 read-only SDIOWAIT SDIO Read Wait Operation Status 12 1 read-only TXRDY Transmit Ready (cleared by writing in HSMCI_TDR) 2 1 read-only UNRE Underrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR or cleared on read if FERRCTRL = 0) 31 1 read-only XFRDONE Transfer Done flag 27 1 read-only TDR Transmit Data Register 0x34 32 write-only n 0x0 0x0 DATA Data to Write 0 32 write-only WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protect Enable 0 1 read-write WPKEY Write Protect Key 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 0x4D4349 WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 read-only WPVSRC Write Protection Violation Source 8 16 read-only ICM Integrity Check Monitor ICM 0x0 0x0 0x50 registers n ICM 9 CFG Configuration Register 0x0 32 read-write n 0x0 0x0 ASCD Automatic Switch To Compare Digest 8 1 read-write BBC Bus Burden Control 4 4 read-write DUALBUFF Dual Input Buffer 9 1 read-write EOMDIS End of Monitoring Disable 1 1 read-write SLBDIS Secondary List Branching Disable 2 1 read-write UALGO User SHA Algorithm 13 3 read-write SHA1 SHA1 algorithm processed 0x0 SHA256 SHA256 algorithm processed 0x1 SHA224 SHA224 algorithm processed 0x4 UIHASH User Initial Hash Value 12 1 read-write WBDIS Write Back Disable 0 1 read-write CTRL Control Register 0x4 32 write-only n 0x0 0x0 DISABLE ICM Disable Register 1 1 write-only ENABLE ICM Enable 0 1 write-only REHASH Recompute Internal Hash 4 4 write-only RMDIS Region Monitoring Disable 8 4 write-only RMEN Region Monitoring Enable 12 4 write-only SWRST Software Reset 2 1 write-only DSCR Region Descriptor Area Start Address Register 0x30 32 read-write n 0x0 0x0 DASA Descriptor Area Start Address 6 26 read-write HASH Region Hash Area Start Address Register 0x34 32 read-write n 0x0 0x0 HASA Hash Area Start Address 7 25 read-write IDR Interrupt Disable Register 0x14 32 write-only n 0x0 0x0 RBE Region Bus Error Interrupt Disable 8 4 write-only RDM Region Digest Mismatch Interrupt Disable 4 4 write-only REC Region End bit Condition detected Interrupt Disable 16 4 write-only RHC Region Hash Completed Interrupt Disable 0 4 write-only RSU Region Status Updated Interrupt Disable 20 4 write-only RWC Region Wrap Condition Detected Interrupt Disable 12 4 write-only URAD Undefined Register Access Detection Interrupt Disable 24 1 write-only IER Interrupt Enable Register 0x10 32 write-only n 0x0 0x0 RBE Region Bus Error Interrupt Enable 8 4 write-only RDM Region Digest Mismatch Interrupt Enable 4 4 write-only REC Region End bit Condition Detected Interrupt Enable 16 4 write-only RHC Region Hash Completed Interrupt Enable 0 4 write-only RSU Region Status Updated Interrupt Disable 20 4 write-only RWC Region Wrap Condition detected Interrupt Enable 12 4 write-only URAD Undefined Register Access Detection Interrupt Enable 24 1 write-only IMR Interrupt Mask Register 0x18 32 read-only n 0x0 0x0 RBE Region Bus Error Interrupt Mask 8 4 read-only RDM Region Digest Mismatch Interrupt Mask 4 4 read-only REC Region End bit Condition Detected Interrupt Mask 16 4 read-only RHC Region Hash Completed Interrupt Mask 0 4 read-only RSU Region Status Updated Interrupt Mask 20 4 read-only RWC Region Wrap Condition Detected Interrupt Mask 12 4 read-only URAD Undefined Register Access Detection Interrupt Mask 24 1 read-only ISR Interrupt Status Register 0x1C 32 read-only n 0x0 0x0 RBE Region Bus Error 8 4 read-only RDM Region Digest Mismatch 4 4 read-only REC Region End bit Condition Detected 16 4 read-only RHC Region Hash Completed 0 4 read-only RSU Region Status Updated Detected 20 4 read-only RWC Region Wrap Condition Detected 12 4 read-only URAD Undefined Register Access Detection Status 24 1 read-only SR Status Register 0x8 32 read-only n 0x0 0x0 ENABLE ICM Controller Enable Register 0 1 read-only RAWRMDIS Region Monitoring Disabled Raw Status 8 4 read-only RMDIS Region Monitoring Disabled Status 12 4 read-only UASR Undefined Access Status Register 0x20 32 read-only n 0x0 0x0 URAT Undefined Register Access Trace 0 3 read-only UNSPEC_STRUCT_MEMBER Unspecified structure member set to one detected when the descriptor is loaded. 0x0 ICM_CFG_MODIFIED ICM_CFG modified during active monitoring. 0x1 ICM_DSCR_MODIFIED ICM_DSCR modified during active monitoring. 0x2 ICM_HASH_MODIFIED ICM_HASH modified during active monitoring 0x3 READ_ACCESS Write-only register read access 0x4 UIHVAL0 User Initial Hash Value 0 Register 0x38 32 write-only n VAL Initial Hash Value 0 32 write-only UIHVAL1 User Initial Hash Value 0 Register 0x3C 32 write-only n VAL Initial Hash Value 0 32 write-only UIHVAL2 User Initial Hash Value 0 Register 0x40 32 write-only n VAL Initial Hash Value 0 32 write-only UIHVAL3 User Initial Hash Value 0 Register 0x44 32 write-only n VAL Initial Hash Value 0 32 write-only UIHVAL4 User Initial Hash Value 0 Register 0x48 32 write-only n VAL Initial Hash Value 0 32 write-only UIHVAL5 User Initial Hash Value 0 Register 0x4C 32 write-only n VAL Initial Hash Value 0 32 write-only UIHVAL6 User Initial Hash Value 0 Register 0x50 32 write-only n VAL Initial Hash Value 0 32 write-only UIHVAL7 User Initial Hash Value 0 Register 0x54 32 write-only n VAL Initial Hash Value 0 32 write-only UIHVAL[0] User Initial Hash Value 0 Register 0x70 32 write-only n 0x0 0x0 VAL Initial Hash Value 0 32 write-only UIHVAL[1] User Initial Hash Value 0 Register 0xAC 32 write-only n 0x0 0x0 VAL Initial Hash Value 0 32 write-only UIHVAL[2] User Initial Hash Value 0 Register 0xEC 32 write-only n 0x0 0x0 VAL Initial Hash Value 0 32 write-only UIHVAL[3] User Initial Hash Value 0 Register 0x130 32 write-only n 0x0 0x0 VAL Initial Hash Value 0 32 write-only UIHVAL[4] User Initial Hash Value 0 Register 0x178 32 write-only n 0x0 0x0 VAL Initial Hash Value 0 32 write-only UIHVAL[5] User Initial Hash Value 0 Register 0x1C4 32 write-only n 0x0 0x0 VAL Initial Hash Value 0 32 write-only UIHVAL[6] User Initial Hash Value 0 Register 0x214 32 write-only n 0x0 0x0 VAL Initial Hash Value 0 32 write-only UIHVAL[7] User Initial Hash Value 0 Register 0x268 32 write-only n 0x0 0x0 VAL Initial Hash Value 0 32 write-only ISI Image Sensor Interface ISI 0x0 0x0 0x50 registers n ISI 52 CFG1 ISI Configuration 1 Register 0x0 32 read-write n 0x0 0x0 CRC_SYNC Embedded Synchronization Correction 7 1 read-write DISCR Disable Codec Request 11 1 read-write EMB_SYNC Embedded Synchronization 6 1 read-write FRATE Frame Rate [0..7] 8 3 read-write FULL Full Mode is Allowed 12 1 read-write HSYNC_POL Horizontal Synchronization Polarity 2 1 read-write PIXCLK_POL Pixel Clock Polarity 4 1 read-write SFD Start of Frame Delay 24 8 read-write SLD Start of Line Delay 16 8 read-write THMASK Threshold Mask 13 2 read-write BEATS_4 Only 4 beats AHB burst allowed 0x0 BEATS_8 Only 4 and 8 beats AHB burst allowed 0x1 BEATS_16 4, 8 and 16 beats AHB burst allowed 0x2 VSYNC_POL Vertical Synchronization Polarity 3 1 read-write CFG2 ISI Configuration 2 Register 0x4 32 read-write n 0x0 0x0 COL_SPACE Color Space for the Image Data 15 1 read-write GRAYSCALE Grayscale Mode Format Enable 13 1 read-write GS_MODE Grayscale Pixel Format Mode 11 1 read-write IM_HSIZE Horizontal Size of the Image Sensor [0..2047] 16 11 read-write IM_VSIZE Vertical Size of the Image Sensor [0..2047] 0 11 read-write RGB_CFG RGB Pixel Mapping Configuration 30 2 read-write DEFAULT Byte 0 R/G(MSB)Byte 1 G(LSB)/BByte 2 R/G(MSB)Byte 3 G(LSB)/B 0x0 MODE1 Byte 0 B/G(MSB)Byte 1 G(LSB)/RByte 2 B/G(MSB)Byte 3 G(LSB)/R 0x1 MODE2 Byte 0 G(LSB)/RByte 1 B/G(MSB)Byte 2 G(LSB)/RByte 3 B/G(MSB) 0x2 MODE3 Byte 0 G(LSB)/BByte 1 R/G(MSB)Byte 2 G(LSB)/BByte 3 R/G(MSB) 0x3 RGB_MODE RGB Input Mode 12 1 read-write RGB_SWAP RGB Format Swap Mode 14 1 read-write YCC_SWAP YCrCb Format Swap Mode 28 2 read-write DEFAULT Byte 0 Cb(i)Byte 1 Y(i)Byte 2 Cr(i)Byte 3 Y(i+1) 0x0 MODE1 Byte 0 Cr(i)Byte 1 Y(i)Byte 2 Cb(i)Byte 3 Y(i+1) 0x1 MODE2 Byte 0 Y(i)Byte 1 Cb(i)Byte 2 Y(i+1)Byte 3 Cr(i) 0x2 MODE3 Byte 0 Y(i)Byte 1 Cr(i)Byte 2 Y(i+1)Byte 3 Cb(i) 0x3 CR ISI Control Register 0x24 32 write-only n 0x0 0x0 ISI_CDC ISI Codec Request 8 1 write-only ISI_DIS ISI Module Disable Request 1 1 write-only ISI_EN ISI Module Enable Request 0 1 write-only ISI_SRST ISI Software Reset Request 2 1 write-only DMA_CHDR DMA Channel Disable Register 0x3C 32 write-only n 0x0 0x0 C_CH_DIS Codec Channel Disable Request 1 1 write-only P_CH_DIS Preview Channel Disable Request 0 1 write-only DMA_CHER DMA Channel Enable Register 0x38 32 write-only n 0x0 0x0 C_CH_EN Codec Channel Enable 1 1 write-only P_CH_EN Preview Channel Enable 0 1 write-only DMA_CHSR DMA Channel Status Register 0x40 32 read-only n 0x0 0x0 C_CH_S Code DMA Channel Status 1 1 read-only P_CH_S Preview DMA Channel Status 0 1 read-only DMA_C_ADDR DMA Codec Base Address Register 0x50 32 read-write n 0x0 0x0 C_ADDR Codec Image Base Address 2 30 read-write DMA_C_CTRL DMA Codec Control Register 0x54 32 read-write n 0x0 0x0 C_DONE Codec Transfer Done 3 1 read-write C_FETCH Descriptor Fetch Control Bit 0 1 read-write C_IEN Transfer Done Flag Control 2 1 read-write C_WB Descriptor Writeback Control Bit 1 1 read-write DMA_C_DSCR DMA Codec Descriptor Address Register 0x58 32 read-write n 0x0 0x0 C_DSCR Codec Descriptor Base Address 2 30 read-write DMA_P_ADDR DMA Preview Base Address Register 0x44 32 read-write n 0x0 0x0 P_ADDR Preview Image Base Address 2 30 read-write DMA_P_CTRL DMA Preview Control Register 0x48 32 read-write n 0x0 0x0 P_DONE Preview Transfer Done 3 1 read-write P_FETCH Descriptor Fetch Control Bit 0 1 read-write P_IEN Transfer Done Flag Control 2 1 read-write P_WB Descriptor Writeback Control Bit 1 1 read-write DMA_P_DSCR DMA Preview Descriptor Address Register 0x4C 32 read-write n 0x0 0x0 P_DSCR Preview Descriptor Base Address 2 30 read-write IDR ISI Interrupt Disable Register 0x30 32 write-only n 0x0 0x0 CRC_ERR Embedded Synchronization CRC Error Interrupt Disable 26 1 write-only CXFR_DONE Codec DMA Transfer Done Interrupt Disable 17 1 write-only C_OVR Codec Datapath Overflow Interrupt Disable 25 1 write-only DIS_DONE Disable Done Interrupt Disable 1 1 write-only FR_OVR Frame Rate Overflow Interrupt Disable 27 1 write-only PXFR_DONE Preview DMA Transfer Done Interrupt Disable 16 1 write-only P_OVR Preview Datapath Overflow Interrupt Disable 24 1 write-only SRST Software Reset Interrupt Disable 2 1 write-only VSYNC Vertical Synchronization Interrupt Disable 10 1 write-only IER ISI Interrupt Enable Register 0x2C 32 write-only n 0x0 0x0 CRC_ERR Embedded Synchronization CRC Error Interrupt Enable 26 1 write-only CXFR_DONE Codec DMA Transfer Done Interrupt Enable 17 1 write-only C_OVR Codec Datapath Overflow Interrupt Enable 25 1 write-only DIS_DONE Disable Done Interrupt Enable 1 1 write-only FR_OVR Frame Rate Overflow Interrupt Enable 27 1 write-only PXFR_DONE Preview DMA Transfer Done Interrupt Enable 16 1 write-only P_OVR Preview Datapath Overflow Interrupt Enable 24 1 write-only SRST Software Reset Interrupt Enable 2 1 write-only VSYNC Vertical Synchronization Interrupt Enable 10 1 write-only IMR ISI Interrupt Mask Register 0x34 32 read-only n 0x0 0x0 CRC_ERR CRC Synchronization Error 26 1 read-only CXFR_DONE Codec DMA Transfer Completed 17 1 read-only C_OVR Codec FIFO Overflow 25 1 read-only DIS_DONE Module Disable Operation Completed 1 1 read-only FR_OVR Frame Rate Overrun 27 1 read-only PXFR_DONE Preview DMA Transfer Completed 16 1 read-only P_OVR Preview FIFO Overflow 24 1 read-only SRST Software Reset Completed 2 1 read-only VSYNC Vertical Synchronization 10 1 read-only PDECF ISI Preview Decimation Factor Register 0xC 32 read-write n 0x0 0x0 DEC_FACTOR Decimation Factor 0 8 read-write PSIZE ISI Preview Size Register 0x8 32 read-write n 0x0 0x0 PREV_HSIZE Horizontal Size for the Preview Path 16 10 read-write PREV_VSIZE Vertical Size for the Preview Path 0 10 read-write R2Y_SET0 ISI Color Space Conversion RGB To YCrCb Set 0 Register 0x18 32 read-write n 0x0 0x0 C0 Color Space Conversion Matrix Coefficient C0 0 7 read-write C1 Color Space Conversion Matrix Coefficient C1 8 7 read-write C2 Color Space Conversion Matrix Coefficient C2 16 7 read-write Roff Color Space Conversion Red Component Offset 24 1 read-write R2Y_SET1 ISI Color Space Conversion RGB To YCrCb Set 1 Register 0x1C 32 read-write n 0x0 0x0 C3 Color Space Conversion Matrix Coefficient C3 0 7 read-write C4 Color Space Conversion Matrix Coefficient C4 8 7 read-write C5 Color Space Conversion Matrix Coefficient C5 16 7 read-write Goff Color Space Conversion Green Component Offset 24 1 read-write R2Y_SET2 ISI Color Space Conversion RGB To YCrCb Set 2 Register 0x20 32 read-write n 0x0 0x0 Boff Color Space Conversion Blue Component Offset 24 1 read-write C6 Color Space Conversion Matrix Coefficient C6 0 7 read-write C7 Color Space Conversion Matrix Coefficient C7 8 7 read-write C8 Color Space Conversion Matrix Coefficient C8 16 7 read-write SR ISI Status Register 0x28 32 read-only n 0x0 0x0 CDC_PND Pending Codec Request 8 1 read-only CRC_ERR CRC Synchronization Error (cleared on read) 26 1 read-only CXFR_DONE Codec DMA Transfer has Terminated (cleared on read) 17 1 read-only C_OVR Codec Datapath Overflow (cleared on read) 25 1 read-only DIS_DONE Module Disable Request has Terminated (cleared on read) 1 1 read-only ENABLE Module Enable 0 1 read-only FR_OVR Frame Rate Overrun (cleared on read) 27 1 read-only PXFR_DONE Preview DMA Transfer has Terminated (cleared on read) 16 1 read-only P_OVR Preview Datapath Overflow (cleared on read) 24 1 read-only SIP Synchronization in Progress 19 1 read-only SRST Module Software Reset Request has Terminated (cleared on read) 2 1 read-only VSYNC Vertical Synchronization (cleared on read) 10 1 read-only WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 read-write WPKEY Write Protection Key Password 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 0x495349 WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 read-only WPVSRC Write Protection Violation Source 8 16 read-only Y2R_SET0 ISI Color Space Conversion YCrCb To RGB Set 0 Register 0x10 32 read-write n 0x0 0x0 C0 Color Space Conversion Matrix Coefficient C0 0 8 read-write C1 Color Space Conversion Matrix Coefficient C1 8 8 read-write C2 Color Space Conversion Matrix Coefficient C2 16 8 read-write C3 Color Space Conversion Matrix Coefficient C3 24 8 read-write Y2R_SET1 ISI Color Space Conversion YCrCb To RGB Set 1 Register 0x14 32 read-write n 0x0 0x0 C4 Color Space Conversion Matrix Coefficient C4 0 9 read-write Cboff Color Space Conversion Blue Chrominance Default Offset 14 1 read-write Croff Color Space Conversion Red Chrominance Default Offset 13 1 read-write Yoff Color Space Conversion Luminance Default Offset 12 1 read-write L2CC L2 Cache Controller L2CC 0x0 0x0 0x100000 registers n L2CC 67 ACR Auxiliary Control Register 0x104 32 read-write n 0x0 0x0 ASS Associativity 16 1 read-write CRPOL Cache Replacement Policy 25 1 read-write DPEN Data Prefetch Enable 28 1 read-write EMBEN Event Monitor Bus Enable 20 1 read-write EXCC Exclusive Cache Configuration 12 1 read-write FWA Force Write Allocate 23 2 read-write HPSO High Priority for SO and Dev Reads Enable 10 1 read-write IPEN Instruction Prefetch Enable 29 1 read-write NSIAC Non-Secure Interrupt Access Control 27 1 read-write NSLEN Non-Secure Lockdown Enable 26 1 read-write PEN Parity Enable 21 1 read-write SAIE Shared Attribute Invalidate Enable 13 1 read-write SAOEN Shared Attribute Override Enable 22 1 read-write SBDLE Store Buffer Device Limitation Enable 11 1 read-write WAYSIZE Way Size 17 3 read-write 16KB_WAY 16-Kbyte way set associative 0x1 CIIR Clean Invalidate Index Register 0x7F8 32 read-write n 0x0 0x0 C Cache Synchronization Status 0 1 read-write IDX Index Number 5 9 read-write WAY Way Number 28 3 read-write CIPALR Clean Invalidate Physical Address Line Register 0x7F0 32 read-write n 0x0 0x0 C Cache Synchronization Status 0 1 read-write IDX Index Number 5 9 read-write TAG Tag Number 14 18 read-write CIR Clean Index Register 0x7B8 32 read-write n 0x0 0x0 C Cache Synchronization Status 0 1 read-write IDX Index number 5 9 read-write WAY Way number 28 3 read-write CIWR Clean Invalidate Way Register 0x7FC 32 read-write n 0x0 0x0 WAY0 Clean Invalidate Way Number 0 0 1 read-write WAY1 Clean Invalidate Way Number 1 1 1 read-write WAY2 Clean Invalidate Way Number 2 2 1 read-write WAY3 Clean Invalidate Way Number 3 3 1 read-write WAY4 Clean Invalidate Way Number 4 4 1 read-write WAY5 Clean Invalidate Way Number 5 5 1 read-write WAY6 Clean Invalidate Way Number 6 6 1 read-write WAY7 Clean Invalidate Way Number 7 7 1 read-write CPALR Clean Physical Address Line Register 0x7B0 32 read-write n 0x0 0x0 C Cache Synchronization Status 0 1 read-write IDX Index number 5 9 read-write TAG Tag number 14 18 read-write CR Control Register 0x100 32 read-write n 0x0 0x0 L2CEN L2 Cache Enable 0 1 read-write CSR Cache Synchronization Register 0x730 32 read-write n 0x0 0x0 C Cache Synchronization Status 0 1 read-write CWR Clean Way Register 0x7BC 32 read-write n 0x0 0x0 WAY0 Clean Way Number 0 0 1 read-write WAY1 Clean Way Number 1 1 1 read-write WAY2 Clean Way Number 2 2 1 read-write WAY3 Clean Way Number 3 3 1 read-write WAY4 Clean Way Number 4 4 1 read-write WAY5 Clean Way Number 5 5 1 read-write WAY6 Clean Way Number 6 6 1 read-write WAY7 Clean Way Number 7 7 1 read-write DCR Debug Control Register 0xF40 32 read-write n 0x0 0x0 DCL Disable Cache Linefill 0 1 read-write DWB Disable Write-back, Force Write-through 1 1 read-write SPNIDEN SPNIDEN Value 2 1 read-write DLKR Data Lockdown Register 0x900 32 read-write n 0x0 0x0 DLK0 Data Lockdown in Way Number 0 0 1 read-write DLK1 Data Lockdown in Way Number 1 1 1 read-write DLK2 Data Lockdown in Way Number 2 2 1 read-write DLK3 Data Lockdown in Way Number 3 3 1 read-write DLK4 Data Lockdown in Way Number 4 4 1 read-write DLK5 Data Lockdown in Way Number 5 5 1 read-write DLK6 Data Lockdown in Way Number 6 6 1 read-write DLK7 Data Lockdown in Way Number 7 7 1 read-write DRCR Data RAM Control Register 0x10C 32 read-write n 0x0 0x0 DRDLAT Read Access Latency 4 3 read-write DSETLAT Setup Latency 0 3 read-write DWRLAT Write Access Latency 8 3 read-write ECFGR0 Event Counter 0 Configuration Register 0x208 32 read-write n 0x0 0x0 EIGEN Event Counter Interrupt Generation 0 2 read-write INT_DIS Disables (default) 0x0 INT_EN_INCR Enables with Increment condition 0x1 INT_EN_OVER Enables with Overflow condition 0x2 INT_GEN_DIS Disables Interrupt generation 0x3 ESRC Event Counter Source 2 4 read-write CNT_DIS Counter Disabled 0x0 SRC_CO Source is CO 0x1 SRC_DRHIT Source is DRHIT 0x2 SRC_DRREQ Source is DRREQ 0x3 SRC_DWHIT Source is DWHIT 0x4 SRC_DWREQ Source is DWREQ 0x5 SRC_DWTREQ Source is DWTREQ 0x6 SRC_IRHIT Source is IRHIT 0x7 SRC_IRREQ Source is IRREQ 0x8 SRC_WA Source is WA 0x9 SRC_IPFALLOC Source is IPFALLOC 0xa SRC_EPFHIT Source is EPFHIT 0xb SRC_EPFALLOC Source is EPFALLOC 0xc SRC_SRRCVD Source is SRRCVD 0xd SRC_SRCONF Source is SRCONF 0xe SRC_EPFRCVD Source is EPFRCVD 0xf ECFGR1 Event Counter 1 Configuration Register 0x204 32 read-write n 0x0 0x0 EIGEN Event Counter Interrupt Generation 0 2 read-write INT_DIS Disables (default) 0x0 INT_EN_INCR Enables with Increment condition 0x1 INT_EN_OVER Enables with Overflow condition 0x2 INT_GEN_DIS Disables Interrupt generation 0x3 ESRC Event Counter Source 2 4 read-write CNT_DIS Counter Disabled 0x0 SRC_CO Source is CO 0x1 SRC_DRHIT Source is DRHIT 0x2 SRC_DRREQ Source is DRREQ 0x3 SRC_DWHIT Source is DWHIT 0x4 SRC_DWREQ Source is DWREQ 0x5 SRC_DWTREQ Source is DWTREQ 0x6 SRC_IRHIT Source is IRHIT 0x7 SRC_IRREQ Source is IRREQ 0x8 SRC_WA Source is WA 0x9 SRC_IPFALLOC Source is IPFALLOC 0xa SRC_EPFHIT Source is EPFHIT 0xb SRC_EPFALLOC Source is EPFALLOC 0xc SRC_SRRCVD Source is SRRCVD 0xd SRC_SRCONF Source is SRCONF 0xe SRC_EPFRCVD Source is EPFRCVD 0xf ECR Event Counter Control Register 0x200 32 read-write n 0x0 0x0 EVC0RST Event Counter 0 Reset 1 1 read-write EVC1RST Event Counter 1 Reset 2 1 read-write EVCEN Event Counter Enable 0 1 read-write EVR0 Event Counter 0 Value Register 0x210 32 read-write n 0x0 0x0 VALUE Event Counter Value 0 32 read-write EVR1 Event Counter 1 Value Register 0x20C 32 read-write n 0x0 0x0 VALUE Event Counter Value 0 32 read-write ICR Interrupt Clear Register 0x220 32 read-write n 0x0 0x0 DECERR DECERR from L3 memory 8 1 read-write ECNTR Event Counter 1/0 Overflow Increment 0 1 read-write ERRRD Error on L2 Data RAM, Read 6 1 read-write ERRRT Error on L2 Tag RAM, Read 5 1 read-write ERRWD Error on L2 Data RAM, Write 4 1 read-write ERRWT Error on L2 Tag RAM, Write 3 1 read-write PARRD Parity Error on L2 Data RAM, Read 2 1 read-write PARRT Parity Error on L2 Tag RAM, Read 1 1 read-write SLVERR SLVERR from L3 memory 7 1 read-write IDR Cache ID Register 0x0 32 read-only n 0x0 0x0 ID Cache Controller ID 0 32 read-only ILKR Instruction Lockdown Register 0x904 32 read-write n 0x0 0x0 ILK0 Instruction Lockdown in Way Number 0 0 1 read-write ILK1 Instruction Lockdown in Way Number 1 1 1 read-write ILK2 Instruction Lockdown in Way Number 2 2 1 read-write ILK3 Instruction Lockdown in Way Number 3 3 1 read-write ILK4 Instruction Lockdown in Way Number 4 4 1 read-write ILK5 Instruction Lockdown in Way Number 5 5 1 read-write ILK6 Instruction Lockdown in Way Number 6 6 1 read-write ILK7 Instruction Lockdown in Way Number 7 7 1 read-write IMR Interrupt Mask Register 0x214 32 read-write n 0x0 0x0 DECERR DECERR from L3 Memory 8 1 read-write ECNTR Event Counter 1/0 Overflow Increment 0 1 read-write ERRRD Error on L2 Data RAM, Read 6 1 read-write ERRRT Error on L2 Tag RAM, Read 5 1 read-write ERRWD Error on L2 Data RAM, Write 4 1 read-write ERRWT Error on L2 Tag RAM, Write 3 1 read-write PARRD Parity Error on L2 Data RAM, Read 2 1 read-write PARRT Parity Error on L2 Tag RAM, Read 1 1 read-write SLVERR SLVERR from L3 Memory 7 1 read-write IPALR Invalidate Physical Address Line Register 0x770 32 read-write n 0x0 0x0 C Cache Synchronization Status 0 1 read-write IDX Index Number 5 9 read-write TAG Tag Number 14 18 read-write IWR Invalidate Way Register 0x77C 32 read-write n 0x0 0x0 WAY0 Invalidate Way Number 0 0 1 read-write WAY1 Invalidate Way Number 1 1 1 read-write WAY2 Invalidate Way Number 2 2 1 read-write WAY3 Invalidate Way Number 3 3 1 read-write WAY4 Invalidate Way Number 4 4 1 read-write WAY5 Invalidate Way Number 5 5 1 read-write WAY6 Invalidate Way Number 6 6 1 read-write WAY7 Invalidate Way Number 7 7 1 read-write MISR Masked Interrupt Status Register 0x218 32 read-only n 0x0 0x0 DECERR DECERR from L3 memory 8 1 read-only ECNTR Event Counter 1/0 Overflow Increment 0 1 read-only ERRRD Error on L2 Data RAM, Read 6 1 read-only ERRRT Error on L2 Tag RAM, Read 5 1 read-only ERRWD Error on L2 Data RAM, Write 4 1 read-only ERRWT Error on L2 Tag RAM, Write 3 1 read-only PARRD Parity Error on L2 Data RAM, Read 2 1 read-only PARRT Parity Error on L2 Tag RAM, Read 1 1 read-only SLVERR SLVERR from L3 memory 7 1 read-only PCR Prefetch Control Register 0xF60 32 read-write n 0x0 0x0 DATPEN Data Prefetch Enable 28 1 read-write DLEN Double Linefill Enable 30 1 read-write DLFWRDIS Double Linefill on WRAP Read Disable 27 1 read-write IDLEN INCR Double Linefill Enable 23 1 read-write INSPEN Instruction Prefetch Enable 29 1 read-write NSIDEN Not Same ID on Exclusive Sequence Enable 21 1 read-write OFFSET Prefetch Offset 0 5 read-write PDEN Prefetch Drop Enable 24 1 read-write POWCR Power Control Register 0xF80 32 read-write n 0x0 0x0 DCKGATEN Dynamic Clock Gating Enable 1 1 read-write STBYEN Standby Mode Enable 0 1 read-write RISR Raw Interrupt Status Register 0x21C 32 read-only n 0x0 0x0 DECERR DECERR from L3 memory 8 1 read-only ECNTR Event Counter 1/0 Overflow Increment 0 1 read-only ERRRD Error on L2 Data RAM, Read 6 1 read-only ERRRT Error on L2 Tag RAM, Read 5 1 read-only ERRWD Error on L2 Data RAM, Write 4 1 read-only ERRWT Error on L2 Tag RAM, Write 3 1 read-only PARRD Parity Error on L2 Data RAM, Read 2 1 read-only PARRT Parity Error on L2 Tag RAM, Read 1 1 read-only SLVERR SLVERR from L3 memory 7 1 read-only TRCR Tag RAM Control Register 0x108 32 read-write n 0x0 0x0 TRDLAT Read Access Latency 4 3 read-write TSETLAT Setup Latency 0 3 read-write TWRLAT Write Access Latency 8 3 read-write TYPR Cache Type Register 0x4 32 read-only n 0x0 0x0 DL2ASS Data L2 Cache Associativity 18 1 read-only DL2WSIZE Data L2 Cache Way Size 20 3 read-only IL2ASS Instruction L2 Cache Associativity 6 1 read-only IL2WSIZE Instruction L2 Cache Way Size 8 3 read-only LCDC LCD Controller LCDC 0x0 0x0 0x50 registers n LCDC 51 ATTR LCD Controller Attribute Register 0x3C 32 write-only n 0x0 0x0 BASE Base Layer Update Attribute 0 1 write-only BASEA2Q Base Layer Update Add To Queue 8 1 write-only HEO High End Overlay Update Attribute 3 1 write-only HEOA2Q High End Overlay Update Add To Queue 11 1 write-only OVR1 Overlay 1 Update Attribute 1 1 write-only OVR1A2Q Overlay 1 Update Add To Queue 9 1 write-only BASEADDR Base DMA Address Register 0x60 32 read-write n 0x0 0x0 ADDR DMA Transfer Start Address 0 32 read-write BASECFG0 Base Layer Configuration Register 0 0x6C 32 read-write n 0x0 0x0 BLEN AHB Burst Length 4 2 read-write AHB_SINGLE AHB Access is started as soon as there is enough space in the FIFO to store one data. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. 0x0 AHB_INCR4 AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 4 data. An AHB INCR4 Burst is used. SINGLE, INCR and INCR4 bursts are used. INCR is used for a burst of 2 and 3 beats. 0x1 AHB_INCR8 AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 8 data. An AHB INCR8 Burst is used. SINGLE, INCR, INCR4 and INCR8 bursts are used. INCR is used for a burst of 2 and 3 beats. 0x2 AHB_INCR16 AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 16 data. An AHB INCR16 Burst is used. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. 0x3 DLBO Defined Length Burst Only For Channel Bus Transaction 8 1 read-write SIF Source Interface 0 1 read-write BASECFG1 Base Layer Configuration Register 1 0x70 32 read-write n 0x0 0x0 CLUTEN Color Lookup Table Mode Enable 0 1 read-write CLUTMODE Color Lookup Table Mode Input Selection 8 2 read-write CLUT_1BPP Color Lookup Table mode set to 1 bit per pixel 0x0 CLUT_2BPP Color Lookup Table mode set to 2 bits per pixel 0x1 CLUT_4BPP Color Lookup Table mode set to 4 bits per pixel 0x2 CLUT_8BPP Color Lookup Table mode set to 8 bits per pixel 0x3 RGBMODE RGB Mode Input Selection 4 4 read-write 12BPP_RGB_444 12 bpp RGB 444 0x0 16BPP_ARGB_4444 16 bpp ARGB 4444 0x1 16BPP_RGBA_4444 16 bpp RGBA 4444 0x2 16BPP_RGB_565 16 bpp RGB 565 0x3 16BPP_TRGB_1555 16 bpp TRGB 1555 0x4 18BPP_RGB_666 18 bpp RGB 666 0x5 18BPP_RGB_666PACKED 18 bpp RGB 666 PACKED 0x6 19BPP_TRGB_1666 19 bpp TRGB 1666 0x7 19BPP_TRGB_PACKED 19 bpp TRGB 1666 PACKED 0x8 24BPP_RGB_888 24 bpp RGB 888 0x9 24BPP_RGB_888_PACKED 24 bpp RGB 888 PACKED 0xA 25BPP_TRGB_1888 25 bpp TRGB 1888 0xB 32BPP_ARGB_8888 32 bpp ARGB 8888 0xC 32BPP_RGBA_8888 32 bpp RGBA 8888 0xD BASECFG2 Base Layer Configuration Register 2 0x74 32 read-write n 0x0 0x0 XSTRIDE Horizontal Stride 0 32 read-write BASECFG3 Base Layer Configuration Register 3 0x78 32 read-write n 0x0 0x0 BDEF Blue Default 0 8 read-write GDEF Green Default 8 8 read-write RDEF Red Default 16 8 read-write BASECFG4 Base Layer Configuration Register 4 0x7C 32 read-write n 0x0 0x0 DISCEN Discard Area Enable 11 1 read-write DMA Use DMA Data Path 8 1 read-write REP Use Replication logic to expand RGB color to 24 bits 9 1 read-write BASECFG5 Base Layer Configuration Register 5 0x80 32 read-write n 0x0 0x0 DISCXPOS Discard Area Horizontal Coordinate 0 11 read-write DISCYPOS Discard Area Vertical Coordinate 16 11 read-write BASECFG6 Base Layer Configuration Register 6 0x84 32 read-write n 0x0 0x0 DISCXSIZE Discard Area Horizontal Size 0 11 read-write DISCYSIZE Discard Area Vertical Size 16 11 read-write BASECHDR Base Layer Channel Disable Register 0x44 32 write-only n 0x0 0x0 CHDIS Channel Disable 0 1 write-only CHRST Channel Reset 8 1 write-only BASECHER Base Layer Channel Enable Register 0x40 32 write-only n 0x0 0x0 A2QEN Add To Queue Enable 2 1 write-only CHEN Channel Enable 0 1 write-only UPDATEEN Update Overlay Attributes Enable 1 1 write-only BASECHSR Base Layer Channel Status Register 0x48 32 read-only n 0x0 0x0 A2QSR Add To Queue Status 2 1 read-only CHSR Channel Status 0 1 read-only UPDATESR Update Overlay Attributes In Progress Status 1 1 read-only BASECLUT0 Base CLUT Register 0x600 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT1 Base CLUT Register 0x604 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT10 Base CLUT Register 0x628 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT100 Base CLUT Register 0x790 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT101 Base CLUT Register 0x794 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT102 Base CLUT Register 0x798 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT103 Base CLUT Register 0x79C 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT104 Base CLUT Register 0x7A0 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT105 Base CLUT Register 0x7A4 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT106 Base CLUT Register 0x7A8 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT107 Base CLUT Register 0x7AC 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT108 Base CLUT Register 0x7B0 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT109 Base CLUT Register 0x7B4 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT11 Base CLUT Register 0x62C 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT110 Base CLUT Register 0x7B8 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT111 Base CLUT Register 0x7BC 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT112 Base CLUT Register 0x7C0 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT113 Base CLUT Register 0x7C4 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT114 Base CLUT Register 0x7C8 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT115 Base CLUT Register 0x7CC 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT116 Base CLUT Register 0x7D0 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT117 Base CLUT Register 0x7D4 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT118 Base CLUT Register 0x7D8 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT119 Base CLUT Register 0x7DC 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT12 Base CLUT Register 0x630 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT120 Base CLUT Register 0x7E0 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT121 Base CLUT Register 0x7E4 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT122 Base CLUT Register 0x7E8 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT123 Base CLUT Register 0x7EC 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT124 Base CLUT Register 0x7F0 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT125 Base CLUT Register 0x7F4 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT126 Base CLUT Register 0x7F8 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT127 Base CLUT Register 0x7FC 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT128 Base CLUT Register 0x800 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT129 Base CLUT Register 0x804 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT13 Base CLUT Register 0x634 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT130 Base CLUT Register 0x808 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT131 Base CLUT Register 0x80C 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT132 Base CLUT Register 0x810 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT133 Base CLUT Register 0x814 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT134 Base CLUT Register 0x818 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT135 Base CLUT Register 0x81C 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT136 Base CLUT Register 0x820 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT137 Base CLUT Register 0x824 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT138 Base CLUT Register 0x828 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT139 Base CLUT Register 0x82C 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT14 Base CLUT Register 0x638 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT140 Base CLUT Register 0x830 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT141 Base CLUT Register 0x834 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT142 Base CLUT Register 0x838 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT143 Base CLUT Register 0x83C 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT144 Base CLUT Register 0x840 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT145 Base CLUT Register 0x844 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT146 Base CLUT Register 0x848 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT147 Base CLUT Register 0x84C 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT148 Base CLUT Register 0x850 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT149 Base CLUT Register 0x854 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT15 Base CLUT Register 0x63C 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT150 Base CLUT Register 0x858 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT151 Base CLUT Register 0x85C 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT152 Base CLUT Register 0x860 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT153 Base CLUT Register 0x864 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT154 Base CLUT Register 0x868 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT155 Base CLUT Register 0x86C 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT156 Base CLUT Register 0x870 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT157 Base CLUT Register 0x874 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT158 Base CLUT Register 0x878 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT159 Base CLUT Register 0x87C 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT16 Base CLUT Register 0x640 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT160 Base CLUT Register 0x880 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT161 Base CLUT Register 0x884 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT162 Base CLUT Register 0x888 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT163 Base CLUT Register 0x88C 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT164 Base CLUT Register 0x890 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT165 Base CLUT Register 0x894 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT166 Base CLUT Register 0x898 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT167 Base CLUT Register 0x89C 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT168 Base CLUT Register 0x8A0 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT169 Base CLUT Register 0x8A4 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT17 Base CLUT Register 0x644 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT170 Base CLUT Register 0x8A8 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT171 Base CLUT Register 0x8AC 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT172 Base CLUT Register 0x8B0 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT173 Base CLUT Register 0x8B4 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT174 Base CLUT Register 0x8B8 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT175 Base CLUT Register 0x8BC 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT176 Base CLUT Register 0x8C0 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT177 Base CLUT Register 0x8C4 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT178 Base CLUT Register 0x8C8 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT179 Base CLUT Register 0x8CC 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT18 Base CLUT Register 0x648 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT180 Base CLUT Register 0x8D0 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT181 Base CLUT Register 0x8D4 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT182 Base CLUT Register 0x8D8 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT183 Base CLUT Register 0x8DC 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT184 Base CLUT Register 0x8E0 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT185 Base CLUT Register 0x8E4 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT186 Base CLUT Register 0x8E8 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT187 Base CLUT Register 0x8EC 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT188 Base CLUT Register 0x8F0 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT189 Base CLUT Register 0x8F4 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT19 Base CLUT Register 0x64C 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT190 Base CLUT Register 0x8F8 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT191 Base CLUT Register 0x8FC 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT192 Base CLUT Register 0x900 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT193 Base CLUT Register 0x904 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT194 Base CLUT Register 0x908 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT195 Base CLUT Register 0x90C 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT196 Base CLUT Register 0x910 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT197 Base CLUT Register 0x914 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT198 Base CLUT Register 0x918 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT199 Base CLUT Register 0x91C 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT2 Base CLUT Register 0x608 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT20 Base CLUT Register 0x650 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT200 Base CLUT Register 0x920 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT201 Base CLUT Register 0x924 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT202 Base CLUT Register 0x928 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT203 Base CLUT Register 0x92C 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT204 Base CLUT Register 0x930 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT205 Base CLUT Register 0x934 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT206 Base CLUT Register 0x938 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT207 Base CLUT Register 0x93C 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT208 Base CLUT Register 0x940 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT209 Base CLUT Register 0x944 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT21 Base CLUT Register 0x654 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT210 Base CLUT Register 0x948 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT211 Base CLUT Register 0x94C 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT212 Base CLUT Register 0x950 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT213 Base CLUT Register 0x954 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT214 Base CLUT Register 0x958 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT215 Base CLUT Register 0x95C 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT216 Base CLUT Register 0x960 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT217 Base CLUT Register 0x964 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT218 Base CLUT Register 0x968 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT219 Base CLUT Register 0x96C 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT22 Base CLUT Register 0x658 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT220 Base CLUT Register 0x970 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT221 Base CLUT Register 0x974 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT222 Base CLUT Register 0x978 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT223 Base CLUT Register 0x97C 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT224 Base CLUT Register 0x980 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT225 Base CLUT Register 0x984 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT226 Base CLUT Register 0x988 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT227 Base CLUT Register 0x98C 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT228 Base CLUT Register 0x990 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT229 Base CLUT Register 0x994 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT23 Base CLUT Register 0x65C 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT230 Base CLUT Register 0x998 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT231 Base CLUT Register 0x99C 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT232 Base CLUT Register 0x9A0 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT233 Base CLUT Register 0x9A4 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT234 Base CLUT Register 0x9A8 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT235 Base CLUT Register 0x9AC 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT236 Base CLUT Register 0x9B0 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT237 Base CLUT Register 0x9B4 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT238 Base CLUT Register 0x9B8 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT239 Base CLUT Register 0x9BC 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT24 Base CLUT Register 0x660 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT240 Base CLUT Register 0x9C0 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT241 Base CLUT Register 0x9C4 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT242 Base CLUT Register 0x9C8 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT243 Base CLUT Register 0x9CC 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT244 Base CLUT Register 0x9D0 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT245 Base CLUT Register 0x9D4 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT246 Base CLUT Register 0x9D8 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT247 Base CLUT Register 0x9DC 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT248 Base CLUT Register 0x9E0 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT249 Base CLUT Register 0x9E4 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT25 Base CLUT Register 0x664 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT250 Base CLUT Register 0x9E8 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT251 Base CLUT Register 0x9EC 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT252 Base CLUT Register 0x9F0 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT253 Base CLUT Register 0x9F4 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT254 Base CLUT Register 0x9F8 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT255 Base CLUT Register 0x9FC 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT26 Base CLUT Register 0x668 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT27 Base CLUT Register 0x66C 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT28 Base CLUT Register 0x670 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT29 Base CLUT Register 0x674 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT3 Base CLUT Register 0x60C 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT30 Base CLUT Register 0x678 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT31 Base CLUT Register 0x67C 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT32 Base CLUT Register 0x680 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT33 Base CLUT Register 0x684 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT34 Base CLUT Register 0x688 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT35 Base CLUT Register 0x68C 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT36 Base CLUT Register 0x690 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT37 Base CLUT Register 0x694 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT38 Base CLUT Register 0x698 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT39 Base CLUT Register 0x69C 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT4 Base CLUT Register 0x610 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT40 Base CLUT Register 0x6A0 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT41 Base CLUT Register 0x6A4 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT42 Base CLUT Register 0x6A8 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT43 Base CLUT Register 0x6AC 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT44 Base CLUT Register 0x6B0 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT45 Base CLUT Register 0x6B4 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT46 Base CLUT Register 0x6B8 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT47 Base CLUT Register 0x6BC 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT48 Base CLUT Register 0x6C0 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT49 Base CLUT Register 0x6C4 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT5 Base CLUT Register 0x614 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT50 Base CLUT Register 0x6C8 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT51 Base CLUT Register 0x6CC 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT52 Base CLUT Register 0x6D0 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT53 Base CLUT Register 0x6D4 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT54 Base CLUT Register 0x6D8 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT55 Base CLUT Register 0x6DC 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT56 Base CLUT Register 0x6E0 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT57 Base CLUT Register 0x6E4 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT58 Base CLUT Register 0x6E8 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT59 Base CLUT Register 0x6EC 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT6 Base CLUT Register 0x618 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT60 Base CLUT Register 0x6F0 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT61 Base CLUT Register 0x6F4 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT62 Base CLUT Register 0x6F8 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT63 Base CLUT Register 0x6FC 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT64 Base CLUT Register 0x700 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT65 Base CLUT Register 0x704 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT66 Base CLUT Register 0x708 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT67 Base CLUT Register 0x70C 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT68 Base CLUT Register 0x710 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT69 Base CLUT Register 0x714 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT7 Base CLUT Register 0x61C 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT70 Base CLUT Register 0x718 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT71 Base CLUT Register 0x71C 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT72 Base CLUT Register 0x720 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT73 Base CLUT Register 0x724 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT74 Base CLUT Register 0x728 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT75 Base CLUT Register 0x72C 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT76 Base CLUT Register 0x730 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT77 Base CLUT Register 0x734 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT78 Base CLUT Register 0x738 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT79 Base CLUT Register 0x73C 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT8 Base CLUT Register 0x620 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT80 Base CLUT Register 0x740 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT81 Base CLUT Register 0x744 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT82 Base CLUT Register 0x748 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT83 Base CLUT Register 0x74C 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT84 Base CLUT Register 0x750 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT85 Base CLUT Register 0x754 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT86 Base CLUT Register 0x758 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT87 Base CLUT Register 0x75C 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT88 Base CLUT Register 0x760 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT89 Base CLUT Register 0x764 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT9 Base CLUT Register 0x624 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT90 Base CLUT Register 0x768 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT91 Base CLUT Register 0x76C 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT92 Base CLUT Register 0x770 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT93 Base CLUT Register 0x774 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT94 Base CLUT Register 0x778 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT95 Base CLUT Register 0x77C 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT96 Base CLUT Register 0x780 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT97 Base CLUT Register 0x784 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT98 Base CLUT Register 0x788 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT99 Base CLUT Register 0x78C 32 read-write n BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[0] Base CLUT Register 0xC00 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[100] Base CLUT Register 0x2B2E8 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[101] Base CLUT Register 0x2BA7C 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[102] Base CLUT Register 0x2C214 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[103] Base CLUT Register 0x2C9B0 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[104] Base CLUT Register 0x2D150 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[105] Base CLUT Register 0x2D8F4 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[106] Base CLUT Register 0x2E09C 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[107] Base CLUT Register 0x2E848 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[108] Base CLUT Register 0x2EFF8 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[109] Base CLUT Register 0x2F7AC 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[10] Base CLUT Register 0x48DC 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[110] Base CLUT Register 0x2FF64 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[111] Base CLUT Register 0x30720 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[112] Base CLUT Register 0x30EE0 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[113] Base CLUT Register 0x316A4 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[114] Base CLUT Register 0x31E6C 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[115] Base CLUT Register 0x32638 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[116] Base CLUT Register 0x32E08 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[117] Base CLUT Register 0x335DC 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[118] Base CLUT Register 0x33DB4 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[119] Base CLUT Register 0x34590 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[11] Base CLUT Register 0x4F08 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[120] Base CLUT Register 0x34D70 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[121] Base CLUT Register 0x35554 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[122] Base CLUT Register 0x35D3C 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[123] Base CLUT Register 0x36528 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[124] Base CLUT Register 0x36D18 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[125] Base CLUT Register 0x3750C 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[126] Base CLUT Register 0x37D04 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[127] Base CLUT Register 0x38500 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[128] Base CLUT Register 0x38D00 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[129] Base CLUT Register 0x39504 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[12] Base CLUT Register 0x5538 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[130] Base CLUT Register 0x39D0C 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[131] Base CLUT Register 0x3A518 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[132] Base CLUT Register 0x3AD28 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[133] Base CLUT Register 0x3B53C 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[134] Base CLUT Register 0x3BD54 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[135] Base CLUT Register 0x3C570 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[136] Base CLUT Register 0x3CD90 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[137] Base CLUT Register 0x3D5B4 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[138] Base CLUT Register 0x3DDDC 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[139] Base CLUT Register 0x3E608 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[13] Base CLUT Register 0x5B6C 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[140] Base CLUT Register 0x3EE38 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[141] Base CLUT Register 0x3F66C 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[142] Base CLUT Register 0x3FEA4 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[143] Base CLUT Register 0x406E0 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[144] Base CLUT Register 0x40F20 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[145] Base CLUT Register 0x41764 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[146] Base CLUT Register 0x41FAC 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[147] Base CLUT Register 0x427F8 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[148] Base CLUT Register 0x43048 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[149] Base CLUT Register 0x4389C 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[14] Base CLUT Register 0x61A4 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[150] Base CLUT Register 0x440F4 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[151] Base CLUT Register 0x44950 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[152] Base CLUT Register 0x451B0 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[153] Base CLUT Register 0x45A14 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[154] Base CLUT Register 0x4627C 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[155] Base CLUT Register 0x46AE8 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[156] Base CLUT Register 0x47358 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[157] Base CLUT Register 0x47BCC 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[158] Base CLUT Register 0x48444 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[159] Base CLUT Register 0x48CC0 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[15] Base CLUT Register 0x67E0 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[160] Base CLUT Register 0x49540 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[161] Base CLUT Register 0x49DC4 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[162] Base CLUT Register 0x4A64C 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[163] Base CLUT Register 0x4AED8 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[164] Base CLUT Register 0x4B768 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[165] Base CLUT Register 0x4BFFC 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[166] Base CLUT Register 0x4C894 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[167] Base CLUT Register 0x4D130 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[168] Base CLUT Register 0x4D9D0 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[169] Base CLUT Register 0x4E274 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[16] Base CLUT Register 0x6E20 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[170] Base CLUT Register 0x4EB1C 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[171] Base CLUT Register 0x4F3C8 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[172] Base CLUT Register 0x4FC78 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[173] Base CLUT Register 0x5052C 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[174] Base CLUT Register 0x50DE4 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[175] Base CLUT Register 0x516A0 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[176] Base CLUT Register 0x51F60 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[177] Base CLUT Register 0x52824 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[178] Base CLUT Register 0x530EC 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[179] Base CLUT Register 0x539B8 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[17] Base CLUT Register 0x7464 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[180] Base CLUT Register 0x54288 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[181] Base CLUT Register 0x54B5C 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[182] Base CLUT Register 0x55434 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[183] Base CLUT Register 0x55D10 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[184] Base CLUT Register 0x565F0 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[185] Base CLUT Register 0x56ED4 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[186] Base CLUT Register 0x577BC 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[187] Base CLUT Register 0x580A8 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[188] Base CLUT Register 0x58998 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[189] Base CLUT Register 0x5928C 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[18] Base CLUT Register 0x7AAC 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[190] Base CLUT Register 0x59B84 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[191] Base CLUT Register 0x5A480 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[192] Base CLUT Register 0x5AD80 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[193] Base CLUT Register 0x5B684 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[194] Base CLUT Register 0x5BF8C 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[195] Base CLUT Register 0x5C898 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[196] Base CLUT Register 0x5D1A8 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[197] Base CLUT Register 0x5DABC 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[198] Base CLUT Register 0x5E3D4 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[199] Base CLUT Register 0x5ECF0 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[19] Base CLUT Register 0x80F8 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[1] Base CLUT Register 0x1204 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[200] Base CLUT Register 0x5F610 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[201] Base CLUT Register 0x5FF34 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[202] Base CLUT Register 0x6085C 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[203] Base CLUT Register 0x61188 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[204] Base CLUT Register 0x61AB8 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[205] Base CLUT Register 0x623EC 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[206] Base CLUT Register 0x62D24 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[207] Base CLUT Register 0x63660 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[208] Base CLUT Register 0x63FA0 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[209] Base CLUT Register 0x648E4 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[20] Base CLUT Register 0x8748 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[210] Base CLUT Register 0x6522C 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[211] Base CLUT Register 0x65B78 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[212] Base CLUT Register 0x664C8 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[213] Base CLUT Register 0x66E1C 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[214] Base CLUT Register 0x67774 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[215] Base CLUT Register 0x680D0 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[216] Base CLUT Register 0x68A30 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[217] Base CLUT Register 0x69394 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[218] Base CLUT Register 0x69CFC 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[219] Base CLUT Register 0x6A668 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[21] Base CLUT Register 0x8D9C 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[220] Base CLUT Register 0x6AFD8 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[221] Base CLUT Register 0x6B94C 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[222] Base CLUT Register 0x6C2C4 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[223] Base CLUT Register 0x6CC40 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[224] Base CLUT Register 0x6D5C0 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[225] Base CLUT Register 0x6DF44 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[226] Base CLUT Register 0x6E8CC 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[227] Base CLUT Register 0x6F258 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[228] Base CLUT Register 0x6FBE8 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[229] Base CLUT Register 0x7057C 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[22] Base CLUT Register 0x93F4 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[230] Base CLUT Register 0x70F14 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[231] Base CLUT Register 0x718B0 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[232] Base CLUT Register 0x72250 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[233] Base CLUT Register 0x72BF4 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[234] Base CLUT Register 0x7359C 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[235] Base CLUT Register 0x73F48 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[236] Base CLUT Register 0x748F8 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[237] Base CLUT Register 0x752AC 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[238] Base CLUT Register 0x75C64 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[239] Base CLUT Register 0x76620 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[23] Base CLUT Register 0x9A50 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[240] Base CLUT Register 0x76FE0 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[241] Base CLUT Register 0x779A4 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[242] Base CLUT Register 0x7836C 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[243] Base CLUT Register 0x78D38 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[244] Base CLUT Register 0x79708 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[245] Base CLUT Register 0x7A0DC 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[246] Base CLUT Register 0x7AAB4 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[247] Base CLUT Register 0x7B490 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[248] Base CLUT Register 0x7BE70 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[249] Base CLUT Register 0x7C854 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[24] Base CLUT Register 0xA0B0 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[250] Base CLUT Register 0x7D23C 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[251] Base CLUT Register 0x7DC28 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[252] Base CLUT Register 0x7E618 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[253] Base CLUT Register 0x7F00C 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[254] Base CLUT Register 0x7FA04 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[255] Base CLUT Register 0x80400 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[25] Base CLUT Register 0xA714 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[26] Base CLUT Register 0xAD7C 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[27] Base CLUT Register 0xB3E8 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[28] Base CLUT Register 0xBA58 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[29] Base CLUT Register 0xC0CC 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[2] Base CLUT Register 0x180C 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[30] Base CLUT Register 0xC744 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[31] Base CLUT Register 0xCDC0 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[32] Base CLUT Register 0xD440 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[33] Base CLUT Register 0xDAC4 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[34] Base CLUT Register 0xE14C 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[35] Base CLUT Register 0xE7D8 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[36] Base CLUT Register 0xEE68 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[37] Base CLUT Register 0xF4FC 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[38] Base CLUT Register 0xFB94 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[39] Base CLUT Register 0x10230 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[3] Base CLUT Register 0x1E18 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[40] Base CLUT Register 0x108D0 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[41] Base CLUT Register 0x10F74 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[42] Base CLUT Register 0x1161C 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[43] Base CLUT Register 0x11CC8 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[44] Base CLUT Register 0x12378 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[45] Base CLUT Register 0x12A2C 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[46] Base CLUT Register 0x130E4 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[47] Base CLUT Register 0x137A0 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[48] Base CLUT Register 0x13E60 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[49] Base CLUT Register 0x14524 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[4] Base CLUT Register 0x2428 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[50] Base CLUT Register 0x14BEC 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[51] Base CLUT Register 0x152B8 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[52] Base CLUT Register 0x15988 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[53] Base CLUT Register 0x1605C 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[54] Base CLUT Register 0x16734 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[55] Base CLUT Register 0x16E10 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[56] Base CLUT Register 0x174F0 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[57] Base CLUT Register 0x17BD4 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[58] Base CLUT Register 0x182BC 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[59] Base CLUT Register 0x189A8 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[5] Base CLUT Register 0x2A3C 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[60] Base CLUT Register 0x19098 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[61] Base CLUT Register 0x1978C 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[62] Base CLUT Register 0x19E84 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[63] Base CLUT Register 0x1A580 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[64] Base CLUT Register 0x1AC80 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[65] Base CLUT Register 0x1B384 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[66] Base CLUT Register 0x1BA8C 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[67] Base CLUT Register 0x1C198 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[68] Base CLUT Register 0x1C8A8 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[69] Base CLUT Register 0x1CFBC 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[6] Base CLUT Register 0x3054 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[70] Base CLUT Register 0x1D6D4 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[71] Base CLUT Register 0x1DDF0 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[72] Base CLUT Register 0x1E510 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[73] Base CLUT Register 0x1EC34 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[74] Base CLUT Register 0x1F35C 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[75] Base CLUT Register 0x1FA88 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[76] Base CLUT Register 0x201B8 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[77] Base CLUT Register 0x208EC 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[78] Base CLUT Register 0x21024 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[79] Base CLUT Register 0x21760 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[7] Base CLUT Register 0x3670 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[80] Base CLUT Register 0x21EA0 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[81] Base CLUT Register 0x225E4 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[82] Base CLUT Register 0x22D2C 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[83] Base CLUT Register 0x23478 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[84] Base CLUT Register 0x23BC8 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[85] Base CLUT Register 0x2431C 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[86] Base CLUT Register 0x24A74 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[87] Base CLUT Register 0x251D0 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[88] Base CLUT Register 0x25930 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[89] Base CLUT Register 0x26094 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[8] Base CLUT Register 0x3C90 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[90] Base CLUT Register 0x267FC 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[91] Base CLUT Register 0x26F68 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[92] Base CLUT Register 0x276D8 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[93] Base CLUT Register 0x27E4C 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[94] Base CLUT Register 0x285C4 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[95] Base CLUT Register 0x28D40 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[96] Base CLUT Register 0x294C0 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[97] Base CLUT Register 0x29C44 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[98] Base CLUT Register 0x2A3CC 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[99] Base CLUT Register 0x2AB58 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECLUT[9] Base CLUT Register 0x42B4 32 read-write n 0x0 0x0 BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write BASECTRL Base DMA Control Register 0x64 32 read-write n 0x0 0x0 ADDIEN Add Head Descriptor to Queue Interrupt Enable 4 1 read-write DFETCH Transfer Descriptor Fetch Enable 0 1 read-write DMAIEN End of DMA Transfer Interrupt Enable 2 1 read-write DONEIEN End of List Interrupt Enable 5 1 read-write DSCRIEN Descriptor Loaded Interrupt Enable 3 1 read-write LFETCH Lookup Table Fetch Enable 1 1 read-write BASEHEAD Base DMA Head Register 0x5C 32 read-write n 0x0 0x0 HEAD DMA Head Pointer 2 30 read-write BASEIDR Base Layer Interrupt Disabled Register 0x50 32 write-only n 0x0 0x0 ADD Head Descriptor Loaded Interrupt Disable 4 1 write-only DMA End of DMA Transfer Interrupt Disable 2 1 write-only DONE End of List Interrupt Disable 5 1 write-only DSCR Descriptor Loaded Interrupt Disable 3 1 write-only OVR Overflow Interrupt Disable 6 1 write-only BASEIER Base Layer Interrupt Enable Register 0x4C 32 write-only n 0x0 0x0 ADD Head Descriptor Loaded Interrupt Enable 4 1 write-only DMA End of DMA Transfer Interrupt Enable 2 1 write-only DONE End of List Interrupt Enable 5 1 write-only DSCR Descriptor Loaded Interrupt Enable 3 1 write-only OVR Overflow Interrupt Enable 6 1 write-only BASEIMR Base Layer Interrupt Mask Register 0x54 32 read-only n 0x0 0x0 ADD Head Descriptor Loaded Interrupt Mask 4 1 read-only DMA End of DMA Transfer Interrupt Mask 2 1 read-only DONE End of List Interrupt Mask 5 1 read-only DSCR Descriptor Loaded Interrupt Mask 3 1 read-only OVR Overflow Interrupt Mask 6 1 read-only BASEISR Base Layer Interrupt Status Register 0x58 32 read-only n 0x0 0x0 ADD Head Descriptor Loaded 4 1 read-only DMA End of DMA Transfer 2 1 read-only DONE End of List Detected 5 1 read-only DSCR DMA Descriptor Loaded 3 1 read-only OVR Overflow Detected 6 1 read-only BASENEXT Base DMA Next Register 0x68 32 read-write n 0x0 0x0 NEXT DMA Descriptor Next Address 0 32 read-write HEOADDR High End Overlay DMA Address Register 0x360 32 read-write n 0x0 0x0 ADDR DMA Transfer Start Address 0 32 read-write HEOCFG0 High End Overlay Configuration Register 0 0x38C 32 read-write n 0x0 0x0 BLEN AHB Burst Length 4 2 read-write AHB_BLEN_SINGLE AHB Access is started as soon as there is enough space in the FIFO to store one data. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. 0x0 AHB_BLEN_INCR4 AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 4 data. An AHB INCR4 Burst is used. SINGLE, INCR and INCR4 bursts are used. INCR is used for a burst of 2 and 3 beats. 0x1 AHB_BLEN_INCR8 AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 8 data. An AHB INCR8 Burst is used. SINGLE, INCR, INCR4 and INCR8 bursts are used. INCR is used for a burst of 2 and 3 beats. 0x2 AHB_BLEN_INCR16 AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 16 data. An AHB INCR16 Burst is used. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. 0x3 BLENUV AHB Burst Length for U-V Channel 6 2 read-write AHB_SINGLE AHB Access is started as soon as there is enough space in the FIFO to store one data. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. 0x0 AHB_INCR4 AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 4 data. An AHB INCR4 Burst is used. SINGLE, INCR and INCR4 bursts are used. INCR is used for a burst of 2 and 3 beats. 0x1 AHB_INCR8 AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 8 data. An AHB INCR8 Burst is used. SINGLE, INCR, INCR4 and INCR8 bursts are used. INCR is used for a burst of 2 and 3 beats. 0x2 AHB_INCR16 AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 16 data. An AHB INCR16 Burst is used. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. 0x3 DLBO Defined Length Burst Only For Channel Bus Transaction 8 1 read-write LOCKDIS Hardware Rotation Lock Disable 13 1 read-write ROTDIS Hardware Rotation Optimization Disable 12 1 read-write SIF Source Interface 0 1 read-write HEOCFG1 High End Overlay Configuration Register 1 0x390 32 read-write n 0x0 0x0 CLUTEN Color Lookup Table Mode Enable 0 1 read-write CLUTMODE Color Lookup Table Mode Input Selection 8 2 read-write CLUT_1BPP Color Lookup Table mode set to 1 bit per pixel 0x0 CLUT_2BPP Color Lookup Table mode set to 2 bits per pixel 0x1 CLUT_4BPP Color Lookup Table mode set to 4 bits per pixel 0x2 CLUT_8BPP Color Lookup Table mode set to 8 bits per pixel 0x3 DSCALEOPT Down Scaling Bandwidth Optimization 20 1 read-write RGBMODE RGB Mode Input Selection 4 4 read-write 12BPP_RGB_444 12 bpp RGB 444 0x0 16BPP_ARGB_4444 16 bpp ARGB 4444 0x1 16BPP_RGBA_4444 16 bpp RGBA 4444 0x2 16BPP_RGB_565 16 bpp RGB 565 0x3 16BPP_TRGB_1555 16 bpp TRGB 1555 0x4 18BPP_RGB_666 18 bpp RGB 666 0x5 18BPP_RGB_666PACKED 18 bpp RGB 666 PACKED 0x6 19BPP_TRGB_1666 19 bpp TRGB 1666 0x7 19BPP_TRGB_PACKED 19 bpp TRGB 1666 PACKED 0x8 24BPP_RGB_888 24 bpp RGB 888 0x9 24BPP_RGB_888_PACKED 24 bpp RGB 888 PACKED 0xA 25BPP_TRGB_1888 25 bpp TRGB 1888 0xB 32BPP_ARGB_8888 32 bpp ARGB 8888 0xC 32BPP_RGBA_8888 32 bpp RGBA 8888 0xD YUV422ROT YUV 4:2:2 Rotation 16 1 read-write YUV422SWP YUV 4:2:2 Swap 17 1 read-write YUVEN YUV Color Space Enable 1 1 read-write YUVMODE YUV Mode Input Selection 12 4 read-write 32BPP_AYCBCR 32 bpp AYCbCr 444 0x0 16BPP_YCBCR_MODE0 16 bpp Cr(n)Y(n+1)Cb(n)Y(n) 422 0x1 16BPP_YCBCR_MODE1 16 bpp Y(n+1)Cr(n)Y(n)Cb(n) 422 0x2 16BPP_YCBCR_MODE2 16 bpp Cb(n)Y(+1)Cr(n)Y(n) 422 0x3 16BPP_YCBCR_MODE3 16 bpp Y(n+1)Cb(n)Y(n)Cr(n) 422 0x4 16BPP_YCBCR_SEMIPLANAR 16 bpp Semiplanar 422 YCbCr 0x5 16BPP_YCBCR_PLANAR 16 bpp Planar 422 YCbCr 0x6 12BPP_YCBCR_SEMIPLANAR 12 bpp Semiplanar 420 YCbCr 0x7 12BPP_YCBCR_PLANAR 12 bpp Planar 420 YCbCr 0x8 HEOCFG10 High End Overlay Configuration Register 10 0x3B4 32 read-write n 0x0 0x0 BKEY Blue Color Component Chroma Key 0 8 read-write GKEY Green Color Component Chroma Key 8 8 read-write RKEY Red Color Component Chroma Key 16 8 read-write HEOCFG11 High End Overlay Configuration Register 11 0x3B8 32 read-write n 0x0 0x0 BMASK Blue Color Component Chroma Key Mask 0 8 read-write GMASK Green Color Component Chroma Key Mask 8 8 read-write RMASK Red Color Component Chroma Key Mask 16 8 read-write HEOCFG12 High End Overlay Configuration Register 12 0x3BC 32 read-write n 0x0 0x0 CRKEY Blender Chroma Key Enable 0 1 read-write DMA Blender DMA Layer Enable 8 1 read-write DSTKEY Destination Chroma Keying 10 1 read-write GA Blender Global Alpha 16 8 read-write GAEN Blender Global Alpha Enable 5 1 read-write INV Blender Inverted Blender Output Enable 1 1 read-write ITER Blender Use Iterated Color 3 1 read-write ITER2BL Blender Iterated Color Enable 2 1 read-write LAEN Blender Local Alpha Enable 6 1 read-write OVR Blender Overlay Layer Enable 7 1 read-write REP Use Replication logic to expand RGB color to 24 bits 9 1 read-write REVALPHA Blender Reverse Alpha 4 1 read-write VIDPRI 12 1 read-write HEOCFG13 High End Overlay Configuration Register 13 0x3C0 32 read-write n 0x0 0x0 SCALEN Hardware Scaler Enable 31 1 read-write XFACTOR Horizontal Scaling Factor 0 14 read-write YFACTOR Vertical Scaling Factor 16 14 read-write HEOCFG14 High End Overlay Configuration Register 14 0x3C4 32 read-write n 0x0 0x0 CSCRU Color Space Conversion U coefficient for Red Component 1:2:7 format 10 10 read-write CSCRV Color Space Conversion V coefficient for Red Component 1:2:7 format 20 10 read-write CSCRY Color Space Conversion Y coefficient for Red Component 1:2:7 format 0 10 read-write CSCYOFF Color Space Conversion Offset 30 1 read-write HEOCFG15 High End Overlay Configuration Register 15 0x3C8 32 read-write n 0x0 0x0 CSCGU Color Space Conversion U coefficient for Green Component 1:2:7 format 10 10 read-write CSCGV Color Space Conversion V coefficient for Green Component 1:2:7 format 20 10 read-write CSCGY Color Space Conversion Y coefficient for Green Component 1:2:7 format 0 10 read-write CSCUOFF Color Space Conversion Offset 30 1 read-write HEOCFG16 High End Overlay Configuration Register 16 0x3CC 32 read-write n 0x0 0x0 CSCBU Color Space Conversion U coefficient for Blue Component 1:2:7 format 10 10 read-write CSCBV Color Space Conversion V coefficient for Blue Component 1:2:7 format 20 10 read-write CSCBY Color Space Conversion Y coefficient for Blue Component 1:2:7 format 0 10 read-write CSCVOFF Color Space Conversion Offset 30 1 read-write HEOCFG17 High End Overlay Configuration Register 17 0x3D0 32 read-write n 0x0 0x0 XPHI0COEFF0 Horizontal Coefficient for phase 0 tap 0 0 8 read-write XPHI0COEFF1 Horizontal Coefficient for phase 0 tap 1 8 8 read-write XPHI0COEFF2 Horizontal Coefficient for phase 0 tap 2 16 8 read-write XPHI0COEFF3 Horizontal Coefficient for phase 0 tap 3 24 8 read-write HEOCFG18 High End Overlay Configuration Register 18 0x3D4 32 read-write n 0x0 0x0 XPHI0COEFF4 Horizontal Coefficient for phase 0 tap 4 0 8 read-write HEOCFG19 High End Overlay Configuration Register 19 0x3D8 32 read-write n 0x0 0x0 XPHI1COEFF0 Horizontal Coefficient for phase 1 tap 0 0 8 read-write XPHI1COEFF1 Horizontal Coefficient for phase 1 tap 1 8 8 read-write XPHI1COEFF2 Horizontal Coefficient for phase 1 tap 2 16 8 read-write XPHI1COEFF3 Horizontal Coefficient for phase 1 tap 3 24 8 read-write HEOCFG2 High End Overlay Configuration Register 2 0x394 32 read-write n 0x0 0x0 XPOS Horizontal Window Position 0 11 read-write YPOS Vertical Window Position 16 11 read-write HEOCFG20 High End Overlay Configuration Register 20 0x3DC 32 read-write n 0x0 0x0 XPHI1COEFF4 Horizontal Coefficient for phase 1 tap 4 0 8 read-write HEOCFG21 High End Overlay Configuration Register 21 0x3E0 32 read-write n 0x0 0x0 XPHI2COEFF0 Horizontal Coefficient for phase 2 tap 0 0 8 read-write XPHI2COEFF1 Horizontal Coefficient for phase 2 tap 1 8 8 read-write XPHI2COEFF2 Horizontal Coefficient for phase 2 tap 2 16 8 read-write XPHI2COEFF3 Horizontal Coefficient for phase 2 tap 3 24 8 read-write HEOCFG22 High End Overlay Configuration Register 22 0x3E4 32 read-write n 0x0 0x0 XPHI2COEFF4 Horizontal Coefficient for phase 2 tap 4 0 8 read-write HEOCFG23 High End Overlay Configuration Register 23 0x3E8 32 read-write n 0x0 0x0 XPHI3COEFF0 Horizontal Coefficient for phase 3 tap 0 0 8 read-write XPHI3COEFF1 Horizontal Coefficient for phase 3 tap 1 8 8 read-write XPHI3COEFF2 Horizontal Coefficient for phase 3 tap 2 16 8 read-write XPHI3COEFF3 Horizontal Coefficient for phase 3 tap 3 24 8 read-write HEOCFG24 High End Overlay Configuration Register 24 0x3EC 32 read-write n 0x0 0x0 XPHI3COEFF4 Horizontal Coefficient for phase 3 tap 4 0 8 read-write HEOCFG25 High End Overlay Configuration Register 25 0x3F0 32 read-write n 0x0 0x0 XPHI4COEFF0 Horizontal Coefficient for phase 4 tap 0 0 8 read-write XPHI4COEFF1 Horizontal Coefficient for phase 4 tap 1 8 8 read-write XPHI4COEFF2 Horizontal Coefficient for phase 4 tap 2 16 8 read-write XPHI4COEFF3 Horizontal Coefficient for phase 4 tap 3 24 8 read-write HEOCFG26 High End Overlay Configuration Register 26 0x3F4 32 read-write n 0x0 0x0 XPHI4COEFF4 Horizontal Coefficient for phase 4 tap 4 0 8 read-write HEOCFG27 High End Overlay Configuration Register 27 0x3F8 32 read-write n 0x0 0x0 XPHI5COEFF0 Horizontal Coefficient for phase 5 tap 0 0 8 read-write XPHI5COEFF1 Horizontal Coefficient for phase 5 tap 1 8 8 read-write XPHI5COEFF2 Horizontal Coefficient for phase 5 tap 2 16 8 read-write XPHI5COEFF3 Horizontal Coefficient for phase 5 tap 3 24 8 read-write HEOCFG28 High End Overlay Configuration Register 28 0x3FC 32 read-write n 0x0 0x0 XPHI5COEFF4 Horizontal Coefficient for phase 5 tap 4 0 8 read-write HEOCFG29 High End Overlay Configuration Register 29 0x400 32 read-write n 0x0 0x0 XPHI6COEFF0 Horizontal Coefficient for phase 6 tap 0 0 8 read-write XPHI6COEFF1 Horizontal Coefficient for phase 6 tap 1 8 8 read-write XPHI6COEFF2 Horizontal Coefficient for phase 6 tap 2 16 8 read-write XPHI6COEFF3 Horizontal Coefficient for phase 6 tap 3 24 8 read-write HEOCFG3 High End Overlay Configuration Register 3 0x398 32 read-write n 0x0 0x0 XSIZE Horizontal Window Size 0 11 read-write YSIZE Vertical Window Size 16 11 read-write HEOCFG30 High End Overlay Configuration Register 30 0x404 32 read-write n 0x0 0x0 XPHI6COEFF4 Horizontal Coefficient for phase 6 tap 4 0 8 read-write HEOCFG31 High End Overlay Configuration Register 31 0x408 32 read-write n 0x0 0x0 XPHI7COEFF0 Horizontal Coefficient for phase 7 tap 0 0 8 read-write XPHI7COEFF1 Horizontal Coefficient for phase 7 tap 1 8 8 read-write XPHI7COEFF2 Horizontal Coefficient for phase 7 tap 2 16 8 read-write XPHI7COEFF3 Horizontal Coefficient for phase 7 tap 3 24 8 read-write HEOCFG32 High End Overlay Configuration Register 32 0x40C 32 read-write n 0x0 0x0 XPHI7COEFF4 Horizontal Coefficient for phase 7 tap 4 0 8 read-write HEOCFG33 High End Overlay Configuration Register 33 0x410 32 read-write n 0x0 0x0 YPHI0COEFF0 Vertical Coefficient for phase 0 tap 0 0 8 read-write YPHI0COEFF1 Vertical Coefficient for phase 0 tap 1 8 8 read-write YPHI0COEFF2 Vertical Coefficient for phase 0 tap 2 16 8 read-write HEOCFG34 High End Overlay Configuration Register 34 0x414 32 read-write n 0x0 0x0 YPHI1COEFF0 Vertical Coefficient for phase 1 tap 0 0 8 read-write YPHI1COEFF1 Vertical Coefficient for phase 1 tap 1 8 8 read-write YPHI1COEFF2 Vertical Coefficient for phase 1 tap 2 16 8 read-write HEOCFG35 High End Overlay Configuration Register 35 0x418 32 read-write n 0x0 0x0 YPHI2COEFF0 Vertical Coefficient for phase 2 tap 0 0 8 read-write YPHI2COEFF1 Vertical Coefficient for phase 2 tap 1 8 8 read-write YPHI2COEFF2 Vertical Coefficient for phase 2 tap 2 16 8 read-write HEOCFG36 High End Overlay Configuration Register 36 0x41C 32 read-write n 0x0 0x0 YPHI3COEFF0 Vertical Coefficient for phase 3 tap 0 0 8 read-write YPHI3COEFF1 Vertical Coefficient for phase 3 tap 1 8 8 read-write YPHI3COEFF2 Vertical Coefficient for phase 3 tap 2 16 8 read-write HEOCFG37 High End Overlay Configuration Register 37 0x420 32 read-write n 0x0 0x0 YPHI4COEFF0 Vertical Coefficient for phase 4 tap 0 0 8 read-write YPHI4COEFF1 Vertical Coefficient for phase 4 tap 1 8 8 read-write YPHI4COEFF2 Vertical Coefficient for phase 4 tap 2 16 8 read-write HEOCFG38 High End Overlay Configuration Register 38 0x424 32 read-write n 0x0 0x0 YPHI5COEFF0 Vertical Coefficient for phase 5 tap 0 0 8 read-write YPHI5COEFF1 Vertical Coefficient for phase 5 tap 1 8 8 read-write YPHI5COEFF2 Vertical Coefficient for phase 5 tap 2 16 8 read-write HEOCFG39 High End Overlay Configuration Register 39 0x428 32 read-write n 0x0 0x0 YPHI6COEFF0 Vertical Coefficient for phase 6 tap 0 0 8 read-write YPHI6COEFF1 Vertical Coefficient for phase 6 tap 1 8 8 read-write YPHI6COEFF2 Vertical Coefficient for phase 6 tap 2 16 8 read-write HEOCFG4 High End Overlay Configuration Register 4 0x39C 32 read-write n 0x0 0x0 XMEMSIZE Horizontal image Size in Memory 0 11 read-write YMEMSIZE Vertical image Size in Memory 16 11 read-write HEOCFG40 High End Overlay Configuration Register 40 0x42C 32 read-write n 0x0 0x0 YPHI7COEFF0 Vertical Coefficient for phase 7 tap 0 0 8 read-write YPHI7COEFF1 Vertical Coefficient for phase 7 tap 1 8 8 read-write YPHI7COEFF2 Vertical Coefficient for phase 7 tap 2 16 8 read-write HEOCFG41 High End Overlay Configuration Register 41 0x430 32 read-write n 0x0 0x0 XPHIDEF Horizontal Filter Phase Offset 0 3 read-write YPHIDEF Vertical Filter Phase Offset 16 3 read-write HEOCFG5 High End Overlay Configuration Register 5 0x3A0 32 read-write n 0x0 0x0 XSTRIDE Horizontal Stride 0 32 read-write HEOCFG6 High End Overlay Configuration Register 6 0x3A4 32 read-write n 0x0 0x0 PSTRIDE Pixel Stride 0 32 read-write HEOCFG7 High End Overlay Configuration Register 7 0x3A8 32 read-write n 0x0 0x0 UVXSTRIDE UV Horizontal Stride 0 32 read-write HEOCFG8 High End Overlay Configuration Register 8 0x3AC 32 read-write n 0x0 0x0 UVPSTRIDE UV Pixel Stride 0 32 read-write HEOCFG9 High End Overlay Configuration Register 9 0x3B0 32 read-write n 0x0 0x0 BDEF Blue Default 0 8 read-write GDEF Green Default 8 8 read-write RDEF Red Default 16 8 read-write HEOCHDR High End Overlay Channel Disable Register 0x344 32 write-only n 0x0 0x0 CHDIS Channel Disable 0 1 write-only CHRST Channel Reset 8 1 write-only HEOCHER High End Overlay Channel Enable Register 0x340 32 write-only n 0x0 0x0 A2QEN Add To Queue Enable 2 1 write-only CHEN Channel Enable 0 1 write-only UPDATEEN Update Overlay Attributes Enable 1 1 write-only HEOCHSR High End Overlay Channel Status Register 0x348 32 read-only n 0x0 0x0 A2QSR Add To Queue Status 2 1 read-only CHSR Channel Status 0 1 read-only UPDATESR Update Overlay Attributes In Progress Status 1 1 read-only HEOCLUT0 High End Overlay CLUT Register 0x1200 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT1 High End Overlay CLUT Register 0x1204 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT10 High End Overlay CLUT Register 0x1228 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT100 High End Overlay CLUT Register 0x1390 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT101 High End Overlay CLUT Register 0x1394 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT102 High End Overlay CLUT Register 0x1398 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT103 High End Overlay CLUT Register 0x139C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT104 High End Overlay CLUT Register 0x13A0 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT105 High End Overlay CLUT Register 0x13A4 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT106 High End Overlay CLUT Register 0x13A8 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT107 High End Overlay CLUT Register 0x13AC 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT108 High End Overlay CLUT Register 0x13B0 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT109 High End Overlay CLUT Register 0x13B4 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT11 High End Overlay CLUT Register 0x122C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT110 High End Overlay CLUT Register 0x13B8 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT111 High End Overlay CLUT Register 0x13BC 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT112 High End Overlay CLUT Register 0x13C0 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT113 High End Overlay CLUT Register 0x13C4 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT114 High End Overlay CLUT Register 0x13C8 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT115 High End Overlay CLUT Register 0x13CC 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT116 High End Overlay CLUT Register 0x13D0 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT117 High End Overlay CLUT Register 0x13D4 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT118 High End Overlay CLUT Register 0x13D8 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT119 High End Overlay CLUT Register 0x13DC 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT12 High End Overlay CLUT Register 0x1230 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT120 High End Overlay CLUT Register 0x13E0 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT121 High End Overlay CLUT Register 0x13E4 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT122 High End Overlay CLUT Register 0x13E8 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT123 High End Overlay CLUT Register 0x13EC 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT124 High End Overlay CLUT Register 0x13F0 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT125 High End Overlay CLUT Register 0x13F4 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT126 High End Overlay CLUT Register 0x13F8 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT127 High End Overlay CLUT Register 0x13FC 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT128 High End Overlay CLUT Register 0x1400 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT129 High End Overlay CLUT Register 0x1404 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT13 High End Overlay CLUT Register 0x1234 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT130 High End Overlay CLUT Register 0x1408 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT131 High End Overlay CLUT Register 0x140C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT132 High End Overlay CLUT Register 0x1410 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT133 High End Overlay CLUT Register 0x1414 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT134 High End Overlay CLUT Register 0x1418 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT135 High End Overlay CLUT Register 0x141C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT136 High End Overlay CLUT Register 0x1420 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT137 High End Overlay CLUT Register 0x1424 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT138 High End Overlay CLUT Register 0x1428 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT139 High End Overlay CLUT Register 0x142C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT14 High End Overlay CLUT Register 0x1238 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT140 High End Overlay CLUT Register 0x1430 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT141 High End Overlay CLUT Register 0x1434 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT142 High End Overlay CLUT Register 0x1438 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT143 High End Overlay CLUT Register 0x143C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT144 High End Overlay CLUT Register 0x1440 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT145 High End Overlay CLUT Register 0x1444 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT146 High End Overlay CLUT Register 0x1448 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT147 High End Overlay CLUT Register 0x144C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT148 High End Overlay CLUT Register 0x1450 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT149 High End Overlay CLUT Register 0x1454 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT15 High End Overlay CLUT Register 0x123C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT150 High End Overlay CLUT Register 0x1458 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT151 High End Overlay CLUT Register 0x145C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT152 High End Overlay CLUT Register 0x1460 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT153 High End Overlay CLUT Register 0x1464 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT154 High End Overlay CLUT Register 0x1468 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT155 High End Overlay CLUT Register 0x146C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT156 High End Overlay CLUT Register 0x1470 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT157 High End Overlay CLUT Register 0x1474 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT158 High End Overlay CLUT Register 0x1478 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT159 High End Overlay CLUT Register 0x147C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT16 High End Overlay CLUT Register 0x1240 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT160 High End Overlay CLUT Register 0x1480 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT161 High End Overlay CLUT Register 0x1484 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT162 High End Overlay CLUT Register 0x1488 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT163 High End Overlay CLUT Register 0x148C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT164 High End Overlay CLUT Register 0x1490 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT165 High End Overlay CLUT Register 0x1494 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT166 High End Overlay CLUT Register 0x1498 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT167 High End Overlay CLUT Register 0x149C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT168 High End Overlay CLUT Register 0x14A0 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT169 High End Overlay CLUT Register 0x14A4 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT17 High End Overlay CLUT Register 0x1244 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT170 High End Overlay CLUT Register 0x14A8 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT171 High End Overlay CLUT Register 0x14AC 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT172 High End Overlay CLUT Register 0x14B0 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT173 High End Overlay CLUT Register 0x14B4 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT174 High End Overlay CLUT Register 0x14B8 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT175 High End Overlay CLUT Register 0x14BC 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT176 High End Overlay CLUT Register 0x14C0 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT177 High End Overlay CLUT Register 0x14C4 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT178 High End Overlay CLUT Register 0x14C8 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT179 High End Overlay CLUT Register 0x14CC 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT18 High End Overlay CLUT Register 0x1248 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT180 High End Overlay CLUT Register 0x14D0 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT181 High End Overlay CLUT Register 0x14D4 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT182 High End Overlay CLUT Register 0x14D8 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT183 High End Overlay CLUT Register 0x14DC 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT184 High End Overlay CLUT Register 0x14E0 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT185 High End Overlay CLUT Register 0x14E4 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT186 High End Overlay CLUT Register 0x14E8 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT187 High End Overlay CLUT Register 0x14EC 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT188 High End Overlay CLUT Register 0x14F0 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT189 High End Overlay CLUT Register 0x14F4 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT19 High End Overlay CLUT Register 0x124C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT190 High End Overlay CLUT Register 0x14F8 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT191 High End Overlay CLUT Register 0x14FC 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT192 High End Overlay CLUT Register 0x1500 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT193 High End Overlay CLUT Register 0x1504 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT194 High End Overlay CLUT Register 0x1508 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT195 High End Overlay CLUT Register 0x150C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT196 High End Overlay CLUT Register 0x1510 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT197 High End Overlay CLUT Register 0x1514 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT198 High End Overlay CLUT Register 0x1518 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT199 High End Overlay CLUT Register 0x151C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT2 High End Overlay CLUT Register 0x1208 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT20 High End Overlay CLUT Register 0x1250 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT200 High End Overlay CLUT Register 0x1520 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT201 High End Overlay CLUT Register 0x1524 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT202 High End Overlay CLUT Register 0x1528 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT203 High End Overlay CLUT Register 0x152C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT204 High End Overlay CLUT Register 0x1530 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT205 High End Overlay CLUT Register 0x1534 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT206 High End Overlay CLUT Register 0x1538 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT207 High End Overlay CLUT Register 0x153C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT208 High End Overlay CLUT Register 0x1540 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT209 High End Overlay CLUT Register 0x1544 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT21 High End Overlay CLUT Register 0x1254 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT210 High End Overlay CLUT Register 0x1548 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT211 High End Overlay CLUT Register 0x154C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT212 High End Overlay CLUT Register 0x1550 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT213 High End Overlay CLUT Register 0x1554 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT214 High End Overlay CLUT Register 0x1558 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT215 High End Overlay CLUT Register 0x155C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT216 High End Overlay CLUT Register 0x1560 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT217 High End Overlay CLUT Register 0x1564 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT218 High End Overlay CLUT Register 0x1568 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT219 High End Overlay CLUT Register 0x156C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT22 High End Overlay CLUT Register 0x1258 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT220 High End Overlay CLUT Register 0x1570 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT221 High End Overlay CLUT Register 0x1574 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT222 High End Overlay CLUT Register 0x1578 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT223 High End Overlay CLUT Register 0x157C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT224 High End Overlay CLUT Register 0x1580 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT225 High End Overlay CLUT Register 0x1584 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT226 High End Overlay CLUT Register 0x1588 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT227 High End Overlay CLUT Register 0x158C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT228 High End Overlay CLUT Register 0x1590 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT229 High End Overlay CLUT Register 0x1594 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT23 High End Overlay CLUT Register 0x125C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT230 High End Overlay CLUT Register 0x1598 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT231 High End Overlay CLUT Register 0x159C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT232 High End Overlay CLUT Register 0x15A0 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT233 High End Overlay CLUT Register 0x15A4 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT234 High End Overlay CLUT Register 0x15A8 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT235 High End Overlay CLUT Register 0x15AC 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT236 High End Overlay CLUT Register 0x15B0 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT237 High End Overlay CLUT Register 0x15B4 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT238 High End Overlay CLUT Register 0x15B8 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT239 High End Overlay CLUT Register 0x15BC 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT24 High End Overlay CLUT Register 0x1260 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT240 High End Overlay CLUT Register 0x15C0 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT241 High End Overlay CLUT Register 0x15C4 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT242 High End Overlay CLUT Register 0x15C8 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT243 High End Overlay CLUT Register 0x15CC 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT244 High End Overlay CLUT Register 0x15D0 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT245 High End Overlay CLUT Register 0x15D4 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT246 High End Overlay CLUT Register 0x15D8 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT247 High End Overlay CLUT Register 0x15DC 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT248 High End Overlay CLUT Register 0x15E0 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT249 High End Overlay CLUT Register 0x15E4 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT25 High End Overlay CLUT Register 0x1264 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT250 High End Overlay CLUT Register 0x15E8 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT251 High End Overlay CLUT Register 0x15EC 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT252 High End Overlay CLUT Register 0x15F0 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT253 High End Overlay CLUT Register 0x15F4 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT254 High End Overlay CLUT Register 0x15F8 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT255 High End Overlay CLUT Register 0x15FC 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT26 High End Overlay CLUT Register 0x1268 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT27 High End Overlay CLUT Register 0x126C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT28 High End Overlay CLUT Register 0x1270 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT29 High End Overlay CLUT Register 0x1274 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT3 High End Overlay CLUT Register 0x120C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT30 High End Overlay CLUT Register 0x1278 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT31 High End Overlay CLUT Register 0x127C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT32 High End Overlay CLUT Register 0x1280 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT33 High End Overlay CLUT Register 0x1284 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT34 High End Overlay CLUT Register 0x1288 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT35 High End Overlay CLUT Register 0x128C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT36 High End Overlay CLUT Register 0x1290 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT37 High End Overlay CLUT Register 0x1294 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT38 High End Overlay CLUT Register 0x1298 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT39 High End Overlay CLUT Register 0x129C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT4 High End Overlay CLUT Register 0x1210 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT40 High End Overlay CLUT Register 0x12A0 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT41 High End Overlay CLUT Register 0x12A4 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT42 High End Overlay CLUT Register 0x12A8 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT43 High End Overlay CLUT Register 0x12AC 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT44 High End Overlay CLUT Register 0x12B0 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT45 High End Overlay CLUT Register 0x12B4 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT46 High End Overlay CLUT Register 0x12B8 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT47 High End Overlay CLUT Register 0x12BC 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT48 High End Overlay CLUT Register 0x12C0 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT49 High End Overlay CLUT Register 0x12C4 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT5 High End Overlay CLUT Register 0x1214 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT50 High End Overlay CLUT Register 0x12C8 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT51 High End Overlay CLUT Register 0x12CC 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT52 High End Overlay CLUT Register 0x12D0 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT53 High End Overlay CLUT Register 0x12D4 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT54 High End Overlay CLUT Register 0x12D8 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT55 High End Overlay CLUT Register 0x12DC 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT56 High End Overlay CLUT Register 0x12E0 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT57 High End Overlay CLUT Register 0x12E4 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT58 High End Overlay CLUT Register 0x12E8 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT59 High End Overlay CLUT Register 0x12EC 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT6 High End Overlay CLUT Register 0x1218 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT60 High End Overlay CLUT Register 0x12F0 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT61 High End Overlay CLUT Register 0x12F4 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT62 High End Overlay CLUT Register 0x12F8 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT63 High End Overlay CLUT Register 0x12FC 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT64 High End Overlay CLUT Register 0x1300 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT65 High End Overlay CLUT Register 0x1304 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT66 High End Overlay CLUT Register 0x1308 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT67 High End Overlay CLUT Register 0x130C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT68 High End Overlay CLUT Register 0x1310 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT69 High End Overlay CLUT Register 0x1314 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT7 High End Overlay CLUT Register 0x121C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT70 High End Overlay CLUT Register 0x1318 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT71 High End Overlay CLUT Register 0x131C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT72 High End Overlay CLUT Register 0x1320 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT73 High End Overlay CLUT Register 0x1324 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT74 High End Overlay CLUT Register 0x1328 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT75 High End Overlay CLUT Register 0x132C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT76 High End Overlay CLUT Register 0x1330 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT77 High End Overlay CLUT Register 0x1334 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT78 High End Overlay CLUT Register 0x1338 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT79 High End Overlay CLUT Register 0x133C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT8 High End Overlay CLUT Register 0x1220 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT80 High End Overlay CLUT Register 0x1340 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT81 High End Overlay CLUT Register 0x1344 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT82 High End Overlay CLUT Register 0x1348 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT83 High End Overlay CLUT Register 0x134C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT84 High End Overlay CLUT Register 0x1350 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT85 High End Overlay CLUT Register 0x1354 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT86 High End Overlay CLUT Register 0x1358 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT87 High End Overlay CLUT Register 0x135C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT88 High End Overlay CLUT Register 0x1360 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT89 High End Overlay CLUT Register 0x1364 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT9 High End Overlay CLUT Register 0x1224 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT90 High End Overlay CLUT Register 0x1368 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT91 High End Overlay CLUT Register 0x136C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT92 High End Overlay CLUT Register 0x1370 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT93 High End Overlay CLUT Register 0x1374 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT94 High End Overlay CLUT Register 0x1378 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT95 High End Overlay CLUT Register 0x137C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT96 High End Overlay CLUT Register 0x1380 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT97 High End Overlay CLUT Register 0x1384 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT98 High End Overlay CLUT Register 0x1388 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT99 High End Overlay CLUT Register 0x138C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[0] High End Overlay CLUT Register 0x2400 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[100] High End Overlay CLUT Register 0x77AE8 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[101] High End Overlay CLUT Register 0x78E7C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[102] High End Overlay CLUT Register 0x7A214 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[103] High End Overlay CLUT Register 0x7B5B0 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[104] High End Overlay CLUT Register 0x7C950 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[105] High End Overlay CLUT Register 0x7DCF4 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[106] High End Overlay CLUT Register 0x7F09C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[107] High End Overlay CLUT Register 0x80448 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[108] High End Overlay CLUT Register 0x817F8 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[109] High End Overlay CLUT Register 0x82BAC 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[10] High End Overlay CLUT Register 0xD8DC 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[110] High End Overlay CLUT Register 0x83F64 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[111] High End Overlay CLUT Register 0x85320 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[112] High End Overlay CLUT Register 0x866E0 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[113] High End Overlay CLUT Register 0x87AA4 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[114] High End Overlay CLUT Register 0x88E6C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[115] High End Overlay CLUT Register 0x8A238 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[116] High End Overlay CLUT Register 0x8B608 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[117] High End Overlay CLUT Register 0x8C9DC 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[118] High End Overlay CLUT Register 0x8DDB4 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[119] High End Overlay CLUT Register 0x8F190 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[11] High End Overlay CLUT Register 0xEB08 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[120] High End Overlay CLUT Register 0x90570 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[121] High End Overlay CLUT Register 0x91954 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[122] High End Overlay CLUT Register 0x92D3C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[123] High End Overlay CLUT Register 0x94128 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[124] High End Overlay CLUT Register 0x95518 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[125] High End Overlay CLUT Register 0x9690C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[126] High End Overlay CLUT Register 0x97D04 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[127] High End Overlay CLUT Register 0x99100 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[128] High End Overlay CLUT Register 0x9A500 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[129] High End Overlay CLUT Register 0x9B904 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[12] High End Overlay CLUT Register 0xFD38 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[130] High End Overlay CLUT Register 0x9CD0C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[131] High End Overlay CLUT Register 0x9E118 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[132] High End Overlay CLUT Register 0x9F528 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[133] High End Overlay CLUT Register 0xA093C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[134] High End Overlay CLUT Register 0xA1D54 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[135] High End Overlay CLUT Register 0xA3170 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[136] High End Overlay CLUT Register 0xA4590 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[137] High End Overlay CLUT Register 0xA59B4 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[138] High End Overlay CLUT Register 0xA6DDC 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[139] High End Overlay CLUT Register 0xA8208 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[13] High End Overlay CLUT Register 0x10F6C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[140] High End Overlay CLUT Register 0xA9638 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[141] High End Overlay CLUT Register 0xAAA6C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[142] High End Overlay CLUT Register 0xABEA4 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[143] High End Overlay CLUT Register 0xAD2E0 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[144] High End Overlay CLUT Register 0xAE720 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[145] High End Overlay CLUT Register 0xAFB64 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[146] High End Overlay CLUT Register 0xB0FAC 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[147] High End Overlay CLUT Register 0xB23F8 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[148] High End Overlay CLUT Register 0xB3848 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[149] High End Overlay CLUT Register 0xB4C9C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[14] High End Overlay CLUT Register 0x121A4 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[150] High End Overlay CLUT Register 0xB60F4 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[151] High End Overlay CLUT Register 0xB7550 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[152] High End Overlay CLUT Register 0xB89B0 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[153] High End Overlay CLUT Register 0xB9E14 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[154] High End Overlay CLUT Register 0xBB27C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[155] High End Overlay CLUT Register 0xBC6E8 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[156] High End Overlay CLUT Register 0xBDB58 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[157] High End Overlay CLUT Register 0xBEFCC 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[158] High End Overlay CLUT Register 0xC0444 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[159] High End Overlay CLUT Register 0xC18C0 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[15] High End Overlay CLUT Register 0x133E0 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[160] High End Overlay CLUT Register 0xC2D40 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[161] High End Overlay CLUT Register 0xC41C4 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[162] High End Overlay CLUT Register 0xC564C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[163] High End Overlay CLUT Register 0xC6AD8 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[164] High End Overlay CLUT Register 0xC7F68 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[165] High End Overlay CLUT Register 0xC93FC 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[166] High End Overlay CLUT Register 0xCA894 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[167] High End Overlay CLUT Register 0xCBD30 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[168] High End Overlay CLUT Register 0xCD1D0 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[169] High End Overlay CLUT Register 0xCE674 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[16] High End Overlay CLUT Register 0x14620 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[170] High End Overlay CLUT Register 0xCFB1C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[171] High End Overlay CLUT Register 0xD0FC8 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[172] High End Overlay CLUT Register 0xD2478 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[173] High End Overlay CLUT Register 0xD392C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[174] High End Overlay CLUT Register 0xD4DE4 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[175] High End Overlay CLUT Register 0xD62A0 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[176] High End Overlay CLUT Register 0xD7760 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[177] High End Overlay CLUT Register 0xD8C24 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[178] High End Overlay CLUT Register 0xDA0EC 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[179] High End Overlay CLUT Register 0xDB5B8 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[17] High End Overlay CLUT Register 0x15864 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[180] High End Overlay CLUT Register 0xDCA88 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[181] High End Overlay CLUT Register 0xDDF5C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[182] High End Overlay CLUT Register 0xDF434 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[183] High End Overlay CLUT Register 0xE0910 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[184] High End Overlay CLUT Register 0xE1DF0 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[185] High End Overlay CLUT Register 0xE32D4 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[186] High End Overlay CLUT Register 0xE47BC 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[187] High End Overlay CLUT Register 0xE5CA8 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[188] High End Overlay CLUT Register 0xE7198 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[189] High End Overlay CLUT Register 0xE868C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[18] High End Overlay CLUT Register 0x16AAC 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[190] High End Overlay CLUT Register 0xE9B84 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[191] High End Overlay CLUT Register 0xEB080 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[192] High End Overlay CLUT Register 0xEC580 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[193] High End Overlay CLUT Register 0xEDA84 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[194] High End Overlay CLUT Register 0xEEF8C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[195] High End Overlay CLUT Register 0xF0498 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[196] High End Overlay CLUT Register 0xF19A8 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[197] High End Overlay CLUT Register 0xF2EBC 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[198] High End Overlay CLUT Register 0xF43D4 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[199] High End Overlay CLUT Register 0xF58F0 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[19] High End Overlay CLUT Register 0x17CF8 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[1] High End Overlay CLUT Register 0x3604 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[200] High End Overlay CLUT Register 0xF6E10 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[201] High End Overlay CLUT Register 0xF8334 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[202] High End Overlay CLUT Register 0xF985C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[203] High End Overlay CLUT Register 0xFAD88 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[204] High End Overlay CLUT Register 0xFC2B8 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[205] High End Overlay CLUT Register 0xFD7EC 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[206] High End Overlay CLUT Register 0xFED24 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[207] High End Overlay CLUT Register 0x100260 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[208] High End Overlay CLUT Register 0x1017A0 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[209] High End Overlay CLUT Register 0x102CE4 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[20] High End Overlay CLUT Register 0x18F48 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[210] High End Overlay CLUT Register 0x10422C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[211] High End Overlay CLUT Register 0x105778 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[212] High End Overlay CLUT Register 0x106CC8 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[213] High End Overlay CLUT Register 0x10821C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[214] High End Overlay CLUT Register 0x109774 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[215] High End Overlay CLUT Register 0x10ACD0 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[216] High End Overlay CLUT Register 0x10C230 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[217] High End Overlay CLUT Register 0x10D794 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[218] High End Overlay CLUT Register 0x10ECFC 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[219] High End Overlay CLUT Register 0x110268 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[21] High End Overlay CLUT Register 0x1A19C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[220] High End Overlay CLUT Register 0x1117D8 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[221] High End Overlay CLUT Register 0x112D4C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[222] High End Overlay CLUT Register 0x1142C4 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[223] High End Overlay CLUT Register 0x115840 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[224] High End Overlay CLUT Register 0x116DC0 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[225] High End Overlay CLUT Register 0x118344 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[226] High End Overlay CLUT Register 0x1198CC 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[227] High End Overlay CLUT Register 0x11AE58 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[228] High End Overlay CLUT Register 0x11C3E8 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[229] High End Overlay CLUT Register 0x11D97C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[22] High End Overlay CLUT Register 0x1B3F4 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[230] High End Overlay CLUT Register 0x11EF14 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[231] High End Overlay CLUT Register 0x1204B0 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[232] High End Overlay CLUT Register 0x121A50 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[233] High End Overlay CLUT Register 0x122FF4 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[234] High End Overlay CLUT Register 0x12459C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[235] High End Overlay CLUT Register 0x125B48 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[236] High End Overlay CLUT Register 0x1270F8 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[237] High End Overlay CLUT Register 0x1286AC 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[238] High End Overlay CLUT Register 0x129C64 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[239] High End Overlay CLUT Register 0x12B220 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[23] High End Overlay CLUT Register 0x1C650 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[240] High End Overlay CLUT Register 0x12C7E0 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[241] High End Overlay CLUT Register 0x12DDA4 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[242] High End Overlay CLUT Register 0x12F36C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[243] High End Overlay CLUT Register 0x130938 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[244] High End Overlay CLUT Register 0x131F08 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[245] High End Overlay CLUT Register 0x1334DC 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[246] High End Overlay CLUT Register 0x134AB4 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[247] High End Overlay CLUT Register 0x136090 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[248] High End Overlay CLUT Register 0x137670 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[249] High End Overlay CLUT Register 0x138C54 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[24] High End Overlay CLUT Register 0x1D8B0 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[250] High End Overlay CLUT Register 0x13A23C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[251] High End Overlay CLUT Register 0x13B828 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[252] High End Overlay CLUT Register 0x13CE18 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[253] High End Overlay CLUT Register 0x13E40C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[254] High End Overlay CLUT Register 0x13FA04 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[255] High End Overlay CLUT Register 0x141000 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[25] High End Overlay CLUT Register 0x1EB14 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[26] High End Overlay CLUT Register 0x1FD7C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[27] High End Overlay CLUT Register 0x20FE8 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[28] High End Overlay CLUT Register 0x22258 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[29] High End Overlay CLUT Register 0x234CC 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[2] High End Overlay CLUT Register 0x480C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[30] High End Overlay CLUT Register 0x24744 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[31] High End Overlay CLUT Register 0x259C0 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[32] High End Overlay CLUT Register 0x26C40 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[33] High End Overlay CLUT Register 0x27EC4 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[34] High End Overlay CLUT Register 0x2914C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[35] High End Overlay CLUT Register 0x2A3D8 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[36] High End Overlay CLUT Register 0x2B668 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[37] High End Overlay CLUT Register 0x2C8FC 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[38] High End Overlay CLUT Register 0x2DB94 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[39] High End Overlay CLUT Register 0x2EE30 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[3] High End Overlay CLUT Register 0x5A18 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[40] High End Overlay CLUT Register 0x300D0 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[41] High End Overlay CLUT Register 0x31374 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[42] High End Overlay CLUT Register 0x3261C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[43] High End Overlay CLUT Register 0x338C8 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[44] High End Overlay CLUT Register 0x34B78 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[45] High End Overlay CLUT Register 0x35E2C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[46] High End Overlay CLUT Register 0x370E4 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[47] High End Overlay CLUT Register 0x383A0 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[48] High End Overlay CLUT Register 0x39660 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[49] High End Overlay CLUT Register 0x3A924 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[4] High End Overlay CLUT Register 0x6C28 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[50] High End Overlay CLUT Register 0x3BBEC 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[51] High End Overlay CLUT Register 0x3CEB8 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[52] High End Overlay CLUT Register 0x3E188 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[53] High End Overlay CLUT Register 0x3F45C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[54] High End Overlay CLUT Register 0x40734 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[55] High End Overlay CLUT Register 0x41A10 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[56] High End Overlay CLUT Register 0x42CF0 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[57] High End Overlay CLUT Register 0x43FD4 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[58] High End Overlay CLUT Register 0x452BC 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[59] High End Overlay CLUT Register 0x465A8 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[5] High End Overlay CLUT Register 0x7E3C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[60] High End Overlay CLUT Register 0x47898 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[61] High End Overlay CLUT Register 0x48B8C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[62] High End Overlay CLUT Register 0x49E84 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[63] High End Overlay CLUT Register 0x4B180 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[64] High End Overlay CLUT Register 0x4C480 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[65] High End Overlay CLUT Register 0x4D784 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[66] High End Overlay CLUT Register 0x4EA8C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[67] High End Overlay CLUT Register 0x4FD98 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[68] High End Overlay CLUT Register 0x510A8 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[69] High End Overlay CLUT Register 0x523BC 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[6] High End Overlay CLUT Register 0x9054 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[70] High End Overlay CLUT Register 0x536D4 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[71] High End Overlay CLUT Register 0x549F0 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[72] High End Overlay CLUT Register 0x55D10 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[73] High End Overlay CLUT Register 0x57034 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[74] High End Overlay CLUT Register 0x5835C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[75] High End Overlay CLUT Register 0x59688 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[76] High End Overlay CLUT Register 0x5A9B8 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[77] High End Overlay CLUT Register 0x5BCEC 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[78] High End Overlay CLUT Register 0x5D024 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[79] High End Overlay CLUT Register 0x5E360 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[7] High End Overlay CLUT Register 0xA270 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[80] High End Overlay CLUT Register 0x5F6A0 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[81] High End Overlay CLUT Register 0x609E4 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[82] High End Overlay CLUT Register 0x61D2C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[83] High End Overlay CLUT Register 0x63078 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[84] High End Overlay CLUT Register 0x643C8 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[85] High End Overlay CLUT Register 0x6571C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[86] High End Overlay CLUT Register 0x66A74 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[87] High End Overlay CLUT Register 0x67DD0 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[88] High End Overlay CLUT Register 0x69130 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[89] High End Overlay CLUT Register 0x6A494 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[8] High End Overlay CLUT Register 0xB490 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[90] High End Overlay CLUT Register 0x6B7FC 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[91] High End Overlay CLUT Register 0x6CB68 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[92] High End Overlay CLUT Register 0x6DED8 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[93] High End Overlay CLUT Register 0x6F24C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[94] High End Overlay CLUT Register 0x705C4 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[95] High End Overlay CLUT Register 0x71940 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[96] High End Overlay CLUT Register 0x72CC0 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[97] High End Overlay CLUT Register 0x74044 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[98] High End Overlay CLUT Register 0x753CC 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[99] High End Overlay CLUT Register 0x76758 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCLUT[9] High End Overlay CLUT Register 0xC6B4 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write HEOCTRL High End Overlay DMA Control Register 0x364 32 read-write n 0x0 0x0 ADDIEN Add Head Descriptor to Queue Interrupt Enable 4 1 read-write DFETCH Transfer Descriptor Fetch Enable 0 1 read-write DMAIEN End of DMA Transfer Interrupt Enable 2 1 read-write DONEIEN End of List Interrupt Enable 5 1 read-write DSCRIEN Descriptor Loaded Interrupt Enable 3 1 read-write LFETCH Lookup Table Fetch Enable 1 1 read-write HEOHEAD High End Overlay DMA Head Register 0x35C 32 read-write n 0x0 0x0 HEAD DMA Head Pointer 2 30 read-write HEOIDR High End Overlay Interrupt Disable Register 0x350 32 write-only n 0x0 0x0 ADD Head Descriptor Loaded Interrupt Disable 4 1 write-only DMA End of DMA Transfer Interrupt Disable 2 1 write-only DONE End of List Interrupt Disable 5 1 write-only DSCR Descriptor Loaded Interrupt Disable 3 1 write-only OVR Overflow Interrupt Disable 6 1 write-only UADD Head Descriptor Loaded for U or UV Chrominance Component Interrupt Disable 12 1 write-only UDMA End of DMA Transfer for U or UV Chrominance Component Interrupt Disable 10 1 write-only UDONE End of List Interrupt for U or UV Chrominance Component Disable 13 1 write-only UDSCR Descriptor Loaded for U or UV Chrominance Component Interrupt Disable 11 1 write-only UOVR Overflow Interrupt for U or UV Chrominance Component Disable 14 1 write-only VADD Head Descriptor Loaded for V Chrominance Component Interrupt Disable 20 1 write-only VDMA End of DMA Transfer for V Chrominance Component Interrupt Disable 18 1 write-only VDONE End of List for V Chrominance Component Interrupt Disable 21 1 write-only VDSCR Descriptor Loaded for V Chrominance Component Interrupt Disable 19 1 write-only VOVR Overflow for V Chrominance Component Interrupt Disable 22 1 write-only HEOIER High End Overlay Interrupt Enable Register 0x34C 32 write-only n 0x0 0x0 ADD Head Descriptor Loaded Interrupt Enable 4 1 write-only DMA End of DMA Transfer Interrupt Enable 2 1 write-only DONE End of List Interrupt Enable 5 1 write-only DSCR Descriptor Loaded Interrupt Enable 3 1 write-only OVR Overflow Interrupt Enable 6 1 write-only UADD Head Descriptor Loaded for U or UV Chrominance Interrupt Enable 12 1 write-only UDMA End of DMA Transfer for U or UV Chrominance Interrupt Enable 10 1 write-only UDONE End of List for U or UV Chrominance Interrupt Enable 13 1 write-only UDSCR Descriptor Loaded for U or UV Chrominance Interrupt Enable 11 1 write-only UOVR Overflow for U or UV Chrominance Interrupt Enable 14 1 write-only VADD Head Descriptor Loaded for V Chrominance Interrupt Enable 20 1 write-only VDMA End of DMA for V Chrominance Transfer Interrupt Enable 18 1 write-only VDONE End of List for V Chrominance Interrupt Enable 21 1 write-only VDSCR Descriptor Loaded for V Chrominance Interrupt Enable 19 1 write-only VOVR Overflow for V Chrominance Interrupt Enable 22 1 write-only HEOIMR High End Overlay Interrupt Mask Register 0x354 32 read-only n 0x0 0x0 ADD Head Descriptor Loaded Interrupt Mask 4 1 read-only DMA End of DMA Transfer Interrupt Mask 2 1 read-only DONE End of List Interrupt Mask 5 1 read-only DSCR Descriptor Loaded Interrupt Mask 3 1 read-only OVR Overflow Interrupt Mask 6 1 read-only UADD Head Descriptor Loaded for U or UV Chrominance Component Mask 12 1 read-only UDMA End of DMA Transfer for U or UV Chrominance Component Interrupt Mask 10 1 read-only UDONE End of List for U or UV Chrominance Component Mask 13 1 read-only UDSCR Descriptor Loaded for U or UV Chrominance Component Interrupt Mask 11 1 read-only UOVR Overflow for U Chrominance Interrupt Mask 14 1 read-only VADD Head Descriptor Loaded for V Chrominance Component Mask 20 1 read-only VDMA End of DMA Transfer for V Chrominance Component Interrupt Mask 18 1 read-only VDONE End of List for V Chrominance Component Mask 21 1 read-only VDSCR Descriptor Loaded for V Chrominance Component Interrupt Mask 19 1 read-only VOVR Overflow for V Chrominance Interrupt Mask 22 1 read-only HEOISR High End Overlay Interrupt Status Register 0x358 32 read-only n 0x0 0x0 ADD Head Descriptor Loaded 4 1 read-only DMA End of DMA Transfer 2 1 read-only DONE End of List Detected 5 1 read-only DSCR DMA Descriptor Loaded 3 1 read-only OVR Overflow Detected 6 1 read-only UADD Head Descriptor Loaded for U Component 12 1 read-only UDMA End of DMA Transfer for U Component 10 1 read-only UDONE End of List Detected for U Component 13 1 read-only UDSCR DMA Descriptor Loaded for U Component 11 1 read-only UOVR Overflow Detected for U Component 14 1 read-only VADD Head Descriptor Loaded for V Component 20 1 read-only VDMA End of DMA Transfer for V Component 18 1 read-only VDONE End of List Detected for V Component 21 1 read-only VDSCR DMA Descriptor Loaded for V Component 19 1 read-only VOVR Overflow Detected for V Component 22 1 read-only HEONEXT High End Overlay DMA Next Register 0x368 32 read-write n 0x0 0x0 NEXT DMA Descriptor Next Address 0 32 read-write HEOUADDR High End Overlay U-UV DMA Address Register 0x370 32 read-write n 0x0 0x0 UADDR DMA Transfer Start Address for U or UV Chrominance 0 32 read-write HEOUCTRL High End Overlay U-UV DMA Control Register 0x374 32 read-write n 0x0 0x0 UADDIEN Add Head Descriptor to Queue Interrupt Enable 4 1 read-write UDFETCH Transfer Descriptor Fetch Enable 0 1 read-write UDMAIEN End of DMA Transfer Interrupt Enable 2 1 read-write UDONEIEN End of List Interrupt Enable 5 1 read-write UDSCRIEN Descriptor Loaded Interrupt Enable 3 1 read-write HEOUHEAD High End Overlay U-UV DMA Head Register 0x36C 32 read-write n 0x0 0x0 UHEAD DMA Head Pointer 0 32 read-write HEOUNEXT High End Overlay U-UV DMA Next Register 0x378 32 read-write n 0x0 0x0 UNEXT DMA Descriptor Next Address 0 32 read-write HEOVADDR High End Overlay V DMA Address Register 0x380 32 read-write n 0x0 0x0 VADDR DMA Transfer Start Address for V Chrominance 0 32 read-write HEOVCTRL High End Overlay V DMA Control Register 0x384 32 read-write n 0x0 0x0 VADDIEN Add Head Descriptor to Queue Interrupt Enable 4 1 read-write VDFETCH Transfer Descriptor Fetch Enable 0 1 read-write VDMAIEN End of DMA Transfer Interrupt Enable 2 1 read-write VDONEIEN End of List Interrupt Enable 5 1 read-write VDSCRIEN Descriptor Loaded Interrupt Enable 3 1 read-write HEOVHEAD High End Overlay V DMA Head Register 0x37C 32 read-write n 0x0 0x0 VHEAD DMA Head Pointer 0 32 read-write HEOVNEXT High End Overlay V DMA Next Register 0x388 32 read-write n 0x0 0x0 VNEXT DMA Descriptor Next Address 0 32 read-write LCDCFG0 LCD Controller Configuration Register 0 0x0 32 read-write n 0x0 0x0 CGDISBASE Clock Gating Disable Control for the Base Layer 8 1 read-write CGDISHEO Clock Gating Disable Control for the High End Overlay 11 1 read-write CGDISOVR1 Clock Gating Disable Control for the Overlay 1 Layer 9 1 read-write CLKDIV LCD Controller Clock Divider 16 8 read-write CLKPOL LCD Controller Clock Polarity 0 1 read-write CLKPWMSEL LCD Controller PWM Clock Source Selection 3 1 read-write CLKSEL LCD Controller Clock Source Selection 2 1 read-write LCDCFG1 LCD Controller Configuration Register 1 0x4 32 read-write n 0x0 0x0 HSPW Horizontal Synchronization Pulse Width 0 10 read-write VSPW Vertical Synchronization Pulse Width 16 10 read-write LCDCFG2 LCD Controller Configuration Register 2 0x8 32 read-write n 0x0 0x0 VBPW Vertical Back Porch Width 16 10 read-write VFPW Vertical Front Porch Width 0 10 read-write LCDCFG3 LCD Controller Configuration Register 3 0xC 32 read-write n 0x0 0x0 HBPW Horizontal Back Porch Width 16 10 read-write HFPW Horizontal Front Porch Width 0 10 read-write LCDCFG4 LCD Controller Configuration Register 4 0x10 32 read-write n 0x0 0x0 PPL Number of Pixels Per Line 0 11 read-write RPF Number of Active Row Per Frame 16 11 read-write LCDCFG5 LCD Controller Configuration Register 5 0x14 32 read-write n 0x0 0x0 DISPDLY LCD Controller Display Power Signal Synchronization 7 1 read-write DISPPOL Display Signal Polarity 4 1 read-write DITHER LCD Controller Dithering 6 1 read-write GUARDTIME LCD DISPLAY Guard Time 16 8 read-write HSPOL Horizontal Synchronization Pulse Polarity 0 1 read-write MODE LCD Controller Output Mode 8 2 read-write OUTPUT_12BPP LCD Output mode is set to 12 bits per pixel 0x0 OUTPUT_16BPP LCD Output mode is set to 16 bits per pixel 0x1 OUTPUT_18BPP LCD Output mode is set to 18 bits per pixel 0x2 OUTPUT_24BPP LCD Output mode is set to 24 bits per pixel 0x3 VSPDLYE Vertical Synchronization Pulse End 3 1 read-write VSPDLYS Vertical Synchronization Pulse Start 2 1 read-write VSPHO LCD Controller Vertical synchronization Pulse Hold Configuration 13 1 read-write VSPOL Vertical Synchronization Pulse Polarity 1 1 read-write VSPSU LCD Controller Vertical synchronization Pulse Setup Configuration 12 1 read-write LCDCFG6 LCD Controller Configuration Register 6 0x18 32 read-write n 0x0 0x0 PWMCVAL LCD Controller PWM Compare Value 8 8 read-write PWMPOL LCD Controller PWM Signal Polarity 4 1 read-write PWMPS PWM Clock Prescaler 0 3 read-write DIV_1 The counter advances at a rate of fCOUNTER = fPWM_SELECTED_CLOCK 0x0 DIV_2 The counter advances at a rate of fCOUNTER = fPWM_SELECTED_CLOCK/2 0x1 DIV_4 The counter advances at a rate of fCOUNTER = fPWM_SELECTED_CLOCK/4 0x2 DIV_8 The counter advances at a rate of fCOUNTER = fPWM_SELECTED_CLOCK/8 0x3 DIV_16 The counter advances at a rate of fCOUNTER = fPWM_SELECTED_CLOCK/16 0x4 DIV_32 The counter advances at a of rate fCOUNTER = fPWM_SELECTED_CLOCK/32 0x5 DIV_64 The counter advances at a of rate fCOUNTER = fPWM_SELECTED_CLOCK/64 0x6 LCDDIS LCD Controller Disable Register 0x24 32 write-only n 0x0 0x0 CLKDIS LCD Controller Pixel Clock Disable 0 1 write-only CLKRST LCD Controller Clock Reset 8 1 write-only DISPDIS LCD Controller DISP Signal Disable 2 1 write-only DISPRST LCD Controller DISP Signal Reset 10 1 write-only PWMDIS LCD Controller Pulse Width Modulation Disable 3 1 write-only PWMRST LCD Controller PWM Reset 11 1 write-only SYNCDIS LCD Controller Horizontal and Vertical Synchronization Disable 1 1 write-only SYNCRST LCD Controller Horizontal and Vertical Synchronization Reset 9 1 write-only LCDEN LCD Controller Enable Register 0x20 32 write-only n 0x0 0x0 CLKEN LCD Controller Pixel Clock Enable 0 1 write-only DISPEN LCD Controller DISP Signal Enable 2 1 write-only PWMEN LCD Controller Pulse Width Modulation Enable 3 1 write-only SYNCEN LCD Controller Horizontal and Vertical Synchronization Enable 1 1 write-only LCDIDR LCD Controller Interrupt Disable Register 0x30 32 write-only n 0x0 0x0 BASEID Base Layer Interrupt Disable 8 1 write-only DISID LCD Disable Interrupt Disable 1 1 write-only DISPID Power UP/Down Sequence Terminated Interrupt Disable 2 1 write-only FIFOERRID Output FIFO Error Interrupt Disable 4 1 write-only HEOID High End Overlay Interrupt Disable 11 1 write-only OVR1ID Overlay 1 Interrupt Disable 9 1 write-only SOFID Start of Frame Interrupt Disable 0 1 write-only LCDIER LCD Controller Interrupt Enable Register 0x2C 32 write-only n 0x0 0x0 BASEIE Base Layer Interrupt Enable 8 1 write-only DISIE LCD Disable Interrupt Enable 1 1 write-only DISPIE Power UP/Down Sequence Terminated Interrupt Enable 2 1 write-only FIFOERRIE Output FIFO Error Interrupt Enable 4 1 write-only HEOIE High End Overlay Interrupt Enable 11 1 write-only OVR1IE Overlay 1 Interrupt Enable 9 1 write-only SOFIE Start of Frame Interrupt Enable 0 1 write-only LCDIMR LCD Controller Interrupt Mask Register 0x34 32 read-only n 0x0 0x0 BASEIM Base Layer Interrupt Mask 8 1 read-only DISIM LCD Disable Interrupt Mask 1 1 read-only DISPIM Power UP/Down Sequence Terminated Interrupt Mask 2 1 read-only FIFOERRIM Output FIFO Error Interrupt Mask 4 1 read-only HEOIM High End Overlay Interrupt Mask 11 1 read-only OVR1IM Overlay 1 Interrupt Mask 9 1 read-only SOFIM Start of Frame Interrupt Mask 0 1 read-only LCDISR LCD Controller Interrupt Status Register 0x38 32 read-only n 0x0 0x0 BASE Base Layer Raw Interrupt Status 8 1 read-only DIS LCD Disable Interrupt Status 1 1 read-only DISP Power-up/Power-down Sequence Terminated Interrupt Status 2 1 read-only FIFOERR Output FIFO Error 4 1 read-only HEO High End Overlay Raw Interrupt Status 11 1 read-only OVR1 Overlay 1 Raw Interrupt Status 9 1 read-only SOF Start of Frame Interrupt Status 0 1 read-only LCDSR LCD Controller Status Register 0x28 32 read-only n 0x0 0x0 CLKSTS Clock Status 0 1 read-only DISPSTS LCD Controller DISP Signal Status 2 1 read-only LCDSTS LCD Controller Synchronization status 1 1 read-only PWMSTS LCD Controller PWM Signal Status 3 1 read-only SIPSTS Synchronization In Progress 4 1 read-only OVR1ADDR Overlay 1 DMA Address Register 0x160 32 read-write n 0x0 0x0 ADDR DMA Transfer Overlay 1 Address 0 32 read-write OVR1CFG0 Overlay 1 Configuration Register 0 0x16C 32 read-write n 0x0 0x0 BLEN AHB Burst Length 4 2 read-write AHB_BLEN_SINGLE AHB Access is started as soon as there is enough space in the FIFO to store one data. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. 0x0 AHB_BLEN_INCR4 AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 4 data. An AHB INCR4 Burst is used. SINGLE, INCR and INCR4 bursts are used. INCR is used for a burst of 2 and 3 beats. 0x1 AHB_BLEN_INCR8 AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 8 data. An AHB INCR8 Burst is used. SINGLE, INCR, INCR4 and INCR8 bursts are used. INCR is used for a burst of 2 and 3 beats. 0x2 AHB_BLEN_INCR16 AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 16 data. An AHB INCR16 Burst is used. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. 0x3 DLBO Defined Length Burst Only for Channel Bus Transaction 8 1 read-write LOCKDIS Hardware Rotation Lock Disable 13 1 read-write ROTDIS Hardware Rotation Optimization Disable 12 1 read-write SIF Source Interface 0 1 read-write OVR1CFG1 Overlay 1 Configuration Register 1 0x170 32 read-write n 0x0 0x0 CLUTEN Color Lookup Table Mode Enable 0 1 read-write CLUTMODE Color Lookup Table Mode Input Selection 8 2 read-write CLUT_1BPP Color Lookup Table mode set to 1 bit per pixel 0x0 CLUT_2BPP Color Lookup Table mode set to 2 bits per pixel 0x1 CLUT_4BPP Color Lookup Table mode set to 4 bits per pixel 0x2 CLUT_8BPP Color Lookup Table mode set to 8 bits per pixel 0x3 RGBMODE RGB Mode Input Selection 4 4 read-write 12BPP_RGB_444 12 bpp RGB 444 0x0 16BPP_ARGB_4444 16 bpp ARGB 4444 0x1 16BPP_RGBA_4444 16 bpp RGBA 4444 0x2 16BPP_RGB_565 16 bpp RGB 565 0x3 16BPP_TRGB_1555 16 bpp TRGB 1555 0x4 18BPP_RGB_666 18 bpp RGB 666 0x5 18BPP_RGB_666PACKED 18 bpp RGB 666 PACKED 0x6 19BPP_TRGB_1666 19 bpp TRGB 1666 0x7 19BPP_TRGB_PACKED 19 bpp TRGB 1666 PACKED 0x8 24BPP_RGB_888 24 bpp RGB 888 0x9 24BPP_RGB_888_PACKED 24 bpp RGB 888 PACKED 0xA 25BPP_TRGB_1888 25 bpp TRGB 1888 0xB 32BPP_ARGB_8888 32 bpp ARGB 8888 0xC 32BPP_RGBA_8888 32 bpp RGBA 8888 0xD OVR1CFG2 Overlay 1 Configuration Register 2 0x174 32 read-write n 0x0 0x0 XPOS Horizontal Window Position 0 11 read-write YPOS Vertical Window Position 16 11 read-write OVR1CFG3 Overlay 1 Configuration Register 3 0x178 32 read-write n 0x0 0x0 XSIZE Horizontal Window Size 0 11 read-write YSIZE Vertical Window Size 16 11 read-write OVR1CFG4 Overlay 1 Configuration Register 4 0x17C 32 read-write n 0x0 0x0 XSTRIDE Horizontal Stride 0 32 read-write OVR1CFG5 Overlay 1 Configuration Register 5 0x180 32 read-write n 0x0 0x0 PSTRIDE Pixel Stride 0 32 read-write OVR1CFG6 Overlay 1 Configuration Register 6 0x184 32 read-write n 0x0 0x0 BDEF Blue Default 0 8 read-write GDEF Green Default 8 8 read-write RDEF Red Default 16 8 read-write OVR1CFG7 Overlay 1 Configuration Register 7 0x188 32 read-write n 0x0 0x0 BKEY Blue Color Component Chroma Key 0 8 read-write GKEY Green Color Component Chroma Key 8 8 read-write RKEY Red Color Component Chroma Key 16 8 read-write OVR1CFG8 Overlay 1 Configuration Register 8 0x18C 32 read-write n 0x0 0x0 BMASK Blue Color Component Chroma Key Mask 0 8 read-write GMASK Green Color Component Chroma Key Mask 8 8 read-write RMASK Red Color Component Chroma Key Mask 16 8 read-write OVR1CFG9 Overlay 1 Configuration Register 9 0x190 32 read-write n 0x0 0x0 CRKEY Blender Chroma Key Enable 0 1 read-write DMA Blender DMA Layer Enable 8 1 read-write DSTKEY Destination Chroma Keying 10 1 read-write GA Blender Global Alpha 16 8 read-write GAEN Blender Global Alpha Enable 5 1 read-write INV Blender Inverted Blender Output Enable 1 1 read-write ITER Blender Use Iterated Color 3 1 read-write ITER2BL Blender Iterated Color Enable 2 1 read-write LAEN Blender Local Alpha Enable 6 1 read-write OVR Blender Overlay Layer Enable 7 1 read-write REP Use Replication logic to expand RGB color to 24 bits 9 1 read-write REVALPHA Blender Reverse Alpha 4 1 read-write OVR1CHDR Overlay 1 Channel Disable Register 0x144 32 write-only n 0x0 0x0 CHDIS Channel Disable 0 1 write-only CHRST Channel Reset 8 1 write-only OVR1CHER Overlay 1 Channel Enable Register 0x140 32 write-only n 0x0 0x0 A2QEN Add To Queue Enable 2 1 write-only CHEN Channel Enable 0 1 write-only UPDATEEN Update Overlay Attributes Enable 1 1 write-only OVR1CHSR Overlay 1 Channel Status Register 0x148 32 read-only n 0x0 0x0 A2QSR Add To Queue Status 2 1 read-only CHSR Channel Status 0 1 read-only UPDATESR Update Overlay Attributes In Progress Status 1 1 read-only OVR1CLUT0 Overlay 1 CLUT Register 0xA00 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT1 Overlay 1 CLUT Register 0xA04 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT10 Overlay 1 CLUT Register 0xA28 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT100 Overlay 1 CLUT Register 0xB90 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT101 Overlay 1 CLUT Register 0xB94 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT102 Overlay 1 CLUT Register 0xB98 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT103 Overlay 1 CLUT Register 0xB9C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT104 Overlay 1 CLUT Register 0xBA0 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT105 Overlay 1 CLUT Register 0xBA4 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT106 Overlay 1 CLUT Register 0xBA8 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT107 Overlay 1 CLUT Register 0xBAC 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT108 Overlay 1 CLUT Register 0xBB0 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT109 Overlay 1 CLUT Register 0xBB4 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT11 Overlay 1 CLUT Register 0xA2C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT110 Overlay 1 CLUT Register 0xBB8 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT111 Overlay 1 CLUT Register 0xBBC 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT112 Overlay 1 CLUT Register 0xBC0 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT113 Overlay 1 CLUT Register 0xBC4 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT114 Overlay 1 CLUT Register 0xBC8 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT115 Overlay 1 CLUT Register 0xBCC 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT116 Overlay 1 CLUT Register 0xBD0 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT117 Overlay 1 CLUT Register 0xBD4 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT118 Overlay 1 CLUT Register 0xBD8 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT119 Overlay 1 CLUT Register 0xBDC 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT12 Overlay 1 CLUT Register 0xA30 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT120 Overlay 1 CLUT Register 0xBE0 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT121 Overlay 1 CLUT Register 0xBE4 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT122 Overlay 1 CLUT Register 0xBE8 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT123 Overlay 1 CLUT Register 0xBEC 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT124 Overlay 1 CLUT Register 0xBF0 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT125 Overlay 1 CLUT Register 0xBF4 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT126 Overlay 1 CLUT Register 0xBF8 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT127 Overlay 1 CLUT Register 0xBFC 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT128 Overlay 1 CLUT Register 0xC00 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT129 Overlay 1 CLUT Register 0xC04 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT13 Overlay 1 CLUT Register 0xA34 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT130 Overlay 1 CLUT Register 0xC08 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT131 Overlay 1 CLUT Register 0xC0C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT132 Overlay 1 CLUT Register 0xC10 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT133 Overlay 1 CLUT Register 0xC14 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT134 Overlay 1 CLUT Register 0xC18 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT135 Overlay 1 CLUT Register 0xC1C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT136 Overlay 1 CLUT Register 0xC20 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT137 Overlay 1 CLUT Register 0xC24 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT138 Overlay 1 CLUT Register 0xC28 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT139 Overlay 1 CLUT Register 0xC2C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT14 Overlay 1 CLUT Register 0xA38 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT140 Overlay 1 CLUT Register 0xC30 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT141 Overlay 1 CLUT Register 0xC34 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT142 Overlay 1 CLUT Register 0xC38 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT143 Overlay 1 CLUT Register 0xC3C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT144 Overlay 1 CLUT Register 0xC40 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT145 Overlay 1 CLUT Register 0xC44 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT146 Overlay 1 CLUT Register 0xC48 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT147 Overlay 1 CLUT Register 0xC4C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT148 Overlay 1 CLUT Register 0xC50 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT149 Overlay 1 CLUT Register 0xC54 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT15 Overlay 1 CLUT Register 0xA3C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT150 Overlay 1 CLUT Register 0xC58 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT151 Overlay 1 CLUT Register 0xC5C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT152 Overlay 1 CLUT Register 0xC60 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT153 Overlay 1 CLUT Register 0xC64 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT154 Overlay 1 CLUT Register 0xC68 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT155 Overlay 1 CLUT Register 0xC6C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT156 Overlay 1 CLUT Register 0xC70 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT157 Overlay 1 CLUT Register 0xC74 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT158 Overlay 1 CLUT Register 0xC78 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT159 Overlay 1 CLUT Register 0xC7C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT16 Overlay 1 CLUT Register 0xA40 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT160 Overlay 1 CLUT Register 0xC80 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT161 Overlay 1 CLUT Register 0xC84 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT162 Overlay 1 CLUT Register 0xC88 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT163 Overlay 1 CLUT Register 0xC8C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT164 Overlay 1 CLUT Register 0xC90 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT165 Overlay 1 CLUT Register 0xC94 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT166 Overlay 1 CLUT Register 0xC98 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT167 Overlay 1 CLUT Register 0xC9C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT168 Overlay 1 CLUT Register 0xCA0 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT169 Overlay 1 CLUT Register 0xCA4 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT17 Overlay 1 CLUT Register 0xA44 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT170 Overlay 1 CLUT Register 0xCA8 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT171 Overlay 1 CLUT Register 0xCAC 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT172 Overlay 1 CLUT Register 0xCB0 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT173 Overlay 1 CLUT Register 0xCB4 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT174 Overlay 1 CLUT Register 0xCB8 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT175 Overlay 1 CLUT Register 0xCBC 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT176 Overlay 1 CLUT Register 0xCC0 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT177 Overlay 1 CLUT Register 0xCC4 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT178 Overlay 1 CLUT Register 0xCC8 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT179 Overlay 1 CLUT Register 0xCCC 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT18 Overlay 1 CLUT Register 0xA48 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT180 Overlay 1 CLUT Register 0xCD0 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT181 Overlay 1 CLUT Register 0xCD4 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT182 Overlay 1 CLUT Register 0xCD8 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT183 Overlay 1 CLUT Register 0xCDC 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT184 Overlay 1 CLUT Register 0xCE0 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT185 Overlay 1 CLUT Register 0xCE4 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT186 Overlay 1 CLUT Register 0xCE8 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT187 Overlay 1 CLUT Register 0xCEC 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT188 Overlay 1 CLUT Register 0xCF0 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT189 Overlay 1 CLUT Register 0xCF4 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT19 Overlay 1 CLUT Register 0xA4C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT190 Overlay 1 CLUT Register 0xCF8 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT191 Overlay 1 CLUT Register 0xCFC 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT192 Overlay 1 CLUT Register 0xD00 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT193 Overlay 1 CLUT Register 0xD04 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT194 Overlay 1 CLUT Register 0xD08 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT195 Overlay 1 CLUT Register 0xD0C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT196 Overlay 1 CLUT Register 0xD10 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT197 Overlay 1 CLUT Register 0xD14 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT198 Overlay 1 CLUT Register 0xD18 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT199 Overlay 1 CLUT Register 0xD1C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT2 Overlay 1 CLUT Register 0xA08 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT20 Overlay 1 CLUT Register 0xA50 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT200 Overlay 1 CLUT Register 0xD20 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT201 Overlay 1 CLUT Register 0xD24 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT202 Overlay 1 CLUT Register 0xD28 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT203 Overlay 1 CLUT Register 0xD2C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT204 Overlay 1 CLUT Register 0xD30 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT205 Overlay 1 CLUT Register 0xD34 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT206 Overlay 1 CLUT Register 0xD38 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT207 Overlay 1 CLUT Register 0xD3C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT208 Overlay 1 CLUT Register 0xD40 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT209 Overlay 1 CLUT Register 0xD44 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT21 Overlay 1 CLUT Register 0xA54 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT210 Overlay 1 CLUT Register 0xD48 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT211 Overlay 1 CLUT Register 0xD4C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT212 Overlay 1 CLUT Register 0xD50 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT213 Overlay 1 CLUT Register 0xD54 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT214 Overlay 1 CLUT Register 0xD58 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT215 Overlay 1 CLUT Register 0xD5C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT216 Overlay 1 CLUT Register 0xD60 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT217 Overlay 1 CLUT Register 0xD64 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT218 Overlay 1 CLUT Register 0xD68 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT219 Overlay 1 CLUT Register 0xD6C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT22 Overlay 1 CLUT Register 0xA58 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT220 Overlay 1 CLUT Register 0xD70 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT221 Overlay 1 CLUT Register 0xD74 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT222 Overlay 1 CLUT Register 0xD78 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT223 Overlay 1 CLUT Register 0xD7C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT224 Overlay 1 CLUT Register 0xD80 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT225 Overlay 1 CLUT Register 0xD84 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT226 Overlay 1 CLUT Register 0xD88 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT227 Overlay 1 CLUT Register 0xD8C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT228 Overlay 1 CLUT Register 0xD90 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT229 Overlay 1 CLUT Register 0xD94 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT23 Overlay 1 CLUT Register 0xA5C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT230 Overlay 1 CLUT Register 0xD98 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT231 Overlay 1 CLUT Register 0xD9C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT232 Overlay 1 CLUT Register 0xDA0 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT233 Overlay 1 CLUT Register 0xDA4 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT234 Overlay 1 CLUT Register 0xDA8 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT235 Overlay 1 CLUT Register 0xDAC 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT236 Overlay 1 CLUT Register 0xDB0 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT237 Overlay 1 CLUT Register 0xDB4 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT238 Overlay 1 CLUT Register 0xDB8 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT239 Overlay 1 CLUT Register 0xDBC 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT24 Overlay 1 CLUT Register 0xA60 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT240 Overlay 1 CLUT Register 0xDC0 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT241 Overlay 1 CLUT Register 0xDC4 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT242 Overlay 1 CLUT Register 0xDC8 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT243 Overlay 1 CLUT Register 0xDCC 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT244 Overlay 1 CLUT Register 0xDD0 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT245 Overlay 1 CLUT Register 0xDD4 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT246 Overlay 1 CLUT Register 0xDD8 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT247 Overlay 1 CLUT Register 0xDDC 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT248 Overlay 1 CLUT Register 0xDE0 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT249 Overlay 1 CLUT Register 0xDE4 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT25 Overlay 1 CLUT Register 0xA64 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT250 Overlay 1 CLUT Register 0xDE8 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT251 Overlay 1 CLUT Register 0xDEC 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT252 Overlay 1 CLUT Register 0xDF0 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT253 Overlay 1 CLUT Register 0xDF4 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT254 Overlay 1 CLUT Register 0xDF8 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT255 Overlay 1 CLUT Register 0xDFC 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT26 Overlay 1 CLUT Register 0xA68 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT27 Overlay 1 CLUT Register 0xA6C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT28 Overlay 1 CLUT Register 0xA70 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT29 Overlay 1 CLUT Register 0xA74 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT3 Overlay 1 CLUT Register 0xA0C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT30 Overlay 1 CLUT Register 0xA78 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT31 Overlay 1 CLUT Register 0xA7C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT32 Overlay 1 CLUT Register 0xA80 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT33 Overlay 1 CLUT Register 0xA84 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT34 Overlay 1 CLUT Register 0xA88 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT35 Overlay 1 CLUT Register 0xA8C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT36 Overlay 1 CLUT Register 0xA90 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT37 Overlay 1 CLUT Register 0xA94 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT38 Overlay 1 CLUT Register 0xA98 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT39 Overlay 1 CLUT Register 0xA9C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT4 Overlay 1 CLUT Register 0xA10 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT40 Overlay 1 CLUT Register 0xAA0 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT41 Overlay 1 CLUT Register 0xAA4 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT42 Overlay 1 CLUT Register 0xAA8 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT43 Overlay 1 CLUT Register 0xAAC 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT44 Overlay 1 CLUT Register 0xAB0 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT45 Overlay 1 CLUT Register 0xAB4 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT46 Overlay 1 CLUT Register 0xAB8 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT47 Overlay 1 CLUT Register 0xABC 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT48 Overlay 1 CLUT Register 0xAC0 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT49 Overlay 1 CLUT Register 0xAC4 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT5 Overlay 1 CLUT Register 0xA14 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT50 Overlay 1 CLUT Register 0xAC8 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT51 Overlay 1 CLUT Register 0xACC 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT52 Overlay 1 CLUT Register 0xAD0 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT53 Overlay 1 CLUT Register 0xAD4 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT54 Overlay 1 CLUT Register 0xAD8 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT55 Overlay 1 CLUT Register 0xADC 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT56 Overlay 1 CLUT Register 0xAE0 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT57 Overlay 1 CLUT Register 0xAE4 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT58 Overlay 1 CLUT Register 0xAE8 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT59 Overlay 1 CLUT Register 0xAEC 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT6 Overlay 1 CLUT Register 0xA18 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT60 Overlay 1 CLUT Register 0xAF0 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT61 Overlay 1 CLUT Register 0xAF4 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT62 Overlay 1 CLUT Register 0xAF8 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT63 Overlay 1 CLUT Register 0xAFC 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT64 Overlay 1 CLUT Register 0xB00 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT65 Overlay 1 CLUT Register 0xB04 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT66 Overlay 1 CLUT Register 0xB08 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT67 Overlay 1 CLUT Register 0xB0C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT68 Overlay 1 CLUT Register 0xB10 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT69 Overlay 1 CLUT Register 0xB14 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT7 Overlay 1 CLUT Register 0xA1C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT70 Overlay 1 CLUT Register 0xB18 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT71 Overlay 1 CLUT Register 0xB1C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT72 Overlay 1 CLUT Register 0xB20 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT73 Overlay 1 CLUT Register 0xB24 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT74 Overlay 1 CLUT Register 0xB28 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT75 Overlay 1 CLUT Register 0xB2C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT76 Overlay 1 CLUT Register 0xB30 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT77 Overlay 1 CLUT Register 0xB34 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT78 Overlay 1 CLUT Register 0xB38 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT79 Overlay 1 CLUT Register 0xB3C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT8 Overlay 1 CLUT Register 0xA20 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT80 Overlay 1 CLUT Register 0xB40 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT81 Overlay 1 CLUT Register 0xB44 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT82 Overlay 1 CLUT Register 0xB48 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT83 Overlay 1 CLUT Register 0xB4C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT84 Overlay 1 CLUT Register 0xB50 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT85 Overlay 1 CLUT Register 0xB54 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT86 Overlay 1 CLUT Register 0xB58 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT87 Overlay 1 CLUT Register 0xB5C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT88 Overlay 1 CLUT Register 0xB60 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT89 Overlay 1 CLUT Register 0xB64 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT9 Overlay 1 CLUT Register 0xA24 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT90 Overlay 1 CLUT Register 0xB68 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT91 Overlay 1 CLUT Register 0xB6C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT92 Overlay 1 CLUT Register 0xB70 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT93 Overlay 1 CLUT Register 0xB74 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT94 Overlay 1 CLUT Register 0xB78 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT95 Overlay 1 CLUT Register 0xB7C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT96 Overlay 1 CLUT Register 0xB80 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT97 Overlay 1 CLUT Register 0xB84 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT98 Overlay 1 CLUT Register 0xB88 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT99 Overlay 1 CLUT Register 0xB8C 32 read-write n ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[0] Overlay 1 CLUT Register 0x1400 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[100] Overlay 1 CLUT Register 0x44AE8 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[101] Overlay 1 CLUT Register 0x4567C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[102] Overlay 1 CLUT Register 0x46214 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[103] Overlay 1 CLUT Register 0x46DB0 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[104] Overlay 1 CLUT Register 0x47950 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[105] Overlay 1 CLUT Register 0x484F4 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[106] Overlay 1 CLUT Register 0x4909C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[107] Overlay 1 CLUT Register 0x49C48 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[108] Overlay 1 CLUT Register 0x4A7F8 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[109] Overlay 1 CLUT Register 0x4B3AC 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[10] Overlay 1 CLUT Register 0x78DC 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[110] Overlay 1 CLUT Register 0x4BF64 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[111] Overlay 1 CLUT Register 0x4CB20 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[112] Overlay 1 CLUT Register 0x4D6E0 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[113] Overlay 1 CLUT Register 0x4E2A4 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[114] Overlay 1 CLUT Register 0x4EE6C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[115] Overlay 1 CLUT Register 0x4FA38 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[116] Overlay 1 CLUT Register 0x50608 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[117] Overlay 1 CLUT Register 0x511DC 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[118] Overlay 1 CLUT Register 0x51DB4 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[119] Overlay 1 CLUT Register 0x52990 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[11] Overlay 1 CLUT Register 0x8308 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[120] Overlay 1 CLUT Register 0x53570 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[121] Overlay 1 CLUT Register 0x54154 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[122] Overlay 1 CLUT Register 0x54D3C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[123] Overlay 1 CLUT Register 0x55928 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[124] Overlay 1 CLUT Register 0x56518 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[125] Overlay 1 CLUT Register 0x5710C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[126] Overlay 1 CLUT Register 0x57D04 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[127] Overlay 1 CLUT Register 0x58900 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[128] Overlay 1 CLUT Register 0x59500 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[129] Overlay 1 CLUT Register 0x5A104 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[12] Overlay 1 CLUT Register 0x8D38 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[130] Overlay 1 CLUT Register 0x5AD0C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[131] Overlay 1 CLUT Register 0x5B918 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[132] Overlay 1 CLUT Register 0x5C528 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[133] Overlay 1 CLUT Register 0x5D13C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[134] Overlay 1 CLUT Register 0x5DD54 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[135] Overlay 1 CLUT Register 0x5E970 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[136] Overlay 1 CLUT Register 0x5F590 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[137] Overlay 1 CLUT Register 0x601B4 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[138] Overlay 1 CLUT Register 0x60DDC 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[139] Overlay 1 CLUT Register 0x61A08 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[13] Overlay 1 CLUT Register 0x976C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[140] Overlay 1 CLUT Register 0x62638 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[141] Overlay 1 CLUT Register 0x6326C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[142] Overlay 1 CLUT Register 0x63EA4 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[143] Overlay 1 CLUT Register 0x64AE0 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[144] Overlay 1 CLUT Register 0x65720 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[145] Overlay 1 CLUT Register 0x66364 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[146] Overlay 1 CLUT Register 0x66FAC 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[147] Overlay 1 CLUT Register 0x67BF8 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[148] Overlay 1 CLUT Register 0x68848 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[149] Overlay 1 CLUT Register 0x6949C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[14] Overlay 1 CLUT Register 0xA1A4 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[150] Overlay 1 CLUT Register 0x6A0F4 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[151] Overlay 1 CLUT Register 0x6AD50 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[152] Overlay 1 CLUT Register 0x6B9B0 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[153] Overlay 1 CLUT Register 0x6C614 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[154] Overlay 1 CLUT Register 0x6D27C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[155] Overlay 1 CLUT Register 0x6DEE8 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[156] Overlay 1 CLUT Register 0x6EB58 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[157] Overlay 1 CLUT Register 0x6F7CC 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[158] Overlay 1 CLUT Register 0x70444 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[159] Overlay 1 CLUT Register 0x710C0 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[15] Overlay 1 CLUT Register 0xABE0 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[160] Overlay 1 CLUT Register 0x71D40 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[161] Overlay 1 CLUT Register 0x729C4 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[162] Overlay 1 CLUT Register 0x7364C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[163] Overlay 1 CLUT Register 0x742D8 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[164] Overlay 1 CLUT Register 0x74F68 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[165] Overlay 1 CLUT Register 0x75BFC 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[166] Overlay 1 CLUT Register 0x76894 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[167] Overlay 1 CLUT Register 0x77530 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[168] Overlay 1 CLUT Register 0x781D0 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[169] Overlay 1 CLUT Register 0x78E74 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[16] Overlay 1 CLUT Register 0xB620 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[170] Overlay 1 CLUT Register 0x79B1C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[171] Overlay 1 CLUT Register 0x7A7C8 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[172] Overlay 1 CLUT Register 0x7B478 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[173] Overlay 1 CLUT Register 0x7C12C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[174] Overlay 1 CLUT Register 0x7CDE4 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[175] Overlay 1 CLUT Register 0x7DAA0 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[176] Overlay 1 CLUT Register 0x7E760 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[177] Overlay 1 CLUT Register 0x7F424 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[178] Overlay 1 CLUT Register 0x800EC 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[179] Overlay 1 CLUT Register 0x80DB8 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[17] Overlay 1 CLUT Register 0xC064 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[180] Overlay 1 CLUT Register 0x81A88 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[181] Overlay 1 CLUT Register 0x8275C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[182] Overlay 1 CLUT Register 0x83434 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[183] Overlay 1 CLUT Register 0x84110 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[184] Overlay 1 CLUT Register 0x84DF0 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[185] Overlay 1 CLUT Register 0x85AD4 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[186] Overlay 1 CLUT Register 0x867BC 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[187] Overlay 1 CLUT Register 0x874A8 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[188] Overlay 1 CLUT Register 0x88198 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[189] Overlay 1 CLUT Register 0x88E8C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[18] Overlay 1 CLUT Register 0xCAAC 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[190] Overlay 1 CLUT Register 0x89B84 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[191] Overlay 1 CLUT Register 0x8A880 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[192] Overlay 1 CLUT Register 0x8B580 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[193] Overlay 1 CLUT Register 0x8C284 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[194] Overlay 1 CLUT Register 0x8CF8C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[195] Overlay 1 CLUT Register 0x8DC98 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[196] Overlay 1 CLUT Register 0x8E9A8 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[197] Overlay 1 CLUT Register 0x8F6BC 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[198] Overlay 1 CLUT Register 0x903D4 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[199] Overlay 1 CLUT Register 0x910F0 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[19] Overlay 1 CLUT Register 0xD4F8 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[1] Overlay 1 CLUT Register 0x1E04 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[200] Overlay 1 CLUT Register 0x91E10 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[201] Overlay 1 CLUT Register 0x92B34 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[202] Overlay 1 CLUT Register 0x9385C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[203] Overlay 1 CLUT Register 0x94588 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[204] Overlay 1 CLUT Register 0x952B8 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[205] Overlay 1 CLUT Register 0x95FEC 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[206] Overlay 1 CLUT Register 0x96D24 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[207] Overlay 1 CLUT Register 0x97A60 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[208] Overlay 1 CLUT Register 0x987A0 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[209] Overlay 1 CLUT Register 0x994E4 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[20] Overlay 1 CLUT Register 0xDF48 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[210] Overlay 1 CLUT Register 0x9A22C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[211] Overlay 1 CLUT Register 0x9AF78 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[212] Overlay 1 CLUT Register 0x9BCC8 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[213] Overlay 1 CLUT Register 0x9CA1C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[214] Overlay 1 CLUT Register 0x9D774 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[215] Overlay 1 CLUT Register 0x9E4D0 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[216] Overlay 1 CLUT Register 0x9F230 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[217] Overlay 1 CLUT Register 0x9FF94 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[218] Overlay 1 CLUT Register 0xA0CFC 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[219] Overlay 1 CLUT Register 0xA1A68 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[21] Overlay 1 CLUT Register 0xE99C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[220] Overlay 1 CLUT Register 0xA27D8 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[221] Overlay 1 CLUT Register 0xA354C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[222] Overlay 1 CLUT Register 0xA42C4 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[223] Overlay 1 CLUT Register 0xA5040 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[224] Overlay 1 CLUT Register 0xA5DC0 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[225] Overlay 1 CLUT Register 0xA6B44 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[226] Overlay 1 CLUT Register 0xA78CC 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[227] Overlay 1 CLUT Register 0xA8658 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[228] Overlay 1 CLUT Register 0xA93E8 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[229] Overlay 1 CLUT Register 0xAA17C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[22] Overlay 1 CLUT Register 0xF3F4 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[230] Overlay 1 CLUT Register 0xAAF14 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[231] Overlay 1 CLUT Register 0xABCB0 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[232] Overlay 1 CLUT Register 0xACA50 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[233] Overlay 1 CLUT Register 0xAD7F4 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[234] Overlay 1 CLUT Register 0xAE59C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[235] Overlay 1 CLUT Register 0xAF348 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[236] Overlay 1 CLUT Register 0xB00F8 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[237] Overlay 1 CLUT Register 0xB0EAC 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[238] Overlay 1 CLUT Register 0xB1C64 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[239] Overlay 1 CLUT Register 0xB2A20 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[23] Overlay 1 CLUT Register 0xFE50 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[240] Overlay 1 CLUT Register 0xB37E0 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[241] Overlay 1 CLUT Register 0xB45A4 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[242] Overlay 1 CLUT Register 0xB536C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[243] Overlay 1 CLUT Register 0xB6138 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[244] Overlay 1 CLUT Register 0xB6F08 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[245] Overlay 1 CLUT Register 0xB7CDC 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[246] Overlay 1 CLUT Register 0xB8AB4 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[247] Overlay 1 CLUT Register 0xB9890 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[248] Overlay 1 CLUT Register 0xBA670 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[249] Overlay 1 CLUT Register 0xBB454 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[24] Overlay 1 CLUT Register 0x108B0 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[250] Overlay 1 CLUT Register 0xBC23C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[251] Overlay 1 CLUT Register 0xBD028 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[252] Overlay 1 CLUT Register 0xBDE18 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[253] Overlay 1 CLUT Register 0xBEC0C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[254] Overlay 1 CLUT Register 0xBFA04 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[255] Overlay 1 CLUT Register 0xC0800 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[25] Overlay 1 CLUT Register 0x11314 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[26] Overlay 1 CLUT Register 0x11D7C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[27] Overlay 1 CLUT Register 0x127E8 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[28] Overlay 1 CLUT Register 0x13258 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[29] Overlay 1 CLUT Register 0x13CCC 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[2] Overlay 1 CLUT Register 0x280C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[30] Overlay 1 CLUT Register 0x14744 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[31] Overlay 1 CLUT Register 0x151C0 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[32] Overlay 1 CLUT Register 0x15C40 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[33] Overlay 1 CLUT Register 0x166C4 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[34] Overlay 1 CLUT Register 0x1714C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[35] Overlay 1 CLUT Register 0x17BD8 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[36] Overlay 1 CLUT Register 0x18668 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[37] Overlay 1 CLUT Register 0x190FC 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[38] Overlay 1 CLUT Register 0x19B94 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[39] Overlay 1 CLUT Register 0x1A630 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[3] Overlay 1 CLUT Register 0x3218 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[40] Overlay 1 CLUT Register 0x1B0D0 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[41] Overlay 1 CLUT Register 0x1BB74 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[42] Overlay 1 CLUT Register 0x1C61C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[43] Overlay 1 CLUT Register 0x1D0C8 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[44] Overlay 1 CLUT Register 0x1DB78 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[45] Overlay 1 CLUT Register 0x1E62C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[46] Overlay 1 CLUT Register 0x1F0E4 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[47] Overlay 1 CLUT Register 0x1FBA0 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[48] Overlay 1 CLUT Register 0x20660 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[49] Overlay 1 CLUT Register 0x21124 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[4] Overlay 1 CLUT Register 0x3C28 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[50] Overlay 1 CLUT Register 0x21BEC 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[51] Overlay 1 CLUT Register 0x226B8 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[52] Overlay 1 CLUT Register 0x23188 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[53] Overlay 1 CLUT Register 0x23C5C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[54] Overlay 1 CLUT Register 0x24734 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[55] Overlay 1 CLUT Register 0x25210 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[56] Overlay 1 CLUT Register 0x25CF0 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[57] Overlay 1 CLUT Register 0x267D4 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[58] Overlay 1 CLUT Register 0x272BC 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[59] Overlay 1 CLUT Register 0x27DA8 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[5] Overlay 1 CLUT Register 0x463C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[60] Overlay 1 CLUT Register 0x28898 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[61] Overlay 1 CLUT Register 0x2938C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[62] Overlay 1 CLUT Register 0x29E84 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[63] Overlay 1 CLUT Register 0x2A980 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[64] Overlay 1 CLUT Register 0x2B480 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[65] Overlay 1 CLUT Register 0x2BF84 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[66] Overlay 1 CLUT Register 0x2CA8C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[67] Overlay 1 CLUT Register 0x2D598 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[68] Overlay 1 CLUT Register 0x2E0A8 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[69] Overlay 1 CLUT Register 0x2EBBC 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[6] Overlay 1 CLUT Register 0x5054 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[70] Overlay 1 CLUT Register 0x2F6D4 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[71] Overlay 1 CLUT Register 0x301F0 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[72] Overlay 1 CLUT Register 0x30D10 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[73] Overlay 1 CLUT Register 0x31834 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[74] Overlay 1 CLUT Register 0x3235C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[75] Overlay 1 CLUT Register 0x32E88 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[76] Overlay 1 CLUT Register 0x339B8 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[77] Overlay 1 CLUT Register 0x344EC 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[78] Overlay 1 CLUT Register 0x35024 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[79] Overlay 1 CLUT Register 0x35B60 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[7] Overlay 1 CLUT Register 0x5A70 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[80] Overlay 1 CLUT Register 0x366A0 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[81] Overlay 1 CLUT Register 0x371E4 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[82] Overlay 1 CLUT Register 0x37D2C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[83] Overlay 1 CLUT Register 0x38878 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[84] Overlay 1 CLUT Register 0x393C8 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[85] Overlay 1 CLUT Register 0x39F1C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[86] Overlay 1 CLUT Register 0x3AA74 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[87] Overlay 1 CLUT Register 0x3B5D0 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[88] Overlay 1 CLUT Register 0x3C130 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[89] Overlay 1 CLUT Register 0x3CC94 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[8] Overlay 1 CLUT Register 0x6490 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[90] Overlay 1 CLUT Register 0x3D7FC 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[91] Overlay 1 CLUT Register 0x3E368 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[92] Overlay 1 CLUT Register 0x3EED8 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[93] Overlay 1 CLUT Register 0x3FA4C 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[94] Overlay 1 CLUT Register 0x405C4 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[95] Overlay 1 CLUT Register 0x41140 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[96] Overlay 1 CLUT Register 0x41CC0 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[97] Overlay 1 CLUT Register 0x42844 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[98] Overlay 1 CLUT Register 0x433CC 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[99] Overlay 1 CLUT Register 0x43F58 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CLUT[9] Overlay 1 CLUT Register 0x6EB4 32 read-write n 0x0 0x0 ACLUT Alpha Color Entry 24 8 read-write BCLUT Blue Color Entry 0 8 read-write GCLUT Green Color Entry 8 8 read-write RCLUT Red Color Entry 16 8 read-write OVR1CTRL Overlay 1 DMA Control Register 0x164 32 read-write n 0x0 0x0 ADDIEN Add Head Descriptor to Queue Interrupt Enable 4 1 read-write DFETCH Transfer Descriptor Fetch Enable 0 1 read-write DMAIEN End of DMA Transfer Interrupt Enable 2 1 read-write DONEIEN End of List Interrupt Enable 5 1 read-write DSCRIEN Descriptor Loaded Interrupt Enable 3 1 read-write LFETCH Lookup Table Fetch Enable 1 1 read-write OVR1HEAD Overlay 1 DMA Head Register 0x15C 32 read-write n 0x0 0x0 HEAD DMA Head Pointer 2 30 read-write OVR1IDR Overlay 1 Interrupt Disable Register 0x150 32 write-only n 0x0 0x0 ADD Head Descriptor Loaded Interrupt Disable 4 1 write-only DMA End of DMA Transfer Interrupt Disable 2 1 write-only DONE End of List Interrupt Disable 5 1 write-only DSCR Descriptor Loaded Interrupt Disable 3 1 write-only OVR Overflow Interrupt Disable 6 1 write-only OVR1IER Overlay 1 Interrupt Enable Register 0x14C 32 write-only n 0x0 0x0 ADD Head Descriptor Loaded Interrupt Enable 4 1 write-only DMA End of DMA Transfer Interrupt Enable 2 1 write-only DONE End of List Interrupt Enable 5 1 write-only DSCR Descriptor Loaded Interrupt Enable 3 1 write-only OVR Overflow Interrupt Enable 6 1 write-only OVR1IMR Overlay 1 Interrupt Mask Register 0x154 32 read-only n 0x0 0x0 ADD Head Descriptor Loaded Interrupt Mask 4 1 read-only DMA End of DMA Transfer Interrupt Mask 2 1 read-only DONE End of List Interrupt Mask 5 1 read-only DSCR Descriptor Loaded Interrupt Mask 3 1 read-only OVR Overflow Interrupt Mask 6 1 read-only OVR1ISR Overlay 1 Interrupt Status Register 0x158 32 read-only n 0x0 0x0 ADD Head Descriptor Loaded 4 1 read-only DMA End of DMA Transfer 2 1 read-only DONE End of List Detected 5 1 read-only DSCR DMA Descriptor Loaded 3 1 read-only OVR Overflow Detected 6 1 read-only OVR1NEXT Overlay 1 DMA Next Register 0x168 32 read-write n 0x0 0x0 NEXT DMA Descriptor Next Address 0 32 read-write MATRIX0 AHB Bus Matrix 0 MATRIX 0x0 0x0 0x50 registers n MATRIX0 18 MCFG0 Master Configuration Register 0x0 32 read-write n ULBT Undefined Length Burst Type 0 3 read-write UNLIMITED Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0x0 SINGLE Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 0x1 4_BEAT 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 0x2 8_BEAT 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 0x3 16_BEAT 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 0x4 32_BEAT 32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 0x5 64_BEAT 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 0x6 128_BEAT 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving. 0x7 MCFG1 Master Configuration Register 0x4 32 read-write n ULBT Undefined Length Burst Type 0 3 read-write UNLIMITED Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0x0 SINGLE Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 0x1 4_BEAT 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 0x2 8_BEAT 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 0x3 16_BEAT 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 0x4 32_BEAT 32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 0x5 64_BEAT 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 0x6 128_BEAT 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving. 0x7 MCFG2 Master Configuration Register 0x8 32 read-write n ULBT Undefined Length Burst Type 0 3 read-write UNLIMITED Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0x0 SINGLE Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 0x1 4_BEAT 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 0x2 8_BEAT 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 0x3 16_BEAT 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 0x4 32_BEAT 32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 0x5 64_BEAT 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 0x6 128_BEAT 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving. 0x7 MCFG3 Master Configuration Register 0xC 32 read-write n ULBT Undefined Length Burst Type 0 3 read-write UNLIMITED Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0x0 SINGLE Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 0x1 4_BEAT 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 0x2 8_BEAT 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 0x3 16_BEAT 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 0x4 32_BEAT 32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 0x5 64_BEAT 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 0x6 128_BEAT 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving. 0x7 MCFG4 Master Configuration Register 0x10 32 read-write n ULBT Undefined Length Burst Type 0 3 read-write UNLIMITED Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0x0 SINGLE Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 0x1 4_BEAT 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 0x2 8_BEAT 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 0x3 16_BEAT 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 0x4 32_BEAT 32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 0x5 64_BEAT 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 0x6 128_BEAT 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving. 0x7 MCFG5 Master Configuration Register 0x14 32 read-write n ULBT Undefined Length Burst Type 0 3 read-write UNLIMITED Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0x0 SINGLE Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 0x1 4_BEAT 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 0x2 8_BEAT 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 0x3 16_BEAT 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 0x4 32_BEAT 32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 0x5 64_BEAT 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 0x6 128_BEAT 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving. 0x7 MCFG6 Master Configuration Register 0x18 32 read-write n ULBT Undefined Length Burst Type 0 3 read-write UNLIMITED Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0x0 SINGLE Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 0x1 4_BEAT 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 0x2 8_BEAT 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 0x3 16_BEAT 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 0x4 32_BEAT 32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 0x5 64_BEAT 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 0x6 128_BEAT 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving. 0x7 MCFG7 Master Configuration Register 0x1C 32 read-write n ULBT Undefined Length Burst Type 0 3 read-write UNLIMITED Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0x0 SINGLE Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 0x1 4_BEAT 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 0x2 8_BEAT 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 0x3 16_BEAT 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 0x4 32_BEAT 32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 0x5 64_BEAT 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 0x6 128_BEAT 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving. 0x7 MCFG8 Master Configuration Register 0x20 32 read-write n ULBT Undefined Length Burst Type 0 3 read-write UNLIMITED Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0x0 SINGLE Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 0x1 4_BEAT 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 0x2 8_BEAT 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 0x3 16_BEAT 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 0x4 32_BEAT 32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 0x5 64_BEAT 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 0x6 128_BEAT 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving. 0x7 MCFG9 Master Configuration Register 0x24 32 read-write n ULBT Undefined Length Burst Type 0 3 read-write UNLIMITED Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0x0 SINGLE Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 0x1 4_BEAT 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 0x2 8_BEAT 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 0x3 16_BEAT 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 0x4 32_BEAT 32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 0x5 64_BEAT 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 0x6 128_BEAT 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving. 0x7 MCFG[0] Master Configuration Register 0x0 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 read-write UNLIMITED Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0x0 SINGLE Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 0x1 4_BEAT 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 0x2 8_BEAT 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 0x3 16_BEAT 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 0x4 32_BEAT 32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 0x5 64_BEAT 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 0x6 128_BEAT 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving. 0x7 MCFG[1] Master Configuration Register 0x4 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 read-write UNLIMITED Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0x0 SINGLE Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 0x1 4_BEAT 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 0x2 8_BEAT 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 0x3 16_BEAT 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 0x4 32_BEAT 32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 0x5 64_BEAT 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 0x6 128_BEAT 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving. 0x7 MCFG[2] Master Configuration Register 0xC 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 read-write UNLIMITED Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0x0 SINGLE Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 0x1 4_BEAT 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 0x2 8_BEAT 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 0x3 16_BEAT 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 0x4 32_BEAT 32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 0x5 64_BEAT 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 0x6 128_BEAT 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving. 0x7 MCFG[3] Master Configuration Register 0x18 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 read-write UNLIMITED Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0x0 SINGLE Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 0x1 4_BEAT 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 0x2 8_BEAT 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 0x3 16_BEAT 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 0x4 32_BEAT 32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 0x5 64_BEAT 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 0x6 128_BEAT 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving. 0x7 MCFG[4] Master Configuration Register 0x28 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 read-write UNLIMITED Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0x0 SINGLE Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 0x1 4_BEAT 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 0x2 8_BEAT 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 0x3 16_BEAT 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 0x4 32_BEAT 32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 0x5 64_BEAT 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 0x6 128_BEAT 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving. 0x7 MCFG[5] Master Configuration Register 0x3C 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 read-write UNLIMITED Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0x0 SINGLE Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 0x1 4_BEAT 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 0x2 8_BEAT 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 0x3 16_BEAT 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 0x4 32_BEAT 32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 0x5 64_BEAT 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 0x6 128_BEAT 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving. 0x7 MCFG[6] Master Configuration Register 0x54 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 read-write UNLIMITED Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0x0 SINGLE Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 0x1 4_BEAT 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 0x2 8_BEAT 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 0x3 16_BEAT 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 0x4 32_BEAT 32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 0x5 64_BEAT 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 0x6 128_BEAT 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving. 0x7 MCFG[7] Master Configuration Register 0x70 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 read-write UNLIMITED Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0x0 SINGLE Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 0x1 4_BEAT 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 0x2 8_BEAT 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 0x3 16_BEAT 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 0x4 32_BEAT 32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 0x5 64_BEAT 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 0x6 128_BEAT 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving. 0x7 MCFG[8] Master Configuration Register 0x90 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 read-write UNLIMITED Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0x0 SINGLE Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 0x1 4_BEAT 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 0x2 8_BEAT 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 0x3 16_BEAT 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 0x4 32_BEAT 32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 0x5 64_BEAT 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 0x6 128_BEAT 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving. 0x7 MCFG[9] Master Configuration Register 0xB4 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 read-write UNLIMITED Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0x0 SINGLE Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 0x1 4_BEAT 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 0x2 8_BEAT 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 0x3 16_BEAT 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 0x4 32_BEAT 32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 0x5 64_BEAT 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 0x6 128_BEAT 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving. 0x7 MEAR0 Master 0 Error Address Register 0x160 32 read-only n ERRADD Master Error Address 0 32 read-only MEAR1 Master 0 Error Address Register 0x164 32 read-only n ERRADD Master Error Address 0 32 read-only MEAR2 Master 0 Error Address Register 0x168 32 read-only n ERRADD Master Error Address 0 32 read-only MEAR3 Master 0 Error Address Register 0x16C 32 read-only n ERRADD Master Error Address 0 32 read-only MEAR4 Master 0 Error Address Register 0x170 32 read-only n ERRADD Master Error Address 0 32 read-only MEAR5 Master 0 Error Address Register 0x174 32 read-only n ERRADD Master Error Address 0 32 read-only MEAR6 Master 0 Error Address Register 0x178 32 read-only n ERRADD Master Error Address 0 32 read-only MEAR7 Master 0 Error Address Register 0x17C 32 read-only n ERRADD Master Error Address 0 32 read-only MEAR8 Master 0 Error Address Register 0x180 32 read-only n ERRADD Master Error Address 0 32 read-only MEAR9 Master 0 Error Address Register 0x184 32 read-only n ERRADD Master Error Address 0 32 read-only MEAR[0] Master 0 Error Address Register 0x2C0 32 read-only n 0x0 0x0 ERRADD Master Error Address 0 32 read-only MEAR[1] Master 0 Error Address Register 0x424 32 read-only n 0x0 0x0 ERRADD Master Error Address 0 32 read-only MEAR[2] Master 0 Error Address Register 0x58C 32 read-only n 0x0 0x0 ERRADD Master Error Address 0 32 read-only MEAR[3] Master 0 Error Address Register 0x6F8 32 read-only n 0x0 0x0 ERRADD Master Error Address 0 32 read-only MEAR[4] Master 0 Error Address Register 0x868 32 read-only n 0x0 0x0 ERRADD Master Error Address 0 32 read-only MEAR[5] Master 0 Error Address Register 0x9DC 32 read-only n 0x0 0x0 ERRADD Master Error Address 0 32 read-only MEAR[6] Master 0 Error Address Register 0xB54 32 read-only n 0x0 0x0 ERRADD Master Error Address 0 32 read-only MEAR[7] Master 0 Error Address Register 0xCD0 32 read-only n 0x0 0x0 ERRADD Master Error Address 0 32 read-only MEAR[8] Master 0 Error Address Register 0xE50 32 read-only n 0x0 0x0 ERRADD Master Error Address 0 32 read-only MEAR[9] Master 0 Error Address Register 0xFD4 32 read-only n 0x0 0x0 ERRADD Master Error Address 0 32 read-only MEIDR Master Error Interrupt Disable Register 0x154 32 write-only n 0x0 0x0 MERR0 Master 0 Access Error 0 1 write-only MERR1 Master 1 Access Error 1 1 write-only MERR2 Master 2 Access Error 2 1 write-only MERR3 Master 3 Access Error 3 1 write-only MERR4 Master 4 Access Error 4 1 write-only MERR5 Master 5 Access Error 5 1 write-only MERR6 Master 6 Access Error 6 1 write-only MERR7 Master 7 Access Error 7 1 write-only MERR8 Master 8 Access Error 8 1 write-only MERR9 Master 9 Access Error 9 1 write-only MEIER Master Error Interrupt Enable Register 0x150 32 write-only n 0x0 0x0 MERR0 Master 0 Access Error 0 1 write-only MERR1 Master 1 Access Error 1 1 write-only MERR2 Master 2 Access Error 2 1 write-only MERR3 Master 3 Access Error 3 1 write-only MERR4 Master 4 Access Error 4 1 write-only MERR5 Master 5 Access Error 5 1 write-only MERR6 Master 6 Access Error 6 1 write-only MERR7 Master 7 Access Error 7 1 write-only MERR8 Master 8 Access Error 8 1 write-only MERR9 Master 9 Access Error 9 1 write-only MEIMR Master Error Interrupt Mask Register 0x158 32 read-only n 0x0 0x0 MERR0 Master 0 Access Error 0 1 read-only MERR1 Master 1 Access Error 1 1 read-only MERR2 Master 2 Access Error 2 1 read-only MERR3 Master 3 Access Error 3 1 read-only MERR4 Master 4 Access Error 4 1 read-only MERR5 Master 5 Access Error 5 1 read-only MERR6 Master 6 Access Error 6 1 read-only MERR7 Master 7 Access Error 7 1 read-only MERR8 Master 8 Access Error 8 1 read-only MERR9 Master 9 Access Error 9 1 read-only MESR Master Error Status Register 0x15C 32 read-only n 0x0 0x0 MERR0 Master 0 Access Error 0 1 read-only MERR1 Master 1 Access Error 1 1 read-only MERR2 Master 2 Access Error 2 1 read-only MERR3 Master 3 Access Error 3 1 read-only MERR4 Master 4 Access Error 4 1 read-only MERR5 Master 5 Access Error 5 1 read-only MERR6 Master 6 Access Error 6 1 read-only MERR7 Master 7 Access Error 7 1 read-only MERR8 Master 8 Access Error 8 1 read-only MERR9 Master 9 Access Error 9 1 read-only PRAS0 Priority Register A for Slave 0 0x80 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 2 read-write M1PR Master 1 Priority 4 2 read-write M2PR Master 2 Priority 8 2 read-write M3PR Master 3 Priority 12 2 read-write M4PR Master 4 Priority 16 2 read-write M5PR Master 5 Priority 20 2 read-write M6PR Master 6 Priority 24 2 read-write M7PR Master 7 Priority 28 2 read-write PRAS1 Priority Register A for Slave 1 0x88 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 2 read-write M1PR Master 1 Priority 4 2 read-write M2PR Master 2 Priority 8 2 read-write M3PR Master 3 Priority 12 2 read-write M4PR Master 4 Priority 16 2 read-write M5PR Master 5 Priority 20 2 read-write M6PR Master 6 Priority 24 2 read-write M7PR Master 7 Priority 28 2 read-write PRAS10 Priority Register A for Slave 10 0xD0 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 2 read-write M1PR Master 1 Priority 4 2 read-write M2PR Master 2 Priority 8 2 read-write M3PR Master 3 Priority 12 2 read-write M4PR Master 4 Priority 16 2 read-write M5PR Master 5 Priority 20 2 read-write M6PR Master 6 Priority 24 2 read-write M7PR Master 7 Priority 28 2 read-write PRAS11 Priority Register A for Slave 11 0xD8 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 2 read-write M1PR Master 1 Priority 4 2 read-write M2PR Master 2 Priority 8 2 read-write M3PR Master 3 Priority 12 2 read-write M4PR Master 4 Priority 16 2 read-write M5PR Master 5 Priority 20 2 read-write M6PR Master 6 Priority 24 2 read-write M7PR Master 7 Priority 28 2 read-write PRAS12 Priority Register A for Slave 12 0xE0 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 2 read-write M1PR Master 1 Priority 4 2 read-write M2PR Master 2 Priority 8 2 read-write M3PR Master 3 Priority 12 2 read-write M4PR Master 4 Priority 16 2 read-write M5PR Master 5 Priority 20 2 read-write M6PR Master 6 Priority 24 2 read-write M7PR Master 7 Priority 28 2 read-write PRAS2 Priority Register A for Slave 2 0x90 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 2 read-write M1PR Master 1 Priority 4 2 read-write M2PR Master 2 Priority 8 2 read-write M3PR Master 3 Priority 12 2 read-write M4PR Master 4 Priority 16 2 read-write M5PR Master 5 Priority 20 2 read-write M6PR Master 6 Priority 24 2 read-write M7PR Master 7 Priority 28 2 read-write PRAS3 Priority Register A for Slave 3 0x98 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 2 read-write M1PR Master 1 Priority 4 2 read-write M2PR Master 2 Priority 8 2 read-write M3PR Master 3 Priority 12 2 read-write M4PR Master 4 Priority 16 2 read-write M5PR Master 5 Priority 20 2 read-write M6PR Master 6 Priority 24 2 read-write M7PR Master 7 Priority 28 2 read-write PRAS4 Priority Register A for Slave 4 0xA0 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 2 read-write M1PR Master 1 Priority 4 2 read-write M2PR Master 2 Priority 8 2 read-write M3PR Master 3 Priority 12 2 read-write M4PR Master 4 Priority 16 2 read-write M5PR Master 5 Priority 20 2 read-write M6PR Master 6 Priority 24 2 read-write M7PR Master 7 Priority 28 2 read-write PRAS5 Priority Register A for Slave 5 0xA8 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 2 read-write M1PR Master 1 Priority 4 2 read-write M2PR Master 2 Priority 8 2 read-write M3PR Master 3 Priority 12 2 read-write M4PR Master 4 Priority 16 2 read-write M5PR Master 5 Priority 20 2 read-write M6PR Master 6 Priority 24 2 read-write M7PR Master 7 Priority 28 2 read-write PRAS6 Priority Register A for Slave 6 0xB0 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 2 read-write M1PR Master 1 Priority 4 2 read-write M2PR Master 2 Priority 8 2 read-write M3PR Master 3 Priority 12 2 read-write M4PR Master 4 Priority 16 2 read-write M5PR Master 5 Priority 20 2 read-write M6PR Master 6 Priority 24 2 read-write M7PR Master 7 Priority 28 2 read-write PRAS7 Priority Register A for Slave 7 0xB8 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 2 read-write M1PR Master 1 Priority 4 2 read-write M2PR Master 2 Priority 8 2 read-write M3PR Master 3 Priority 12 2 read-write M4PR Master 4 Priority 16 2 read-write M5PR Master 5 Priority 20 2 read-write M6PR Master 6 Priority 24 2 read-write M7PR Master 7 Priority 28 2 read-write PRAS8 Priority Register A for Slave 8 0xC0 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 2 read-write M1PR Master 1 Priority 4 2 read-write M2PR Master 2 Priority 8 2 read-write M3PR Master 3 Priority 12 2 read-write M4PR Master 4 Priority 16 2 read-write M5PR Master 5 Priority 20 2 read-write M6PR Master 6 Priority 24 2 read-write M7PR Master 7 Priority 28 2 read-write PRAS9 Priority Register A for Slave 9 0xC8 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 2 read-write M1PR Master 1 Priority 4 2 read-write M2PR Master 2 Priority 8 2 read-write M3PR Master 3 Priority 12 2 read-write M4PR Master 4 Priority 16 2 read-write M5PR Master 5 Priority 20 2 read-write M6PR Master 6 Priority 24 2 read-write M7PR Master 7 Priority 28 2 read-write PRBS0 Priority Register B for Slave 0 0x84 32 read-write n 0x0 0x0 M8PR Master 8 Priority 0 2 read-write M9PR Master 9 Priority 4 2 read-write PRBS1 Priority Register B for Slave 1 0x8C 32 read-write n 0x0 0x0 M8PR Master 8 Priority 0 2 read-write M9PR Master 9 Priority 4 2 read-write PRBS10 Priority Register B for Slave 10 0xD4 32 read-write n 0x0 0x0 M8PR Master 8 Priority 0 2 read-write M9PR Master 9 Priority 4 2 read-write PRBS11 Priority Register B for Slave 11 0xDC 32 read-write n 0x0 0x0 M8PR Master 8 Priority 0 2 read-write M9PR Master 9 Priority 4 2 read-write PRBS12 Priority Register B for Slave 12 0xE4 32 read-write n 0x0 0x0 M8PR Master 8 Priority 0 2 read-write M9PR Master 9 Priority 4 2 read-write PRBS2 Priority Register B for Slave 2 0x94 32 read-write n 0x0 0x0 M8PR Master 8 Priority 0 2 read-write M9PR Master 9 Priority 4 2 read-write PRBS3 Priority Register B for Slave 3 0x9C 32 read-write n 0x0 0x0 M8PR Master 8 Priority 0 2 read-write M9PR Master 9 Priority 4 2 read-write PRBS4 Priority Register B for Slave 4 0xA4 32 read-write n 0x0 0x0 M8PR Master 8 Priority 0 2 read-write M9PR Master 9 Priority 4 2 read-write PRBS5 Priority Register B for Slave 5 0xAC 32 read-write n 0x0 0x0 M8PR Master 8 Priority 0 2 read-write M9PR Master 9 Priority 4 2 read-write PRBS6 Priority Register B for Slave 6 0xB4 32 read-write n 0x0 0x0 M8PR Master 8 Priority 0 2 read-write M9PR Master 9 Priority 4 2 read-write PRBS7 Priority Register B for Slave 7 0xBC 32 read-write n 0x0 0x0 M8PR Master 8 Priority 0 2 read-write M9PR Master 9 Priority 4 2 read-write PRBS8 Priority Register B for Slave 8 0xC4 32 read-write n 0x0 0x0 M8PR Master 8 Priority 0 2 read-write M9PR Master 9 Priority 4 2 read-write PRBS9 Priority Register B for Slave 9 0xCC 32 read-write n 0x0 0x0 M8PR Master 8 Priority 0 2 read-write M9PR Master 9 Priority 4 2 read-write SASSR0 Security Areas Split Slave 0 Register 0x240 32 read-write n SASPLIT0 Security Areas Split for HSELx Security Region 0 4 read-write SASPLIT1 Security Areas Split for HSELx Security Region 4 4 read-write SASPLIT2 Security Areas Split for HSELx Security Region 8 4 read-write SASPLIT3 Security Areas Split for HSELx Security Region 12 4 read-write SASPLIT4 Security Areas Split for HSELx Security Region 16 4 read-write SASPLIT5 Security Areas Split for HSELx Security Region 20 4 read-write SASPLIT6 Security Areas Split for HSELx Security Region 24 4 read-write SASPLIT7 Security Areas Split for HSELx Security Region 28 4 read-write SASSR1 Security Areas Split Slave 0 Register 0x244 32 read-write n SASPLIT0 Security Areas Split for HSELx Security Region 0 4 read-write SASPLIT1 Security Areas Split for HSELx Security Region 4 4 read-write SASPLIT2 Security Areas Split for HSELx Security Region 8 4 read-write SASPLIT3 Security Areas Split for HSELx Security Region 12 4 read-write SASPLIT4 Security Areas Split for HSELx Security Region 16 4 read-write SASPLIT5 Security Areas Split for HSELx Security Region 20 4 read-write SASPLIT6 Security Areas Split for HSELx Security Region 24 4 read-write SASPLIT7 Security Areas Split for HSELx Security Region 28 4 read-write SASSR10 Security Areas Split Slave 0 Register 0x268 32 read-write n SASPLIT0 Security Areas Split for HSELx Security Region 0 4 read-write SASPLIT1 Security Areas Split for HSELx Security Region 4 4 read-write SASPLIT2 Security Areas Split for HSELx Security Region 8 4 read-write SASPLIT3 Security Areas Split for HSELx Security Region 12 4 read-write SASPLIT4 Security Areas Split for HSELx Security Region 16 4 read-write SASPLIT5 Security Areas Split for HSELx Security Region 20 4 read-write SASPLIT6 Security Areas Split for HSELx Security Region 24 4 read-write SASPLIT7 Security Areas Split for HSELx Security Region 28 4 read-write SASSR11 Security Areas Split Slave 0 Register 0x26C 32 read-write n SASPLIT0 Security Areas Split for HSELx Security Region 0 4 read-write SASPLIT1 Security Areas Split for HSELx Security Region 4 4 read-write SASPLIT2 Security Areas Split for HSELx Security Region 8 4 read-write SASPLIT3 Security Areas Split for HSELx Security Region 12 4 read-write SASPLIT4 Security Areas Split for HSELx Security Region 16 4 read-write SASPLIT5 Security Areas Split for HSELx Security Region 20 4 read-write SASPLIT6 Security Areas Split for HSELx Security Region 24 4 read-write SASPLIT7 Security Areas Split for HSELx Security Region 28 4 read-write SASSR12 Security Areas Split Slave 0 Register 0x270 32 read-write n SASPLIT0 Security Areas Split for HSELx Security Region 0 4 read-write SASPLIT1 Security Areas Split for HSELx Security Region 4 4 read-write SASPLIT2 Security Areas Split for HSELx Security Region 8 4 read-write SASPLIT3 Security Areas Split for HSELx Security Region 12 4 read-write SASPLIT4 Security Areas Split for HSELx Security Region 16 4 read-write SASPLIT5 Security Areas Split for HSELx Security Region 20 4 read-write SASPLIT6 Security Areas Split for HSELx Security Region 24 4 read-write SASPLIT7 Security Areas Split for HSELx Security Region 28 4 read-write SASSR2 Security Areas Split Slave 0 Register 0x248 32 read-write n SASPLIT0 Security Areas Split for HSELx Security Region 0 4 read-write SASPLIT1 Security Areas Split for HSELx Security Region 4 4 read-write SASPLIT2 Security Areas Split for HSELx Security Region 8 4 read-write SASPLIT3 Security Areas Split for HSELx Security Region 12 4 read-write SASPLIT4 Security Areas Split for HSELx Security Region 16 4 read-write SASPLIT5 Security Areas Split for HSELx Security Region 20 4 read-write SASPLIT6 Security Areas Split for HSELx Security Region 24 4 read-write SASPLIT7 Security Areas Split for HSELx Security Region 28 4 read-write SASSR3 Security Areas Split Slave 0 Register 0x24C 32 read-write n SASPLIT0 Security Areas Split for HSELx Security Region 0 4 read-write SASPLIT1 Security Areas Split for HSELx Security Region 4 4 read-write SASPLIT2 Security Areas Split for HSELx Security Region 8 4 read-write SASPLIT3 Security Areas Split for HSELx Security Region 12 4 read-write SASPLIT4 Security Areas Split for HSELx Security Region 16 4 read-write SASPLIT5 Security Areas Split for HSELx Security Region 20 4 read-write SASPLIT6 Security Areas Split for HSELx Security Region 24 4 read-write SASPLIT7 Security Areas Split for HSELx Security Region 28 4 read-write SASSR4 Security Areas Split Slave 0 Register 0x250 32 read-write n SASPLIT0 Security Areas Split for HSELx Security Region 0 4 read-write SASPLIT1 Security Areas Split for HSELx Security Region 4 4 read-write SASPLIT2 Security Areas Split for HSELx Security Region 8 4 read-write SASPLIT3 Security Areas Split for HSELx Security Region 12 4 read-write SASPLIT4 Security Areas Split for HSELx Security Region 16 4 read-write SASPLIT5 Security Areas Split for HSELx Security Region 20 4 read-write SASPLIT6 Security Areas Split for HSELx Security Region 24 4 read-write SASPLIT7 Security Areas Split for HSELx Security Region 28 4 read-write SASSR5 Security Areas Split Slave 0 Register 0x254 32 read-write n SASPLIT0 Security Areas Split for HSELx Security Region 0 4 read-write SASPLIT1 Security Areas Split for HSELx Security Region 4 4 read-write SASPLIT2 Security Areas Split for HSELx Security Region 8 4 read-write SASPLIT3 Security Areas Split for HSELx Security Region 12 4 read-write SASPLIT4 Security Areas Split for HSELx Security Region 16 4 read-write SASPLIT5 Security Areas Split for HSELx Security Region 20 4 read-write SASPLIT6 Security Areas Split for HSELx Security Region 24 4 read-write SASPLIT7 Security Areas Split for HSELx Security Region 28 4 read-write SASSR6 Security Areas Split Slave 0 Register 0x258 32 read-write n SASPLIT0 Security Areas Split for HSELx Security Region 0 4 read-write SASPLIT1 Security Areas Split for HSELx Security Region 4 4 read-write SASPLIT2 Security Areas Split for HSELx Security Region 8 4 read-write SASPLIT3 Security Areas Split for HSELx Security Region 12 4 read-write SASPLIT4 Security Areas Split for HSELx Security Region 16 4 read-write SASPLIT5 Security Areas Split for HSELx Security Region 20 4 read-write SASPLIT6 Security Areas Split for HSELx Security Region 24 4 read-write SASPLIT7 Security Areas Split for HSELx Security Region 28 4 read-write SASSR7 Security Areas Split Slave 0 Register 0x25C 32 read-write n SASPLIT0 Security Areas Split for HSELx Security Region 0 4 read-write SASPLIT1 Security Areas Split for HSELx Security Region 4 4 read-write SASPLIT2 Security Areas Split for HSELx Security Region 8 4 read-write SASPLIT3 Security Areas Split for HSELx Security Region 12 4 read-write SASPLIT4 Security Areas Split for HSELx Security Region 16 4 read-write SASPLIT5 Security Areas Split for HSELx Security Region 20 4 read-write SASPLIT6 Security Areas Split for HSELx Security Region 24 4 read-write SASPLIT7 Security Areas Split for HSELx Security Region 28 4 read-write SASSR8 Security Areas Split Slave 0 Register 0x260 32 read-write n SASPLIT0 Security Areas Split for HSELx Security Region 0 4 read-write SASPLIT1 Security Areas Split for HSELx Security Region 4 4 read-write SASPLIT2 Security Areas Split for HSELx Security Region 8 4 read-write SASPLIT3 Security Areas Split for HSELx Security Region 12 4 read-write SASPLIT4 Security Areas Split for HSELx Security Region 16 4 read-write SASPLIT5 Security Areas Split for HSELx Security Region 20 4 read-write SASPLIT6 Security Areas Split for HSELx Security Region 24 4 read-write SASPLIT7 Security Areas Split for HSELx Security Region 28 4 read-write SASSR9 Security Areas Split Slave 0 Register 0x264 32 read-write n SASPLIT0 Security Areas Split for HSELx Security Region 0 4 read-write SASPLIT1 Security Areas Split for HSELx Security Region 4 4 read-write SASPLIT2 Security Areas Split for HSELx Security Region 8 4 read-write SASPLIT3 Security Areas Split for HSELx Security Region 12 4 read-write SASPLIT4 Security Areas Split for HSELx Security Region 16 4 read-write SASPLIT5 Security Areas Split for HSELx Security Region 20 4 read-write SASPLIT6 Security Areas Split for HSELx Security Region 24 4 read-write SASPLIT7 Security Areas Split for HSELx Security Region 28 4 read-write SASSR[0] Security Areas Split Slave 0 Register 0x480 32 read-write n 0x0 0x0 SASPLIT0 Security Areas Split for HSELx Security Region 0 4 read-write SASPLIT1 Security Areas Split for HSELx Security Region 4 4 read-write SASPLIT2 Security Areas Split for HSELx Security Region 8 4 read-write SASPLIT3 Security Areas Split for HSELx Security Region 12 4 read-write SASPLIT4 Security Areas Split for HSELx Security Region 16 4 read-write SASPLIT5 Security Areas Split for HSELx Security Region 20 4 read-write SASPLIT6 Security Areas Split for HSELx Security Region 24 4 read-write SASPLIT7 Security Areas Split for HSELx Security Region 28 4 read-write SASSR[10] Security Areas Split Slave 0 Register 0x1BDC 32 read-write n 0x0 0x0 SASPLIT0 Security Areas Split for HSELx Security Region 0 4 read-write SASPLIT1 Security Areas Split for HSELx Security Region 4 4 read-write SASPLIT2 Security Areas Split for HSELx Security Region 8 4 read-write SASPLIT3 Security Areas Split for HSELx Security Region 12 4 read-write SASPLIT4 Security Areas Split for HSELx Security Region 16 4 read-write SASPLIT5 Security Areas Split for HSELx Security Region 20 4 read-write SASPLIT6 Security Areas Split for HSELx Security Region 24 4 read-write SASPLIT7 Security Areas Split for HSELx Security Region 28 4 read-write SASSR[11] Security Areas Split Slave 0 Register 0x1E48 32 read-write n 0x0 0x0 SASPLIT0 Security Areas Split for HSELx Security Region 0 4 read-write SASPLIT1 Security Areas Split for HSELx Security Region 4 4 read-write SASPLIT2 Security Areas Split for HSELx Security Region 8 4 read-write SASPLIT3 Security Areas Split for HSELx Security Region 12 4 read-write SASPLIT4 Security Areas Split for HSELx Security Region 16 4 read-write SASPLIT5 Security Areas Split for HSELx Security Region 20 4 read-write SASPLIT6 Security Areas Split for HSELx Security Region 24 4 read-write SASPLIT7 Security Areas Split for HSELx Security Region 28 4 read-write SASSR[12] Security Areas Split Slave 0 Register 0x20B8 32 read-write n 0x0 0x0 SASPLIT0 Security Areas Split for HSELx Security Region 0 4 read-write SASPLIT1 Security Areas Split for HSELx Security Region 4 4 read-write SASPLIT2 Security Areas Split for HSELx Security Region 8 4 read-write SASPLIT3 Security Areas Split for HSELx Security Region 12 4 read-write SASPLIT4 Security Areas Split for HSELx Security Region 16 4 read-write SASPLIT5 Security Areas Split for HSELx Security Region 20 4 read-write SASPLIT6 Security Areas Split for HSELx Security Region 24 4 read-write SASPLIT7 Security Areas Split for HSELx Security Region 28 4 read-write SASSR[1] Security Areas Split Slave 0 Register 0x6C4 32 read-write n 0x0 0x0 SASPLIT0 Security Areas Split for HSELx Security Region 0 4 read-write SASPLIT1 Security Areas Split for HSELx Security Region 4 4 read-write SASPLIT2 Security Areas Split for HSELx Security Region 8 4 read-write SASPLIT3 Security Areas Split for HSELx Security Region 12 4 read-write SASPLIT4 Security Areas Split for HSELx Security Region 16 4 read-write SASPLIT5 Security Areas Split for HSELx Security Region 20 4 read-write SASPLIT6 Security Areas Split for HSELx Security Region 24 4 read-write SASPLIT7 Security Areas Split for HSELx Security Region 28 4 read-write SASSR[2] Security Areas Split Slave 0 Register 0x90C 32 read-write n 0x0 0x0 SASPLIT0 Security Areas Split for HSELx Security Region 0 4 read-write SASPLIT1 Security Areas Split for HSELx Security Region 4 4 read-write SASPLIT2 Security Areas Split for HSELx Security Region 8 4 read-write SASPLIT3 Security Areas Split for HSELx Security Region 12 4 read-write SASPLIT4 Security Areas Split for HSELx Security Region 16 4 read-write SASPLIT5 Security Areas Split for HSELx Security Region 20 4 read-write SASPLIT6 Security Areas Split for HSELx Security Region 24 4 read-write SASPLIT7 Security Areas Split for HSELx Security Region 28 4 read-write SASSR[3] Security Areas Split Slave 0 Register 0xB58 32 read-write n 0x0 0x0 SASPLIT0 Security Areas Split for HSELx Security Region 0 4 read-write SASPLIT1 Security Areas Split for HSELx Security Region 4 4 read-write SASPLIT2 Security Areas Split for HSELx Security Region 8 4 read-write SASPLIT3 Security Areas Split for HSELx Security Region 12 4 read-write SASPLIT4 Security Areas Split for HSELx Security Region 16 4 read-write SASPLIT5 Security Areas Split for HSELx Security Region 20 4 read-write SASPLIT6 Security Areas Split for HSELx Security Region 24 4 read-write SASPLIT7 Security Areas Split for HSELx Security Region 28 4 read-write SASSR[4] Security Areas Split Slave 0 Register 0xDA8 32 read-write n 0x0 0x0 SASPLIT0 Security Areas Split for HSELx Security Region 0 4 read-write SASPLIT1 Security Areas Split for HSELx Security Region 4 4 read-write SASPLIT2 Security Areas Split for HSELx Security Region 8 4 read-write SASPLIT3 Security Areas Split for HSELx Security Region 12 4 read-write SASPLIT4 Security Areas Split for HSELx Security Region 16 4 read-write SASPLIT5 Security Areas Split for HSELx Security Region 20 4 read-write SASPLIT6 Security Areas Split for HSELx Security Region 24 4 read-write SASPLIT7 Security Areas Split for HSELx Security Region 28 4 read-write SASSR[5] Security Areas Split Slave 0 Register 0xFFC 32 read-write n 0x0 0x0 SASPLIT0 Security Areas Split for HSELx Security Region 0 4 read-write SASPLIT1 Security Areas Split for HSELx Security Region 4 4 read-write SASPLIT2 Security Areas Split for HSELx Security Region 8 4 read-write SASPLIT3 Security Areas Split for HSELx Security Region 12 4 read-write SASPLIT4 Security Areas Split for HSELx Security Region 16 4 read-write SASPLIT5 Security Areas Split for HSELx Security Region 20 4 read-write SASPLIT6 Security Areas Split for HSELx Security Region 24 4 read-write SASPLIT7 Security Areas Split for HSELx Security Region 28 4 read-write SASSR[6] Security Areas Split Slave 0 Register 0x1254 32 read-write n 0x0 0x0 SASPLIT0 Security Areas Split for HSELx Security Region 0 4 read-write SASPLIT1 Security Areas Split for HSELx Security Region 4 4 read-write SASPLIT2 Security Areas Split for HSELx Security Region 8 4 read-write SASPLIT3 Security Areas Split for HSELx Security Region 12 4 read-write SASPLIT4 Security Areas Split for HSELx Security Region 16 4 read-write SASPLIT5 Security Areas Split for HSELx Security Region 20 4 read-write SASPLIT6 Security Areas Split for HSELx Security Region 24 4 read-write SASPLIT7 Security Areas Split for HSELx Security Region 28 4 read-write SASSR[7] Security Areas Split Slave 0 Register 0x14B0 32 read-write n 0x0 0x0 SASPLIT0 Security Areas Split for HSELx Security Region 0 4 read-write SASPLIT1 Security Areas Split for HSELx Security Region 4 4 read-write SASPLIT2 Security Areas Split for HSELx Security Region 8 4 read-write SASPLIT3 Security Areas Split for HSELx Security Region 12 4 read-write SASPLIT4 Security Areas Split for HSELx Security Region 16 4 read-write SASPLIT5 Security Areas Split for HSELx Security Region 20 4 read-write SASPLIT6 Security Areas Split for HSELx Security Region 24 4 read-write SASPLIT7 Security Areas Split for HSELx Security Region 28 4 read-write SASSR[8] Security Areas Split Slave 0 Register 0x1710 32 read-write n 0x0 0x0 SASPLIT0 Security Areas Split for HSELx Security Region 0 4 read-write SASPLIT1 Security Areas Split for HSELx Security Region 4 4 read-write SASPLIT2 Security Areas Split for HSELx Security Region 8 4 read-write SASPLIT3 Security Areas Split for HSELx Security Region 12 4 read-write SASPLIT4 Security Areas Split for HSELx Security Region 16 4 read-write SASPLIT5 Security Areas Split for HSELx Security Region 20 4 read-write SASPLIT6 Security Areas Split for HSELx Security Region 24 4 read-write SASPLIT7 Security Areas Split for HSELx Security Region 28 4 read-write SASSR[9] Security Areas Split Slave 0 Register 0x1974 32 read-write n 0x0 0x0 SASPLIT0 Security Areas Split for HSELx Security Region 0 4 read-write SASPLIT1 Security Areas Split for HSELx Security Region 4 4 read-write SASPLIT2 Security Areas Split for HSELx Security Region 8 4 read-write SASPLIT3 Security Areas Split for HSELx Security Region 12 4 read-write SASPLIT4 Security Areas Split for HSELx Security Region 16 4 read-write SASPLIT5 Security Areas Split for HSELx Security Region 20 4 read-write SASPLIT6 Security Areas Split for HSELx Security Region 24 4 read-write SASPLIT7 Security Areas Split for HSELx Security Region 28 4 read-write SCFG0 Slave Configuration Register 0x40 32 read-write n DEFMSTR_TYPE Default Master Type 16 2 read-write NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 0x1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 4 read-write SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 read-write SCFG1 Slave Configuration Register 0x44 32 read-write n DEFMSTR_TYPE Default Master Type 16 2 read-write NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 0x1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 4 read-write SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 read-write SCFG10 Slave Configuration Register 0x68 32 read-write n DEFMSTR_TYPE Default Master Type 16 2 read-write NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 0x1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 4 read-write SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 read-write SCFG11 Slave Configuration Register 0x6C 32 read-write n DEFMSTR_TYPE Default Master Type 16 2 read-write NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 0x1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 4 read-write SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 read-write SCFG12 Slave Configuration Register 0x70 32 read-write n DEFMSTR_TYPE Default Master Type 16 2 read-write NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 0x1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 4 read-write SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 read-write SCFG2 Slave Configuration Register 0x48 32 read-write n DEFMSTR_TYPE Default Master Type 16 2 read-write NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 0x1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 4 read-write SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 read-write SCFG3 Slave Configuration Register 0x4C 32 read-write n DEFMSTR_TYPE Default Master Type 16 2 read-write NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 0x1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 4 read-write SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 read-write SCFG4 Slave Configuration Register 0x50 32 read-write n DEFMSTR_TYPE Default Master Type 16 2 read-write NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 0x1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 4 read-write SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 read-write SCFG5 Slave Configuration Register 0x54 32 read-write n DEFMSTR_TYPE Default Master Type 16 2 read-write NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 0x1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 4 read-write SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 read-write SCFG6 Slave Configuration Register 0x58 32 read-write n DEFMSTR_TYPE Default Master Type 16 2 read-write NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 0x1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 4 read-write SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 read-write SCFG7 Slave Configuration Register 0x5C 32 read-write n DEFMSTR_TYPE Default Master Type 16 2 read-write NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 0x1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 4 read-write SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 read-write SCFG8 Slave Configuration Register 0x60 32 read-write n DEFMSTR_TYPE Default Master Type 16 2 read-write NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 0x1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 4 read-write SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 read-write SCFG9 Slave Configuration Register 0x64 32 read-write n DEFMSTR_TYPE Default Master Type 16 2 read-write NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 0x1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 4 read-write SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 read-write SCFG[0] Slave Configuration Register 0x80 32 read-write n 0x0 0x0 DEFMSTR_TYPE Default Master Type 16 2 read-write NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 0x1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 4 read-write SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 read-write SCFG[10] Slave Configuration Register 0x3DC 32 read-write n 0x0 0x0 DEFMSTR_TYPE Default Master Type 16 2 read-write NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 0x1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 4 read-write SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 read-write SCFG[11] Slave Configuration Register 0x448 32 read-write n 0x0 0x0 DEFMSTR_TYPE Default Master Type 16 2 read-write NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 0x1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 4 read-write SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 read-write SCFG[12] Slave Configuration Register 0x4B8 32 read-write n 0x0 0x0 DEFMSTR_TYPE Default Master Type 16 2 read-write NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 0x1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 4 read-write SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 read-write SCFG[1] Slave Configuration Register 0xC4 32 read-write n 0x0 0x0 DEFMSTR_TYPE Default Master Type 16 2 read-write NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 0x1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 4 read-write SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 read-write SCFG[2] Slave Configuration Register 0x10C 32 read-write n 0x0 0x0 DEFMSTR_TYPE Default Master Type 16 2 read-write NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 0x1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 4 read-write SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 read-write SCFG[3] Slave Configuration Register 0x158 32 read-write n 0x0 0x0 DEFMSTR_TYPE Default Master Type 16 2 read-write NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 0x1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 4 read-write SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 read-write SCFG[4] Slave Configuration Register 0x1A8 32 read-write n 0x0 0x0 DEFMSTR_TYPE Default Master Type 16 2 read-write NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 0x1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 4 read-write SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 read-write SCFG[5] Slave Configuration Register 0x1FC 32 read-write n 0x0 0x0 DEFMSTR_TYPE Default Master Type 16 2 read-write NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 0x1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 4 read-write SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 read-write SCFG[6] Slave Configuration Register 0x254 32 read-write n 0x0 0x0 DEFMSTR_TYPE Default Master Type 16 2 read-write NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 0x1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 4 read-write SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 read-write SCFG[7] Slave Configuration Register 0x2B0 32 read-write n 0x0 0x0 DEFMSTR_TYPE Default Master Type 16 2 read-write NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 0x1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 4 read-write SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 read-write SCFG[8] Slave Configuration Register 0x310 32 read-write n 0x0 0x0 DEFMSTR_TYPE Default Master Type 16 2 read-write NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 0x1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 4 read-write SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 read-write SCFG[9] Slave Configuration Register 0x374 32 read-write n 0x0 0x0 DEFMSTR_TYPE Default Master Type 16 2 read-write NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 0x1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 4 read-write SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 read-write SPSELR0 Security Peripheral Select 1 Register 0x2C0 32 read-write n NSECP0 Non-secured Peripheral 0 1 read-write NSECP1 Non-secured Peripheral 1 1 read-write NSECP10 Non-secured Peripheral 10 1 read-write NSECP11 Non-secured Peripheral 11 1 read-write NSECP12 Non-secured Peripheral 12 1 read-write NSECP13 Non-secured Peripheral 13 1 read-write NSECP14 Non-secured Peripheral 14 1 read-write NSECP15 Non-secured Peripheral 15 1 read-write NSECP16 Non-secured Peripheral 16 1 read-write NSECP17 Non-secured Peripheral 17 1 read-write NSECP18 Non-secured Peripheral 18 1 read-write NSECP19 Non-secured Peripheral 19 1 read-write NSECP2 Non-secured Peripheral 2 1 read-write NSECP20 Non-secured Peripheral 20 1 read-write NSECP21 Non-secured Peripheral 21 1 read-write NSECP22 Non-secured Peripheral 22 1 read-write NSECP23 Non-secured Peripheral 23 1 read-write NSECP24 Non-secured Peripheral 24 1 read-write NSECP25 Non-secured Peripheral 25 1 read-write NSECP26 Non-secured Peripheral 26 1 read-write NSECP27 Non-secured Peripheral 27 1 read-write NSECP28 Non-secured Peripheral 28 1 read-write NSECP29 Non-secured Peripheral 29 1 read-write NSECP3 Non-secured Peripheral 3 1 read-write NSECP30 Non-secured Peripheral 30 1 read-write NSECP31 Non-secured Peripheral 31 1 read-write NSECP4 Non-secured Peripheral 4 1 read-write NSECP5 Non-secured Peripheral 5 1 read-write NSECP6 Non-secured Peripheral 6 1 read-write NSECP7 Non-secured Peripheral 7 1 read-write NSECP8 Non-secured Peripheral 8 1 read-write NSECP9 Non-secured Peripheral 9 1 read-write SPSELR1 Security Peripheral Select 1 Register 0x2C4 32 read-write n NSECP0 Non-secured Peripheral 0 1 read-write NSECP1 Non-secured Peripheral 1 1 read-write NSECP10 Non-secured Peripheral 10 1 read-write NSECP11 Non-secured Peripheral 11 1 read-write NSECP12 Non-secured Peripheral 12 1 read-write NSECP13 Non-secured Peripheral 13 1 read-write NSECP14 Non-secured Peripheral 14 1 read-write NSECP15 Non-secured Peripheral 15 1 read-write NSECP16 Non-secured Peripheral 16 1 read-write NSECP17 Non-secured Peripheral 17 1 read-write NSECP18 Non-secured Peripheral 18 1 read-write NSECP19 Non-secured Peripheral 19 1 read-write NSECP2 Non-secured Peripheral 2 1 read-write NSECP20 Non-secured Peripheral 20 1 read-write NSECP21 Non-secured Peripheral 21 1 read-write NSECP22 Non-secured Peripheral 22 1 read-write NSECP23 Non-secured Peripheral 23 1 read-write NSECP24 Non-secured Peripheral 24 1 read-write NSECP25 Non-secured Peripheral 25 1 read-write NSECP26 Non-secured Peripheral 26 1 read-write NSECP27 Non-secured Peripheral 27 1 read-write NSECP28 Non-secured Peripheral 28 1 read-write NSECP29 Non-secured Peripheral 29 1 read-write NSECP3 Non-secured Peripheral 3 1 read-write NSECP30 Non-secured Peripheral 30 1 read-write NSECP31 Non-secured Peripheral 31 1 read-write NSECP4 Non-secured Peripheral 4 1 read-write NSECP5 Non-secured Peripheral 5 1 read-write NSECP6 Non-secured Peripheral 6 1 read-write NSECP7 Non-secured Peripheral 7 1 read-write NSECP8 Non-secured Peripheral 8 1 read-write NSECP9 Non-secured Peripheral 9 1 read-write SPSELR2 Security Peripheral Select 1 Register 0x2C8 32 read-write n NSECP0 Non-secured Peripheral 0 1 read-write NSECP1 Non-secured Peripheral 1 1 read-write NSECP10 Non-secured Peripheral 10 1 read-write NSECP11 Non-secured Peripheral 11 1 read-write NSECP12 Non-secured Peripheral 12 1 read-write NSECP13 Non-secured Peripheral 13 1 read-write NSECP14 Non-secured Peripheral 14 1 read-write NSECP15 Non-secured Peripheral 15 1 read-write NSECP16 Non-secured Peripheral 16 1 read-write NSECP17 Non-secured Peripheral 17 1 read-write NSECP18 Non-secured Peripheral 18 1 read-write NSECP19 Non-secured Peripheral 19 1 read-write NSECP2 Non-secured Peripheral 2 1 read-write NSECP20 Non-secured Peripheral 20 1 read-write NSECP21 Non-secured Peripheral 21 1 read-write NSECP22 Non-secured Peripheral 22 1 read-write NSECP23 Non-secured Peripheral 23 1 read-write NSECP24 Non-secured Peripheral 24 1 read-write NSECP25 Non-secured Peripheral 25 1 read-write NSECP26 Non-secured Peripheral 26 1 read-write NSECP27 Non-secured Peripheral 27 1 read-write NSECP28 Non-secured Peripheral 28 1 read-write NSECP29 Non-secured Peripheral 29 1 read-write NSECP3 Non-secured Peripheral 3 1 read-write NSECP30 Non-secured Peripheral 30 1 read-write NSECP31 Non-secured Peripheral 31 1 read-write NSECP4 Non-secured Peripheral 4 1 read-write NSECP5 Non-secured Peripheral 5 1 read-write NSECP6 Non-secured Peripheral 6 1 read-write NSECP7 Non-secured Peripheral 7 1 read-write NSECP8 Non-secured Peripheral 8 1 read-write NSECP9 Non-secured Peripheral 9 1 read-write SPSELR[0] Security Peripheral Select 1 Register 0x580 32 read-write n 0x0 0x0 NSECP0 Non-secured Peripheral 0 1 read-write NSECP1 Non-secured Peripheral 1 1 read-write NSECP10 Non-secured Peripheral 10 1 read-write NSECP11 Non-secured Peripheral 11 1 read-write NSECP12 Non-secured Peripheral 12 1 read-write NSECP13 Non-secured Peripheral 13 1 read-write NSECP14 Non-secured Peripheral 14 1 read-write NSECP15 Non-secured Peripheral 15 1 read-write NSECP16 Non-secured Peripheral 16 1 read-write NSECP17 Non-secured Peripheral 17 1 read-write NSECP18 Non-secured Peripheral 18 1 read-write NSECP19 Non-secured Peripheral 19 1 read-write NSECP2 Non-secured Peripheral 2 1 read-write NSECP20 Non-secured Peripheral 20 1 read-write NSECP21 Non-secured Peripheral 21 1 read-write NSECP22 Non-secured Peripheral 22 1 read-write NSECP23 Non-secured Peripheral 23 1 read-write NSECP24 Non-secured Peripheral 24 1 read-write NSECP25 Non-secured Peripheral 25 1 read-write NSECP26 Non-secured Peripheral 26 1 read-write NSECP27 Non-secured Peripheral 27 1 read-write NSECP28 Non-secured Peripheral 28 1 read-write NSECP29 Non-secured Peripheral 29 1 read-write NSECP3 Non-secured Peripheral 3 1 read-write NSECP30 Non-secured Peripheral 30 1 read-write NSECP31 Non-secured Peripheral 31 1 read-write NSECP4 Non-secured Peripheral 4 1 read-write NSECP5 Non-secured Peripheral 5 1 read-write NSECP6 Non-secured Peripheral 6 1 read-write NSECP7 Non-secured Peripheral 7 1 read-write NSECP8 Non-secured Peripheral 8 1 read-write NSECP9 Non-secured Peripheral 9 1 read-write SPSELR[1] Security Peripheral Select 1 Register 0x844 32 read-write n 0x0 0x0 NSECP0 Non-secured Peripheral 0 1 read-write NSECP1 Non-secured Peripheral 1 1 read-write NSECP10 Non-secured Peripheral 10 1 read-write NSECP11 Non-secured Peripheral 11 1 read-write NSECP12 Non-secured Peripheral 12 1 read-write NSECP13 Non-secured Peripheral 13 1 read-write NSECP14 Non-secured Peripheral 14 1 read-write NSECP15 Non-secured Peripheral 15 1 read-write NSECP16 Non-secured Peripheral 16 1 read-write NSECP17 Non-secured Peripheral 17 1 read-write NSECP18 Non-secured Peripheral 18 1 read-write NSECP19 Non-secured Peripheral 19 1 read-write NSECP2 Non-secured Peripheral 2 1 read-write NSECP20 Non-secured Peripheral 20 1 read-write NSECP21 Non-secured Peripheral 21 1 read-write NSECP22 Non-secured Peripheral 22 1 read-write NSECP23 Non-secured Peripheral 23 1 read-write NSECP24 Non-secured Peripheral 24 1 read-write NSECP25 Non-secured Peripheral 25 1 read-write NSECP26 Non-secured Peripheral 26 1 read-write NSECP27 Non-secured Peripheral 27 1 read-write NSECP28 Non-secured Peripheral 28 1 read-write NSECP29 Non-secured Peripheral 29 1 read-write NSECP3 Non-secured Peripheral 3 1 read-write NSECP30 Non-secured Peripheral 30 1 read-write NSECP31 Non-secured Peripheral 31 1 read-write NSECP4 Non-secured Peripheral 4 1 read-write NSECP5 Non-secured Peripheral 5 1 read-write NSECP6 Non-secured Peripheral 6 1 read-write NSECP7 Non-secured Peripheral 7 1 read-write NSECP8 Non-secured Peripheral 8 1 read-write NSECP9 Non-secured Peripheral 9 1 read-write SPSELR[2] Security Peripheral Select 1 Register 0xB0C 32 read-write n 0x0 0x0 NSECP0 Non-secured Peripheral 0 1 read-write NSECP1 Non-secured Peripheral 1 1 read-write NSECP10 Non-secured Peripheral 10 1 read-write NSECP11 Non-secured Peripheral 11 1 read-write NSECP12 Non-secured Peripheral 12 1 read-write NSECP13 Non-secured Peripheral 13 1 read-write NSECP14 Non-secured Peripheral 14 1 read-write NSECP15 Non-secured Peripheral 15 1 read-write NSECP16 Non-secured Peripheral 16 1 read-write NSECP17 Non-secured Peripheral 17 1 read-write NSECP18 Non-secured Peripheral 18 1 read-write NSECP19 Non-secured Peripheral 19 1 read-write NSECP2 Non-secured Peripheral 2 1 read-write NSECP20 Non-secured Peripheral 20 1 read-write NSECP21 Non-secured Peripheral 21 1 read-write NSECP22 Non-secured Peripheral 22 1 read-write NSECP23 Non-secured Peripheral 23 1 read-write NSECP24 Non-secured Peripheral 24 1 read-write NSECP25 Non-secured Peripheral 25 1 read-write NSECP26 Non-secured Peripheral 26 1 read-write NSECP27 Non-secured Peripheral 27 1 read-write NSECP28 Non-secured Peripheral 28 1 read-write NSECP29 Non-secured Peripheral 29 1 read-write NSECP3 Non-secured Peripheral 3 1 read-write NSECP30 Non-secured Peripheral 30 1 read-write NSECP31 Non-secured Peripheral 31 1 read-write NSECP4 Non-secured Peripheral 4 1 read-write NSECP5 Non-secured Peripheral 5 1 read-write NSECP6 Non-secured Peripheral 6 1 read-write NSECP7 Non-secured Peripheral 7 1 read-write NSECP8 Non-secured Peripheral 8 1 read-write NSECP9 Non-secured Peripheral 9 1 read-write SRTSR0 Security Region Top Slave 1 Register 0x284 32 read-write n SRTOP0 HSELx Security Region Top 0 4 read-write SRTOP1 HSELx Security Region Top 4 4 read-write SRTOP2 HSELx Security Region Top 8 4 read-write SRTOP3 HSELx Security Region Top 12 4 read-write SRTOP4 HSELx Security Region Top 16 4 read-write SRTOP5 HSELx Security Region Top 20 4 read-write SRTOP6 HSELx Security Region Top 24 4 read-write SRTOP7 HSELx Security Region Top 28 4 read-write SRTSR1 Security Region Top Slave 1 Register 0x288 32 read-write n SRTOP0 HSELx Security Region Top 0 4 read-write SRTOP1 HSELx Security Region Top 4 4 read-write SRTOP2 HSELx Security Region Top 8 4 read-write SRTOP3 HSELx Security Region Top 12 4 read-write SRTOP4 HSELx Security Region Top 16 4 read-write SRTOP5 HSELx Security Region Top 20 4 read-write SRTOP6 HSELx Security Region Top 24 4 read-write SRTOP7 HSELx Security Region Top 28 4 read-write SRTSR10 Security Region Top Slave 1 Register 0x2AC 32 read-write n SRTOP0 HSELx Security Region Top 0 4 read-write SRTOP1 HSELx Security Region Top 4 4 read-write SRTOP2 HSELx Security Region Top 8 4 read-write SRTOP3 HSELx Security Region Top 12 4 read-write SRTOP4 HSELx Security Region Top 16 4 read-write SRTOP5 HSELx Security Region Top 20 4 read-write SRTOP6 HSELx Security Region Top 24 4 read-write SRTOP7 HSELx Security Region Top 28 4 read-write SRTSR11 Security Region Top Slave 1 Register 0x2B0 32 read-write n SRTOP0 HSELx Security Region Top 0 4 read-write SRTOP1 HSELx Security Region Top 4 4 read-write SRTOP2 HSELx Security Region Top 8 4 read-write SRTOP3 HSELx Security Region Top 12 4 read-write SRTOP4 HSELx Security Region Top 16 4 read-write SRTOP5 HSELx Security Region Top 20 4 read-write SRTOP6 HSELx Security Region Top 24 4 read-write SRTOP7 HSELx Security Region Top 28 4 read-write SRTSR2 Security Region Top Slave 1 Register 0x28C 32 read-write n SRTOP0 HSELx Security Region Top 0 4 read-write SRTOP1 HSELx Security Region Top 4 4 read-write SRTOP2 HSELx Security Region Top 8 4 read-write SRTOP3 HSELx Security Region Top 12 4 read-write SRTOP4 HSELx Security Region Top 16 4 read-write SRTOP5 HSELx Security Region Top 20 4 read-write SRTOP6 HSELx Security Region Top 24 4 read-write SRTOP7 HSELx Security Region Top 28 4 read-write SRTSR3 Security Region Top Slave 1 Register 0x290 32 read-write n SRTOP0 HSELx Security Region Top 0 4 read-write SRTOP1 HSELx Security Region Top 4 4 read-write SRTOP2 HSELx Security Region Top 8 4 read-write SRTOP3 HSELx Security Region Top 12 4 read-write SRTOP4 HSELx Security Region Top 16 4 read-write SRTOP5 HSELx Security Region Top 20 4 read-write SRTOP6 HSELx Security Region Top 24 4 read-write SRTOP7 HSELx Security Region Top 28 4 read-write SRTSR4 Security Region Top Slave 1 Register 0x294 32 read-write n SRTOP0 HSELx Security Region Top 0 4 read-write SRTOP1 HSELx Security Region Top 4 4 read-write SRTOP2 HSELx Security Region Top 8 4 read-write SRTOP3 HSELx Security Region Top 12 4 read-write SRTOP4 HSELx Security Region Top 16 4 read-write SRTOP5 HSELx Security Region Top 20 4 read-write SRTOP6 HSELx Security Region Top 24 4 read-write SRTOP7 HSELx Security Region Top 28 4 read-write SRTSR5 Security Region Top Slave 1 Register 0x298 32 read-write n SRTOP0 HSELx Security Region Top 0 4 read-write SRTOP1 HSELx Security Region Top 4 4 read-write SRTOP2 HSELx Security Region Top 8 4 read-write SRTOP3 HSELx Security Region Top 12 4 read-write SRTOP4 HSELx Security Region Top 16 4 read-write SRTOP5 HSELx Security Region Top 20 4 read-write SRTOP6 HSELx Security Region Top 24 4 read-write SRTOP7 HSELx Security Region Top 28 4 read-write SRTSR6 Security Region Top Slave 1 Register 0x29C 32 read-write n SRTOP0 HSELx Security Region Top 0 4 read-write SRTOP1 HSELx Security Region Top 4 4 read-write SRTOP2 HSELx Security Region Top 8 4 read-write SRTOP3 HSELx Security Region Top 12 4 read-write SRTOP4 HSELx Security Region Top 16 4 read-write SRTOP5 HSELx Security Region Top 20 4 read-write SRTOP6 HSELx Security Region Top 24 4 read-write SRTOP7 HSELx Security Region Top 28 4 read-write SRTSR7 Security Region Top Slave 1 Register 0x2A0 32 read-write n SRTOP0 HSELx Security Region Top 0 4 read-write SRTOP1 HSELx Security Region Top 4 4 read-write SRTOP2 HSELx Security Region Top 8 4 read-write SRTOP3 HSELx Security Region Top 12 4 read-write SRTOP4 HSELx Security Region Top 16 4 read-write SRTOP5 HSELx Security Region Top 20 4 read-write SRTOP6 HSELx Security Region Top 24 4 read-write SRTOP7 HSELx Security Region Top 28 4 read-write SRTSR8 Security Region Top Slave 1 Register 0x2A4 32 read-write n SRTOP0 HSELx Security Region Top 0 4 read-write SRTOP1 HSELx Security Region Top 4 4 read-write SRTOP2 HSELx Security Region Top 8 4 read-write SRTOP3 HSELx Security Region Top 12 4 read-write SRTOP4 HSELx Security Region Top 16 4 read-write SRTOP5 HSELx Security Region Top 20 4 read-write SRTOP6 HSELx Security Region Top 24 4 read-write SRTOP7 HSELx Security Region Top 28 4 read-write SRTSR9 Security Region Top Slave 1 Register 0x2A8 32 read-write n SRTOP0 HSELx Security Region Top 0 4 read-write SRTOP1 HSELx Security Region Top 4 4 read-write SRTOP2 HSELx Security Region Top 8 4 read-write SRTOP3 HSELx Security Region Top 12 4 read-write SRTOP4 HSELx Security Region Top 16 4 read-write SRTOP5 HSELx Security Region Top 20 4 read-write SRTOP6 HSELx Security Region Top 24 4 read-write SRTOP7 HSELx Security Region Top 28 4 read-write SRTSR[0] Security Region Top Slave 1 Register 0x508 32 read-write n 0x0 0x0 SRTOP0 HSELx Security Region Top 0 4 read-write SRTOP1 HSELx Security Region Top 4 4 read-write SRTOP2 HSELx Security Region Top 8 4 read-write SRTOP3 HSELx Security Region Top 12 4 read-write SRTOP4 HSELx Security Region Top 16 4 read-write SRTOP5 HSELx Security Region Top 20 4 read-write SRTOP6 HSELx Security Region Top 24 4 read-write SRTOP7 HSELx Security Region Top 28 4 read-write SRTSR[10] Security Region Top Slave 1 Register 0x1F0C 32 read-write n 0x0 0x0 SRTOP0 HSELx Security Region Top 0 4 read-write SRTOP1 HSELx Security Region Top 4 4 read-write SRTOP2 HSELx Security Region Top 8 4 read-write SRTOP3 HSELx Security Region Top 12 4 read-write SRTOP4 HSELx Security Region Top 16 4 read-write SRTOP5 HSELx Security Region Top 20 4 read-write SRTOP6 HSELx Security Region Top 24 4 read-write SRTOP7 HSELx Security Region Top 28 4 read-write SRTSR[11] Security Region Top Slave 1 Register 0x21BC 32 read-write n 0x0 0x0 SRTOP0 HSELx Security Region Top 0 4 read-write SRTOP1 HSELx Security Region Top 4 4 read-write SRTOP2 HSELx Security Region Top 8 4 read-write SRTOP3 HSELx Security Region Top 12 4 read-write SRTOP4 HSELx Security Region Top 16 4 read-write SRTOP5 HSELx Security Region Top 20 4 read-write SRTOP6 HSELx Security Region Top 24 4 read-write SRTOP7 HSELx Security Region Top 28 4 read-write SRTSR[1] Security Region Top Slave 1 Register 0x790 32 read-write n 0x0 0x0 SRTOP0 HSELx Security Region Top 0 4 read-write SRTOP1 HSELx Security Region Top 4 4 read-write SRTOP2 HSELx Security Region Top 8 4 read-write SRTOP3 HSELx Security Region Top 12 4 read-write SRTOP4 HSELx Security Region Top 16 4 read-write SRTOP5 HSELx Security Region Top 20 4 read-write SRTOP6 HSELx Security Region Top 24 4 read-write SRTOP7 HSELx Security Region Top 28 4 read-write SRTSR[2] Security Region Top Slave 1 Register 0xA1C 32 read-write n 0x0 0x0 SRTOP0 HSELx Security Region Top 0 4 read-write SRTOP1 HSELx Security Region Top 4 4 read-write SRTOP2 HSELx Security Region Top 8 4 read-write SRTOP3 HSELx Security Region Top 12 4 read-write SRTOP4 HSELx Security Region Top 16 4 read-write SRTOP5 HSELx Security Region Top 20 4 read-write SRTOP6 HSELx Security Region Top 24 4 read-write SRTOP7 HSELx Security Region Top 28 4 read-write SRTSR[3] Security Region Top Slave 1 Register 0xCAC 32 read-write n 0x0 0x0 SRTOP0 HSELx Security Region Top 0 4 read-write SRTOP1 HSELx Security Region Top 4 4 read-write SRTOP2 HSELx Security Region Top 8 4 read-write SRTOP3 HSELx Security Region Top 12 4 read-write SRTOP4 HSELx Security Region Top 16 4 read-write SRTOP5 HSELx Security Region Top 20 4 read-write SRTOP6 HSELx Security Region Top 24 4 read-write SRTOP7 HSELx Security Region Top 28 4 read-write SRTSR[4] Security Region Top Slave 1 Register 0xF40 32 read-write n 0x0 0x0 SRTOP0 HSELx Security Region Top 0 4 read-write SRTOP1 HSELx Security Region Top 4 4 read-write SRTOP2 HSELx Security Region Top 8 4 read-write SRTOP3 HSELx Security Region Top 12 4 read-write SRTOP4 HSELx Security Region Top 16 4 read-write SRTOP5 HSELx Security Region Top 20 4 read-write SRTOP6 HSELx Security Region Top 24 4 read-write SRTOP7 HSELx Security Region Top 28 4 read-write SRTSR[5] Security Region Top Slave 1 Register 0x11D8 32 read-write n 0x0 0x0 SRTOP0 HSELx Security Region Top 0 4 read-write SRTOP1 HSELx Security Region Top 4 4 read-write SRTOP2 HSELx Security Region Top 8 4 read-write SRTOP3 HSELx Security Region Top 12 4 read-write SRTOP4 HSELx Security Region Top 16 4 read-write SRTOP5 HSELx Security Region Top 20 4 read-write SRTOP6 HSELx Security Region Top 24 4 read-write SRTOP7 HSELx Security Region Top 28 4 read-write SRTSR[6] Security Region Top Slave 1 Register 0x1474 32 read-write n 0x0 0x0 SRTOP0 HSELx Security Region Top 0 4 read-write SRTOP1 HSELx Security Region Top 4 4 read-write SRTOP2 HSELx Security Region Top 8 4 read-write SRTOP3 HSELx Security Region Top 12 4 read-write SRTOP4 HSELx Security Region Top 16 4 read-write SRTOP5 HSELx Security Region Top 20 4 read-write SRTOP6 HSELx Security Region Top 24 4 read-write SRTOP7 HSELx Security Region Top 28 4 read-write SRTSR[7] Security Region Top Slave 1 Register 0x1714 32 read-write n 0x0 0x0 SRTOP0 HSELx Security Region Top 0 4 read-write SRTOP1 HSELx Security Region Top 4 4 read-write SRTOP2 HSELx Security Region Top 8 4 read-write SRTOP3 HSELx Security Region Top 12 4 read-write SRTOP4 HSELx Security Region Top 16 4 read-write SRTOP5 HSELx Security Region Top 20 4 read-write SRTOP6 HSELx Security Region Top 24 4 read-write SRTOP7 HSELx Security Region Top 28 4 read-write SRTSR[8] Security Region Top Slave 1 Register 0x19B8 32 read-write n 0x0 0x0 SRTOP0 HSELx Security Region Top 0 4 read-write SRTOP1 HSELx Security Region Top 4 4 read-write SRTOP2 HSELx Security Region Top 8 4 read-write SRTOP3 HSELx Security Region Top 12 4 read-write SRTOP4 HSELx Security Region Top 16 4 read-write SRTOP5 HSELx Security Region Top 20 4 read-write SRTOP6 HSELx Security Region Top 24 4 read-write SRTOP7 HSELx Security Region Top 28 4 read-write SRTSR[9] Security Region Top Slave 1 Register 0x1C60 32 read-write n 0x0 0x0 SRTOP0 HSELx Security Region Top 0 4 read-write SRTOP1 HSELx Security Region Top 4 4 read-write SRTOP2 HSELx Security Region Top 8 4 read-write SRTOP3 HSELx Security Region Top 12 4 read-write SRTOP4 HSELx Security Region Top 16 4 read-write SRTOP5 HSELx Security Region Top 20 4 read-write SRTOP6 HSELx Security Region Top 24 4 read-write SRTOP7 HSELx Security Region Top 28 4 read-write SSR0 Security Slave 0 Register 0x200 32 read-write n LANSECH0 Low Area Non-secured in HSELx Security Region 0 1 read-write LANSECH1 Low Area Non-secured in HSELx Security Region 1 1 read-write LANSECH2 Low Area Non-secured in HSELx Security Region 2 1 read-write LANSECH3 Low Area Non-secured in HSELx Security Region 3 1 read-write LANSECH4 Low Area Non-secured in HSELx Security Region 4 1 read-write LANSECH5 Low Area Non-secured in HSELx Security Region 5 1 read-write LANSECH6 Low Area Non-secured in HSELx Security Region 6 1 read-write LANSECH7 Low Area Non-secured in HSELx Security Region 7 1 read-write RDNSECH0 Read Non-secured for HSELx Security Region 8 1 read-write RDNSECH1 Read Non-secured for HSELx Security Region 9 1 read-write RDNSECH2 Read Non-secured for HSELx Security Region 10 1 read-write RDNSECH3 Read Non-secured for HSELx Security Region 11 1 read-write RDNSECH4 Read Non-secured for HSELx Security Region 12 1 read-write RDNSECH5 Read Non-secured for HSELx Security Region 13 1 read-write RDNSECH6 Read Non-secured for HSELx Security Region 14 1 read-write RDNSECH7 Read Non-secured for HSELx Security Region 15 1 read-write WRNSECH0 Write Non-secured for HSELx Security Region 16 1 read-write WRNSECH1 Write Non-secured for HSELx Security Region 17 1 read-write WRNSECH2 Write Non-secured for HSELx Security Region 18 1 read-write WRNSECH3 Write Non-secured for HSELx Security Region 19 1 read-write WRNSECH4 Write Non-secured for HSELx Security Region 20 1 read-write WRNSECH5 Write Non-secured for HSELx Security Region 21 1 read-write WRNSECH6 Write Non-secured for HSELx Security Region 22 1 read-write WRNSECH7 Write Non-secured for HSELx Security Region 23 1 read-write SSR1 Security Slave 0 Register 0x204 32 read-write n LANSECH0 Low Area Non-secured in HSELx Security Region 0 1 read-write LANSECH1 Low Area Non-secured in HSELx Security Region 1 1 read-write LANSECH2 Low Area Non-secured in HSELx Security Region 2 1 read-write LANSECH3 Low Area Non-secured in HSELx Security Region 3 1 read-write LANSECH4 Low Area Non-secured in HSELx Security Region 4 1 read-write LANSECH5 Low Area Non-secured in HSELx Security Region 5 1 read-write LANSECH6 Low Area Non-secured in HSELx Security Region 6 1 read-write LANSECH7 Low Area Non-secured in HSELx Security Region 7 1 read-write RDNSECH0 Read Non-secured for HSELx Security Region 8 1 read-write RDNSECH1 Read Non-secured for HSELx Security Region 9 1 read-write RDNSECH2 Read Non-secured for HSELx Security Region 10 1 read-write RDNSECH3 Read Non-secured for HSELx Security Region 11 1 read-write RDNSECH4 Read Non-secured for HSELx Security Region 12 1 read-write RDNSECH5 Read Non-secured for HSELx Security Region 13 1 read-write RDNSECH6 Read Non-secured for HSELx Security Region 14 1 read-write RDNSECH7 Read Non-secured for HSELx Security Region 15 1 read-write WRNSECH0 Write Non-secured for HSELx Security Region 16 1 read-write WRNSECH1 Write Non-secured for HSELx Security Region 17 1 read-write WRNSECH2 Write Non-secured for HSELx Security Region 18 1 read-write WRNSECH3 Write Non-secured for HSELx Security Region 19 1 read-write WRNSECH4 Write Non-secured for HSELx Security Region 20 1 read-write WRNSECH5 Write Non-secured for HSELx Security Region 21 1 read-write WRNSECH6 Write Non-secured for HSELx Security Region 22 1 read-write WRNSECH7 Write Non-secured for HSELx Security Region 23 1 read-write SSR10 Security Slave 0 Register 0x228 32 read-write n LANSECH0 Low Area Non-secured in HSELx Security Region 0 1 read-write LANSECH1 Low Area Non-secured in HSELx Security Region 1 1 read-write LANSECH2 Low Area Non-secured in HSELx Security Region 2 1 read-write LANSECH3 Low Area Non-secured in HSELx Security Region 3 1 read-write LANSECH4 Low Area Non-secured in HSELx Security Region 4 1 read-write LANSECH5 Low Area Non-secured in HSELx Security Region 5 1 read-write LANSECH6 Low Area Non-secured in HSELx Security Region 6 1 read-write LANSECH7 Low Area Non-secured in HSELx Security Region 7 1 read-write RDNSECH0 Read Non-secured for HSELx Security Region 8 1 read-write RDNSECH1 Read Non-secured for HSELx Security Region 9 1 read-write RDNSECH2 Read Non-secured for HSELx Security Region 10 1 read-write RDNSECH3 Read Non-secured for HSELx Security Region 11 1 read-write RDNSECH4 Read Non-secured for HSELx Security Region 12 1 read-write RDNSECH5 Read Non-secured for HSELx Security Region 13 1 read-write RDNSECH6 Read Non-secured for HSELx Security Region 14 1 read-write RDNSECH7 Read Non-secured for HSELx Security Region 15 1 read-write WRNSECH0 Write Non-secured for HSELx Security Region 16 1 read-write WRNSECH1 Write Non-secured for HSELx Security Region 17 1 read-write WRNSECH2 Write Non-secured for HSELx Security Region 18 1 read-write WRNSECH3 Write Non-secured for HSELx Security Region 19 1 read-write WRNSECH4 Write Non-secured for HSELx Security Region 20 1 read-write WRNSECH5 Write Non-secured for HSELx Security Region 21 1 read-write WRNSECH6 Write Non-secured for HSELx Security Region 22 1 read-write WRNSECH7 Write Non-secured for HSELx Security Region 23 1 read-write SSR11 Security Slave 0 Register 0x22C 32 read-write n LANSECH0 Low Area Non-secured in HSELx Security Region 0 1 read-write LANSECH1 Low Area Non-secured in HSELx Security Region 1 1 read-write LANSECH2 Low Area Non-secured in HSELx Security Region 2 1 read-write LANSECH3 Low Area Non-secured in HSELx Security Region 3 1 read-write LANSECH4 Low Area Non-secured in HSELx Security Region 4 1 read-write LANSECH5 Low Area Non-secured in HSELx Security Region 5 1 read-write LANSECH6 Low Area Non-secured in HSELx Security Region 6 1 read-write LANSECH7 Low Area Non-secured in HSELx Security Region 7 1 read-write RDNSECH0 Read Non-secured for HSELx Security Region 8 1 read-write RDNSECH1 Read Non-secured for HSELx Security Region 9 1 read-write RDNSECH2 Read Non-secured for HSELx Security Region 10 1 read-write RDNSECH3 Read Non-secured for HSELx Security Region 11 1 read-write RDNSECH4 Read Non-secured for HSELx Security Region 12 1 read-write RDNSECH5 Read Non-secured for HSELx Security Region 13 1 read-write RDNSECH6 Read Non-secured for HSELx Security Region 14 1 read-write RDNSECH7 Read Non-secured for HSELx Security Region 15 1 read-write WRNSECH0 Write Non-secured for HSELx Security Region 16 1 read-write WRNSECH1 Write Non-secured for HSELx Security Region 17 1 read-write WRNSECH2 Write Non-secured for HSELx Security Region 18 1 read-write WRNSECH3 Write Non-secured for HSELx Security Region 19 1 read-write WRNSECH4 Write Non-secured for HSELx Security Region 20 1 read-write WRNSECH5 Write Non-secured for HSELx Security Region 21 1 read-write WRNSECH6 Write Non-secured for HSELx Security Region 22 1 read-write WRNSECH7 Write Non-secured for HSELx Security Region 23 1 read-write SSR12 Security Slave 0 Register 0x230 32 read-write n LANSECH0 Low Area Non-secured in HSELx Security Region 0 1 read-write LANSECH1 Low Area Non-secured in HSELx Security Region 1 1 read-write LANSECH2 Low Area Non-secured in HSELx Security Region 2 1 read-write LANSECH3 Low Area Non-secured in HSELx Security Region 3 1 read-write LANSECH4 Low Area Non-secured in HSELx Security Region 4 1 read-write LANSECH5 Low Area Non-secured in HSELx Security Region 5 1 read-write LANSECH6 Low Area Non-secured in HSELx Security Region 6 1 read-write LANSECH7 Low Area Non-secured in HSELx Security Region 7 1 read-write RDNSECH0 Read Non-secured for HSELx Security Region 8 1 read-write RDNSECH1 Read Non-secured for HSELx Security Region 9 1 read-write RDNSECH2 Read Non-secured for HSELx Security Region 10 1 read-write RDNSECH3 Read Non-secured for HSELx Security Region 11 1 read-write RDNSECH4 Read Non-secured for HSELx Security Region 12 1 read-write RDNSECH5 Read Non-secured for HSELx Security Region 13 1 read-write RDNSECH6 Read Non-secured for HSELx Security Region 14 1 read-write RDNSECH7 Read Non-secured for HSELx Security Region 15 1 read-write WRNSECH0 Write Non-secured for HSELx Security Region 16 1 read-write WRNSECH1 Write Non-secured for HSELx Security Region 17 1 read-write WRNSECH2 Write Non-secured for HSELx Security Region 18 1 read-write WRNSECH3 Write Non-secured for HSELx Security Region 19 1 read-write WRNSECH4 Write Non-secured for HSELx Security Region 20 1 read-write WRNSECH5 Write Non-secured for HSELx Security Region 21 1 read-write WRNSECH6 Write Non-secured for HSELx Security Region 22 1 read-write WRNSECH7 Write Non-secured for HSELx Security Region 23 1 read-write SSR2 Security Slave 0 Register 0x208 32 read-write n LANSECH0 Low Area Non-secured in HSELx Security Region 0 1 read-write LANSECH1 Low Area Non-secured in HSELx Security Region 1 1 read-write LANSECH2 Low Area Non-secured in HSELx Security Region 2 1 read-write LANSECH3 Low Area Non-secured in HSELx Security Region 3 1 read-write LANSECH4 Low Area Non-secured in HSELx Security Region 4 1 read-write LANSECH5 Low Area Non-secured in HSELx Security Region 5 1 read-write LANSECH6 Low Area Non-secured in HSELx Security Region 6 1 read-write LANSECH7 Low Area Non-secured in HSELx Security Region 7 1 read-write RDNSECH0 Read Non-secured for HSELx Security Region 8 1 read-write RDNSECH1 Read Non-secured for HSELx Security Region 9 1 read-write RDNSECH2 Read Non-secured for HSELx Security Region 10 1 read-write RDNSECH3 Read Non-secured for HSELx Security Region 11 1 read-write RDNSECH4 Read Non-secured for HSELx Security Region 12 1 read-write RDNSECH5 Read Non-secured for HSELx Security Region 13 1 read-write RDNSECH6 Read Non-secured for HSELx Security Region 14 1 read-write RDNSECH7 Read Non-secured for HSELx Security Region 15 1 read-write WRNSECH0 Write Non-secured for HSELx Security Region 16 1 read-write WRNSECH1 Write Non-secured for HSELx Security Region 17 1 read-write WRNSECH2 Write Non-secured for HSELx Security Region 18 1 read-write WRNSECH3 Write Non-secured for HSELx Security Region 19 1 read-write WRNSECH4 Write Non-secured for HSELx Security Region 20 1 read-write WRNSECH5 Write Non-secured for HSELx Security Region 21 1 read-write WRNSECH6 Write Non-secured for HSELx Security Region 22 1 read-write WRNSECH7 Write Non-secured for HSELx Security Region 23 1 read-write SSR3 Security Slave 0 Register 0x20C 32 read-write n LANSECH0 Low Area Non-secured in HSELx Security Region 0 1 read-write LANSECH1 Low Area Non-secured in HSELx Security Region 1 1 read-write LANSECH2 Low Area Non-secured in HSELx Security Region 2 1 read-write LANSECH3 Low Area Non-secured in HSELx Security Region 3 1 read-write LANSECH4 Low Area Non-secured in HSELx Security Region 4 1 read-write LANSECH5 Low Area Non-secured in HSELx Security Region 5 1 read-write LANSECH6 Low Area Non-secured in HSELx Security Region 6 1 read-write LANSECH7 Low Area Non-secured in HSELx Security Region 7 1 read-write RDNSECH0 Read Non-secured for HSELx Security Region 8 1 read-write RDNSECH1 Read Non-secured for HSELx Security Region 9 1 read-write RDNSECH2 Read Non-secured for HSELx Security Region 10 1 read-write RDNSECH3 Read Non-secured for HSELx Security Region 11 1 read-write RDNSECH4 Read Non-secured for HSELx Security Region 12 1 read-write RDNSECH5 Read Non-secured for HSELx Security Region 13 1 read-write RDNSECH6 Read Non-secured for HSELx Security Region 14 1 read-write RDNSECH7 Read Non-secured for HSELx Security Region 15 1 read-write WRNSECH0 Write Non-secured for HSELx Security Region 16 1 read-write WRNSECH1 Write Non-secured for HSELx Security Region 17 1 read-write WRNSECH2 Write Non-secured for HSELx Security Region 18 1 read-write WRNSECH3 Write Non-secured for HSELx Security Region 19 1 read-write WRNSECH4 Write Non-secured for HSELx Security Region 20 1 read-write WRNSECH5 Write Non-secured for HSELx Security Region 21 1 read-write WRNSECH6 Write Non-secured for HSELx Security Region 22 1 read-write WRNSECH7 Write Non-secured for HSELx Security Region 23 1 read-write SSR4 Security Slave 0 Register 0x210 32 read-write n LANSECH0 Low Area Non-secured in HSELx Security Region 0 1 read-write LANSECH1 Low Area Non-secured in HSELx Security Region 1 1 read-write LANSECH2 Low Area Non-secured in HSELx Security Region 2 1 read-write LANSECH3 Low Area Non-secured in HSELx Security Region 3 1 read-write LANSECH4 Low Area Non-secured in HSELx Security Region 4 1 read-write LANSECH5 Low Area Non-secured in HSELx Security Region 5 1 read-write LANSECH6 Low Area Non-secured in HSELx Security Region 6 1 read-write LANSECH7 Low Area Non-secured in HSELx Security Region 7 1 read-write RDNSECH0 Read Non-secured for HSELx Security Region 8 1 read-write RDNSECH1 Read Non-secured for HSELx Security Region 9 1 read-write RDNSECH2 Read Non-secured for HSELx Security Region 10 1 read-write RDNSECH3 Read Non-secured for HSELx Security Region 11 1 read-write RDNSECH4 Read Non-secured for HSELx Security Region 12 1 read-write RDNSECH5 Read Non-secured for HSELx Security Region 13 1 read-write RDNSECH6 Read Non-secured for HSELx Security Region 14 1 read-write RDNSECH7 Read Non-secured for HSELx Security Region 15 1 read-write WRNSECH0 Write Non-secured for HSELx Security Region 16 1 read-write WRNSECH1 Write Non-secured for HSELx Security Region 17 1 read-write WRNSECH2 Write Non-secured for HSELx Security Region 18 1 read-write WRNSECH3 Write Non-secured for HSELx Security Region 19 1 read-write WRNSECH4 Write Non-secured for HSELx Security Region 20 1 read-write WRNSECH5 Write Non-secured for HSELx Security Region 21 1 read-write WRNSECH6 Write Non-secured for HSELx Security Region 22 1 read-write WRNSECH7 Write Non-secured for HSELx Security Region 23 1 read-write SSR5 Security Slave 0 Register 0x214 32 read-write n LANSECH0 Low Area Non-secured in HSELx Security Region 0 1 read-write LANSECH1 Low Area Non-secured in HSELx Security Region 1 1 read-write LANSECH2 Low Area Non-secured in HSELx Security Region 2 1 read-write LANSECH3 Low Area Non-secured in HSELx Security Region 3 1 read-write LANSECH4 Low Area Non-secured in HSELx Security Region 4 1 read-write LANSECH5 Low Area Non-secured in HSELx Security Region 5 1 read-write LANSECH6 Low Area Non-secured in HSELx Security Region 6 1 read-write LANSECH7 Low Area Non-secured in HSELx Security Region 7 1 read-write RDNSECH0 Read Non-secured for HSELx Security Region 8 1 read-write RDNSECH1 Read Non-secured for HSELx Security Region 9 1 read-write RDNSECH2 Read Non-secured for HSELx Security Region 10 1 read-write RDNSECH3 Read Non-secured for HSELx Security Region 11 1 read-write RDNSECH4 Read Non-secured for HSELx Security Region 12 1 read-write RDNSECH5 Read Non-secured for HSELx Security Region 13 1 read-write RDNSECH6 Read Non-secured for HSELx Security Region 14 1 read-write RDNSECH7 Read Non-secured for HSELx Security Region 15 1 read-write WRNSECH0 Write Non-secured for HSELx Security Region 16 1 read-write WRNSECH1 Write Non-secured for HSELx Security Region 17 1 read-write WRNSECH2 Write Non-secured for HSELx Security Region 18 1 read-write WRNSECH3 Write Non-secured for HSELx Security Region 19 1 read-write WRNSECH4 Write Non-secured for HSELx Security Region 20 1 read-write WRNSECH5 Write Non-secured for HSELx Security Region 21 1 read-write WRNSECH6 Write Non-secured for HSELx Security Region 22 1 read-write WRNSECH7 Write Non-secured for HSELx Security Region 23 1 read-write SSR6 Security Slave 0 Register 0x218 32 read-write n LANSECH0 Low Area Non-secured in HSELx Security Region 0 1 read-write LANSECH1 Low Area Non-secured in HSELx Security Region 1 1 read-write LANSECH2 Low Area Non-secured in HSELx Security Region 2 1 read-write LANSECH3 Low Area Non-secured in HSELx Security Region 3 1 read-write LANSECH4 Low Area Non-secured in HSELx Security Region 4 1 read-write LANSECH5 Low Area Non-secured in HSELx Security Region 5 1 read-write LANSECH6 Low Area Non-secured in HSELx Security Region 6 1 read-write LANSECH7 Low Area Non-secured in HSELx Security Region 7 1 read-write RDNSECH0 Read Non-secured for HSELx Security Region 8 1 read-write RDNSECH1 Read Non-secured for HSELx Security Region 9 1 read-write RDNSECH2 Read Non-secured for HSELx Security Region 10 1 read-write RDNSECH3 Read Non-secured for HSELx Security Region 11 1 read-write RDNSECH4 Read Non-secured for HSELx Security Region 12 1 read-write RDNSECH5 Read Non-secured for HSELx Security Region 13 1 read-write RDNSECH6 Read Non-secured for HSELx Security Region 14 1 read-write RDNSECH7 Read Non-secured for HSELx Security Region 15 1 read-write WRNSECH0 Write Non-secured for HSELx Security Region 16 1 read-write WRNSECH1 Write Non-secured for HSELx Security Region 17 1 read-write WRNSECH2 Write Non-secured for HSELx Security Region 18 1 read-write WRNSECH3 Write Non-secured for HSELx Security Region 19 1 read-write WRNSECH4 Write Non-secured for HSELx Security Region 20 1 read-write WRNSECH5 Write Non-secured for HSELx Security Region 21 1 read-write WRNSECH6 Write Non-secured for HSELx Security Region 22 1 read-write WRNSECH7 Write Non-secured for HSELx Security Region 23 1 read-write SSR7 Security Slave 0 Register 0x21C 32 read-write n LANSECH0 Low Area Non-secured in HSELx Security Region 0 1 read-write LANSECH1 Low Area Non-secured in HSELx Security Region 1 1 read-write LANSECH2 Low Area Non-secured in HSELx Security Region 2 1 read-write LANSECH3 Low Area Non-secured in HSELx Security Region 3 1 read-write LANSECH4 Low Area Non-secured in HSELx Security Region 4 1 read-write LANSECH5 Low Area Non-secured in HSELx Security Region 5 1 read-write LANSECH6 Low Area Non-secured in HSELx Security Region 6 1 read-write LANSECH7 Low Area Non-secured in HSELx Security Region 7 1 read-write RDNSECH0 Read Non-secured for HSELx Security Region 8 1 read-write RDNSECH1 Read Non-secured for HSELx Security Region 9 1 read-write RDNSECH2 Read Non-secured for HSELx Security Region 10 1 read-write RDNSECH3 Read Non-secured for HSELx Security Region 11 1 read-write RDNSECH4 Read Non-secured for HSELx Security Region 12 1 read-write RDNSECH5 Read Non-secured for HSELx Security Region 13 1 read-write RDNSECH6 Read Non-secured for HSELx Security Region 14 1 read-write RDNSECH7 Read Non-secured for HSELx Security Region 15 1 read-write WRNSECH0 Write Non-secured for HSELx Security Region 16 1 read-write WRNSECH1 Write Non-secured for HSELx Security Region 17 1 read-write WRNSECH2 Write Non-secured for HSELx Security Region 18 1 read-write WRNSECH3 Write Non-secured for HSELx Security Region 19 1 read-write WRNSECH4 Write Non-secured for HSELx Security Region 20 1 read-write WRNSECH5 Write Non-secured for HSELx Security Region 21 1 read-write WRNSECH6 Write Non-secured for HSELx Security Region 22 1 read-write WRNSECH7 Write Non-secured for HSELx Security Region 23 1 read-write SSR8 Security Slave 0 Register 0x220 32 read-write n LANSECH0 Low Area Non-secured in HSELx Security Region 0 1 read-write LANSECH1 Low Area Non-secured in HSELx Security Region 1 1 read-write LANSECH2 Low Area Non-secured in HSELx Security Region 2 1 read-write LANSECH3 Low Area Non-secured in HSELx Security Region 3 1 read-write LANSECH4 Low Area Non-secured in HSELx Security Region 4 1 read-write LANSECH5 Low Area Non-secured in HSELx Security Region 5 1 read-write LANSECH6 Low Area Non-secured in HSELx Security Region 6 1 read-write LANSECH7 Low Area Non-secured in HSELx Security Region 7 1 read-write RDNSECH0 Read Non-secured for HSELx Security Region 8 1 read-write RDNSECH1 Read Non-secured for HSELx Security Region 9 1 read-write RDNSECH2 Read Non-secured for HSELx Security Region 10 1 read-write RDNSECH3 Read Non-secured for HSELx Security Region 11 1 read-write RDNSECH4 Read Non-secured for HSELx Security Region 12 1 read-write RDNSECH5 Read Non-secured for HSELx Security Region 13 1 read-write RDNSECH6 Read Non-secured for HSELx Security Region 14 1 read-write RDNSECH7 Read Non-secured for HSELx Security Region 15 1 read-write WRNSECH0 Write Non-secured for HSELx Security Region 16 1 read-write WRNSECH1 Write Non-secured for HSELx Security Region 17 1 read-write WRNSECH2 Write Non-secured for HSELx Security Region 18 1 read-write WRNSECH3 Write Non-secured for HSELx Security Region 19 1 read-write WRNSECH4 Write Non-secured for HSELx Security Region 20 1 read-write WRNSECH5 Write Non-secured for HSELx Security Region 21 1 read-write WRNSECH6 Write Non-secured for HSELx Security Region 22 1 read-write WRNSECH7 Write Non-secured for HSELx Security Region 23 1 read-write SSR9 Security Slave 0 Register 0x224 32 read-write n LANSECH0 Low Area Non-secured in HSELx Security Region 0 1 read-write LANSECH1 Low Area Non-secured in HSELx Security Region 1 1 read-write LANSECH2 Low Area Non-secured in HSELx Security Region 2 1 read-write LANSECH3 Low Area Non-secured in HSELx Security Region 3 1 read-write LANSECH4 Low Area Non-secured in HSELx Security Region 4 1 read-write LANSECH5 Low Area Non-secured in HSELx Security Region 5 1 read-write LANSECH6 Low Area Non-secured in HSELx Security Region 6 1 read-write LANSECH7 Low Area Non-secured in HSELx Security Region 7 1 read-write RDNSECH0 Read Non-secured for HSELx Security Region 8 1 read-write RDNSECH1 Read Non-secured for HSELx Security Region 9 1 read-write RDNSECH2 Read Non-secured for HSELx Security Region 10 1 read-write RDNSECH3 Read Non-secured for HSELx Security Region 11 1 read-write RDNSECH4 Read Non-secured for HSELx Security Region 12 1 read-write RDNSECH5 Read Non-secured for HSELx Security Region 13 1 read-write RDNSECH6 Read Non-secured for HSELx Security Region 14 1 read-write RDNSECH7 Read Non-secured for HSELx Security Region 15 1 read-write WRNSECH0 Write Non-secured for HSELx Security Region 16 1 read-write WRNSECH1 Write Non-secured for HSELx Security Region 17 1 read-write WRNSECH2 Write Non-secured for HSELx Security Region 18 1 read-write WRNSECH3 Write Non-secured for HSELx Security Region 19 1 read-write WRNSECH4 Write Non-secured for HSELx Security Region 20 1 read-write WRNSECH5 Write Non-secured for HSELx Security Region 21 1 read-write WRNSECH6 Write Non-secured for HSELx Security Region 22 1 read-write WRNSECH7 Write Non-secured for HSELx Security Region 23 1 read-write SSR[0] Security Slave 0 Register 0x400 32 read-write n 0x0 0x0 LANSECH0 Low Area Non-secured in HSELx Security Region 0 1 read-write LANSECH1 Low Area Non-secured in HSELx Security Region 1 1 read-write LANSECH2 Low Area Non-secured in HSELx Security Region 2 1 read-write LANSECH3 Low Area Non-secured in HSELx Security Region 3 1 read-write LANSECH4 Low Area Non-secured in HSELx Security Region 4 1 read-write LANSECH5 Low Area Non-secured in HSELx Security Region 5 1 read-write LANSECH6 Low Area Non-secured in HSELx Security Region 6 1 read-write LANSECH7 Low Area Non-secured in HSELx Security Region 7 1 read-write RDNSECH0 Read Non-secured for HSELx Security Region 8 1 read-write RDNSECH1 Read Non-secured for HSELx Security Region 9 1 read-write RDNSECH2 Read Non-secured for HSELx Security Region 10 1 read-write RDNSECH3 Read Non-secured for HSELx Security Region 11 1 read-write RDNSECH4 Read Non-secured for HSELx Security Region 12 1 read-write RDNSECH5 Read Non-secured for HSELx Security Region 13 1 read-write RDNSECH6 Read Non-secured for HSELx Security Region 14 1 read-write RDNSECH7 Read Non-secured for HSELx Security Region 15 1 read-write WRNSECH0 Write Non-secured for HSELx Security Region 16 1 read-write WRNSECH1 Write Non-secured for HSELx Security Region 17 1 read-write WRNSECH2 Write Non-secured for HSELx Security Region 18 1 read-write WRNSECH3 Write Non-secured for HSELx Security Region 19 1 read-write WRNSECH4 Write Non-secured for HSELx Security Region 20 1 read-write WRNSECH5 Write Non-secured for HSELx Security Region 21 1 read-write WRNSECH6 Write Non-secured for HSELx Security Region 22 1 read-write WRNSECH7 Write Non-secured for HSELx Security Region 23 1 read-write SSR[10] Security Slave 0 Register 0x18DC 32 read-write n 0x0 0x0 LANSECH0 Low Area Non-secured in HSELx Security Region 0 1 read-write LANSECH1 Low Area Non-secured in HSELx Security Region 1 1 read-write LANSECH2 Low Area Non-secured in HSELx Security Region 2 1 read-write LANSECH3 Low Area Non-secured in HSELx Security Region 3 1 read-write LANSECH4 Low Area Non-secured in HSELx Security Region 4 1 read-write LANSECH5 Low Area Non-secured in HSELx Security Region 5 1 read-write LANSECH6 Low Area Non-secured in HSELx Security Region 6 1 read-write LANSECH7 Low Area Non-secured in HSELx Security Region 7 1 read-write RDNSECH0 Read Non-secured for HSELx Security Region 8 1 read-write RDNSECH1 Read Non-secured for HSELx Security Region 9 1 read-write RDNSECH2 Read Non-secured for HSELx Security Region 10 1 read-write RDNSECH3 Read Non-secured for HSELx Security Region 11 1 read-write RDNSECH4 Read Non-secured for HSELx Security Region 12 1 read-write RDNSECH5 Read Non-secured for HSELx Security Region 13 1 read-write RDNSECH6 Read Non-secured for HSELx Security Region 14 1 read-write RDNSECH7 Read Non-secured for HSELx Security Region 15 1 read-write WRNSECH0 Write Non-secured for HSELx Security Region 16 1 read-write WRNSECH1 Write Non-secured for HSELx Security Region 17 1 read-write WRNSECH2 Write Non-secured for HSELx Security Region 18 1 read-write WRNSECH3 Write Non-secured for HSELx Security Region 19 1 read-write WRNSECH4 Write Non-secured for HSELx Security Region 20 1 read-write WRNSECH5 Write Non-secured for HSELx Security Region 21 1 read-write WRNSECH6 Write Non-secured for HSELx Security Region 22 1 read-write WRNSECH7 Write Non-secured for HSELx Security Region 23 1 read-write SSR[11] Security Slave 0 Register 0x1B08 32 read-write n 0x0 0x0 LANSECH0 Low Area Non-secured in HSELx Security Region 0 1 read-write LANSECH1 Low Area Non-secured in HSELx Security Region 1 1 read-write LANSECH2 Low Area Non-secured in HSELx Security Region 2 1 read-write LANSECH3 Low Area Non-secured in HSELx Security Region 3 1 read-write LANSECH4 Low Area Non-secured in HSELx Security Region 4 1 read-write LANSECH5 Low Area Non-secured in HSELx Security Region 5 1 read-write LANSECH6 Low Area Non-secured in HSELx Security Region 6 1 read-write LANSECH7 Low Area Non-secured in HSELx Security Region 7 1 read-write RDNSECH0 Read Non-secured for HSELx Security Region 8 1 read-write RDNSECH1 Read Non-secured for HSELx Security Region 9 1 read-write RDNSECH2 Read Non-secured for HSELx Security Region 10 1 read-write RDNSECH3 Read Non-secured for HSELx Security Region 11 1 read-write RDNSECH4 Read Non-secured for HSELx Security Region 12 1 read-write RDNSECH5 Read Non-secured for HSELx Security Region 13 1 read-write RDNSECH6 Read Non-secured for HSELx Security Region 14 1 read-write RDNSECH7 Read Non-secured for HSELx Security Region 15 1 read-write WRNSECH0 Write Non-secured for HSELx Security Region 16 1 read-write WRNSECH1 Write Non-secured for HSELx Security Region 17 1 read-write WRNSECH2 Write Non-secured for HSELx Security Region 18 1 read-write WRNSECH3 Write Non-secured for HSELx Security Region 19 1 read-write WRNSECH4 Write Non-secured for HSELx Security Region 20 1 read-write WRNSECH5 Write Non-secured for HSELx Security Region 21 1 read-write WRNSECH6 Write Non-secured for HSELx Security Region 22 1 read-write WRNSECH7 Write Non-secured for HSELx Security Region 23 1 read-write SSR[12] Security Slave 0 Register 0x1D38 32 read-write n 0x0 0x0 LANSECH0 Low Area Non-secured in HSELx Security Region 0 1 read-write LANSECH1 Low Area Non-secured in HSELx Security Region 1 1 read-write LANSECH2 Low Area Non-secured in HSELx Security Region 2 1 read-write LANSECH3 Low Area Non-secured in HSELx Security Region 3 1 read-write LANSECH4 Low Area Non-secured in HSELx Security Region 4 1 read-write LANSECH5 Low Area Non-secured in HSELx Security Region 5 1 read-write LANSECH6 Low Area Non-secured in HSELx Security Region 6 1 read-write LANSECH7 Low Area Non-secured in HSELx Security Region 7 1 read-write RDNSECH0 Read Non-secured for HSELx Security Region 8 1 read-write RDNSECH1 Read Non-secured for HSELx Security Region 9 1 read-write RDNSECH2 Read Non-secured for HSELx Security Region 10 1 read-write RDNSECH3 Read Non-secured for HSELx Security Region 11 1 read-write RDNSECH4 Read Non-secured for HSELx Security Region 12 1 read-write RDNSECH5 Read Non-secured for HSELx Security Region 13 1 read-write RDNSECH6 Read Non-secured for HSELx Security Region 14 1 read-write RDNSECH7 Read Non-secured for HSELx Security Region 15 1 read-write WRNSECH0 Write Non-secured for HSELx Security Region 16 1 read-write WRNSECH1 Write Non-secured for HSELx Security Region 17 1 read-write WRNSECH2 Write Non-secured for HSELx Security Region 18 1 read-write WRNSECH3 Write Non-secured for HSELx Security Region 19 1 read-write WRNSECH4 Write Non-secured for HSELx Security Region 20 1 read-write WRNSECH5 Write Non-secured for HSELx Security Region 21 1 read-write WRNSECH6 Write Non-secured for HSELx Security Region 22 1 read-write WRNSECH7 Write Non-secured for HSELx Security Region 23 1 read-write SSR[1] Security Slave 0 Register 0x604 32 read-write n 0x0 0x0 LANSECH0 Low Area Non-secured in HSELx Security Region 0 1 read-write LANSECH1 Low Area Non-secured in HSELx Security Region 1 1 read-write LANSECH2 Low Area Non-secured in HSELx Security Region 2 1 read-write LANSECH3 Low Area Non-secured in HSELx Security Region 3 1 read-write LANSECH4 Low Area Non-secured in HSELx Security Region 4 1 read-write LANSECH5 Low Area Non-secured in HSELx Security Region 5 1 read-write LANSECH6 Low Area Non-secured in HSELx Security Region 6 1 read-write LANSECH7 Low Area Non-secured in HSELx Security Region 7 1 read-write RDNSECH0 Read Non-secured for HSELx Security Region 8 1 read-write RDNSECH1 Read Non-secured for HSELx Security Region 9 1 read-write RDNSECH2 Read Non-secured for HSELx Security Region 10 1 read-write RDNSECH3 Read Non-secured for HSELx Security Region 11 1 read-write RDNSECH4 Read Non-secured for HSELx Security Region 12 1 read-write RDNSECH5 Read Non-secured for HSELx Security Region 13 1 read-write RDNSECH6 Read Non-secured for HSELx Security Region 14 1 read-write RDNSECH7 Read Non-secured for HSELx Security Region 15 1 read-write WRNSECH0 Write Non-secured for HSELx Security Region 16 1 read-write WRNSECH1 Write Non-secured for HSELx Security Region 17 1 read-write WRNSECH2 Write Non-secured for HSELx Security Region 18 1 read-write WRNSECH3 Write Non-secured for HSELx Security Region 19 1 read-write WRNSECH4 Write Non-secured for HSELx Security Region 20 1 read-write WRNSECH5 Write Non-secured for HSELx Security Region 21 1 read-write WRNSECH6 Write Non-secured for HSELx Security Region 22 1 read-write WRNSECH7 Write Non-secured for HSELx Security Region 23 1 read-write SSR[2] Security Slave 0 Register 0x80C 32 read-write n 0x0 0x0 LANSECH0 Low Area Non-secured in HSELx Security Region 0 1 read-write LANSECH1 Low Area Non-secured in HSELx Security Region 1 1 read-write LANSECH2 Low Area Non-secured in HSELx Security Region 2 1 read-write LANSECH3 Low Area Non-secured in HSELx Security Region 3 1 read-write LANSECH4 Low Area Non-secured in HSELx Security Region 4 1 read-write LANSECH5 Low Area Non-secured in HSELx Security Region 5 1 read-write LANSECH6 Low Area Non-secured in HSELx Security Region 6 1 read-write LANSECH7 Low Area Non-secured in HSELx Security Region 7 1 read-write RDNSECH0 Read Non-secured for HSELx Security Region 8 1 read-write RDNSECH1 Read Non-secured for HSELx Security Region 9 1 read-write RDNSECH2 Read Non-secured for HSELx Security Region 10 1 read-write RDNSECH3 Read Non-secured for HSELx Security Region 11 1 read-write RDNSECH4 Read Non-secured for HSELx Security Region 12 1 read-write RDNSECH5 Read Non-secured for HSELx Security Region 13 1 read-write RDNSECH6 Read Non-secured for HSELx Security Region 14 1 read-write RDNSECH7 Read Non-secured for HSELx Security Region 15 1 read-write WRNSECH0 Write Non-secured for HSELx Security Region 16 1 read-write WRNSECH1 Write Non-secured for HSELx Security Region 17 1 read-write WRNSECH2 Write Non-secured for HSELx Security Region 18 1 read-write WRNSECH3 Write Non-secured for HSELx Security Region 19 1 read-write WRNSECH4 Write Non-secured for HSELx Security Region 20 1 read-write WRNSECH5 Write Non-secured for HSELx Security Region 21 1 read-write WRNSECH6 Write Non-secured for HSELx Security Region 22 1 read-write WRNSECH7 Write Non-secured for HSELx Security Region 23 1 read-write SSR[3] Security Slave 0 Register 0xA18 32 read-write n 0x0 0x0 LANSECH0 Low Area Non-secured in HSELx Security Region 0 1 read-write LANSECH1 Low Area Non-secured in HSELx Security Region 1 1 read-write LANSECH2 Low Area Non-secured in HSELx Security Region 2 1 read-write LANSECH3 Low Area Non-secured in HSELx Security Region 3 1 read-write LANSECH4 Low Area Non-secured in HSELx Security Region 4 1 read-write LANSECH5 Low Area Non-secured in HSELx Security Region 5 1 read-write LANSECH6 Low Area Non-secured in HSELx Security Region 6 1 read-write LANSECH7 Low Area Non-secured in HSELx Security Region 7 1 read-write RDNSECH0 Read Non-secured for HSELx Security Region 8 1 read-write RDNSECH1 Read Non-secured for HSELx Security Region 9 1 read-write RDNSECH2 Read Non-secured for HSELx Security Region 10 1 read-write RDNSECH3 Read Non-secured for HSELx Security Region 11 1 read-write RDNSECH4 Read Non-secured for HSELx Security Region 12 1 read-write RDNSECH5 Read Non-secured for HSELx Security Region 13 1 read-write RDNSECH6 Read Non-secured for HSELx Security Region 14 1 read-write RDNSECH7 Read Non-secured for HSELx Security Region 15 1 read-write WRNSECH0 Write Non-secured for HSELx Security Region 16 1 read-write WRNSECH1 Write Non-secured for HSELx Security Region 17 1 read-write WRNSECH2 Write Non-secured for HSELx Security Region 18 1 read-write WRNSECH3 Write Non-secured for HSELx Security Region 19 1 read-write WRNSECH4 Write Non-secured for HSELx Security Region 20 1 read-write WRNSECH5 Write Non-secured for HSELx Security Region 21 1 read-write WRNSECH6 Write Non-secured for HSELx Security Region 22 1 read-write WRNSECH7 Write Non-secured for HSELx Security Region 23 1 read-write SSR[4] Security Slave 0 Register 0xC28 32 read-write n 0x0 0x0 LANSECH0 Low Area Non-secured in HSELx Security Region 0 1 read-write LANSECH1 Low Area Non-secured in HSELx Security Region 1 1 read-write LANSECH2 Low Area Non-secured in HSELx Security Region 2 1 read-write LANSECH3 Low Area Non-secured in HSELx Security Region 3 1 read-write LANSECH4 Low Area Non-secured in HSELx Security Region 4 1 read-write LANSECH5 Low Area Non-secured in HSELx Security Region 5 1 read-write LANSECH6 Low Area Non-secured in HSELx Security Region 6 1 read-write LANSECH7 Low Area Non-secured in HSELx Security Region 7 1 read-write RDNSECH0 Read Non-secured for HSELx Security Region 8 1 read-write RDNSECH1 Read Non-secured for HSELx Security Region 9 1 read-write RDNSECH2 Read Non-secured for HSELx Security Region 10 1 read-write RDNSECH3 Read Non-secured for HSELx Security Region 11 1 read-write RDNSECH4 Read Non-secured for HSELx Security Region 12 1 read-write RDNSECH5 Read Non-secured for HSELx Security Region 13 1 read-write RDNSECH6 Read Non-secured for HSELx Security Region 14 1 read-write RDNSECH7 Read Non-secured for HSELx Security Region 15 1 read-write WRNSECH0 Write Non-secured for HSELx Security Region 16 1 read-write WRNSECH1 Write Non-secured for HSELx Security Region 17 1 read-write WRNSECH2 Write Non-secured for HSELx Security Region 18 1 read-write WRNSECH3 Write Non-secured for HSELx Security Region 19 1 read-write WRNSECH4 Write Non-secured for HSELx Security Region 20 1 read-write WRNSECH5 Write Non-secured for HSELx Security Region 21 1 read-write WRNSECH6 Write Non-secured for HSELx Security Region 22 1 read-write WRNSECH7 Write Non-secured for HSELx Security Region 23 1 read-write SSR[5] Security Slave 0 Register 0xE3C 32 read-write n 0x0 0x0 LANSECH0 Low Area Non-secured in HSELx Security Region 0 1 read-write LANSECH1 Low Area Non-secured in HSELx Security Region 1 1 read-write LANSECH2 Low Area Non-secured in HSELx Security Region 2 1 read-write LANSECH3 Low Area Non-secured in HSELx Security Region 3 1 read-write LANSECH4 Low Area Non-secured in HSELx Security Region 4 1 read-write LANSECH5 Low Area Non-secured in HSELx Security Region 5 1 read-write LANSECH6 Low Area Non-secured in HSELx Security Region 6 1 read-write LANSECH7 Low Area Non-secured in HSELx Security Region 7 1 read-write RDNSECH0 Read Non-secured for HSELx Security Region 8 1 read-write RDNSECH1 Read Non-secured for HSELx Security Region 9 1 read-write RDNSECH2 Read Non-secured for HSELx Security Region 10 1 read-write RDNSECH3 Read Non-secured for HSELx Security Region 11 1 read-write RDNSECH4 Read Non-secured for HSELx Security Region 12 1 read-write RDNSECH5 Read Non-secured for HSELx Security Region 13 1 read-write RDNSECH6 Read Non-secured for HSELx Security Region 14 1 read-write RDNSECH7 Read Non-secured for HSELx Security Region 15 1 read-write WRNSECH0 Write Non-secured for HSELx Security Region 16 1 read-write WRNSECH1 Write Non-secured for HSELx Security Region 17 1 read-write WRNSECH2 Write Non-secured for HSELx Security Region 18 1 read-write WRNSECH3 Write Non-secured for HSELx Security Region 19 1 read-write WRNSECH4 Write Non-secured for HSELx Security Region 20 1 read-write WRNSECH5 Write Non-secured for HSELx Security Region 21 1 read-write WRNSECH6 Write Non-secured for HSELx Security Region 22 1 read-write WRNSECH7 Write Non-secured for HSELx Security Region 23 1 read-write SSR[6] Security Slave 0 Register 0x1054 32 read-write n 0x0 0x0 LANSECH0 Low Area Non-secured in HSELx Security Region 0 1 read-write LANSECH1 Low Area Non-secured in HSELx Security Region 1 1 read-write LANSECH2 Low Area Non-secured in HSELx Security Region 2 1 read-write LANSECH3 Low Area Non-secured in HSELx Security Region 3 1 read-write LANSECH4 Low Area Non-secured in HSELx Security Region 4 1 read-write LANSECH5 Low Area Non-secured in HSELx Security Region 5 1 read-write LANSECH6 Low Area Non-secured in HSELx Security Region 6 1 read-write LANSECH7 Low Area Non-secured in HSELx Security Region 7 1 read-write RDNSECH0 Read Non-secured for HSELx Security Region 8 1 read-write RDNSECH1 Read Non-secured for HSELx Security Region 9 1 read-write RDNSECH2 Read Non-secured for HSELx Security Region 10 1 read-write RDNSECH3 Read Non-secured for HSELx Security Region 11 1 read-write RDNSECH4 Read Non-secured for HSELx Security Region 12 1 read-write RDNSECH5 Read Non-secured for HSELx Security Region 13 1 read-write RDNSECH6 Read Non-secured for HSELx Security Region 14 1 read-write RDNSECH7 Read Non-secured for HSELx Security Region 15 1 read-write WRNSECH0 Write Non-secured for HSELx Security Region 16 1 read-write WRNSECH1 Write Non-secured for HSELx Security Region 17 1 read-write WRNSECH2 Write Non-secured for HSELx Security Region 18 1 read-write WRNSECH3 Write Non-secured for HSELx Security Region 19 1 read-write WRNSECH4 Write Non-secured for HSELx Security Region 20 1 read-write WRNSECH5 Write Non-secured for HSELx Security Region 21 1 read-write WRNSECH6 Write Non-secured for HSELx Security Region 22 1 read-write WRNSECH7 Write Non-secured for HSELx Security Region 23 1 read-write SSR[7] Security Slave 0 Register 0x1270 32 read-write n 0x0 0x0 LANSECH0 Low Area Non-secured in HSELx Security Region 0 1 read-write LANSECH1 Low Area Non-secured in HSELx Security Region 1 1 read-write LANSECH2 Low Area Non-secured in HSELx Security Region 2 1 read-write LANSECH3 Low Area Non-secured in HSELx Security Region 3 1 read-write LANSECH4 Low Area Non-secured in HSELx Security Region 4 1 read-write LANSECH5 Low Area Non-secured in HSELx Security Region 5 1 read-write LANSECH6 Low Area Non-secured in HSELx Security Region 6 1 read-write LANSECH7 Low Area Non-secured in HSELx Security Region 7 1 read-write RDNSECH0 Read Non-secured for HSELx Security Region 8 1 read-write RDNSECH1 Read Non-secured for HSELx Security Region 9 1 read-write RDNSECH2 Read Non-secured for HSELx Security Region 10 1 read-write RDNSECH3 Read Non-secured for HSELx Security Region 11 1 read-write RDNSECH4 Read Non-secured for HSELx Security Region 12 1 read-write RDNSECH5 Read Non-secured for HSELx Security Region 13 1 read-write RDNSECH6 Read Non-secured for HSELx Security Region 14 1 read-write RDNSECH7 Read Non-secured for HSELx Security Region 15 1 read-write WRNSECH0 Write Non-secured for HSELx Security Region 16 1 read-write WRNSECH1 Write Non-secured for HSELx Security Region 17 1 read-write WRNSECH2 Write Non-secured for HSELx Security Region 18 1 read-write WRNSECH3 Write Non-secured for HSELx Security Region 19 1 read-write WRNSECH4 Write Non-secured for HSELx Security Region 20 1 read-write WRNSECH5 Write Non-secured for HSELx Security Region 21 1 read-write WRNSECH6 Write Non-secured for HSELx Security Region 22 1 read-write WRNSECH7 Write Non-secured for HSELx Security Region 23 1 read-write SSR[8] Security Slave 0 Register 0x1490 32 read-write n 0x0 0x0 LANSECH0 Low Area Non-secured in HSELx Security Region 0 1 read-write LANSECH1 Low Area Non-secured in HSELx Security Region 1 1 read-write LANSECH2 Low Area Non-secured in HSELx Security Region 2 1 read-write LANSECH3 Low Area Non-secured in HSELx Security Region 3 1 read-write LANSECH4 Low Area Non-secured in HSELx Security Region 4 1 read-write LANSECH5 Low Area Non-secured in HSELx Security Region 5 1 read-write LANSECH6 Low Area Non-secured in HSELx Security Region 6 1 read-write LANSECH7 Low Area Non-secured in HSELx Security Region 7 1 read-write RDNSECH0 Read Non-secured for HSELx Security Region 8 1 read-write RDNSECH1 Read Non-secured for HSELx Security Region 9 1 read-write RDNSECH2 Read Non-secured for HSELx Security Region 10 1 read-write RDNSECH3 Read Non-secured for HSELx Security Region 11 1 read-write RDNSECH4 Read Non-secured for HSELx Security Region 12 1 read-write RDNSECH5 Read Non-secured for HSELx Security Region 13 1 read-write RDNSECH6 Read Non-secured for HSELx Security Region 14 1 read-write RDNSECH7 Read Non-secured for HSELx Security Region 15 1 read-write WRNSECH0 Write Non-secured for HSELx Security Region 16 1 read-write WRNSECH1 Write Non-secured for HSELx Security Region 17 1 read-write WRNSECH2 Write Non-secured for HSELx Security Region 18 1 read-write WRNSECH3 Write Non-secured for HSELx Security Region 19 1 read-write WRNSECH4 Write Non-secured for HSELx Security Region 20 1 read-write WRNSECH5 Write Non-secured for HSELx Security Region 21 1 read-write WRNSECH6 Write Non-secured for HSELx Security Region 22 1 read-write WRNSECH7 Write Non-secured for HSELx Security Region 23 1 read-write SSR[9] Security Slave 0 Register 0x16B4 32 read-write n 0x0 0x0 LANSECH0 Low Area Non-secured in HSELx Security Region 0 1 read-write LANSECH1 Low Area Non-secured in HSELx Security Region 1 1 read-write LANSECH2 Low Area Non-secured in HSELx Security Region 2 1 read-write LANSECH3 Low Area Non-secured in HSELx Security Region 3 1 read-write LANSECH4 Low Area Non-secured in HSELx Security Region 4 1 read-write LANSECH5 Low Area Non-secured in HSELx Security Region 5 1 read-write LANSECH6 Low Area Non-secured in HSELx Security Region 6 1 read-write LANSECH7 Low Area Non-secured in HSELx Security Region 7 1 read-write RDNSECH0 Read Non-secured for HSELx Security Region 8 1 read-write RDNSECH1 Read Non-secured for HSELx Security Region 9 1 read-write RDNSECH2 Read Non-secured for HSELx Security Region 10 1 read-write RDNSECH3 Read Non-secured for HSELx Security Region 11 1 read-write RDNSECH4 Read Non-secured for HSELx Security Region 12 1 read-write RDNSECH5 Read Non-secured for HSELx Security Region 13 1 read-write RDNSECH6 Read Non-secured for HSELx Security Region 14 1 read-write RDNSECH7 Read Non-secured for HSELx Security Region 15 1 read-write WRNSECH0 Write Non-secured for HSELx Security Region 16 1 read-write WRNSECH1 Write Non-secured for HSELx Security Region 17 1 read-write WRNSECH2 Write Non-secured for HSELx Security Region 18 1 read-write WRNSECH3 Write Non-secured for HSELx Security Region 19 1 read-write WRNSECH4 Write Non-secured for HSELx Security Region 20 1 read-write WRNSECH5 Write Non-secured for HSELx Security Region 21 1 read-write WRNSECH6 Write Non-secured for HSELx Security Region 22 1 read-write WRNSECH7 Write Non-secured for HSELx Security Region 23 1 read-write WPMR Write Protection Mode Register 0x1E4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 read-write WPKEY Write Protection Key (Write-only) 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 0x4D4154 WPSR Write Protection Status Register 0x1E8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 read-only WPVSRC Write Protection Violation Source 8 16 read-only MATRIX1 AHB Bus Matrix 1 MATRIX 0x0 0x0 0x50 registers n MATRIX1 17 MCFG0 Master Configuration Register 0x0 32 read-write n ULBT Undefined Length Burst Type 0 3 read-write UNLIMITED Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0x0 SINGLE Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 0x1 4_BEAT 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 0x2 8_BEAT 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 0x3 16_BEAT 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 0x4 32_BEAT 32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 0x5 64_BEAT 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 0x6 128_BEAT 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving. 0x7 MCFG1 Master Configuration Register 0x4 32 read-write n ULBT Undefined Length Burst Type 0 3 read-write UNLIMITED Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0x0 SINGLE Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 0x1 4_BEAT 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 0x2 8_BEAT 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 0x3 16_BEAT 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 0x4 32_BEAT 32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 0x5 64_BEAT 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 0x6 128_BEAT 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving. 0x7 MCFG2 Master Configuration Register 0x8 32 read-write n ULBT Undefined Length Burst Type 0 3 read-write UNLIMITED Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0x0 SINGLE Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 0x1 4_BEAT 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 0x2 8_BEAT 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 0x3 16_BEAT 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 0x4 32_BEAT 32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 0x5 64_BEAT 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 0x6 128_BEAT 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving. 0x7 MCFG3 Master Configuration Register 0xC 32 read-write n ULBT Undefined Length Burst Type 0 3 read-write UNLIMITED Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0x0 SINGLE Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 0x1 4_BEAT 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 0x2 8_BEAT 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 0x3 16_BEAT 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 0x4 32_BEAT 32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 0x5 64_BEAT 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 0x6 128_BEAT 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving. 0x7 MCFG4 Master Configuration Register 0x10 32 read-write n ULBT Undefined Length Burst Type 0 3 read-write UNLIMITED Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0x0 SINGLE Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 0x1 4_BEAT 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 0x2 8_BEAT 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 0x3 16_BEAT 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 0x4 32_BEAT 32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 0x5 64_BEAT 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 0x6 128_BEAT 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving. 0x7 MCFG5 Master Configuration Register 0x14 32 read-write n ULBT Undefined Length Burst Type 0 3 read-write UNLIMITED Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0x0 SINGLE Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 0x1 4_BEAT 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 0x2 8_BEAT 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 0x3 16_BEAT 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 0x4 32_BEAT 32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 0x5 64_BEAT 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 0x6 128_BEAT 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving. 0x7 MCFG6 Master Configuration Register 0x18 32 read-write n ULBT Undefined Length Burst Type 0 3 read-write UNLIMITED Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0x0 SINGLE Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 0x1 4_BEAT 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 0x2 8_BEAT 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 0x3 16_BEAT 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 0x4 32_BEAT 32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 0x5 64_BEAT 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 0x6 128_BEAT 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving. 0x7 MCFG7 Master Configuration Register 0x1C 32 read-write n ULBT Undefined Length Burst Type 0 3 read-write UNLIMITED Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0x0 SINGLE Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 0x1 4_BEAT 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 0x2 8_BEAT 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 0x3 16_BEAT 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 0x4 32_BEAT 32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 0x5 64_BEAT 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 0x6 128_BEAT 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving. 0x7 MCFG8 Master Configuration Register 0x20 32 read-write n ULBT Undefined Length Burst Type 0 3 read-write UNLIMITED Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0x0 SINGLE Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 0x1 4_BEAT 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 0x2 8_BEAT 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 0x3 16_BEAT 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 0x4 32_BEAT 32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 0x5 64_BEAT 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 0x6 128_BEAT 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving. 0x7 MCFG9 Master Configuration Register 0x24 32 read-write n ULBT Undefined Length Burst Type 0 3 read-write UNLIMITED Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0x0 SINGLE Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 0x1 4_BEAT 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 0x2 8_BEAT 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 0x3 16_BEAT 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 0x4 32_BEAT 32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 0x5 64_BEAT 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 0x6 128_BEAT 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving. 0x7 MCFG[0] Master Configuration Register 0x0 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 read-write UNLIMITED Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0x0 SINGLE Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 0x1 4_BEAT 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 0x2 8_BEAT 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 0x3 16_BEAT 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 0x4 32_BEAT 32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 0x5 64_BEAT 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 0x6 128_BEAT 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving. 0x7 MCFG[1] Master Configuration Register 0x4 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 read-write UNLIMITED Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0x0 SINGLE Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 0x1 4_BEAT 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 0x2 8_BEAT 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 0x3 16_BEAT 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 0x4 32_BEAT 32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 0x5 64_BEAT 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 0x6 128_BEAT 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving. 0x7 MCFG[2] Master Configuration Register 0xC 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 read-write UNLIMITED Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0x0 SINGLE Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 0x1 4_BEAT 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 0x2 8_BEAT 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 0x3 16_BEAT 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 0x4 32_BEAT 32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 0x5 64_BEAT 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 0x6 128_BEAT 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving. 0x7 MCFG[3] Master Configuration Register 0x18 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 read-write UNLIMITED Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0x0 SINGLE Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 0x1 4_BEAT 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 0x2 8_BEAT 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 0x3 16_BEAT 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 0x4 32_BEAT 32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 0x5 64_BEAT 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 0x6 128_BEAT 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving. 0x7 MCFG[4] Master Configuration Register 0x28 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 read-write UNLIMITED Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0x0 SINGLE Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 0x1 4_BEAT 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 0x2 8_BEAT 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 0x3 16_BEAT 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 0x4 32_BEAT 32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 0x5 64_BEAT 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 0x6 128_BEAT 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving. 0x7 MCFG[5] Master Configuration Register 0x3C 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 read-write UNLIMITED Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0x0 SINGLE Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 0x1 4_BEAT 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 0x2 8_BEAT 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 0x3 16_BEAT 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 0x4 32_BEAT 32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 0x5 64_BEAT 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 0x6 128_BEAT 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving. 0x7 MCFG[6] Master Configuration Register 0x54 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 read-write UNLIMITED Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0x0 SINGLE Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 0x1 4_BEAT 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 0x2 8_BEAT 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 0x3 16_BEAT 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 0x4 32_BEAT 32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 0x5 64_BEAT 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 0x6 128_BEAT 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving. 0x7 MCFG[7] Master Configuration Register 0x70 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 read-write UNLIMITED Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0x0 SINGLE Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 0x1 4_BEAT 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 0x2 8_BEAT 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 0x3 16_BEAT 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 0x4 32_BEAT 32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 0x5 64_BEAT 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 0x6 128_BEAT 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving. 0x7 MCFG[8] Master Configuration Register 0x90 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 read-write UNLIMITED Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0x0 SINGLE Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 0x1 4_BEAT 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 0x2 8_BEAT 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 0x3 16_BEAT 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 0x4 32_BEAT 32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 0x5 64_BEAT 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 0x6 128_BEAT 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving. 0x7 MCFG[9] Master Configuration Register 0xB4 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 read-write UNLIMITED Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0x0 SINGLE Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 0x1 4_BEAT 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 0x2 8_BEAT 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 0x3 16_BEAT 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 0x4 32_BEAT 32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 0x5 64_BEAT 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 0x6 128_BEAT 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving. 0x7 MEAR0 Master 0 Error Address Register 0x160 32 read-only n ERRADD Master Error Address 0 32 read-only MEAR1 Master 0 Error Address Register 0x164 32 read-only n ERRADD Master Error Address 0 32 read-only MEAR2 Master 0 Error Address Register 0x168 32 read-only n ERRADD Master Error Address 0 32 read-only MEAR3 Master 0 Error Address Register 0x16C 32 read-only n ERRADD Master Error Address 0 32 read-only MEAR4 Master 0 Error Address Register 0x170 32 read-only n ERRADD Master Error Address 0 32 read-only MEAR5 Master 0 Error Address Register 0x174 32 read-only n ERRADD Master Error Address 0 32 read-only MEAR6 Master 0 Error Address Register 0x178 32 read-only n ERRADD Master Error Address 0 32 read-only MEAR7 Master 0 Error Address Register 0x17C 32 read-only n ERRADD Master Error Address 0 32 read-only MEAR8 Master 0 Error Address Register 0x180 32 read-only n ERRADD Master Error Address 0 32 read-only MEAR9 Master 0 Error Address Register 0x184 32 read-only n ERRADD Master Error Address 0 32 read-only MEAR[0] Master 0 Error Address Register 0x2C0 32 read-only n 0x0 0x0 ERRADD Master Error Address 0 32 read-only MEAR[1] Master 0 Error Address Register 0x424 32 read-only n 0x0 0x0 ERRADD Master Error Address 0 32 read-only MEAR[2] Master 0 Error Address Register 0x58C 32 read-only n 0x0 0x0 ERRADD Master Error Address 0 32 read-only MEAR[3] Master 0 Error Address Register 0x6F8 32 read-only n 0x0 0x0 ERRADD Master Error Address 0 32 read-only MEAR[4] Master 0 Error Address Register 0x868 32 read-only n 0x0 0x0 ERRADD Master Error Address 0 32 read-only MEAR[5] Master 0 Error Address Register 0x9DC 32 read-only n 0x0 0x0 ERRADD Master Error Address 0 32 read-only MEAR[6] Master 0 Error Address Register 0xB54 32 read-only n 0x0 0x0 ERRADD Master Error Address 0 32 read-only MEAR[7] Master 0 Error Address Register 0xCD0 32 read-only n 0x0 0x0 ERRADD Master Error Address 0 32 read-only MEAR[8] Master 0 Error Address Register 0xE50 32 read-only n 0x0 0x0 ERRADD Master Error Address 0 32 read-only MEAR[9] Master 0 Error Address Register 0xFD4 32 read-only n 0x0 0x0 ERRADD Master Error Address 0 32 read-only MEIDR Master Error Interrupt Disable Register 0x154 32 write-only n 0x0 0x0 MERR0 Master 0 Access Error 0 1 write-only MERR1 Master 1 Access Error 1 1 write-only MERR2 Master 2 Access Error 2 1 write-only MERR3 Master 3 Access Error 3 1 write-only MERR4 Master 4 Access Error 4 1 write-only MERR5 Master 5 Access Error 5 1 write-only MERR6 Master 6 Access Error 6 1 write-only MERR7 Master 7 Access Error 7 1 write-only MERR8 Master 8 Access Error 8 1 write-only MERR9 Master 9 Access Error 9 1 write-only MEIER Master Error Interrupt Enable Register 0x150 32 write-only n 0x0 0x0 MERR0 Master 0 Access Error 0 1 write-only MERR1 Master 1 Access Error 1 1 write-only MERR2 Master 2 Access Error 2 1 write-only MERR3 Master 3 Access Error 3 1 write-only MERR4 Master 4 Access Error 4 1 write-only MERR5 Master 5 Access Error 5 1 write-only MERR6 Master 6 Access Error 6 1 write-only MERR7 Master 7 Access Error 7 1 write-only MERR8 Master 8 Access Error 8 1 write-only MERR9 Master 9 Access Error 9 1 write-only MEIMR Master Error Interrupt Mask Register 0x158 32 read-only n 0x0 0x0 MERR0 Master 0 Access Error 0 1 read-only MERR1 Master 1 Access Error 1 1 read-only MERR2 Master 2 Access Error 2 1 read-only MERR3 Master 3 Access Error 3 1 read-only MERR4 Master 4 Access Error 4 1 read-only MERR5 Master 5 Access Error 5 1 read-only MERR6 Master 6 Access Error 6 1 read-only MERR7 Master 7 Access Error 7 1 read-only MERR8 Master 8 Access Error 8 1 read-only MERR9 Master 9 Access Error 9 1 read-only MESR Master Error Status Register 0x15C 32 read-only n 0x0 0x0 MERR0 Master 0 Access Error 0 1 read-only MERR1 Master 1 Access Error 1 1 read-only MERR2 Master 2 Access Error 2 1 read-only MERR3 Master 3 Access Error 3 1 read-only MERR4 Master 4 Access Error 4 1 read-only MERR5 Master 5 Access Error 5 1 read-only MERR6 Master 6 Access Error 6 1 read-only MERR7 Master 7 Access Error 7 1 read-only MERR8 Master 8 Access Error 8 1 read-only MERR9 Master 9 Access Error 9 1 read-only PRAS0 Priority Register A for Slave 0 0x80 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 2 read-write M1PR Master 1 Priority 4 2 read-write M2PR Master 2 Priority 8 2 read-write M3PR Master 3 Priority 12 2 read-write M4PR Master 4 Priority 16 2 read-write M5PR Master 5 Priority 20 2 read-write M6PR Master 6 Priority 24 2 read-write M7PR Master 7 Priority 28 2 read-write PRAS1 Priority Register A for Slave 1 0x88 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 2 read-write M1PR Master 1 Priority 4 2 read-write M2PR Master 2 Priority 8 2 read-write M3PR Master 3 Priority 12 2 read-write M4PR Master 4 Priority 16 2 read-write M5PR Master 5 Priority 20 2 read-write M6PR Master 6 Priority 24 2 read-write M7PR Master 7 Priority 28 2 read-write PRAS10 Priority Register A for Slave 10 0xD0 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 2 read-write M1PR Master 1 Priority 4 2 read-write M2PR Master 2 Priority 8 2 read-write M3PR Master 3 Priority 12 2 read-write M4PR Master 4 Priority 16 2 read-write M5PR Master 5 Priority 20 2 read-write M6PR Master 6 Priority 24 2 read-write M7PR Master 7 Priority 28 2 read-write PRAS11 Priority Register A for Slave 11 0xD8 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 2 read-write M1PR Master 1 Priority 4 2 read-write M2PR Master 2 Priority 8 2 read-write M3PR Master 3 Priority 12 2 read-write M4PR Master 4 Priority 16 2 read-write M5PR Master 5 Priority 20 2 read-write M6PR Master 6 Priority 24 2 read-write M7PR Master 7 Priority 28 2 read-write PRAS12 Priority Register A for Slave 12 0xE0 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 2 read-write M1PR Master 1 Priority 4 2 read-write M2PR Master 2 Priority 8 2 read-write M3PR Master 3 Priority 12 2 read-write M4PR Master 4 Priority 16 2 read-write M5PR Master 5 Priority 20 2 read-write M6PR Master 6 Priority 24 2 read-write M7PR Master 7 Priority 28 2 read-write PRAS2 Priority Register A for Slave 2 0x90 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 2 read-write M1PR Master 1 Priority 4 2 read-write M2PR Master 2 Priority 8 2 read-write M3PR Master 3 Priority 12 2 read-write M4PR Master 4 Priority 16 2 read-write M5PR Master 5 Priority 20 2 read-write M6PR Master 6 Priority 24 2 read-write M7PR Master 7 Priority 28 2 read-write PRAS3 Priority Register A for Slave 3 0x98 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 2 read-write M1PR Master 1 Priority 4 2 read-write M2PR Master 2 Priority 8 2 read-write M3PR Master 3 Priority 12 2 read-write M4PR Master 4 Priority 16 2 read-write M5PR Master 5 Priority 20 2 read-write M6PR Master 6 Priority 24 2 read-write M7PR Master 7 Priority 28 2 read-write PRAS4 Priority Register A for Slave 4 0xA0 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 2 read-write M1PR Master 1 Priority 4 2 read-write M2PR Master 2 Priority 8 2 read-write M3PR Master 3 Priority 12 2 read-write M4PR Master 4 Priority 16 2 read-write M5PR Master 5 Priority 20 2 read-write M6PR Master 6 Priority 24 2 read-write M7PR Master 7 Priority 28 2 read-write PRAS5 Priority Register A for Slave 5 0xA8 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 2 read-write M1PR Master 1 Priority 4 2 read-write M2PR Master 2 Priority 8 2 read-write M3PR Master 3 Priority 12 2 read-write M4PR Master 4 Priority 16 2 read-write M5PR Master 5 Priority 20 2 read-write M6PR Master 6 Priority 24 2 read-write M7PR Master 7 Priority 28 2 read-write PRAS6 Priority Register A for Slave 6 0xB0 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 2 read-write M1PR Master 1 Priority 4 2 read-write M2PR Master 2 Priority 8 2 read-write M3PR Master 3 Priority 12 2 read-write M4PR Master 4 Priority 16 2 read-write M5PR Master 5 Priority 20 2 read-write M6PR Master 6 Priority 24 2 read-write M7PR Master 7 Priority 28 2 read-write PRAS7 Priority Register A for Slave 7 0xB8 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 2 read-write M1PR Master 1 Priority 4 2 read-write M2PR Master 2 Priority 8 2 read-write M3PR Master 3 Priority 12 2 read-write M4PR Master 4 Priority 16 2 read-write M5PR Master 5 Priority 20 2 read-write M6PR Master 6 Priority 24 2 read-write M7PR Master 7 Priority 28 2 read-write PRAS8 Priority Register A for Slave 8 0xC0 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 2 read-write M1PR Master 1 Priority 4 2 read-write M2PR Master 2 Priority 8 2 read-write M3PR Master 3 Priority 12 2 read-write M4PR Master 4 Priority 16 2 read-write M5PR Master 5 Priority 20 2 read-write M6PR Master 6 Priority 24 2 read-write M7PR Master 7 Priority 28 2 read-write PRAS9 Priority Register A for Slave 9 0xC8 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 2 read-write M1PR Master 1 Priority 4 2 read-write M2PR Master 2 Priority 8 2 read-write M3PR Master 3 Priority 12 2 read-write M4PR Master 4 Priority 16 2 read-write M5PR Master 5 Priority 20 2 read-write M6PR Master 6 Priority 24 2 read-write M7PR Master 7 Priority 28 2 read-write PRBS0 Priority Register B for Slave 0 0x84 32 read-write n 0x0 0x0 M8PR Master 8 Priority 0 2 read-write M9PR Master 9 Priority 4 2 read-write PRBS1 Priority Register B for Slave 1 0x8C 32 read-write n 0x0 0x0 M8PR Master 8 Priority 0 2 read-write M9PR Master 9 Priority 4 2 read-write PRBS10 Priority Register B for Slave 10 0xD4 32 read-write n 0x0 0x0 M8PR Master 8 Priority 0 2 read-write M9PR Master 9 Priority 4 2 read-write PRBS11 Priority Register B for Slave 11 0xDC 32 read-write n 0x0 0x0 M8PR Master 8 Priority 0 2 read-write M9PR Master 9 Priority 4 2 read-write PRBS12 Priority Register B for Slave 12 0xE4 32 read-write n 0x0 0x0 M8PR Master 8 Priority 0 2 read-write M9PR Master 9 Priority 4 2 read-write PRBS2 Priority Register B for Slave 2 0x94 32 read-write n 0x0 0x0 M8PR Master 8 Priority 0 2 read-write M9PR Master 9 Priority 4 2 read-write PRBS3 Priority Register B for Slave 3 0x9C 32 read-write n 0x0 0x0 M8PR Master 8 Priority 0 2 read-write M9PR Master 9 Priority 4 2 read-write PRBS4 Priority Register B for Slave 4 0xA4 32 read-write n 0x0 0x0 M8PR Master 8 Priority 0 2 read-write M9PR Master 9 Priority 4 2 read-write PRBS5 Priority Register B for Slave 5 0xAC 32 read-write n 0x0 0x0 M8PR Master 8 Priority 0 2 read-write M9PR Master 9 Priority 4 2 read-write PRBS6 Priority Register B for Slave 6 0xB4 32 read-write n 0x0 0x0 M8PR Master 8 Priority 0 2 read-write M9PR Master 9 Priority 4 2 read-write PRBS7 Priority Register B for Slave 7 0xBC 32 read-write n 0x0 0x0 M8PR Master 8 Priority 0 2 read-write M9PR Master 9 Priority 4 2 read-write PRBS8 Priority Register B for Slave 8 0xC4 32 read-write n 0x0 0x0 M8PR Master 8 Priority 0 2 read-write M9PR Master 9 Priority 4 2 read-write PRBS9 Priority Register B for Slave 9 0xCC 32 read-write n 0x0 0x0 M8PR Master 8 Priority 0 2 read-write M9PR Master 9 Priority 4 2 read-write SASSR0 Security Areas Split Slave 0 Register 0x240 32 read-write n SASPLIT0 Security Areas Split for HSELx Security Region 0 4 read-write SASPLIT1 Security Areas Split for HSELx Security Region 4 4 read-write SASPLIT2 Security Areas Split for HSELx Security Region 8 4 read-write SASPLIT3 Security Areas Split for HSELx Security Region 12 4 read-write SASPLIT4 Security Areas Split for HSELx Security Region 16 4 read-write SASPLIT5 Security Areas Split for HSELx Security Region 20 4 read-write SASPLIT6 Security Areas Split for HSELx Security Region 24 4 read-write SASPLIT7 Security Areas Split for HSELx Security Region 28 4 read-write SASSR1 Security Areas Split Slave 0 Register 0x244 32 read-write n SASPLIT0 Security Areas Split for HSELx Security Region 0 4 read-write SASPLIT1 Security Areas Split for HSELx Security Region 4 4 read-write SASPLIT2 Security Areas Split for HSELx Security Region 8 4 read-write SASPLIT3 Security Areas Split for HSELx Security Region 12 4 read-write SASPLIT4 Security Areas Split for HSELx Security Region 16 4 read-write SASPLIT5 Security Areas Split for HSELx Security Region 20 4 read-write SASPLIT6 Security Areas Split for HSELx Security Region 24 4 read-write SASPLIT7 Security Areas Split for HSELx Security Region 28 4 read-write SASSR10 Security Areas Split Slave 0 Register 0x268 32 read-write n SASPLIT0 Security Areas Split for HSELx Security Region 0 4 read-write SASPLIT1 Security Areas Split for HSELx Security Region 4 4 read-write SASPLIT2 Security Areas Split for HSELx Security Region 8 4 read-write SASPLIT3 Security Areas Split for HSELx Security Region 12 4 read-write SASPLIT4 Security Areas Split for HSELx Security Region 16 4 read-write SASPLIT5 Security Areas Split for HSELx Security Region 20 4 read-write SASPLIT6 Security Areas Split for HSELx Security Region 24 4 read-write SASPLIT7 Security Areas Split for HSELx Security Region 28 4 read-write SASSR11 Security Areas Split Slave 0 Register 0x26C 32 read-write n SASPLIT0 Security Areas Split for HSELx Security Region 0 4 read-write SASPLIT1 Security Areas Split for HSELx Security Region 4 4 read-write SASPLIT2 Security Areas Split for HSELx Security Region 8 4 read-write SASPLIT3 Security Areas Split for HSELx Security Region 12 4 read-write SASPLIT4 Security Areas Split for HSELx Security Region 16 4 read-write SASPLIT5 Security Areas Split for HSELx Security Region 20 4 read-write SASPLIT6 Security Areas Split for HSELx Security Region 24 4 read-write SASPLIT7 Security Areas Split for HSELx Security Region 28 4 read-write SASSR12 Security Areas Split Slave 0 Register 0x270 32 read-write n SASPLIT0 Security Areas Split for HSELx Security Region 0 4 read-write SASPLIT1 Security Areas Split for HSELx Security Region 4 4 read-write SASPLIT2 Security Areas Split for HSELx Security Region 8 4 read-write SASPLIT3 Security Areas Split for HSELx Security Region 12 4 read-write SASPLIT4 Security Areas Split for HSELx Security Region 16 4 read-write SASPLIT5 Security Areas Split for HSELx Security Region 20 4 read-write SASPLIT6 Security Areas Split for HSELx Security Region 24 4 read-write SASPLIT7 Security Areas Split for HSELx Security Region 28 4 read-write SASSR2 Security Areas Split Slave 0 Register 0x248 32 read-write n SASPLIT0 Security Areas Split for HSELx Security Region 0 4 read-write SASPLIT1 Security Areas Split for HSELx Security Region 4 4 read-write SASPLIT2 Security Areas Split for HSELx Security Region 8 4 read-write SASPLIT3 Security Areas Split for HSELx Security Region 12 4 read-write SASPLIT4 Security Areas Split for HSELx Security Region 16 4 read-write SASPLIT5 Security Areas Split for HSELx Security Region 20 4 read-write SASPLIT6 Security Areas Split for HSELx Security Region 24 4 read-write SASPLIT7 Security Areas Split for HSELx Security Region 28 4 read-write SASSR3 Security Areas Split Slave 0 Register 0x24C 32 read-write n SASPLIT0 Security Areas Split for HSELx Security Region 0 4 read-write SASPLIT1 Security Areas Split for HSELx Security Region 4 4 read-write SASPLIT2 Security Areas Split for HSELx Security Region 8 4 read-write SASPLIT3 Security Areas Split for HSELx Security Region 12 4 read-write SASPLIT4 Security Areas Split for HSELx Security Region 16 4 read-write SASPLIT5 Security Areas Split for HSELx Security Region 20 4 read-write SASPLIT6 Security Areas Split for HSELx Security Region 24 4 read-write SASPLIT7 Security Areas Split for HSELx Security Region 28 4 read-write SASSR4 Security Areas Split Slave 0 Register 0x250 32 read-write n SASPLIT0 Security Areas Split for HSELx Security Region 0 4 read-write SASPLIT1 Security Areas Split for HSELx Security Region 4 4 read-write SASPLIT2 Security Areas Split for HSELx Security Region 8 4 read-write SASPLIT3 Security Areas Split for HSELx Security Region 12 4 read-write SASPLIT4 Security Areas Split for HSELx Security Region 16 4 read-write SASPLIT5 Security Areas Split for HSELx Security Region 20 4 read-write SASPLIT6 Security Areas Split for HSELx Security Region 24 4 read-write SASPLIT7 Security Areas Split for HSELx Security Region 28 4 read-write SASSR5 Security Areas Split Slave 0 Register 0x254 32 read-write n SASPLIT0 Security Areas Split for HSELx Security Region 0 4 read-write SASPLIT1 Security Areas Split for HSELx Security Region 4 4 read-write SASPLIT2 Security Areas Split for HSELx Security Region 8 4 read-write SASPLIT3 Security Areas Split for HSELx Security Region 12 4 read-write SASPLIT4 Security Areas Split for HSELx Security Region 16 4 read-write SASPLIT5 Security Areas Split for HSELx Security Region 20 4 read-write SASPLIT6 Security Areas Split for HSELx Security Region 24 4 read-write SASPLIT7 Security Areas Split for HSELx Security Region 28 4 read-write SASSR6 Security Areas Split Slave 0 Register 0x258 32 read-write n SASPLIT0 Security Areas Split for HSELx Security Region 0 4 read-write SASPLIT1 Security Areas Split for HSELx Security Region 4 4 read-write SASPLIT2 Security Areas Split for HSELx Security Region 8 4 read-write SASPLIT3 Security Areas Split for HSELx Security Region 12 4 read-write SASPLIT4 Security Areas Split for HSELx Security Region 16 4 read-write SASPLIT5 Security Areas Split for HSELx Security Region 20 4 read-write SASPLIT6 Security Areas Split for HSELx Security Region 24 4 read-write SASPLIT7 Security Areas Split for HSELx Security Region 28 4 read-write SASSR7 Security Areas Split Slave 0 Register 0x25C 32 read-write n SASPLIT0 Security Areas Split for HSELx Security Region 0 4 read-write SASPLIT1 Security Areas Split for HSELx Security Region 4 4 read-write SASPLIT2 Security Areas Split for HSELx Security Region 8 4 read-write SASPLIT3 Security Areas Split for HSELx Security Region 12 4 read-write SASPLIT4 Security Areas Split for HSELx Security Region 16 4 read-write SASPLIT5 Security Areas Split for HSELx Security Region 20 4 read-write SASPLIT6 Security Areas Split for HSELx Security Region 24 4 read-write SASPLIT7 Security Areas Split for HSELx Security Region 28 4 read-write SASSR8 Security Areas Split Slave 0 Register 0x260 32 read-write n SASPLIT0 Security Areas Split for HSELx Security Region 0 4 read-write SASPLIT1 Security Areas Split for HSELx Security Region 4 4 read-write SASPLIT2 Security Areas Split for HSELx Security Region 8 4 read-write SASPLIT3 Security Areas Split for HSELx Security Region 12 4 read-write SASPLIT4 Security Areas Split for HSELx Security Region 16 4 read-write SASPLIT5 Security Areas Split for HSELx Security Region 20 4 read-write SASPLIT6 Security Areas Split for HSELx Security Region 24 4 read-write SASPLIT7 Security Areas Split for HSELx Security Region 28 4 read-write SASSR9 Security Areas Split Slave 0 Register 0x264 32 read-write n SASPLIT0 Security Areas Split for HSELx Security Region 0 4 read-write SASPLIT1 Security Areas Split for HSELx Security Region 4 4 read-write SASPLIT2 Security Areas Split for HSELx Security Region 8 4 read-write SASPLIT3 Security Areas Split for HSELx Security Region 12 4 read-write SASPLIT4 Security Areas Split for HSELx Security Region 16 4 read-write SASPLIT5 Security Areas Split for HSELx Security Region 20 4 read-write SASPLIT6 Security Areas Split for HSELx Security Region 24 4 read-write SASPLIT7 Security Areas Split for HSELx Security Region 28 4 read-write SASSR[0] Security Areas Split Slave 0 Register 0x480 32 read-write n 0x0 0x0 SASPLIT0 Security Areas Split for HSELx Security Region 0 4 read-write SASPLIT1 Security Areas Split for HSELx Security Region 4 4 read-write SASPLIT2 Security Areas Split for HSELx Security Region 8 4 read-write SASPLIT3 Security Areas Split for HSELx Security Region 12 4 read-write SASPLIT4 Security Areas Split for HSELx Security Region 16 4 read-write SASPLIT5 Security Areas Split for HSELx Security Region 20 4 read-write SASPLIT6 Security Areas Split for HSELx Security Region 24 4 read-write SASPLIT7 Security Areas Split for HSELx Security Region 28 4 read-write SASSR[10] Security Areas Split Slave 0 Register 0x1BDC 32 read-write n 0x0 0x0 SASPLIT0 Security Areas Split for HSELx Security Region 0 4 read-write SASPLIT1 Security Areas Split for HSELx Security Region 4 4 read-write SASPLIT2 Security Areas Split for HSELx Security Region 8 4 read-write SASPLIT3 Security Areas Split for HSELx Security Region 12 4 read-write SASPLIT4 Security Areas Split for HSELx Security Region 16 4 read-write SASPLIT5 Security Areas Split for HSELx Security Region 20 4 read-write SASPLIT6 Security Areas Split for HSELx Security Region 24 4 read-write SASPLIT7 Security Areas Split for HSELx Security Region 28 4 read-write SASSR[11] Security Areas Split Slave 0 Register 0x1E48 32 read-write n 0x0 0x0 SASPLIT0 Security Areas Split for HSELx Security Region 0 4 read-write SASPLIT1 Security Areas Split for HSELx Security Region 4 4 read-write SASPLIT2 Security Areas Split for HSELx Security Region 8 4 read-write SASPLIT3 Security Areas Split for HSELx Security Region 12 4 read-write SASPLIT4 Security Areas Split for HSELx Security Region 16 4 read-write SASPLIT5 Security Areas Split for HSELx Security Region 20 4 read-write SASPLIT6 Security Areas Split for HSELx Security Region 24 4 read-write SASPLIT7 Security Areas Split for HSELx Security Region 28 4 read-write SASSR[12] Security Areas Split Slave 0 Register 0x20B8 32 read-write n 0x0 0x0 SASPLIT0 Security Areas Split for HSELx Security Region 0 4 read-write SASPLIT1 Security Areas Split for HSELx Security Region 4 4 read-write SASPLIT2 Security Areas Split for HSELx Security Region 8 4 read-write SASPLIT3 Security Areas Split for HSELx Security Region 12 4 read-write SASPLIT4 Security Areas Split for HSELx Security Region 16 4 read-write SASPLIT5 Security Areas Split for HSELx Security Region 20 4 read-write SASPLIT6 Security Areas Split for HSELx Security Region 24 4 read-write SASPLIT7 Security Areas Split for HSELx Security Region 28 4 read-write SASSR[1] Security Areas Split Slave 0 Register 0x6C4 32 read-write n 0x0 0x0 SASPLIT0 Security Areas Split for HSELx Security Region 0 4 read-write SASPLIT1 Security Areas Split for HSELx Security Region 4 4 read-write SASPLIT2 Security Areas Split for HSELx Security Region 8 4 read-write SASPLIT3 Security Areas Split for HSELx Security Region 12 4 read-write SASPLIT4 Security Areas Split for HSELx Security Region 16 4 read-write SASPLIT5 Security Areas Split for HSELx Security Region 20 4 read-write SASPLIT6 Security Areas Split for HSELx Security Region 24 4 read-write SASPLIT7 Security Areas Split for HSELx Security Region 28 4 read-write SASSR[2] Security Areas Split Slave 0 Register 0x90C 32 read-write n 0x0 0x0 SASPLIT0 Security Areas Split for HSELx Security Region 0 4 read-write SASPLIT1 Security Areas Split for HSELx Security Region 4 4 read-write SASPLIT2 Security Areas Split for HSELx Security Region 8 4 read-write SASPLIT3 Security Areas Split for HSELx Security Region 12 4 read-write SASPLIT4 Security Areas Split for HSELx Security Region 16 4 read-write SASPLIT5 Security Areas Split for HSELx Security Region 20 4 read-write SASPLIT6 Security Areas Split for HSELx Security Region 24 4 read-write SASPLIT7 Security Areas Split for HSELx Security Region 28 4 read-write SASSR[3] Security Areas Split Slave 0 Register 0xB58 32 read-write n 0x0 0x0 SASPLIT0 Security Areas Split for HSELx Security Region 0 4 read-write SASPLIT1 Security Areas Split for HSELx Security Region 4 4 read-write SASPLIT2 Security Areas Split for HSELx Security Region 8 4 read-write SASPLIT3 Security Areas Split for HSELx Security Region 12 4 read-write SASPLIT4 Security Areas Split for HSELx Security Region 16 4 read-write SASPLIT5 Security Areas Split for HSELx Security Region 20 4 read-write SASPLIT6 Security Areas Split for HSELx Security Region 24 4 read-write SASPLIT7 Security Areas Split for HSELx Security Region 28 4 read-write SASSR[4] Security Areas Split Slave 0 Register 0xDA8 32 read-write n 0x0 0x0 SASPLIT0 Security Areas Split for HSELx Security Region 0 4 read-write SASPLIT1 Security Areas Split for HSELx Security Region 4 4 read-write SASPLIT2 Security Areas Split for HSELx Security Region 8 4 read-write SASPLIT3 Security Areas Split for HSELx Security Region 12 4 read-write SASPLIT4 Security Areas Split for HSELx Security Region 16 4 read-write SASPLIT5 Security Areas Split for HSELx Security Region 20 4 read-write SASPLIT6 Security Areas Split for HSELx Security Region 24 4 read-write SASPLIT7 Security Areas Split for HSELx Security Region 28 4 read-write SASSR[5] Security Areas Split Slave 0 Register 0xFFC 32 read-write n 0x0 0x0 SASPLIT0 Security Areas Split for HSELx Security Region 0 4 read-write SASPLIT1 Security Areas Split for HSELx Security Region 4 4 read-write SASPLIT2 Security Areas Split for HSELx Security Region 8 4 read-write SASPLIT3 Security Areas Split for HSELx Security Region 12 4 read-write SASPLIT4 Security Areas Split for HSELx Security Region 16 4 read-write SASPLIT5 Security Areas Split for HSELx Security Region 20 4 read-write SASPLIT6 Security Areas Split for HSELx Security Region 24 4 read-write SASPLIT7 Security Areas Split for HSELx Security Region 28 4 read-write SASSR[6] Security Areas Split Slave 0 Register 0x1254 32 read-write n 0x0 0x0 SASPLIT0 Security Areas Split for HSELx Security Region 0 4 read-write SASPLIT1 Security Areas Split for HSELx Security Region 4 4 read-write SASPLIT2 Security Areas Split for HSELx Security Region 8 4 read-write SASPLIT3 Security Areas Split for HSELx Security Region 12 4 read-write SASPLIT4 Security Areas Split for HSELx Security Region 16 4 read-write SASPLIT5 Security Areas Split for HSELx Security Region 20 4 read-write SASPLIT6 Security Areas Split for HSELx Security Region 24 4 read-write SASPLIT7 Security Areas Split for HSELx Security Region 28 4 read-write SASSR[7] Security Areas Split Slave 0 Register 0x14B0 32 read-write n 0x0 0x0 SASPLIT0 Security Areas Split for HSELx Security Region 0 4 read-write SASPLIT1 Security Areas Split for HSELx Security Region 4 4 read-write SASPLIT2 Security Areas Split for HSELx Security Region 8 4 read-write SASPLIT3 Security Areas Split for HSELx Security Region 12 4 read-write SASPLIT4 Security Areas Split for HSELx Security Region 16 4 read-write SASPLIT5 Security Areas Split for HSELx Security Region 20 4 read-write SASPLIT6 Security Areas Split for HSELx Security Region 24 4 read-write SASPLIT7 Security Areas Split for HSELx Security Region 28 4 read-write SASSR[8] Security Areas Split Slave 0 Register 0x1710 32 read-write n 0x0 0x0 SASPLIT0 Security Areas Split for HSELx Security Region 0 4 read-write SASPLIT1 Security Areas Split for HSELx Security Region 4 4 read-write SASPLIT2 Security Areas Split for HSELx Security Region 8 4 read-write SASPLIT3 Security Areas Split for HSELx Security Region 12 4 read-write SASPLIT4 Security Areas Split for HSELx Security Region 16 4 read-write SASPLIT5 Security Areas Split for HSELx Security Region 20 4 read-write SASPLIT6 Security Areas Split for HSELx Security Region 24 4 read-write SASPLIT7 Security Areas Split for HSELx Security Region 28 4 read-write SASSR[9] Security Areas Split Slave 0 Register 0x1974 32 read-write n 0x0 0x0 SASPLIT0 Security Areas Split for HSELx Security Region 0 4 read-write SASPLIT1 Security Areas Split for HSELx Security Region 4 4 read-write SASPLIT2 Security Areas Split for HSELx Security Region 8 4 read-write SASPLIT3 Security Areas Split for HSELx Security Region 12 4 read-write SASPLIT4 Security Areas Split for HSELx Security Region 16 4 read-write SASPLIT5 Security Areas Split for HSELx Security Region 20 4 read-write SASPLIT6 Security Areas Split for HSELx Security Region 24 4 read-write SASPLIT7 Security Areas Split for HSELx Security Region 28 4 read-write SCFG0 Slave Configuration Register 0x40 32 read-write n DEFMSTR_TYPE Default Master Type 16 2 read-write NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 0x1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 4 read-write SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 read-write SCFG1 Slave Configuration Register 0x44 32 read-write n DEFMSTR_TYPE Default Master Type 16 2 read-write NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 0x1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 4 read-write SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 read-write SCFG10 Slave Configuration Register 0x68 32 read-write n DEFMSTR_TYPE Default Master Type 16 2 read-write NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 0x1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 4 read-write SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 read-write SCFG11 Slave Configuration Register 0x6C 32 read-write n DEFMSTR_TYPE Default Master Type 16 2 read-write NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 0x1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 4 read-write SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 read-write SCFG12 Slave Configuration Register 0x70 32 read-write n DEFMSTR_TYPE Default Master Type 16 2 read-write NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 0x1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 4 read-write SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 read-write SCFG2 Slave Configuration Register 0x48 32 read-write n DEFMSTR_TYPE Default Master Type 16 2 read-write NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 0x1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 4 read-write SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 read-write SCFG3 Slave Configuration Register 0x4C 32 read-write n DEFMSTR_TYPE Default Master Type 16 2 read-write NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 0x1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 4 read-write SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 read-write SCFG4 Slave Configuration Register 0x50 32 read-write n DEFMSTR_TYPE Default Master Type 16 2 read-write NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 0x1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 4 read-write SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 read-write SCFG5 Slave Configuration Register 0x54 32 read-write n DEFMSTR_TYPE Default Master Type 16 2 read-write NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 0x1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 4 read-write SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 read-write SCFG6 Slave Configuration Register 0x58 32 read-write n DEFMSTR_TYPE Default Master Type 16 2 read-write NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 0x1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 4 read-write SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 read-write SCFG7 Slave Configuration Register 0x5C 32 read-write n DEFMSTR_TYPE Default Master Type 16 2 read-write NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 0x1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 4 read-write SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 read-write SCFG8 Slave Configuration Register 0x60 32 read-write n DEFMSTR_TYPE Default Master Type 16 2 read-write NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 0x1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 4 read-write SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 read-write SCFG9 Slave Configuration Register 0x64 32 read-write n DEFMSTR_TYPE Default Master Type 16 2 read-write NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 0x1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 4 read-write SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 read-write SCFG[0] Slave Configuration Register 0x80 32 read-write n 0x0 0x0 DEFMSTR_TYPE Default Master Type 16 2 read-write NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 0x1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 4 read-write SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 read-write SCFG[10] Slave Configuration Register 0x3DC 32 read-write n 0x0 0x0 DEFMSTR_TYPE Default Master Type 16 2 read-write NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 0x1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 4 read-write SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 read-write SCFG[11] Slave Configuration Register 0x448 32 read-write n 0x0 0x0 DEFMSTR_TYPE Default Master Type 16 2 read-write NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 0x1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 4 read-write SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 read-write SCFG[12] Slave Configuration Register 0x4B8 32 read-write n 0x0 0x0 DEFMSTR_TYPE Default Master Type 16 2 read-write NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 0x1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 4 read-write SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 read-write SCFG[1] Slave Configuration Register 0xC4 32 read-write n 0x0 0x0 DEFMSTR_TYPE Default Master Type 16 2 read-write NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 0x1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 4 read-write SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 read-write SCFG[2] Slave Configuration Register 0x10C 32 read-write n 0x0 0x0 DEFMSTR_TYPE Default Master Type 16 2 read-write NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 0x1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 4 read-write SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 read-write SCFG[3] Slave Configuration Register 0x158 32 read-write n 0x0 0x0 DEFMSTR_TYPE Default Master Type 16 2 read-write NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 0x1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 4 read-write SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 read-write SCFG[4] Slave Configuration Register 0x1A8 32 read-write n 0x0 0x0 DEFMSTR_TYPE Default Master Type 16 2 read-write NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 0x1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 4 read-write SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 read-write SCFG[5] Slave Configuration Register 0x1FC 32 read-write n 0x0 0x0 DEFMSTR_TYPE Default Master Type 16 2 read-write NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 0x1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 4 read-write SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 read-write SCFG[6] Slave Configuration Register 0x254 32 read-write n 0x0 0x0 DEFMSTR_TYPE Default Master Type 16 2 read-write NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 0x1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 4 read-write SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 read-write SCFG[7] Slave Configuration Register 0x2B0 32 read-write n 0x0 0x0 DEFMSTR_TYPE Default Master Type 16 2 read-write NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 0x1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 4 read-write SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 read-write SCFG[8] Slave Configuration Register 0x310 32 read-write n 0x0 0x0 DEFMSTR_TYPE Default Master Type 16 2 read-write NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 0x1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 4 read-write SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 read-write SCFG[9] Slave Configuration Register 0x374 32 read-write n 0x0 0x0 DEFMSTR_TYPE Default Master Type 16 2 read-write NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 0x1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 4 read-write SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 read-write SPSELR0 Security Peripheral Select 1 Register 0x2C0 32 read-write n NSECP0 Non-secured Peripheral 0 1 read-write NSECP1 Non-secured Peripheral 1 1 read-write NSECP10 Non-secured Peripheral 10 1 read-write NSECP11 Non-secured Peripheral 11 1 read-write NSECP12 Non-secured Peripheral 12 1 read-write NSECP13 Non-secured Peripheral 13 1 read-write NSECP14 Non-secured Peripheral 14 1 read-write NSECP15 Non-secured Peripheral 15 1 read-write NSECP16 Non-secured Peripheral 16 1 read-write NSECP17 Non-secured Peripheral 17 1 read-write NSECP18 Non-secured Peripheral 18 1 read-write NSECP19 Non-secured Peripheral 19 1 read-write NSECP2 Non-secured Peripheral 2 1 read-write NSECP20 Non-secured Peripheral 20 1 read-write NSECP21 Non-secured Peripheral 21 1 read-write NSECP22 Non-secured Peripheral 22 1 read-write NSECP23 Non-secured Peripheral 23 1 read-write NSECP24 Non-secured Peripheral 24 1 read-write NSECP25 Non-secured Peripheral 25 1 read-write NSECP26 Non-secured Peripheral 26 1 read-write NSECP27 Non-secured Peripheral 27 1 read-write NSECP28 Non-secured Peripheral 28 1 read-write NSECP29 Non-secured Peripheral 29 1 read-write NSECP3 Non-secured Peripheral 3 1 read-write NSECP30 Non-secured Peripheral 30 1 read-write NSECP31 Non-secured Peripheral 31 1 read-write NSECP4 Non-secured Peripheral 4 1 read-write NSECP5 Non-secured Peripheral 5 1 read-write NSECP6 Non-secured Peripheral 6 1 read-write NSECP7 Non-secured Peripheral 7 1 read-write NSECP8 Non-secured Peripheral 8 1 read-write NSECP9 Non-secured Peripheral 9 1 read-write SPSELR1 Security Peripheral Select 1 Register 0x2C4 32 read-write n NSECP0 Non-secured Peripheral 0 1 read-write NSECP1 Non-secured Peripheral 1 1 read-write NSECP10 Non-secured Peripheral 10 1 read-write NSECP11 Non-secured Peripheral 11 1 read-write NSECP12 Non-secured Peripheral 12 1 read-write NSECP13 Non-secured Peripheral 13 1 read-write NSECP14 Non-secured Peripheral 14 1 read-write NSECP15 Non-secured Peripheral 15 1 read-write NSECP16 Non-secured Peripheral 16 1 read-write NSECP17 Non-secured Peripheral 17 1 read-write NSECP18 Non-secured Peripheral 18 1 read-write NSECP19 Non-secured Peripheral 19 1 read-write NSECP2 Non-secured Peripheral 2 1 read-write NSECP20 Non-secured Peripheral 20 1 read-write NSECP21 Non-secured Peripheral 21 1 read-write NSECP22 Non-secured Peripheral 22 1 read-write NSECP23 Non-secured Peripheral 23 1 read-write NSECP24 Non-secured Peripheral 24 1 read-write NSECP25 Non-secured Peripheral 25 1 read-write NSECP26 Non-secured Peripheral 26 1 read-write NSECP27 Non-secured Peripheral 27 1 read-write NSECP28 Non-secured Peripheral 28 1 read-write NSECP29 Non-secured Peripheral 29 1 read-write NSECP3 Non-secured Peripheral 3 1 read-write NSECP30 Non-secured Peripheral 30 1 read-write NSECP31 Non-secured Peripheral 31 1 read-write NSECP4 Non-secured Peripheral 4 1 read-write NSECP5 Non-secured Peripheral 5 1 read-write NSECP6 Non-secured Peripheral 6 1 read-write NSECP7 Non-secured Peripheral 7 1 read-write NSECP8 Non-secured Peripheral 8 1 read-write NSECP9 Non-secured Peripheral 9 1 read-write SPSELR2 Security Peripheral Select 1 Register 0x2C8 32 read-write n NSECP0 Non-secured Peripheral 0 1 read-write NSECP1 Non-secured Peripheral 1 1 read-write NSECP10 Non-secured Peripheral 10 1 read-write NSECP11 Non-secured Peripheral 11 1 read-write NSECP12 Non-secured Peripheral 12 1 read-write NSECP13 Non-secured Peripheral 13 1 read-write NSECP14 Non-secured Peripheral 14 1 read-write NSECP15 Non-secured Peripheral 15 1 read-write NSECP16 Non-secured Peripheral 16 1 read-write NSECP17 Non-secured Peripheral 17 1 read-write NSECP18 Non-secured Peripheral 18 1 read-write NSECP19 Non-secured Peripheral 19 1 read-write NSECP2 Non-secured Peripheral 2 1 read-write NSECP20 Non-secured Peripheral 20 1 read-write NSECP21 Non-secured Peripheral 21 1 read-write NSECP22 Non-secured Peripheral 22 1 read-write NSECP23 Non-secured Peripheral 23 1 read-write NSECP24 Non-secured Peripheral 24 1 read-write NSECP25 Non-secured Peripheral 25 1 read-write NSECP26 Non-secured Peripheral 26 1 read-write NSECP27 Non-secured Peripheral 27 1 read-write NSECP28 Non-secured Peripheral 28 1 read-write NSECP29 Non-secured Peripheral 29 1 read-write NSECP3 Non-secured Peripheral 3 1 read-write NSECP30 Non-secured Peripheral 30 1 read-write NSECP31 Non-secured Peripheral 31 1 read-write NSECP4 Non-secured Peripheral 4 1 read-write NSECP5 Non-secured Peripheral 5 1 read-write NSECP6 Non-secured Peripheral 6 1 read-write NSECP7 Non-secured Peripheral 7 1 read-write NSECP8 Non-secured Peripheral 8 1 read-write NSECP9 Non-secured Peripheral 9 1 read-write SPSELR[0] Security Peripheral Select 1 Register 0x580 32 read-write n 0x0 0x0 NSECP0 Non-secured Peripheral 0 1 read-write NSECP1 Non-secured Peripheral 1 1 read-write NSECP10 Non-secured Peripheral 10 1 read-write NSECP11 Non-secured Peripheral 11 1 read-write NSECP12 Non-secured Peripheral 12 1 read-write NSECP13 Non-secured Peripheral 13 1 read-write NSECP14 Non-secured Peripheral 14 1 read-write NSECP15 Non-secured Peripheral 15 1 read-write NSECP16 Non-secured Peripheral 16 1 read-write NSECP17 Non-secured Peripheral 17 1 read-write NSECP18 Non-secured Peripheral 18 1 read-write NSECP19 Non-secured Peripheral 19 1 read-write NSECP2 Non-secured Peripheral 2 1 read-write NSECP20 Non-secured Peripheral 20 1 read-write NSECP21 Non-secured Peripheral 21 1 read-write NSECP22 Non-secured Peripheral 22 1 read-write NSECP23 Non-secured Peripheral 23 1 read-write NSECP24 Non-secured Peripheral 24 1 read-write NSECP25 Non-secured Peripheral 25 1 read-write NSECP26 Non-secured Peripheral 26 1 read-write NSECP27 Non-secured Peripheral 27 1 read-write NSECP28 Non-secured Peripheral 28 1 read-write NSECP29 Non-secured Peripheral 29 1 read-write NSECP3 Non-secured Peripheral 3 1 read-write NSECP30 Non-secured Peripheral 30 1 read-write NSECP31 Non-secured Peripheral 31 1 read-write NSECP4 Non-secured Peripheral 4 1 read-write NSECP5 Non-secured Peripheral 5 1 read-write NSECP6 Non-secured Peripheral 6 1 read-write NSECP7 Non-secured Peripheral 7 1 read-write NSECP8 Non-secured Peripheral 8 1 read-write NSECP9 Non-secured Peripheral 9 1 read-write SPSELR[1] Security Peripheral Select 1 Register 0x844 32 read-write n 0x0 0x0 NSECP0 Non-secured Peripheral 0 1 read-write NSECP1 Non-secured Peripheral 1 1 read-write NSECP10 Non-secured Peripheral 10 1 read-write NSECP11 Non-secured Peripheral 11 1 read-write NSECP12 Non-secured Peripheral 12 1 read-write NSECP13 Non-secured Peripheral 13 1 read-write NSECP14 Non-secured Peripheral 14 1 read-write NSECP15 Non-secured Peripheral 15 1 read-write NSECP16 Non-secured Peripheral 16 1 read-write NSECP17 Non-secured Peripheral 17 1 read-write NSECP18 Non-secured Peripheral 18 1 read-write NSECP19 Non-secured Peripheral 19 1 read-write NSECP2 Non-secured Peripheral 2 1 read-write NSECP20 Non-secured Peripheral 20 1 read-write NSECP21 Non-secured Peripheral 21 1 read-write NSECP22 Non-secured Peripheral 22 1 read-write NSECP23 Non-secured Peripheral 23 1 read-write NSECP24 Non-secured Peripheral 24 1 read-write NSECP25 Non-secured Peripheral 25 1 read-write NSECP26 Non-secured Peripheral 26 1 read-write NSECP27 Non-secured Peripheral 27 1 read-write NSECP28 Non-secured Peripheral 28 1 read-write NSECP29 Non-secured Peripheral 29 1 read-write NSECP3 Non-secured Peripheral 3 1 read-write NSECP30 Non-secured Peripheral 30 1 read-write NSECP31 Non-secured Peripheral 31 1 read-write NSECP4 Non-secured Peripheral 4 1 read-write NSECP5 Non-secured Peripheral 5 1 read-write NSECP6 Non-secured Peripheral 6 1 read-write NSECP7 Non-secured Peripheral 7 1 read-write NSECP8 Non-secured Peripheral 8 1 read-write NSECP9 Non-secured Peripheral 9 1 read-write SPSELR[2] Security Peripheral Select 1 Register 0xB0C 32 read-write n 0x0 0x0 NSECP0 Non-secured Peripheral 0 1 read-write NSECP1 Non-secured Peripheral 1 1 read-write NSECP10 Non-secured Peripheral 10 1 read-write NSECP11 Non-secured Peripheral 11 1 read-write NSECP12 Non-secured Peripheral 12 1 read-write NSECP13 Non-secured Peripheral 13 1 read-write NSECP14 Non-secured Peripheral 14 1 read-write NSECP15 Non-secured Peripheral 15 1 read-write NSECP16 Non-secured Peripheral 16 1 read-write NSECP17 Non-secured Peripheral 17 1 read-write NSECP18 Non-secured Peripheral 18 1 read-write NSECP19 Non-secured Peripheral 19 1 read-write NSECP2 Non-secured Peripheral 2 1 read-write NSECP20 Non-secured Peripheral 20 1 read-write NSECP21 Non-secured Peripheral 21 1 read-write NSECP22 Non-secured Peripheral 22 1 read-write NSECP23 Non-secured Peripheral 23 1 read-write NSECP24 Non-secured Peripheral 24 1 read-write NSECP25 Non-secured Peripheral 25 1 read-write NSECP26 Non-secured Peripheral 26 1 read-write NSECP27 Non-secured Peripheral 27 1 read-write NSECP28 Non-secured Peripheral 28 1 read-write NSECP29 Non-secured Peripheral 29 1 read-write NSECP3 Non-secured Peripheral 3 1 read-write NSECP30 Non-secured Peripheral 30 1 read-write NSECP31 Non-secured Peripheral 31 1 read-write NSECP4 Non-secured Peripheral 4 1 read-write NSECP5 Non-secured Peripheral 5 1 read-write NSECP6 Non-secured Peripheral 6 1 read-write NSECP7 Non-secured Peripheral 7 1 read-write NSECP8 Non-secured Peripheral 8 1 read-write NSECP9 Non-secured Peripheral 9 1 read-write SRTSR0 Security Region Top Slave 1 Register 0x284 32 read-write n SRTOP0 HSELx Security Region Top 0 4 read-write SRTOP1 HSELx Security Region Top 4 4 read-write SRTOP2 HSELx Security Region Top 8 4 read-write SRTOP3 HSELx Security Region Top 12 4 read-write SRTOP4 HSELx Security Region Top 16 4 read-write SRTOP5 HSELx Security Region Top 20 4 read-write SRTOP6 HSELx Security Region Top 24 4 read-write SRTOP7 HSELx Security Region Top 28 4 read-write SRTSR1 Security Region Top Slave 1 Register 0x288 32 read-write n SRTOP0 HSELx Security Region Top 0 4 read-write SRTOP1 HSELx Security Region Top 4 4 read-write SRTOP2 HSELx Security Region Top 8 4 read-write SRTOP3 HSELx Security Region Top 12 4 read-write SRTOP4 HSELx Security Region Top 16 4 read-write SRTOP5 HSELx Security Region Top 20 4 read-write SRTOP6 HSELx Security Region Top 24 4 read-write SRTOP7 HSELx Security Region Top 28 4 read-write SRTSR10 Security Region Top Slave 1 Register 0x2AC 32 read-write n SRTOP0 HSELx Security Region Top 0 4 read-write SRTOP1 HSELx Security Region Top 4 4 read-write SRTOP2 HSELx Security Region Top 8 4 read-write SRTOP3 HSELx Security Region Top 12 4 read-write SRTOP4 HSELx Security Region Top 16 4 read-write SRTOP5 HSELx Security Region Top 20 4 read-write SRTOP6 HSELx Security Region Top 24 4 read-write SRTOP7 HSELx Security Region Top 28 4 read-write SRTSR11 Security Region Top Slave 1 Register 0x2B0 32 read-write n SRTOP0 HSELx Security Region Top 0 4 read-write SRTOP1 HSELx Security Region Top 4 4 read-write SRTOP2 HSELx Security Region Top 8 4 read-write SRTOP3 HSELx Security Region Top 12 4 read-write SRTOP4 HSELx Security Region Top 16 4 read-write SRTOP5 HSELx Security Region Top 20 4 read-write SRTOP6 HSELx Security Region Top 24 4 read-write SRTOP7 HSELx Security Region Top 28 4 read-write SRTSR2 Security Region Top Slave 1 Register 0x28C 32 read-write n SRTOP0 HSELx Security Region Top 0 4 read-write SRTOP1 HSELx Security Region Top 4 4 read-write SRTOP2 HSELx Security Region Top 8 4 read-write SRTOP3 HSELx Security Region Top 12 4 read-write SRTOP4 HSELx Security Region Top 16 4 read-write SRTOP5 HSELx Security Region Top 20 4 read-write SRTOP6 HSELx Security Region Top 24 4 read-write SRTOP7 HSELx Security Region Top 28 4 read-write SRTSR3 Security Region Top Slave 1 Register 0x290 32 read-write n SRTOP0 HSELx Security Region Top 0 4 read-write SRTOP1 HSELx Security Region Top 4 4 read-write SRTOP2 HSELx Security Region Top 8 4 read-write SRTOP3 HSELx Security Region Top 12 4 read-write SRTOP4 HSELx Security Region Top 16 4 read-write SRTOP5 HSELx Security Region Top 20 4 read-write SRTOP6 HSELx Security Region Top 24 4 read-write SRTOP7 HSELx Security Region Top 28 4 read-write SRTSR4 Security Region Top Slave 1 Register 0x294 32 read-write n SRTOP0 HSELx Security Region Top 0 4 read-write SRTOP1 HSELx Security Region Top 4 4 read-write SRTOP2 HSELx Security Region Top 8 4 read-write SRTOP3 HSELx Security Region Top 12 4 read-write SRTOP4 HSELx Security Region Top 16 4 read-write SRTOP5 HSELx Security Region Top 20 4 read-write SRTOP6 HSELx Security Region Top 24 4 read-write SRTOP7 HSELx Security Region Top 28 4 read-write SRTSR5 Security Region Top Slave 1 Register 0x298 32 read-write n SRTOP0 HSELx Security Region Top 0 4 read-write SRTOP1 HSELx Security Region Top 4 4 read-write SRTOP2 HSELx Security Region Top 8 4 read-write SRTOP3 HSELx Security Region Top 12 4 read-write SRTOP4 HSELx Security Region Top 16 4 read-write SRTOP5 HSELx Security Region Top 20 4 read-write SRTOP6 HSELx Security Region Top 24 4 read-write SRTOP7 HSELx Security Region Top 28 4 read-write SRTSR6 Security Region Top Slave 1 Register 0x29C 32 read-write n SRTOP0 HSELx Security Region Top 0 4 read-write SRTOP1 HSELx Security Region Top 4 4 read-write SRTOP2 HSELx Security Region Top 8 4 read-write SRTOP3 HSELx Security Region Top 12 4 read-write SRTOP4 HSELx Security Region Top 16 4 read-write SRTOP5 HSELx Security Region Top 20 4 read-write SRTOP6 HSELx Security Region Top 24 4 read-write SRTOP7 HSELx Security Region Top 28 4 read-write SRTSR7 Security Region Top Slave 1 Register 0x2A0 32 read-write n SRTOP0 HSELx Security Region Top 0 4 read-write SRTOP1 HSELx Security Region Top 4 4 read-write SRTOP2 HSELx Security Region Top 8 4 read-write SRTOP3 HSELx Security Region Top 12 4 read-write SRTOP4 HSELx Security Region Top 16 4 read-write SRTOP5 HSELx Security Region Top 20 4 read-write SRTOP6 HSELx Security Region Top 24 4 read-write SRTOP7 HSELx Security Region Top 28 4 read-write SRTSR8 Security Region Top Slave 1 Register 0x2A4 32 read-write n SRTOP0 HSELx Security Region Top 0 4 read-write SRTOP1 HSELx Security Region Top 4 4 read-write SRTOP2 HSELx Security Region Top 8 4 read-write SRTOP3 HSELx Security Region Top 12 4 read-write SRTOP4 HSELx Security Region Top 16 4 read-write SRTOP5 HSELx Security Region Top 20 4 read-write SRTOP6 HSELx Security Region Top 24 4 read-write SRTOP7 HSELx Security Region Top 28 4 read-write SRTSR9 Security Region Top Slave 1 Register 0x2A8 32 read-write n SRTOP0 HSELx Security Region Top 0 4 read-write SRTOP1 HSELx Security Region Top 4 4 read-write SRTOP2 HSELx Security Region Top 8 4 read-write SRTOP3 HSELx Security Region Top 12 4 read-write SRTOP4 HSELx Security Region Top 16 4 read-write SRTOP5 HSELx Security Region Top 20 4 read-write SRTOP6 HSELx Security Region Top 24 4 read-write SRTOP7 HSELx Security Region Top 28 4 read-write SRTSR[0] Security Region Top Slave 1 Register 0x508 32 read-write n 0x0 0x0 SRTOP0 HSELx Security Region Top 0 4 read-write SRTOP1 HSELx Security Region Top 4 4 read-write SRTOP2 HSELx Security Region Top 8 4 read-write SRTOP3 HSELx Security Region Top 12 4 read-write SRTOP4 HSELx Security Region Top 16 4 read-write SRTOP5 HSELx Security Region Top 20 4 read-write SRTOP6 HSELx Security Region Top 24 4 read-write SRTOP7 HSELx Security Region Top 28 4 read-write SRTSR[10] Security Region Top Slave 1 Register 0x1F0C 32 read-write n 0x0 0x0 SRTOP0 HSELx Security Region Top 0 4 read-write SRTOP1 HSELx Security Region Top 4 4 read-write SRTOP2 HSELx Security Region Top 8 4 read-write SRTOP3 HSELx Security Region Top 12 4 read-write SRTOP4 HSELx Security Region Top 16 4 read-write SRTOP5 HSELx Security Region Top 20 4 read-write SRTOP6 HSELx Security Region Top 24 4 read-write SRTOP7 HSELx Security Region Top 28 4 read-write SRTSR[11] Security Region Top Slave 1 Register 0x21BC 32 read-write n 0x0 0x0 SRTOP0 HSELx Security Region Top 0 4 read-write SRTOP1 HSELx Security Region Top 4 4 read-write SRTOP2 HSELx Security Region Top 8 4 read-write SRTOP3 HSELx Security Region Top 12 4 read-write SRTOP4 HSELx Security Region Top 16 4 read-write SRTOP5 HSELx Security Region Top 20 4 read-write SRTOP6 HSELx Security Region Top 24 4 read-write SRTOP7 HSELx Security Region Top 28 4 read-write SRTSR[1] Security Region Top Slave 1 Register 0x790 32 read-write n 0x0 0x0 SRTOP0 HSELx Security Region Top 0 4 read-write SRTOP1 HSELx Security Region Top 4 4 read-write SRTOP2 HSELx Security Region Top 8 4 read-write SRTOP3 HSELx Security Region Top 12 4 read-write SRTOP4 HSELx Security Region Top 16 4 read-write SRTOP5 HSELx Security Region Top 20 4 read-write SRTOP6 HSELx Security Region Top 24 4 read-write SRTOP7 HSELx Security Region Top 28 4 read-write SRTSR[2] Security Region Top Slave 1 Register 0xA1C 32 read-write n 0x0 0x0 SRTOP0 HSELx Security Region Top 0 4 read-write SRTOP1 HSELx Security Region Top 4 4 read-write SRTOP2 HSELx Security Region Top 8 4 read-write SRTOP3 HSELx Security Region Top 12 4 read-write SRTOP4 HSELx Security Region Top 16 4 read-write SRTOP5 HSELx Security Region Top 20 4 read-write SRTOP6 HSELx Security Region Top 24 4 read-write SRTOP7 HSELx Security Region Top 28 4 read-write SRTSR[3] Security Region Top Slave 1 Register 0xCAC 32 read-write n 0x0 0x0 SRTOP0 HSELx Security Region Top 0 4 read-write SRTOP1 HSELx Security Region Top 4 4 read-write SRTOP2 HSELx Security Region Top 8 4 read-write SRTOP3 HSELx Security Region Top 12 4 read-write SRTOP4 HSELx Security Region Top 16 4 read-write SRTOP5 HSELx Security Region Top 20 4 read-write SRTOP6 HSELx Security Region Top 24 4 read-write SRTOP7 HSELx Security Region Top 28 4 read-write SRTSR[4] Security Region Top Slave 1 Register 0xF40 32 read-write n 0x0 0x0 SRTOP0 HSELx Security Region Top 0 4 read-write SRTOP1 HSELx Security Region Top 4 4 read-write SRTOP2 HSELx Security Region Top 8 4 read-write SRTOP3 HSELx Security Region Top 12 4 read-write SRTOP4 HSELx Security Region Top 16 4 read-write SRTOP5 HSELx Security Region Top 20 4 read-write SRTOP6 HSELx Security Region Top 24 4 read-write SRTOP7 HSELx Security Region Top 28 4 read-write SRTSR[5] Security Region Top Slave 1 Register 0x11D8 32 read-write n 0x0 0x0 SRTOP0 HSELx Security Region Top 0 4 read-write SRTOP1 HSELx Security Region Top 4 4 read-write SRTOP2 HSELx Security Region Top 8 4 read-write SRTOP3 HSELx Security Region Top 12 4 read-write SRTOP4 HSELx Security Region Top 16 4 read-write SRTOP5 HSELx Security Region Top 20 4 read-write SRTOP6 HSELx Security Region Top 24 4 read-write SRTOP7 HSELx Security Region Top 28 4 read-write SRTSR[6] Security Region Top Slave 1 Register 0x1474 32 read-write n 0x0 0x0 SRTOP0 HSELx Security Region Top 0 4 read-write SRTOP1 HSELx Security Region Top 4 4 read-write SRTOP2 HSELx Security Region Top 8 4 read-write SRTOP3 HSELx Security Region Top 12 4 read-write SRTOP4 HSELx Security Region Top 16 4 read-write SRTOP5 HSELx Security Region Top 20 4 read-write SRTOP6 HSELx Security Region Top 24 4 read-write SRTOP7 HSELx Security Region Top 28 4 read-write SRTSR[7] Security Region Top Slave 1 Register 0x1714 32 read-write n 0x0 0x0 SRTOP0 HSELx Security Region Top 0 4 read-write SRTOP1 HSELx Security Region Top 4 4 read-write SRTOP2 HSELx Security Region Top 8 4 read-write SRTOP3 HSELx Security Region Top 12 4 read-write SRTOP4 HSELx Security Region Top 16 4 read-write SRTOP5 HSELx Security Region Top 20 4 read-write SRTOP6 HSELx Security Region Top 24 4 read-write SRTOP7 HSELx Security Region Top 28 4 read-write SRTSR[8] Security Region Top Slave 1 Register 0x19B8 32 read-write n 0x0 0x0 SRTOP0 HSELx Security Region Top 0 4 read-write SRTOP1 HSELx Security Region Top 4 4 read-write SRTOP2 HSELx Security Region Top 8 4 read-write SRTOP3 HSELx Security Region Top 12 4 read-write SRTOP4 HSELx Security Region Top 16 4 read-write SRTOP5 HSELx Security Region Top 20 4 read-write SRTOP6 HSELx Security Region Top 24 4 read-write SRTOP7 HSELx Security Region Top 28 4 read-write SRTSR[9] Security Region Top Slave 1 Register 0x1C60 32 read-write n 0x0 0x0 SRTOP0 HSELx Security Region Top 0 4 read-write SRTOP1 HSELx Security Region Top 4 4 read-write SRTOP2 HSELx Security Region Top 8 4 read-write SRTOP3 HSELx Security Region Top 12 4 read-write SRTOP4 HSELx Security Region Top 16 4 read-write SRTOP5 HSELx Security Region Top 20 4 read-write SRTOP6 HSELx Security Region Top 24 4 read-write SRTOP7 HSELx Security Region Top 28 4 read-write SSR0 Security Slave 0 Register 0x200 32 read-write n LANSECH0 Low Area Non-secured in HSELx Security Region 0 1 read-write LANSECH1 Low Area Non-secured in HSELx Security Region 1 1 read-write LANSECH2 Low Area Non-secured in HSELx Security Region 2 1 read-write LANSECH3 Low Area Non-secured in HSELx Security Region 3 1 read-write LANSECH4 Low Area Non-secured in HSELx Security Region 4 1 read-write LANSECH5 Low Area Non-secured in HSELx Security Region 5 1 read-write LANSECH6 Low Area Non-secured in HSELx Security Region 6 1 read-write LANSECH7 Low Area Non-secured in HSELx Security Region 7 1 read-write RDNSECH0 Read Non-secured for HSELx Security Region 8 1 read-write RDNSECH1 Read Non-secured for HSELx Security Region 9 1 read-write RDNSECH2 Read Non-secured for HSELx Security Region 10 1 read-write RDNSECH3 Read Non-secured for HSELx Security Region 11 1 read-write RDNSECH4 Read Non-secured for HSELx Security Region 12 1 read-write RDNSECH5 Read Non-secured for HSELx Security Region 13 1 read-write RDNSECH6 Read Non-secured for HSELx Security Region 14 1 read-write RDNSECH7 Read Non-secured for HSELx Security Region 15 1 read-write WRNSECH0 Write Non-secured for HSELx Security Region 16 1 read-write WRNSECH1 Write Non-secured for HSELx Security Region 17 1 read-write WRNSECH2 Write Non-secured for HSELx Security Region 18 1 read-write WRNSECH3 Write Non-secured for HSELx Security Region 19 1 read-write WRNSECH4 Write Non-secured for HSELx Security Region 20 1 read-write WRNSECH5 Write Non-secured for HSELx Security Region 21 1 read-write WRNSECH6 Write Non-secured for HSELx Security Region 22 1 read-write WRNSECH7 Write Non-secured for HSELx Security Region 23 1 read-write SSR1 Security Slave 0 Register 0x204 32 read-write n LANSECH0 Low Area Non-secured in HSELx Security Region 0 1 read-write LANSECH1 Low Area Non-secured in HSELx Security Region 1 1 read-write LANSECH2 Low Area Non-secured in HSELx Security Region 2 1 read-write LANSECH3 Low Area Non-secured in HSELx Security Region 3 1 read-write LANSECH4 Low Area Non-secured in HSELx Security Region 4 1 read-write LANSECH5 Low Area Non-secured in HSELx Security Region 5 1 read-write LANSECH6 Low Area Non-secured in HSELx Security Region 6 1 read-write LANSECH7 Low Area Non-secured in HSELx Security Region 7 1 read-write RDNSECH0 Read Non-secured for HSELx Security Region 8 1 read-write RDNSECH1 Read Non-secured for HSELx Security Region 9 1 read-write RDNSECH2 Read Non-secured for HSELx Security Region 10 1 read-write RDNSECH3 Read Non-secured for HSELx Security Region 11 1 read-write RDNSECH4 Read Non-secured for HSELx Security Region 12 1 read-write RDNSECH5 Read Non-secured for HSELx Security Region 13 1 read-write RDNSECH6 Read Non-secured for HSELx Security Region 14 1 read-write RDNSECH7 Read Non-secured for HSELx Security Region 15 1 read-write WRNSECH0 Write Non-secured for HSELx Security Region 16 1 read-write WRNSECH1 Write Non-secured for HSELx Security Region 17 1 read-write WRNSECH2 Write Non-secured for HSELx Security Region 18 1 read-write WRNSECH3 Write Non-secured for HSELx Security Region 19 1 read-write WRNSECH4 Write Non-secured for HSELx Security Region 20 1 read-write WRNSECH5 Write Non-secured for HSELx Security Region 21 1 read-write WRNSECH6 Write Non-secured for HSELx Security Region 22 1 read-write WRNSECH7 Write Non-secured for HSELx Security Region 23 1 read-write SSR10 Security Slave 0 Register 0x228 32 read-write n LANSECH0 Low Area Non-secured in HSELx Security Region 0 1 read-write LANSECH1 Low Area Non-secured in HSELx Security Region 1 1 read-write LANSECH2 Low Area Non-secured in HSELx Security Region 2 1 read-write LANSECH3 Low Area Non-secured in HSELx Security Region 3 1 read-write LANSECH4 Low Area Non-secured in HSELx Security Region 4 1 read-write LANSECH5 Low Area Non-secured in HSELx Security Region 5 1 read-write LANSECH6 Low Area Non-secured in HSELx Security Region 6 1 read-write LANSECH7 Low Area Non-secured in HSELx Security Region 7 1 read-write RDNSECH0 Read Non-secured for HSELx Security Region 8 1 read-write RDNSECH1 Read Non-secured for HSELx Security Region 9 1 read-write RDNSECH2 Read Non-secured for HSELx Security Region 10 1 read-write RDNSECH3 Read Non-secured for HSELx Security Region 11 1 read-write RDNSECH4 Read Non-secured for HSELx Security Region 12 1 read-write RDNSECH5 Read Non-secured for HSELx Security Region 13 1 read-write RDNSECH6 Read Non-secured for HSELx Security Region 14 1 read-write RDNSECH7 Read Non-secured for HSELx Security Region 15 1 read-write WRNSECH0 Write Non-secured for HSELx Security Region 16 1 read-write WRNSECH1 Write Non-secured for HSELx Security Region 17 1 read-write WRNSECH2 Write Non-secured for HSELx Security Region 18 1 read-write WRNSECH3 Write Non-secured for HSELx Security Region 19 1 read-write WRNSECH4 Write Non-secured for HSELx Security Region 20 1 read-write WRNSECH5 Write Non-secured for HSELx Security Region 21 1 read-write WRNSECH6 Write Non-secured for HSELx Security Region 22 1 read-write WRNSECH7 Write Non-secured for HSELx Security Region 23 1 read-write SSR11 Security Slave 0 Register 0x22C 32 read-write n LANSECH0 Low Area Non-secured in HSELx Security Region 0 1 read-write LANSECH1 Low Area Non-secured in HSELx Security Region 1 1 read-write LANSECH2 Low Area Non-secured in HSELx Security Region 2 1 read-write LANSECH3 Low Area Non-secured in HSELx Security Region 3 1 read-write LANSECH4 Low Area Non-secured in HSELx Security Region 4 1 read-write LANSECH5 Low Area Non-secured in HSELx Security Region 5 1 read-write LANSECH6 Low Area Non-secured in HSELx Security Region 6 1 read-write LANSECH7 Low Area Non-secured in HSELx Security Region 7 1 read-write RDNSECH0 Read Non-secured for HSELx Security Region 8 1 read-write RDNSECH1 Read Non-secured for HSELx Security Region 9 1 read-write RDNSECH2 Read Non-secured for HSELx Security Region 10 1 read-write RDNSECH3 Read Non-secured for HSELx Security Region 11 1 read-write RDNSECH4 Read Non-secured for HSELx Security Region 12 1 read-write RDNSECH5 Read Non-secured for HSELx Security Region 13 1 read-write RDNSECH6 Read Non-secured for HSELx Security Region 14 1 read-write RDNSECH7 Read Non-secured for HSELx Security Region 15 1 read-write WRNSECH0 Write Non-secured for HSELx Security Region 16 1 read-write WRNSECH1 Write Non-secured for HSELx Security Region 17 1 read-write WRNSECH2 Write Non-secured for HSELx Security Region 18 1 read-write WRNSECH3 Write Non-secured for HSELx Security Region 19 1 read-write WRNSECH4 Write Non-secured for HSELx Security Region 20 1 read-write WRNSECH5 Write Non-secured for HSELx Security Region 21 1 read-write WRNSECH6 Write Non-secured for HSELx Security Region 22 1 read-write WRNSECH7 Write Non-secured for HSELx Security Region 23 1 read-write SSR12 Security Slave 0 Register 0x230 32 read-write n LANSECH0 Low Area Non-secured in HSELx Security Region 0 1 read-write LANSECH1 Low Area Non-secured in HSELx Security Region 1 1 read-write LANSECH2 Low Area Non-secured in HSELx Security Region 2 1 read-write LANSECH3 Low Area Non-secured in HSELx Security Region 3 1 read-write LANSECH4 Low Area Non-secured in HSELx Security Region 4 1 read-write LANSECH5 Low Area Non-secured in HSELx Security Region 5 1 read-write LANSECH6 Low Area Non-secured in HSELx Security Region 6 1 read-write LANSECH7 Low Area Non-secured in HSELx Security Region 7 1 read-write RDNSECH0 Read Non-secured for HSELx Security Region 8 1 read-write RDNSECH1 Read Non-secured for HSELx Security Region 9 1 read-write RDNSECH2 Read Non-secured for HSELx Security Region 10 1 read-write RDNSECH3 Read Non-secured for HSELx Security Region 11 1 read-write RDNSECH4 Read Non-secured for HSELx Security Region 12 1 read-write RDNSECH5 Read Non-secured for HSELx Security Region 13 1 read-write RDNSECH6 Read Non-secured for HSELx Security Region 14 1 read-write RDNSECH7 Read Non-secured for HSELx Security Region 15 1 read-write WRNSECH0 Write Non-secured for HSELx Security Region 16 1 read-write WRNSECH1 Write Non-secured for HSELx Security Region 17 1 read-write WRNSECH2 Write Non-secured for HSELx Security Region 18 1 read-write WRNSECH3 Write Non-secured for HSELx Security Region 19 1 read-write WRNSECH4 Write Non-secured for HSELx Security Region 20 1 read-write WRNSECH5 Write Non-secured for HSELx Security Region 21 1 read-write WRNSECH6 Write Non-secured for HSELx Security Region 22 1 read-write WRNSECH7 Write Non-secured for HSELx Security Region 23 1 read-write SSR2 Security Slave 0 Register 0x208 32 read-write n LANSECH0 Low Area Non-secured in HSELx Security Region 0 1 read-write LANSECH1 Low Area Non-secured in HSELx Security Region 1 1 read-write LANSECH2 Low Area Non-secured in HSELx Security Region 2 1 read-write LANSECH3 Low Area Non-secured in HSELx Security Region 3 1 read-write LANSECH4 Low Area Non-secured in HSELx Security Region 4 1 read-write LANSECH5 Low Area Non-secured in HSELx Security Region 5 1 read-write LANSECH6 Low Area Non-secured in HSELx Security Region 6 1 read-write LANSECH7 Low Area Non-secured in HSELx Security Region 7 1 read-write RDNSECH0 Read Non-secured for HSELx Security Region 8 1 read-write RDNSECH1 Read Non-secured for HSELx Security Region 9 1 read-write RDNSECH2 Read Non-secured for HSELx Security Region 10 1 read-write RDNSECH3 Read Non-secured for HSELx Security Region 11 1 read-write RDNSECH4 Read Non-secured for HSELx Security Region 12 1 read-write RDNSECH5 Read Non-secured for HSELx Security Region 13 1 read-write RDNSECH6 Read Non-secured for HSELx Security Region 14 1 read-write RDNSECH7 Read Non-secured for HSELx Security Region 15 1 read-write WRNSECH0 Write Non-secured for HSELx Security Region 16 1 read-write WRNSECH1 Write Non-secured for HSELx Security Region 17 1 read-write WRNSECH2 Write Non-secured for HSELx Security Region 18 1 read-write WRNSECH3 Write Non-secured for HSELx Security Region 19 1 read-write WRNSECH4 Write Non-secured for HSELx Security Region 20 1 read-write WRNSECH5 Write Non-secured for HSELx Security Region 21 1 read-write WRNSECH6 Write Non-secured for HSELx Security Region 22 1 read-write WRNSECH7 Write Non-secured for HSELx Security Region 23 1 read-write SSR3 Security Slave 0 Register 0x20C 32 read-write n LANSECH0 Low Area Non-secured in HSELx Security Region 0 1 read-write LANSECH1 Low Area Non-secured in HSELx Security Region 1 1 read-write LANSECH2 Low Area Non-secured in HSELx Security Region 2 1 read-write LANSECH3 Low Area Non-secured in HSELx Security Region 3 1 read-write LANSECH4 Low Area Non-secured in HSELx Security Region 4 1 read-write LANSECH5 Low Area Non-secured in HSELx Security Region 5 1 read-write LANSECH6 Low Area Non-secured in HSELx Security Region 6 1 read-write LANSECH7 Low Area Non-secured in HSELx Security Region 7 1 read-write RDNSECH0 Read Non-secured for HSELx Security Region 8 1 read-write RDNSECH1 Read Non-secured for HSELx Security Region 9 1 read-write RDNSECH2 Read Non-secured for HSELx Security Region 10 1 read-write RDNSECH3 Read Non-secured for HSELx Security Region 11 1 read-write RDNSECH4 Read Non-secured for HSELx Security Region 12 1 read-write RDNSECH5 Read Non-secured for HSELx Security Region 13 1 read-write RDNSECH6 Read Non-secured for HSELx Security Region 14 1 read-write RDNSECH7 Read Non-secured for HSELx Security Region 15 1 read-write WRNSECH0 Write Non-secured for HSELx Security Region 16 1 read-write WRNSECH1 Write Non-secured for HSELx Security Region 17 1 read-write WRNSECH2 Write Non-secured for HSELx Security Region 18 1 read-write WRNSECH3 Write Non-secured for HSELx Security Region 19 1 read-write WRNSECH4 Write Non-secured for HSELx Security Region 20 1 read-write WRNSECH5 Write Non-secured for HSELx Security Region 21 1 read-write WRNSECH6 Write Non-secured for HSELx Security Region 22 1 read-write WRNSECH7 Write Non-secured for HSELx Security Region 23 1 read-write SSR4 Security Slave 0 Register 0x210 32 read-write n LANSECH0 Low Area Non-secured in HSELx Security Region 0 1 read-write LANSECH1 Low Area Non-secured in HSELx Security Region 1 1 read-write LANSECH2 Low Area Non-secured in HSELx Security Region 2 1 read-write LANSECH3 Low Area Non-secured in HSELx Security Region 3 1 read-write LANSECH4 Low Area Non-secured in HSELx Security Region 4 1 read-write LANSECH5 Low Area Non-secured in HSELx Security Region 5 1 read-write LANSECH6 Low Area Non-secured in HSELx Security Region 6 1 read-write LANSECH7 Low Area Non-secured in HSELx Security Region 7 1 read-write RDNSECH0 Read Non-secured for HSELx Security Region 8 1 read-write RDNSECH1 Read Non-secured for HSELx Security Region 9 1 read-write RDNSECH2 Read Non-secured for HSELx Security Region 10 1 read-write RDNSECH3 Read Non-secured for HSELx Security Region 11 1 read-write RDNSECH4 Read Non-secured for HSELx Security Region 12 1 read-write RDNSECH5 Read Non-secured for HSELx Security Region 13 1 read-write RDNSECH6 Read Non-secured for HSELx Security Region 14 1 read-write RDNSECH7 Read Non-secured for HSELx Security Region 15 1 read-write WRNSECH0 Write Non-secured for HSELx Security Region 16 1 read-write WRNSECH1 Write Non-secured for HSELx Security Region 17 1 read-write WRNSECH2 Write Non-secured for HSELx Security Region 18 1 read-write WRNSECH3 Write Non-secured for HSELx Security Region 19 1 read-write WRNSECH4 Write Non-secured for HSELx Security Region 20 1 read-write WRNSECH5 Write Non-secured for HSELx Security Region 21 1 read-write WRNSECH6 Write Non-secured for HSELx Security Region 22 1 read-write WRNSECH7 Write Non-secured for HSELx Security Region 23 1 read-write SSR5 Security Slave 0 Register 0x214 32 read-write n LANSECH0 Low Area Non-secured in HSELx Security Region 0 1 read-write LANSECH1 Low Area Non-secured in HSELx Security Region 1 1 read-write LANSECH2 Low Area Non-secured in HSELx Security Region 2 1 read-write LANSECH3 Low Area Non-secured in HSELx Security Region 3 1 read-write LANSECH4 Low Area Non-secured in HSELx Security Region 4 1 read-write LANSECH5 Low Area Non-secured in HSELx Security Region 5 1 read-write LANSECH6 Low Area Non-secured in HSELx Security Region 6 1 read-write LANSECH7 Low Area Non-secured in HSELx Security Region 7 1 read-write RDNSECH0 Read Non-secured for HSELx Security Region 8 1 read-write RDNSECH1 Read Non-secured for HSELx Security Region 9 1 read-write RDNSECH2 Read Non-secured for HSELx Security Region 10 1 read-write RDNSECH3 Read Non-secured for HSELx Security Region 11 1 read-write RDNSECH4 Read Non-secured for HSELx Security Region 12 1 read-write RDNSECH5 Read Non-secured for HSELx Security Region 13 1 read-write RDNSECH6 Read Non-secured for HSELx Security Region 14 1 read-write RDNSECH7 Read Non-secured for HSELx Security Region 15 1 read-write WRNSECH0 Write Non-secured for HSELx Security Region 16 1 read-write WRNSECH1 Write Non-secured for HSELx Security Region 17 1 read-write WRNSECH2 Write Non-secured for HSELx Security Region 18 1 read-write WRNSECH3 Write Non-secured for HSELx Security Region 19 1 read-write WRNSECH4 Write Non-secured for HSELx Security Region 20 1 read-write WRNSECH5 Write Non-secured for HSELx Security Region 21 1 read-write WRNSECH6 Write Non-secured for HSELx Security Region 22 1 read-write WRNSECH7 Write Non-secured for HSELx Security Region 23 1 read-write SSR6 Security Slave 0 Register 0x218 32 read-write n LANSECH0 Low Area Non-secured in HSELx Security Region 0 1 read-write LANSECH1 Low Area Non-secured in HSELx Security Region 1 1 read-write LANSECH2 Low Area Non-secured in HSELx Security Region 2 1 read-write LANSECH3 Low Area Non-secured in HSELx Security Region 3 1 read-write LANSECH4 Low Area Non-secured in HSELx Security Region 4 1 read-write LANSECH5 Low Area Non-secured in HSELx Security Region 5 1 read-write LANSECH6 Low Area Non-secured in HSELx Security Region 6 1 read-write LANSECH7 Low Area Non-secured in HSELx Security Region 7 1 read-write RDNSECH0 Read Non-secured for HSELx Security Region 8 1 read-write RDNSECH1 Read Non-secured for HSELx Security Region 9 1 read-write RDNSECH2 Read Non-secured for HSELx Security Region 10 1 read-write RDNSECH3 Read Non-secured for HSELx Security Region 11 1 read-write RDNSECH4 Read Non-secured for HSELx Security Region 12 1 read-write RDNSECH5 Read Non-secured for HSELx Security Region 13 1 read-write RDNSECH6 Read Non-secured for HSELx Security Region 14 1 read-write RDNSECH7 Read Non-secured for HSELx Security Region 15 1 read-write WRNSECH0 Write Non-secured for HSELx Security Region 16 1 read-write WRNSECH1 Write Non-secured for HSELx Security Region 17 1 read-write WRNSECH2 Write Non-secured for HSELx Security Region 18 1 read-write WRNSECH3 Write Non-secured for HSELx Security Region 19 1 read-write WRNSECH4 Write Non-secured for HSELx Security Region 20 1 read-write WRNSECH5 Write Non-secured for HSELx Security Region 21 1 read-write WRNSECH6 Write Non-secured for HSELx Security Region 22 1 read-write WRNSECH7 Write Non-secured for HSELx Security Region 23 1 read-write SSR7 Security Slave 0 Register 0x21C 32 read-write n LANSECH0 Low Area Non-secured in HSELx Security Region 0 1 read-write LANSECH1 Low Area Non-secured in HSELx Security Region 1 1 read-write LANSECH2 Low Area Non-secured in HSELx Security Region 2 1 read-write LANSECH3 Low Area Non-secured in HSELx Security Region 3 1 read-write LANSECH4 Low Area Non-secured in HSELx Security Region 4 1 read-write LANSECH5 Low Area Non-secured in HSELx Security Region 5 1 read-write LANSECH6 Low Area Non-secured in HSELx Security Region 6 1 read-write LANSECH7 Low Area Non-secured in HSELx Security Region 7 1 read-write RDNSECH0 Read Non-secured for HSELx Security Region 8 1 read-write RDNSECH1 Read Non-secured for HSELx Security Region 9 1 read-write RDNSECH2 Read Non-secured for HSELx Security Region 10 1 read-write RDNSECH3 Read Non-secured for HSELx Security Region 11 1 read-write RDNSECH4 Read Non-secured for HSELx Security Region 12 1 read-write RDNSECH5 Read Non-secured for HSELx Security Region 13 1 read-write RDNSECH6 Read Non-secured for HSELx Security Region 14 1 read-write RDNSECH7 Read Non-secured for HSELx Security Region 15 1 read-write WRNSECH0 Write Non-secured for HSELx Security Region 16 1 read-write WRNSECH1 Write Non-secured for HSELx Security Region 17 1 read-write WRNSECH2 Write Non-secured for HSELx Security Region 18 1 read-write WRNSECH3 Write Non-secured for HSELx Security Region 19 1 read-write WRNSECH4 Write Non-secured for HSELx Security Region 20 1 read-write WRNSECH5 Write Non-secured for HSELx Security Region 21 1 read-write WRNSECH6 Write Non-secured for HSELx Security Region 22 1 read-write WRNSECH7 Write Non-secured for HSELx Security Region 23 1 read-write SSR8 Security Slave 0 Register 0x220 32 read-write n LANSECH0 Low Area Non-secured in HSELx Security Region 0 1 read-write LANSECH1 Low Area Non-secured in HSELx Security Region 1 1 read-write LANSECH2 Low Area Non-secured in HSELx Security Region 2 1 read-write LANSECH3 Low Area Non-secured in HSELx Security Region 3 1 read-write LANSECH4 Low Area Non-secured in HSELx Security Region 4 1 read-write LANSECH5 Low Area Non-secured in HSELx Security Region 5 1 read-write LANSECH6 Low Area Non-secured in HSELx Security Region 6 1 read-write LANSECH7 Low Area Non-secured in HSELx Security Region 7 1 read-write RDNSECH0 Read Non-secured for HSELx Security Region 8 1 read-write RDNSECH1 Read Non-secured for HSELx Security Region 9 1 read-write RDNSECH2 Read Non-secured for HSELx Security Region 10 1 read-write RDNSECH3 Read Non-secured for HSELx Security Region 11 1 read-write RDNSECH4 Read Non-secured for HSELx Security Region 12 1 read-write RDNSECH5 Read Non-secured for HSELx Security Region 13 1 read-write RDNSECH6 Read Non-secured for HSELx Security Region 14 1 read-write RDNSECH7 Read Non-secured for HSELx Security Region 15 1 read-write WRNSECH0 Write Non-secured for HSELx Security Region 16 1 read-write WRNSECH1 Write Non-secured for HSELx Security Region 17 1 read-write WRNSECH2 Write Non-secured for HSELx Security Region 18 1 read-write WRNSECH3 Write Non-secured for HSELx Security Region 19 1 read-write WRNSECH4 Write Non-secured for HSELx Security Region 20 1 read-write WRNSECH5 Write Non-secured for HSELx Security Region 21 1 read-write WRNSECH6 Write Non-secured for HSELx Security Region 22 1 read-write WRNSECH7 Write Non-secured for HSELx Security Region 23 1 read-write SSR9 Security Slave 0 Register 0x224 32 read-write n LANSECH0 Low Area Non-secured in HSELx Security Region 0 1 read-write LANSECH1 Low Area Non-secured in HSELx Security Region 1 1 read-write LANSECH2 Low Area Non-secured in HSELx Security Region 2 1 read-write LANSECH3 Low Area Non-secured in HSELx Security Region 3 1 read-write LANSECH4 Low Area Non-secured in HSELx Security Region 4 1 read-write LANSECH5 Low Area Non-secured in HSELx Security Region 5 1 read-write LANSECH6 Low Area Non-secured in HSELx Security Region 6 1 read-write LANSECH7 Low Area Non-secured in HSELx Security Region 7 1 read-write RDNSECH0 Read Non-secured for HSELx Security Region 8 1 read-write RDNSECH1 Read Non-secured for HSELx Security Region 9 1 read-write RDNSECH2 Read Non-secured for HSELx Security Region 10 1 read-write RDNSECH3 Read Non-secured for HSELx Security Region 11 1 read-write RDNSECH4 Read Non-secured for HSELx Security Region 12 1 read-write RDNSECH5 Read Non-secured for HSELx Security Region 13 1 read-write RDNSECH6 Read Non-secured for HSELx Security Region 14 1 read-write RDNSECH7 Read Non-secured for HSELx Security Region 15 1 read-write WRNSECH0 Write Non-secured for HSELx Security Region 16 1 read-write WRNSECH1 Write Non-secured for HSELx Security Region 17 1 read-write WRNSECH2 Write Non-secured for HSELx Security Region 18 1 read-write WRNSECH3 Write Non-secured for HSELx Security Region 19 1 read-write WRNSECH4 Write Non-secured for HSELx Security Region 20 1 read-write WRNSECH5 Write Non-secured for HSELx Security Region 21 1 read-write WRNSECH6 Write Non-secured for HSELx Security Region 22 1 read-write WRNSECH7 Write Non-secured for HSELx Security Region 23 1 read-write SSR[0] Security Slave 0 Register 0x400 32 read-write n 0x0 0x0 LANSECH0 Low Area Non-secured in HSELx Security Region 0 1 read-write LANSECH1 Low Area Non-secured in HSELx Security Region 1 1 read-write LANSECH2 Low Area Non-secured in HSELx Security Region 2 1 read-write LANSECH3 Low Area Non-secured in HSELx Security Region 3 1 read-write LANSECH4 Low Area Non-secured in HSELx Security Region 4 1 read-write LANSECH5 Low Area Non-secured in HSELx Security Region 5 1 read-write LANSECH6 Low Area Non-secured in HSELx Security Region 6 1 read-write LANSECH7 Low Area Non-secured in HSELx Security Region 7 1 read-write RDNSECH0 Read Non-secured for HSELx Security Region 8 1 read-write RDNSECH1 Read Non-secured for HSELx Security Region 9 1 read-write RDNSECH2 Read Non-secured for HSELx Security Region 10 1 read-write RDNSECH3 Read Non-secured for HSELx Security Region 11 1 read-write RDNSECH4 Read Non-secured for HSELx Security Region 12 1 read-write RDNSECH5 Read Non-secured for HSELx Security Region 13 1 read-write RDNSECH6 Read Non-secured for HSELx Security Region 14 1 read-write RDNSECH7 Read Non-secured for HSELx Security Region 15 1 read-write WRNSECH0 Write Non-secured for HSELx Security Region 16 1 read-write WRNSECH1 Write Non-secured for HSELx Security Region 17 1 read-write WRNSECH2 Write Non-secured for HSELx Security Region 18 1 read-write WRNSECH3 Write Non-secured for HSELx Security Region 19 1 read-write WRNSECH4 Write Non-secured for HSELx Security Region 20 1 read-write WRNSECH5 Write Non-secured for HSELx Security Region 21 1 read-write WRNSECH6 Write Non-secured for HSELx Security Region 22 1 read-write WRNSECH7 Write Non-secured for HSELx Security Region 23 1 read-write SSR[10] Security Slave 0 Register 0x18DC 32 read-write n 0x0 0x0 LANSECH0 Low Area Non-secured in HSELx Security Region 0 1 read-write LANSECH1 Low Area Non-secured in HSELx Security Region 1 1 read-write LANSECH2 Low Area Non-secured in HSELx Security Region 2 1 read-write LANSECH3 Low Area Non-secured in HSELx Security Region 3 1 read-write LANSECH4 Low Area Non-secured in HSELx Security Region 4 1 read-write LANSECH5 Low Area Non-secured in HSELx Security Region 5 1 read-write LANSECH6 Low Area Non-secured in HSELx Security Region 6 1 read-write LANSECH7 Low Area Non-secured in HSELx Security Region 7 1 read-write RDNSECH0 Read Non-secured for HSELx Security Region 8 1 read-write RDNSECH1 Read Non-secured for HSELx Security Region 9 1 read-write RDNSECH2 Read Non-secured for HSELx Security Region 10 1 read-write RDNSECH3 Read Non-secured for HSELx Security Region 11 1 read-write RDNSECH4 Read Non-secured for HSELx Security Region 12 1 read-write RDNSECH5 Read Non-secured for HSELx Security Region 13 1 read-write RDNSECH6 Read Non-secured for HSELx Security Region 14 1 read-write RDNSECH7 Read Non-secured for HSELx Security Region 15 1 read-write WRNSECH0 Write Non-secured for HSELx Security Region 16 1 read-write WRNSECH1 Write Non-secured for HSELx Security Region 17 1 read-write WRNSECH2 Write Non-secured for HSELx Security Region 18 1 read-write WRNSECH3 Write Non-secured for HSELx Security Region 19 1 read-write WRNSECH4 Write Non-secured for HSELx Security Region 20 1 read-write WRNSECH5 Write Non-secured for HSELx Security Region 21 1 read-write WRNSECH6 Write Non-secured for HSELx Security Region 22 1 read-write WRNSECH7 Write Non-secured for HSELx Security Region 23 1 read-write SSR[11] Security Slave 0 Register 0x1B08 32 read-write n 0x0 0x0 LANSECH0 Low Area Non-secured in HSELx Security Region 0 1 read-write LANSECH1 Low Area Non-secured in HSELx Security Region 1 1 read-write LANSECH2 Low Area Non-secured in HSELx Security Region 2 1 read-write LANSECH3 Low Area Non-secured in HSELx Security Region 3 1 read-write LANSECH4 Low Area Non-secured in HSELx Security Region 4 1 read-write LANSECH5 Low Area Non-secured in HSELx Security Region 5 1 read-write LANSECH6 Low Area Non-secured in HSELx Security Region 6 1 read-write LANSECH7 Low Area Non-secured in HSELx Security Region 7 1 read-write RDNSECH0 Read Non-secured for HSELx Security Region 8 1 read-write RDNSECH1 Read Non-secured for HSELx Security Region 9 1 read-write RDNSECH2 Read Non-secured for HSELx Security Region 10 1 read-write RDNSECH3 Read Non-secured for HSELx Security Region 11 1 read-write RDNSECH4 Read Non-secured for HSELx Security Region 12 1 read-write RDNSECH5 Read Non-secured for HSELx Security Region 13 1 read-write RDNSECH6 Read Non-secured for HSELx Security Region 14 1 read-write RDNSECH7 Read Non-secured for HSELx Security Region 15 1 read-write WRNSECH0 Write Non-secured for HSELx Security Region 16 1 read-write WRNSECH1 Write Non-secured for HSELx Security Region 17 1 read-write WRNSECH2 Write Non-secured for HSELx Security Region 18 1 read-write WRNSECH3 Write Non-secured for HSELx Security Region 19 1 read-write WRNSECH4 Write Non-secured for HSELx Security Region 20 1 read-write WRNSECH5 Write Non-secured for HSELx Security Region 21 1 read-write WRNSECH6 Write Non-secured for HSELx Security Region 22 1 read-write WRNSECH7 Write Non-secured for HSELx Security Region 23 1 read-write SSR[12] Security Slave 0 Register 0x1D38 32 read-write n 0x0 0x0 LANSECH0 Low Area Non-secured in HSELx Security Region 0 1 read-write LANSECH1 Low Area Non-secured in HSELx Security Region 1 1 read-write LANSECH2 Low Area Non-secured in HSELx Security Region 2 1 read-write LANSECH3 Low Area Non-secured in HSELx Security Region 3 1 read-write LANSECH4 Low Area Non-secured in HSELx Security Region 4 1 read-write LANSECH5 Low Area Non-secured in HSELx Security Region 5 1 read-write LANSECH6 Low Area Non-secured in HSELx Security Region 6 1 read-write LANSECH7 Low Area Non-secured in HSELx Security Region 7 1 read-write RDNSECH0 Read Non-secured for HSELx Security Region 8 1 read-write RDNSECH1 Read Non-secured for HSELx Security Region 9 1 read-write RDNSECH2 Read Non-secured for HSELx Security Region 10 1 read-write RDNSECH3 Read Non-secured for HSELx Security Region 11 1 read-write RDNSECH4 Read Non-secured for HSELx Security Region 12 1 read-write RDNSECH5 Read Non-secured for HSELx Security Region 13 1 read-write RDNSECH6 Read Non-secured for HSELx Security Region 14 1 read-write RDNSECH7 Read Non-secured for HSELx Security Region 15 1 read-write WRNSECH0 Write Non-secured for HSELx Security Region 16 1 read-write WRNSECH1 Write Non-secured for HSELx Security Region 17 1 read-write WRNSECH2 Write Non-secured for HSELx Security Region 18 1 read-write WRNSECH3 Write Non-secured for HSELx Security Region 19 1 read-write WRNSECH4 Write Non-secured for HSELx Security Region 20 1 read-write WRNSECH5 Write Non-secured for HSELx Security Region 21 1 read-write WRNSECH6 Write Non-secured for HSELx Security Region 22 1 read-write WRNSECH7 Write Non-secured for HSELx Security Region 23 1 read-write SSR[1] Security Slave 0 Register 0x604 32 read-write n 0x0 0x0 LANSECH0 Low Area Non-secured in HSELx Security Region 0 1 read-write LANSECH1 Low Area Non-secured in HSELx Security Region 1 1 read-write LANSECH2 Low Area Non-secured in HSELx Security Region 2 1 read-write LANSECH3 Low Area Non-secured in HSELx Security Region 3 1 read-write LANSECH4 Low Area Non-secured in HSELx Security Region 4 1 read-write LANSECH5 Low Area Non-secured in HSELx Security Region 5 1 read-write LANSECH6 Low Area Non-secured in HSELx Security Region 6 1 read-write LANSECH7 Low Area Non-secured in HSELx Security Region 7 1 read-write RDNSECH0 Read Non-secured for HSELx Security Region 8 1 read-write RDNSECH1 Read Non-secured for HSELx Security Region 9 1 read-write RDNSECH2 Read Non-secured for HSELx Security Region 10 1 read-write RDNSECH3 Read Non-secured for HSELx Security Region 11 1 read-write RDNSECH4 Read Non-secured for HSELx Security Region 12 1 read-write RDNSECH5 Read Non-secured for HSELx Security Region 13 1 read-write RDNSECH6 Read Non-secured for HSELx Security Region 14 1 read-write RDNSECH7 Read Non-secured for HSELx Security Region 15 1 read-write WRNSECH0 Write Non-secured for HSELx Security Region 16 1 read-write WRNSECH1 Write Non-secured for HSELx Security Region 17 1 read-write WRNSECH2 Write Non-secured for HSELx Security Region 18 1 read-write WRNSECH3 Write Non-secured for HSELx Security Region 19 1 read-write WRNSECH4 Write Non-secured for HSELx Security Region 20 1 read-write WRNSECH5 Write Non-secured for HSELx Security Region 21 1 read-write WRNSECH6 Write Non-secured for HSELx Security Region 22 1 read-write WRNSECH7 Write Non-secured for HSELx Security Region 23 1 read-write SSR[2] Security Slave 0 Register 0x80C 32 read-write n 0x0 0x0 LANSECH0 Low Area Non-secured in HSELx Security Region 0 1 read-write LANSECH1 Low Area Non-secured in HSELx Security Region 1 1 read-write LANSECH2 Low Area Non-secured in HSELx Security Region 2 1 read-write LANSECH3 Low Area Non-secured in HSELx Security Region 3 1 read-write LANSECH4 Low Area Non-secured in HSELx Security Region 4 1 read-write LANSECH5 Low Area Non-secured in HSELx Security Region 5 1 read-write LANSECH6 Low Area Non-secured in HSELx Security Region 6 1 read-write LANSECH7 Low Area Non-secured in HSELx Security Region 7 1 read-write RDNSECH0 Read Non-secured for HSELx Security Region 8 1 read-write RDNSECH1 Read Non-secured for HSELx Security Region 9 1 read-write RDNSECH2 Read Non-secured for HSELx Security Region 10 1 read-write RDNSECH3 Read Non-secured for HSELx Security Region 11 1 read-write RDNSECH4 Read Non-secured for HSELx Security Region 12 1 read-write RDNSECH5 Read Non-secured for HSELx Security Region 13 1 read-write RDNSECH6 Read Non-secured for HSELx Security Region 14 1 read-write RDNSECH7 Read Non-secured for HSELx Security Region 15 1 read-write WRNSECH0 Write Non-secured for HSELx Security Region 16 1 read-write WRNSECH1 Write Non-secured for HSELx Security Region 17 1 read-write WRNSECH2 Write Non-secured for HSELx Security Region 18 1 read-write WRNSECH3 Write Non-secured for HSELx Security Region 19 1 read-write WRNSECH4 Write Non-secured for HSELx Security Region 20 1 read-write WRNSECH5 Write Non-secured for HSELx Security Region 21 1 read-write WRNSECH6 Write Non-secured for HSELx Security Region 22 1 read-write WRNSECH7 Write Non-secured for HSELx Security Region 23 1 read-write SSR[3] Security Slave 0 Register 0xA18 32 read-write n 0x0 0x0 LANSECH0 Low Area Non-secured in HSELx Security Region 0 1 read-write LANSECH1 Low Area Non-secured in HSELx Security Region 1 1 read-write LANSECH2 Low Area Non-secured in HSELx Security Region 2 1 read-write LANSECH3 Low Area Non-secured in HSELx Security Region 3 1 read-write LANSECH4 Low Area Non-secured in HSELx Security Region 4 1 read-write LANSECH5 Low Area Non-secured in HSELx Security Region 5 1 read-write LANSECH6 Low Area Non-secured in HSELx Security Region 6 1 read-write LANSECH7 Low Area Non-secured in HSELx Security Region 7 1 read-write RDNSECH0 Read Non-secured for HSELx Security Region 8 1 read-write RDNSECH1 Read Non-secured for HSELx Security Region 9 1 read-write RDNSECH2 Read Non-secured for HSELx Security Region 10 1 read-write RDNSECH3 Read Non-secured for HSELx Security Region 11 1 read-write RDNSECH4 Read Non-secured for HSELx Security Region 12 1 read-write RDNSECH5 Read Non-secured for HSELx Security Region 13 1 read-write RDNSECH6 Read Non-secured for HSELx Security Region 14 1 read-write RDNSECH7 Read Non-secured for HSELx Security Region 15 1 read-write WRNSECH0 Write Non-secured for HSELx Security Region 16 1 read-write WRNSECH1 Write Non-secured for HSELx Security Region 17 1 read-write WRNSECH2 Write Non-secured for HSELx Security Region 18 1 read-write WRNSECH3 Write Non-secured for HSELx Security Region 19 1 read-write WRNSECH4 Write Non-secured for HSELx Security Region 20 1 read-write WRNSECH5 Write Non-secured for HSELx Security Region 21 1 read-write WRNSECH6 Write Non-secured for HSELx Security Region 22 1 read-write WRNSECH7 Write Non-secured for HSELx Security Region 23 1 read-write SSR[4] Security Slave 0 Register 0xC28 32 read-write n 0x0 0x0 LANSECH0 Low Area Non-secured in HSELx Security Region 0 1 read-write LANSECH1 Low Area Non-secured in HSELx Security Region 1 1 read-write LANSECH2 Low Area Non-secured in HSELx Security Region 2 1 read-write LANSECH3 Low Area Non-secured in HSELx Security Region 3 1 read-write LANSECH4 Low Area Non-secured in HSELx Security Region 4 1 read-write LANSECH5 Low Area Non-secured in HSELx Security Region 5 1 read-write LANSECH6 Low Area Non-secured in HSELx Security Region 6 1 read-write LANSECH7 Low Area Non-secured in HSELx Security Region 7 1 read-write RDNSECH0 Read Non-secured for HSELx Security Region 8 1 read-write RDNSECH1 Read Non-secured for HSELx Security Region 9 1 read-write RDNSECH2 Read Non-secured for HSELx Security Region 10 1 read-write RDNSECH3 Read Non-secured for HSELx Security Region 11 1 read-write RDNSECH4 Read Non-secured for HSELx Security Region 12 1 read-write RDNSECH5 Read Non-secured for HSELx Security Region 13 1 read-write RDNSECH6 Read Non-secured for HSELx Security Region 14 1 read-write RDNSECH7 Read Non-secured for HSELx Security Region 15 1 read-write WRNSECH0 Write Non-secured for HSELx Security Region 16 1 read-write WRNSECH1 Write Non-secured for HSELx Security Region 17 1 read-write WRNSECH2 Write Non-secured for HSELx Security Region 18 1 read-write WRNSECH3 Write Non-secured for HSELx Security Region 19 1 read-write WRNSECH4 Write Non-secured for HSELx Security Region 20 1 read-write WRNSECH5 Write Non-secured for HSELx Security Region 21 1 read-write WRNSECH6 Write Non-secured for HSELx Security Region 22 1 read-write WRNSECH7 Write Non-secured for HSELx Security Region 23 1 read-write SSR[5] Security Slave 0 Register 0xE3C 32 read-write n 0x0 0x0 LANSECH0 Low Area Non-secured in HSELx Security Region 0 1 read-write LANSECH1 Low Area Non-secured in HSELx Security Region 1 1 read-write LANSECH2 Low Area Non-secured in HSELx Security Region 2 1 read-write LANSECH3 Low Area Non-secured in HSELx Security Region 3 1 read-write LANSECH4 Low Area Non-secured in HSELx Security Region 4 1 read-write LANSECH5 Low Area Non-secured in HSELx Security Region 5 1 read-write LANSECH6 Low Area Non-secured in HSELx Security Region 6 1 read-write LANSECH7 Low Area Non-secured in HSELx Security Region 7 1 read-write RDNSECH0 Read Non-secured for HSELx Security Region 8 1 read-write RDNSECH1 Read Non-secured for HSELx Security Region 9 1 read-write RDNSECH2 Read Non-secured for HSELx Security Region 10 1 read-write RDNSECH3 Read Non-secured for HSELx Security Region 11 1 read-write RDNSECH4 Read Non-secured for HSELx Security Region 12 1 read-write RDNSECH5 Read Non-secured for HSELx Security Region 13 1 read-write RDNSECH6 Read Non-secured for HSELx Security Region 14 1 read-write RDNSECH7 Read Non-secured for HSELx Security Region 15 1 read-write WRNSECH0 Write Non-secured for HSELx Security Region 16 1 read-write WRNSECH1 Write Non-secured for HSELx Security Region 17 1 read-write WRNSECH2 Write Non-secured for HSELx Security Region 18 1 read-write WRNSECH3 Write Non-secured for HSELx Security Region 19 1 read-write WRNSECH4 Write Non-secured for HSELx Security Region 20 1 read-write WRNSECH5 Write Non-secured for HSELx Security Region 21 1 read-write WRNSECH6 Write Non-secured for HSELx Security Region 22 1 read-write WRNSECH7 Write Non-secured for HSELx Security Region 23 1 read-write SSR[6] Security Slave 0 Register 0x1054 32 read-write n 0x0 0x0 LANSECH0 Low Area Non-secured in HSELx Security Region 0 1 read-write LANSECH1 Low Area Non-secured in HSELx Security Region 1 1 read-write LANSECH2 Low Area Non-secured in HSELx Security Region 2 1 read-write LANSECH3 Low Area Non-secured in HSELx Security Region 3 1 read-write LANSECH4 Low Area Non-secured in HSELx Security Region 4 1 read-write LANSECH5 Low Area Non-secured in HSELx Security Region 5 1 read-write LANSECH6 Low Area Non-secured in HSELx Security Region 6 1 read-write LANSECH7 Low Area Non-secured in HSELx Security Region 7 1 read-write RDNSECH0 Read Non-secured for HSELx Security Region 8 1 read-write RDNSECH1 Read Non-secured for HSELx Security Region 9 1 read-write RDNSECH2 Read Non-secured for HSELx Security Region 10 1 read-write RDNSECH3 Read Non-secured for HSELx Security Region 11 1 read-write RDNSECH4 Read Non-secured for HSELx Security Region 12 1 read-write RDNSECH5 Read Non-secured for HSELx Security Region 13 1 read-write RDNSECH6 Read Non-secured for HSELx Security Region 14 1 read-write RDNSECH7 Read Non-secured for HSELx Security Region 15 1 read-write WRNSECH0 Write Non-secured for HSELx Security Region 16 1 read-write WRNSECH1 Write Non-secured for HSELx Security Region 17 1 read-write WRNSECH2 Write Non-secured for HSELx Security Region 18 1 read-write WRNSECH3 Write Non-secured for HSELx Security Region 19 1 read-write WRNSECH4 Write Non-secured for HSELx Security Region 20 1 read-write WRNSECH5 Write Non-secured for HSELx Security Region 21 1 read-write WRNSECH6 Write Non-secured for HSELx Security Region 22 1 read-write WRNSECH7 Write Non-secured for HSELx Security Region 23 1 read-write SSR[7] Security Slave 0 Register 0x1270 32 read-write n 0x0 0x0 LANSECH0 Low Area Non-secured in HSELx Security Region 0 1 read-write LANSECH1 Low Area Non-secured in HSELx Security Region 1 1 read-write LANSECH2 Low Area Non-secured in HSELx Security Region 2 1 read-write LANSECH3 Low Area Non-secured in HSELx Security Region 3 1 read-write LANSECH4 Low Area Non-secured in HSELx Security Region 4 1 read-write LANSECH5 Low Area Non-secured in HSELx Security Region 5 1 read-write LANSECH6 Low Area Non-secured in HSELx Security Region 6 1 read-write LANSECH7 Low Area Non-secured in HSELx Security Region 7 1 read-write RDNSECH0 Read Non-secured for HSELx Security Region 8 1 read-write RDNSECH1 Read Non-secured for HSELx Security Region 9 1 read-write RDNSECH2 Read Non-secured for HSELx Security Region 10 1 read-write RDNSECH3 Read Non-secured for HSELx Security Region 11 1 read-write RDNSECH4 Read Non-secured for HSELx Security Region 12 1 read-write RDNSECH5 Read Non-secured for HSELx Security Region 13 1 read-write RDNSECH6 Read Non-secured for HSELx Security Region 14 1 read-write RDNSECH7 Read Non-secured for HSELx Security Region 15 1 read-write WRNSECH0 Write Non-secured for HSELx Security Region 16 1 read-write WRNSECH1 Write Non-secured for HSELx Security Region 17 1 read-write WRNSECH2 Write Non-secured for HSELx Security Region 18 1 read-write WRNSECH3 Write Non-secured for HSELx Security Region 19 1 read-write WRNSECH4 Write Non-secured for HSELx Security Region 20 1 read-write WRNSECH5 Write Non-secured for HSELx Security Region 21 1 read-write WRNSECH6 Write Non-secured for HSELx Security Region 22 1 read-write WRNSECH7 Write Non-secured for HSELx Security Region 23 1 read-write SSR[8] Security Slave 0 Register 0x1490 32 read-write n 0x0 0x0 LANSECH0 Low Area Non-secured in HSELx Security Region 0 1 read-write LANSECH1 Low Area Non-secured in HSELx Security Region 1 1 read-write LANSECH2 Low Area Non-secured in HSELx Security Region 2 1 read-write LANSECH3 Low Area Non-secured in HSELx Security Region 3 1 read-write LANSECH4 Low Area Non-secured in HSELx Security Region 4 1 read-write LANSECH5 Low Area Non-secured in HSELx Security Region 5 1 read-write LANSECH6 Low Area Non-secured in HSELx Security Region 6 1 read-write LANSECH7 Low Area Non-secured in HSELx Security Region 7 1 read-write RDNSECH0 Read Non-secured for HSELx Security Region 8 1 read-write RDNSECH1 Read Non-secured for HSELx Security Region 9 1 read-write RDNSECH2 Read Non-secured for HSELx Security Region 10 1 read-write RDNSECH3 Read Non-secured for HSELx Security Region 11 1 read-write RDNSECH4 Read Non-secured for HSELx Security Region 12 1 read-write RDNSECH5 Read Non-secured for HSELx Security Region 13 1 read-write RDNSECH6 Read Non-secured for HSELx Security Region 14 1 read-write RDNSECH7 Read Non-secured for HSELx Security Region 15 1 read-write WRNSECH0 Write Non-secured for HSELx Security Region 16 1 read-write WRNSECH1 Write Non-secured for HSELx Security Region 17 1 read-write WRNSECH2 Write Non-secured for HSELx Security Region 18 1 read-write WRNSECH3 Write Non-secured for HSELx Security Region 19 1 read-write WRNSECH4 Write Non-secured for HSELx Security Region 20 1 read-write WRNSECH5 Write Non-secured for HSELx Security Region 21 1 read-write WRNSECH6 Write Non-secured for HSELx Security Region 22 1 read-write WRNSECH7 Write Non-secured for HSELx Security Region 23 1 read-write SSR[9] Security Slave 0 Register 0x16B4 32 read-write n 0x0 0x0 LANSECH0 Low Area Non-secured in HSELx Security Region 0 1 read-write LANSECH1 Low Area Non-secured in HSELx Security Region 1 1 read-write LANSECH2 Low Area Non-secured in HSELx Security Region 2 1 read-write LANSECH3 Low Area Non-secured in HSELx Security Region 3 1 read-write LANSECH4 Low Area Non-secured in HSELx Security Region 4 1 read-write LANSECH5 Low Area Non-secured in HSELx Security Region 5 1 read-write LANSECH6 Low Area Non-secured in HSELx Security Region 6 1 read-write LANSECH7 Low Area Non-secured in HSELx Security Region 7 1 read-write RDNSECH0 Read Non-secured for HSELx Security Region 8 1 read-write RDNSECH1 Read Non-secured for HSELx Security Region 9 1 read-write RDNSECH2 Read Non-secured for HSELx Security Region 10 1 read-write RDNSECH3 Read Non-secured for HSELx Security Region 11 1 read-write RDNSECH4 Read Non-secured for HSELx Security Region 12 1 read-write RDNSECH5 Read Non-secured for HSELx Security Region 13 1 read-write RDNSECH6 Read Non-secured for HSELx Security Region 14 1 read-write RDNSECH7 Read Non-secured for HSELx Security Region 15 1 read-write WRNSECH0 Write Non-secured for HSELx Security Region 16 1 read-write WRNSECH1 Write Non-secured for HSELx Security Region 17 1 read-write WRNSECH2 Write Non-secured for HSELx Security Region 18 1 read-write WRNSECH3 Write Non-secured for HSELx Security Region 19 1 read-write WRNSECH4 Write Non-secured for HSELx Security Region 20 1 read-write WRNSECH5 Write Non-secured for HSELx Security Region 21 1 read-write WRNSECH6 Write Non-secured for HSELx Security Region 22 1 read-write WRNSECH7 Write Non-secured for HSELx Security Region 23 1 read-write WPMR Write Protection Mode Register 0x1E4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 read-write WPKEY Write Protection Key (Write-only) 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 0x4D4154 WPSR Write Protection Status Register 0x1E8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 read-only WPVSRC Write Protection Violation Source 8 16 read-only MPDDRC AHB Multiport DDR-SDRAM Controller EBI 0x0 0x0 0x50 registers n BDW_PORT_0123 MPDDRC Current/Maximum Bandwidth Port 0-1-2-3 Register 0x54 32 read-only n 0x0 0x0 BDW_P0 Current/Maximum Bandwidth from Port 0-1-2-3 0 7 read-only BDW_P1 Current/Maximum Bandwidth from Port 0-1-2-3 8 7 read-only BDW_P2 Current/Maximum Bandwidth from Port 0-1-2-3 16 7 read-only BDW_P3 Current/Maximum Bandwidth from Port 0-1-2-3 24 7 read-only BDW_PORT_4567 MPDDRC Current/Maximum Bandwidth Port 4-5-6-7 Register 0x58 32 read-only n 0x0 0x0 BDW_P4 Current/Maximum Bandwidth from Port 4-5-6-7 0 7 read-only BDW_P5 Current/Maximum Bandwidth from Port 4-5-6-7 8 7 read-only BDW_P6 Current/Maximum Bandwidth from Port 4-5-6-7 16 7 read-only BDW_P7 Current/Maximum Bandwidth from Port 4-5-6-7 24 7 read-only CONF_ARBITER MPDDRC Configuration Arbiter Register 0x44 32 read-write n 0x0 0x0 ARB Type of Arbitration 0 2 read-write ROUND Round Robin 0x0 NB_REQUEST Request Policy 0x1 BANDWIDTH Bandwidth Policy 0x2 BDW_BURST_P0 Bandwidth is Reached or Bandwidth and Current Burst Access is Ended on port X 24 1 read-write BDW_BURST_P1 Bandwidth is Reached or Bandwidth and Current Burst Access is Ended on port X 25 1 read-write BDW_BURST_P2 Bandwidth is Reached or Bandwidth and Current Burst Access is Ended on port X 26 1 read-write BDW_BURST_P3 Bandwidth is Reached or Bandwidth and Current Burst Access is Ended on port X 27 1 read-write BDW_BURST_P4 Bandwidth is Reached or Bandwidth and Current Burst Access is Ended on port X 28 1 read-write BDW_BURST_P5 Bandwidth is Reached or Bandwidth and Current Burst Access is Ended on port X 29 1 read-write BDW_BURST_P6 Bandwidth is Reached or Bandwidth and Current Burst Access is Ended on port X 30 1 read-write BDW_BURST_P7 Bandwidth is Reached or Bandwidth and Current Burst Access is Ended on port X 31 1 read-write BDW_MAX_CUR Bandwidth Max or Current 3 1 read-write MA_PR_P0 Master or Software Provide Information 16 1 read-write MA_PR_P1 Master or Software Provide Information 17 1 read-write MA_PR_P2 Master or Software Provide Information 18 1 read-write MA_PR_P3 Master or Software Provide Information 19 1 read-write MA_PR_P4 Master or Software Provide Information 20 1 read-write MA_PR_P5 Master or Software Provide Information 21 1 read-write MA_PR_P6 Master or Software Provide Information 22 1 read-write MA_PR_P7 Master or Software Provide Information 23 1 read-write RQ_WD_P0 Request or Word from Port X 8 1 read-write RQ_WD_P1 Request or Word from Port X 9 1 read-write RQ_WD_P2 Request or Word from Port X 10 1 read-write RQ_WD_P3 Request or Word from Port X 11 1 read-write RQ_WD_P4 Request or Word from Port X 12 1 read-write RQ_WD_P5 Request or Word from Port X 13 1 read-write RQ_WD_P6 Request or Word from Port X 14 1 read-write RQ_WD_P7 Request or Word from Port X 15 1 read-write CR MPDDRC Configuration Register 0x8 32 read-write n 0x0 0x0 CAS CAS Latency 4 3 read-write DDR_CAS2 LPDDR1 CAS Latency 2 0x2 DDR_CAS3 DDR2/LPDDR2/LPDDR1 CAS Latency 3 0x3 DECOD Type of Decoding 22 1 read-write SEQUENTIAL Method for address mapping where banks alternate at each last DDR-SDRAM page of the current bank. 0 INTERLEAVED Method for address mapping where banks alternate at each DDR-SDRAM end of page of the current bank. 1 DIC_DS Output Driver Impedance Control (Drive Strength) 8 1 read-write DDR2_NORMALSTRENGTH Normal drive strength (DDR2) 0 DDR2_WEAKSTRENGTH Weak drive strength (DDR2) 1 DIS_DLL DISABLE DLL 9 1 read-write DLL Reset DLL 7 1 read-write RESET_DISABLED Disable DLL reset 0 RESET_ENABLED Enable DLL reset 1 DQMS Mask Data is Shared 16 1 read-write NOT_SHARED DQM is not shared with another controller 0 SHARED DQM is shared with another controller 1 ENRDM Enable Read Measure 17 1 read-write OFF DQS/DDR_DATA phase error correction is disabled 0 ON DQS/DDR_DATA phase error correction is enabled 1 LC_LPDDR1 Low-cost Low-power DDR1 19 1 read-write NOT_2_BANKS Any type of memory devices except of low cost, low density Low Power DDR1. 0 2_BANKS_LPDDR1 Low-cost and low-density low-power DDR1. These devices have a density of 32 Mbits and are organized as two internal banks. To use this feature, the user has to define the type of memory and the data bus width (see Section 8.8 "MPDDRC Memory Device Register").The 16-bit memory device is organized as 2 banks, 9 columns and 11 rows. 1 NB Number of Banks 20 1 read-write 4_BANKS 4-bank memory devices 0 8_BANKS 8 banks. Only possible when using the DDR2-SDRAM and low-power DDR2-SDRAM devices. 1 NC Number of Column Bits 0 2 read-write 9_COL_BITS 9 bits to define the column number, up to 512 columns 0x0 10_COL_BITS 10 bits to define the column number, up to 1024 columns 0x1 11_COL_BITS 11 bits to define the column number, up to 2048 columns 0x2 12_COL_BITS 12 bits to define the column number, up to 4096 columns 0x3 NDQS Not DQS 21 1 read-write ENABLED Not DQS is enabled 0 DISABLED Not DQS is disabled 1 NR Number of Row Bits 2 2 read-write 11_ROW_BITS 11 bits to define the row number, up to 2048 rows 0x0 12_ROW_BITS 12 bits to define the row number, up to 4096 rows 0x1 13_ROW_BITS 13 bits to define the row number, up to 8192 rows 0x2 14_ROW_BITS 14 bits to define the row number, up to 16384 rows 0x3 OCD Off-chip Driver 12 3 read-write DDR2_EXITCALIB Exit from OCD Calibration mode and maintain settings 0x0 DDR2_DEFAULT_CALIB OCD calibration default 0x7 UNAL Support Unaligned Access 23 1 read-write UNSUPPORTED Unaligned access is not supported. 0 SUPPORTED Unaligned access is supported. 1 ZQ ZQ Calibration 10 2 read-write INIT Calibration command after initialization 0x0 LONG Long calibration 0x1 SHORT Short calibration 0x2 RESET ZQ Reset 0x3 DLL_ADO MPDDRC DLL CLKAD Offset Register 0x114 32 read-write n 0x0 0x0 ADOFF CLKAD Delay Line Offset 0 8 read-write DLL_MAO MPDDRC DLL Master Offset Register 0x104 32 read-write n 0x0 0x0 MAOFF Master Delay Line Offset 0 8 read-write DLL_OS MPDDRC DLL Offset Selection Register 0x100 32 read-write n 0x0 0x0 SELOFF Offset Selection 0 1 read-write DLL_SAD MPDDRC DLL Status CLKAD Register 0x158 32 read-only n 0x0 0x0 ADDCNT CLKAD Delay Counter Value 0 8 read-only DLL_SM0 MPDDRC DLL Status Master 0 Register 0x118 32 read-only n MDCNT MASTERx Delay Counter Value 20 8 read-only MDDEC MASTERx Delay Decrement 1 1 read-only MDINC MASTERx Delay Increment 0 1 read-only MDLVAL MASTERx Delay Lock Value 8 8 read-only MDOVF MASTERx Delay Overflow Flag 2 1 read-only DLL_SM1 MPDDRC DLL Status Master 0 Register 0x11C 32 read-only n MDCNT MASTERx Delay Counter Value 20 8 read-only MDDEC MASTERx Delay Decrement 1 1 read-only MDINC MASTERx Delay Increment 0 1 read-only MDLVAL MASTERx Delay Lock Value 8 8 read-only MDOVF MASTERx Delay Overflow Flag 2 1 read-only DLL_SM2 MPDDRC DLL Status Master 0 Register 0x120 32 read-only n MDCNT MASTERx Delay Counter Value 20 8 read-only MDDEC MASTERx Delay Decrement 1 1 read-only MDINC MASTERx Delay Increment 0 1 read-only MDLVAL MASTERx Delay Lock Value 8 8 read-only MDOVF MASTERx Delay Overflow Flag 2 1 read-only DLL_SM3 MPDDRC DLL Status Master 0 Register 0x124 32 read-only n MDCNT MASTERx Delay Counter Value 20 8 read-only MDDEC MASTERx Delay Decrement 1 1 read-only MDINC MASTERx Delay Increment 0 1 read-only MDLVAL MASTERx Delay Lock Value 8 8 read-only MDOVF MASTERx Delay Overflow Flag 2 1 read-only DLL_SM[0] MPDDRC DLL Status Master 0 Register 0x230 32 read-only n 0x0 0x0 MDCNT MASTERx Delay Counter Value 20 8 read-only MDDEC MASTERx Delay Decrement 1 1 read-only MDINC MASTERx Delay Increment 0 1 read-only MDLVAL MASTERx Delay Lock Value 8 8 read-only MDOVF MASTERx Delay Overflow Flag 2 1 read-only DLL_SM[1] MPDDRC DLL Status Master 0 Register 0x34C 32 read-only n 0x0 0x0 MDCNT MASTERx Delay Counter Value 20 8 read-only MDDEC MASTERx Delay Decrement 1 1 read-only MDINC MASTERx Delay Increment 0 1 read-only MDLVAL MASTERx Delay Lock Value 8 8 read-only MDOVF MASTERx Delay Overflow Flag 2 1 read-only DLL_SM[2] MPDDRC DLL Status Master 0 Register 0x46C 32 read-only n 0x0 0x0 MDCNT MASTERx Delay Counter Value 20 8 read-only MDDEC MASTERx Delay Decrement 1 1 read-only MDINC MASTERx Delay Increment 0 1 read-only MDLVAL MASTERx Delay Lock Value 8 8 read-only MDOVF MASTERx Delay Overflow Flag 2 1 read-only DLL_SM[3] MPDDRC DLL Status Master 0 Register 0x590 32 read-only n 0x0 0x0 MDCNT MASTERx Delay Counter Value 20 8 read-only MDDEC MASTERx Delay Decrement 1 1 read-only MDINC MASTERx Delay Increment 0 1 read-only MDLVAL MASTERx Delay Lock Value 8 8 read-only MDOVF MASTERx Delay Overflow Flag 2 1 read-only DLL_SO0 MPDDRC DLL Slave Offset 0 Register 0x108 32 read-write n 0x0 0x0 S0OFF SLAVEx Delay Line Offset 0 8 read-write S1OFF SLAVEx Delay Line Offset 8 8 read-write S2OFF SLAVEx Delay Line Offset 16 8 read-write S3OFF SLAVEx Delay Line Offset 24 8 read-write DLL_SO1 MPDDRC DLL Slave Offset 1 Register 0x10C 32 read-write n 0x0 0x0 S4OFF SLAVEx Delay Line Offset 0 8 read-write S5OFF SLAVEx Delay Line Offset 8 8 read-write S6OFF SLAVEx Delay Line Offset 16 8 read-write S7OFF SLAVEx Delay Line Offset 24 8 read-write DLL_SSL0 MPDDRC DLL Status Slave 0 Register 0x128 32 read-only n SDCNT SLAVEx Delay Counter Value 8 8 read-only SDCOVF SLAVEx Delay Correction Overflow Flag 0 1 read-only SDCUDF SLAVEx Delay Correction Underflow Flag 1 1 read-only SDCVAL SLAVEx Delay Correction Value 20 8 read-only SDERF SLAVEx Delay Correction Error Flag 2 1 read-only DLL_SSL1 MPDDRC DLL Status Slave 0 Register 0x12C 32 read-only n SDCNT SLAVEx Delay Counter Value 8 8 read-only SDCOVF SLAVEx Delay Correction Overflow Flag 0 1 read-only SDCUDF SLAVEx Delay Correction Underflow Flag 1 1 read-only SDCVAL SLAVEx Delay Correction Value 20 8 read-only SDERF SLAVEx Delay Correction Error Flag 2 1 read-only DLL_SSL2 MPDDRC DLL Status Slave 0 Register 0x130 32 read-only n SDCNT SLAVEx Delay Counter Value 8 8 read-only SDCOVF SLAVEx Delay Correction Overflow Flag 0 1 read-only SDCUDF SLAVEx Delay Correction Underflow Flag 1 1 read-only SDCVAL SLAVEx Delay Correction Value 20 8 read-only SDERF SLAVEx Delay Correction Error Flag 2 1 read-only DLL_SSL3 MPDDRC DLL Status Slave 0 Register 0x134 32 read-only n SDCNT SLAVEx Delay Counter Value 8 8 read-only SDCOVF SLAVEx Delay Correction Overflow Flag 0 1 read-only SDCUDF SLAVEx Delay Correction Underflow Flag 1 1 read-only SDCVAL SLAVEx Delay Correction Value 20 8 read-only SDERF SLAVEx Delay Correction Error Flag 2 1 read-only DLL_SSL4 MPDDRC DLL Status Slave 0 Register 0x138 32 read-only n SDCNT SLAVEx Delay Counter Value 8 8 read-only SDCOVF SLAVEx Delay Correction Overflow Flag 0 1 read-only SDCUDF SLAVEx Delay Correction Underflow Flag 1 1 read-only SDCVAL SLAVEx Delay Correction Value 20 8 read-only SDERF SLAVEx Delay Correction Error Flag 2 1 read-only DLL_SSL5 MPDDRC DLL Status Slave 0 Register 0x13C 32 read-only n SDCNT SLAVEx Delay Counter Value 8 8 read-only SDCOVF SLAVEx Delay Correction Overflow Flag 0 1 read-only SDCUDF SLAVEx Delay Correction Underflow Flag 1 1 read-only SDCVAL SLAVEx Delay Correction Value 20 8 read-only SDERF SLAVEx Delay Correction Error Flag 2 1 read-only DLL_SSL6 MPDDRC DLL Status Slave 0 Register 0x140 32 read-only n SDCNT SLAVEx Delay Counter Value 8 8 read-only SDCOVF SLAVEx Delay Correction Overflow Flag 0 1 read-only SDCUDF SLAVEx Delay Correction Underflow Flag 1 1 read-only SDCVAL SLAVEx Delay Correction Value 20 8 read-only SDERF SLAVEx Delay Correction Error Flag 2 1 read-only DLL_SSL7 MPDDRC DLL Status Slave 0 Register 0x144 32 read-only n SDCNT SLAVEx Delay Counter Value 8 8 read-only SDCOVF SLAVEx Delay Correction Overflow Flag 0 1 read-only SDCUDF SLAVEx Delay Correction Underflow Flag 1 1 read-only SDCVAL SLAVEx Delay Correction Value 20 8 read-only SDERF SLAVEx Delay Correction Error Flag 2 1 read-only DLL_SSL[0] MPDDRC DLL Status Slave 0 Register 0x250 32 read-only n 0x0 0x0 SDCNT SLAVEx Delay Counter Value 8 8 read-only SDCOVF SLAVEx Delay Correction Overflow Flag 0 1 read-only SDCUDF SLAVEx Delay Correction Underflow Flag 1 1 read-only SDCVAL SLAVEx Delay Correction Value 20 8 read-only SDERF SLAVEx Delay Correction Error Flag 2 1 read-only DLL_SSL[1] MPDDRC DLL Status Slave 0 Register 0x37C 32 read-only n 0x0 0x0 SDCNT SLAVEx Delay Counter Value 8 8 read-only SDCOVF SLAVEx Delay Correction Overflow Flag 0 1 read-only SDCUDF SLAVEx Delay Correction Underflow Flag 1 1 read-only SDCVAL SLAVEx Delay Correction Value 20 8 read-only SDERF SLAVEx Delay Correction Error Flag 2 1 read-only DLL_SSL[2] MPDDRC DLL Status Slave 0 Register 0x4AC 32 read-only n 0x0 0x0 SDCNT SLAVEx Delay Counter Value 8 8 read-only SDCOVF SLAVEx Delay Correction Overflow Flag 0 1 read-only SDCUDF SLAVEx Delay Correction Underflow Flag 1 1 read-only SDCVAL SLAVEx Delay Correction Value 20 8 read-only SDERF SLAVEx Delay Correction Error Flag 2 1 read-only DLL_SSL[3] MPDDRC DLL Status Slave 0 Register 0x5E0 32 read-only n 0x0 0x0 SDCNT SLAVEx Delay Counter Value 8 8 read-only SDCOVF SLAVEx Delay Correction Overflow Flag 0 1 read-only SDCUDF SLAVEx Delay Correction Underflow Flag 1 1 read-only SDCVAL SLAVEx Delay Correction Value 20 8 read-only SDERF SLAVEx Delay Correction Error Flag 2 1 read-only DLL_SSL[4] MPDDRC DLL Status Slave 0 Register 0x718 32 read-only n 0x0 0x0 SDCNT SLAVEx Delay Counter Value 8 8 read-only SDCOVF SLAVEx Delay Correction Overflow Flag 0 1 read-only SDCUDF SLAVEx Delay Correction Underflow Flag 1 1 read-only SDCVAL SLAVEx Delay Correction Value 20 8 read-only SDERF SLAVEx Delay Correction Error Flag 2 1 read-only DLL_SSL[5] MPDDRC DLL Status Slave 0 Register 0x854 32 read-only n 0x0 0x0 SDCNT SLAVEx Delay Counter Value 8 8 read-only SDCOVF SLAVEx Delay Correction Overflow Flag 0 1 read-only SDCUDF SLAVEx Delay Correction Underflow Flag 1 1 read-only SDCVAL SLAVEx Delay Correction Value 20 8 read-only SDERF SLAVEx Delay Correction Error Flag 2 1 read-only DLL_SSL[6] MPDDRC DLL Status Slave 0 Register 0x994 32 read-only n 0x0 0x0 SDCNT SLAVEx Delay Counter Value 8 8 read-only SDCOVF SLAVEx Delay Correction Overflow Flag 0 1 read-only SDCUDF SLAVEx Delay Correction Underflow Flag 1 1 read-only SDCVAL SLAVEx Delay Correction Value 20 8 read-only SDERF SLAVEx Delay Correction Error Flag 2 1 read-only DLL_SSL[7] MPDDRC DLL Status Slave 0 Register 0xAD8 32 read-only n 0x0 0x0 SDCNT SLAVEx Delay Counter Value 8 8 read-only SDCOVF SLAVEx Delay Correction Overflow Flag 0 1 read-only SDCUDF SLAVEx Delay Correction Underflow Flag 1 1 read-only SDCVAL SLAVEx Delay Correction Value 20 8 read-only SDERF SLAVEx Delay Correction Error Flag 2 1 read-only DLL_SWR0 MPDDRC DLL Status CLKWR 0 Register 0x148 32 read-only n WRDCNT CLKWRx Delay Counter Value 0 8 read-only DLL_SWR1 MPDDRC DLL Status CLKWR 0 Register 0x14C 32 read-only n WRDCNT CLKWRx Delay Counter Value 0 8 read-only DLL_SWR2 MPDDRC DLL Status CLKWR 0 Register 0x150 32 read-only n WRDCNT CLKWRx Delay Counter Value 0 8 read-only DLL_SWR3 MPDDRC DLL Status CLKWR 0 Register 0x154 32 read-only n WRDCNT CLKWRx Delay Counter Value 0 8 read-only DLL_SWR[0] MPDDRC DLL Status CLKWR 0 Register 0x290 32 read-only n 0x0 0x0 WRDCNT CLKWRx Delay Counter Value 0 8 read-only DLL_SWR[1] MPDDRC DLL Status CLKWR 0 Register 0x3DC 32 read-only n 0x0 0x0 WRDCNT CLKWRx Delay Counter Value 0 8 read-only DLL_SWR[2] MPDDRC DLL Status CLKWR 0 Register 0x52C 32 read-only n 0x0 0x0 WRDCNT CLKWRx Delay Counter Value 0 8 read-only DLL_SWR[3] MPDDRC DLL Status CLKWR 0 Register 0x680 32 read-only n 0x0 0x0 WRDCNT CLKWRx Delay Counter Value 0 8 read-only DLL_WRO MPDDRC DLL CLKWR Offset Register 0x110 32 read-write n 0x0 0x0 WR0OFF CLKWRx Delay Line Offset 0 8 read-write WR1OFF CLKWRx Delay Line Offset 8 8 read-write WR2OFF CLKWRx Delay Line Offset 16 8 read-write WR3OFF CLKWRx Delay Line Offset 24 8 read-write IO_CALIBR MPDDRC I/O Calibration Register 0x34 32 read-write n 0x0 0x0 CALCODEN Number of Transistor N (read-only) 20 4 read-write CALCODEP Number of Transistor P (read-only) 16 4 read-write EN_CALIB Enable Calibration 4 1 read-write DISABLE_CALIBRATION Calibration is disabled. 0 ENABLE_CALIBRATION Calibration is enabled. 1 RDIV Resistor Divider, Output Driver Impedance 0 3 read-write RZQ_34 LPDDR2 serial impedance line = 34.3 ohms,DDR2/LPDDR1 serial impedance line: Not applicable 0x1 RZQ_40_RZQ_33_3 LPDDR2 serial impedance line = 40 ohms,DDR2/LPDDR1 serial impedance line = 33.3 ohms 0x2 RZQ_48_RZQ_40 LPDDR2 serial impedance line = 48 ohms,DDR2/LPDDR1 serial impedance line = 40 ohms 0x3 RZQ_60_RZQ_50 LPDDR2 serial impedance line = 60 ohms,DDR2/LPDDR1 serial impedance line = 50 ohms 0x4 RZQ_80_RZQ_66_7 LPDDR2 serial impedance line = 80 ohms,DDR2/LPDDR1 serial impedance line = 66.7 ohms 0x6 RZQ_120_RZQ_100 LPDDR2 serial impedance line = 120 ohms,DDR2/LPDDR1 serial impedance line = 100 ohms 0x7 TZQIO IO Calibration 8 3 read-write LPDDR2_CAL_MR4 MPDDRC Low-power DDR2 Calibration and MR4 Register 0x2C 32 read-write n 0x0 0x0 COUNT_CAL LPDDR2Calibration Timer Count 0 16 read-write MR4_READ Mode Register 4 Read Interval 16 16 read-write LPDDR2_LPR MPDDRC Low-power DDR2 Low-power Register 0x28 32 read-write n 0x0 0x0 BK_MASK_PASR Bank Mask Bit/PASR 0 8 read-write DS Drive Strength 24 4 read-write DS_34_3 34.3 ohm typical 0x1 DS_40 40 ohm typical (default) 0x2 DS_48 48 ohm typical 0x3 DS_60 60 ohm typical 0x4 DS_80 80 ohm typical 0x6 DS_120 120 ohm typical 0x7 SEG_MASK Segment Mask Bit 8 16 read-write LPDDR2_TIM_CAL MPDDRC Low-power DDR2 Timing Calibration Register 0x30 32 read-write n 0x0 0x0 ZQCS ZQ Calibration Short 0 8 read-write LPR MPDDRC Low-power Register 0x1C 32 read-write n 0x0 0x0 APDE Active Power Down Exit Time 16 1 read-write DDR2_FAST_EXIT Fast Exit from Power Down. DDR2-SDRAM devices only. 0 DDR2_SLOW_EXIT Slow Exit from Power Down. DDR2-SDRAM devices only. 1 CLK_FR Clock Frozen Command Bit 2 1 read-write DISABLED Clock(s) is/are not frozen. 0 ENABLED Clock(s) is/are frozen. 1 DS Drive Strength 8 3 read-write DS_FULL Full drive strength 0x0 DS_HALF Half drive strength 0x1 DS_QUARTER Quarter drive strength 0x2 DS_OCTANT Octant drive strength 0x3 LPCB Low-power Command Bit 0 2 read-write NOLOWPOWER Low-power feature is inhibited. No Powerdown, Self-refresh and Deep-power modes are issued to the DDR-SDRAM device. 0x0 SELFREFRESH The MPDDRC issues a self-refresh command to the DDR-SDRAM device, the clock(s) is/are deactivated and the CKE signal is set low. The DDR-SDRAM device leaves the Self-refresh mode when accessed and reenters it after the access. 0x1 POWERDOWN The MPDDRC issues a Powerdown command to the DDR-SDRAM device after each access, the CKE signal is set low. The DDR-SDRAM device leaves the Powerdown mode when accessed and reenters it after the access. 0x2 DEEPPOWERDOWN The MPDDRC issues a Deep Powerdown command to the low-power DDR-SDRAM device. 0x3 LPDDR2_PWOFF LPDDR2 - LPDDR3 Power Off Bit 3 1 read-write DISABLED No power-off sequence applied to LPDDR2. 0 ENABLED A power-off sequence is applied to the LPDDR2 device. CKE is forced low. 1 PASR Partial Array Self-refresh 4 3 read-write TIMEOUT Time Between Last Transfer and Low-Power Mode 12 2 read-write NONE SDRAM Low-power mode is activated immediately after the end of the last transfer. 0x0 DELAY_64_CLK SDRAM Low-power mode is activated 64 clock cycles after the end of the last transfer. 0x1 DELAY_128_CLK SDRAM Low-power mode is activated 128 clock cycles after the end of the last transfer. 0x2 UPD_MR Update Load Mode Register and Extended Mode Register 20 2 read-write NO_UPDATE Update of Load Mode and Extended Mode registers is disabled. 0x0 UPDATE_SHAREDBUS MPDDRC shares an external bus. Automatic update is done during a refresh command and a pending read or write access in the SDRAM device. 0x1 UPDATE_NOSHAREDBUS MPDDRC does not share an external bus. Automatic update is done before entering Self-refresh mode. 0x2 MD MPDDRC Memory Device Register 0x20 32 read-write n 0x0 0x0 DBW Data Bus Width 4 1 read-write DBW_32_BITS Data bus width is 32 bits 0 DBW_16_BITS Data bus width is 16 bits. 1 MD Memory Device 0 3 read-write LPDDR_SDRAM Low-power DDR1-SDRAM 0x3 DDR2_SDRAM DDR2-SDRAM 0x6 LPDDR2_SDRAM Low-power DDR2-SDRAM 0x7 MR MPDDRC Mode Register 0x0 32 read-write n 0x0 0x0 MODE MPDDRC Command Mode 0 3 read-write NORMAL_CMD Normal Mode. Any access to the MPDDRC is decoded normally. To activate this mode, the command must be followed by a write to the DDR-SDRAM. 0x0 NOP_CMD The MPDDRC issues a NOP command when the DDR-SDRAM device is accessed regardless of the cycle. To activate this mode, the command must be followed by a write to the DDR-SDRAM. 0x1 PRCGALL_CMD The MPDDRC issues the All Banks Precharge command when the DDR-SDRAM device is accessed regardless of the cycle. To activate this mode, the command must be followed by a write to the SDRAM. 0x2 LMR_CMD The MPDDRC issues a Load Mode Register command when the DDR-SDRAM device is accessed regardless of the cycle. To activate this mode, the command must be followed by a write to the DDR-SDRAM. 0x3 RFSH_CMD The MPDDRC issues an Auto-Refresh command when the DDR-SDRAM device is accessed regardless of the cycle. Previously, an All Banks Precharge command must be issued. To activate this mode, the command must be followed by a write to the DDR-SDRAM. 0x4 EXT_LMR_CMD The MPDDRC issues an Extended Load Mode Register command when the SDRAM device is accessed regardless of the cycle. To activate this mode, the command must be followed by a write to the DDR-SDRAM. The write in the DDR-SDRAM must be done in the appropriate bank. 0x5 DEEP_MD Deep Power mode: Access to Deep Powerdown mode 0x6 LPDDR2_CMD The MPDDRC issues an LPDDR2 Mode Register command when the device is accessed regardless of the cycle. To activate this mode, the Mode Register command must be followed by a write to the low-power DDR2-SDRAM. 0x7 MRS Mode Register Select LPDDR2 8 8 read-write OCMS MPDDRC OCMS Register 0x38 32 read-write n 0x0 0x0 SCR_EN Scrambling Enable 0 1 read-write OCMS_KEY1 MPDDRC OCMS KEY1 Register 0x3C 32 write-only n 0x0 0x0 KEY1 Off-chip Memory Scrambling (OCMS) Key Part 1 0 32 write-only OCMS_KEY2 MPDDRC OCMS KEY2 Register 0x40 32 write-only n 0x0 0x0 KEY2 Off-chip Memory Scrambling (OCMS) Key Part 2 0 32 write-only RD_DATA_PATH MPDDRC Read Data Path Register 0x5C 32 read-write n 0x0 0x0 SHIFT_SAMPLING Shift Sampling Point of Data 0 2 read-write NO_SHIFT Initial sampling point. 0x0 SHIFT_ONE_CYCLE Sampling point is shifted by one cycle. 0x1 SHIFT_TWO_CYCLES Sampling point is shifted by two cycles. 0x2 SHIFT_THREE_CYCLES Sampling point is shifted by three cycles, unique for LPDDR2.Not applicable for DDR2 and LPDDR1 devices. 0x3 REQ_PORT_0123 MPDDRC Request Port 0-1-2-3 Register 0x4C 32 read-write n 0x0 0x0 NRQ_NWD_BDW_P0 Number of Requests, Number of Words or Bandwidth Allocation from Port 0-1-2-3 0 8 read-write NRQ_NWD_BDW_P1 Number of Requests, Number of Words or Bandwidth Allocation from Port 0-1-2-3 8 8 read-write NRQ_NWD_BDW_P2 Number of Requests, Number of Words or Bandwidth Allocation from Port 0-1-2-3 16 8 read-write NRQ_NWD_BDW_P3 Number of Requests, Number of Words or Bandwidth Allocation from Port 0-1-2-3 24 8 read-write REQ_PORT_4567 MPDDRC Request Port 4-5-6-7 Register 0x50 32 read-write n 0x0 0x0 NRQ_NWD_BDW_P4 Number of Requests, Number of Words or Bandwidth allocation from port 4-5-6-7 0 8 read-write NRQ_NWD_BDW_P5 Number of Requests, Number of Words or Bandwidth allocation from port 4-5-6-7 8 8 read-write NRQ_NWD_BDW_P6 Number of Requests, Number of Words or Bandwidth allocation from port 4-5-6-7 16 8 read-write NRQ_NWD_BDW_P7 Number of Requests, Number of Words or Bandwidth allocation from port 4-5-6-7 24 8 read-write RTR MPDDRC Refresh Timer Register 0x4 32 read-write n 0x0 0x0 ADJ_REF Adjust Refresh Rate 16 1 read-write COUNT MPDDRC Refresh Timer Count 0 12 read-write MR4_VALUE Content of MR4 Register (read-only) 20 3 read-write REF_PB Refresh Per Bank 17 1 read-write TIMEOUT MPDDRC Timeout Register 0x48 32 read-write n 0x0 0x0 TIMEOUT_P0 Timeout for Ports 0, 1, 2, 3, 4, 5, 6 and 7 0 4 read-write TIMEOUT_P1 Timeout for Ports 0, 1, 2, 3, 4, 5, 6 and 7 4 4 read-write TIMEOUT_P2 Timeout for Ports 0, 1, 2, 3, 4, 5, 6 and 7 8 4 read-write TIMEOUT_P3 Timeout for Ports 0, 1, 2, 3, 4, 5, 6 and 7 12 4 read-write TIMEOUT_P4 Timeout for Ports 0, 1, 2, 3, 4, 5, 6 and 7 16 4 read-write TIMEOUT_P5 Timeout for Ports 0, 1, 2, 3, 4, 5, 6 and 7 20 4 read-write TIMEOUT_P6 Timeout for Ports 0, 1, 2, 3, 4, 5, 6 and 7 24 4 read-write TIMEOUT_P7 Timeout for Ports 0, 1, 2, 3, 4, 5, 6 and 7 28 4 read-write TPR0 MPDDRC Timing Parameter 0 Register 0xC 32 read-write n 0x0 0x0 TMRD Load Mode Register Command to Activate or Refresh Command 28 4 read-write TRAS Active to Precharge Delay 0 4 read-write TRC Row Cycle Delay 12 4 read-write TRCD Row to Column Delay 4 4 read-write TRP Row Precharge Delay 16 4 read-write TRRD Active BankA to Active BankB 20 4 read-write TWR Write Recovery Delay 8 4 read-write TWTR Internal Write to Read Delay 24 4 read-write TPR1 MPDDRC Timing Parameter 1 Register 0x10 32 read-write n 0x0 0x0 TRFC Row Cycle Delay 0 7 read-write TXP Exit Powerdown Delay to First Command 24 4 read-write TXSNR Exit Self-refresh Delay to Non-Read Command 8 8 read-write TXSRD Exit Self-refresh Delay to Read Command 16 8 read-write TPR2 MPDDRC Timing Parameter 2 Register 0x14 32 read-write n 0x0 0x0 TFAW Four Active Windows 16 4 read-write TRPA Row Precharge All Delay 8 4 read-write TRTP Read to Precharge 12 3 read-write TXARD Exit Active Power Down Delay to Read Command in Mode "Fast Exit" 0 4 read-write TXARDS Exit Active Power Down Delay to Read Command in Mode "Slow Exit" 4 4 read-write WPMR MPDDRC Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 read-write WPKEY Write Protection Key 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 0x444452 WPSR MPDDRC Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Enable 0 1 read-only WPVSRC Write Protection Violation Source 8 16 read-only PIOA Parallel Input/Output Controller A PIO 0x0 0x0 0x1000 registers n PIOA 23 ABCDSR0 Peripheral ABCD Select Register 0x70 32 read-write n P0 Peripheral Select 0 1 read-write P1 Peripheral Select 1 1 read-write P10 Peripheral Select 10 1 read-write P11 Peripheral Select 11 1 read-write P12 Peripheral Select 12 1 read-write P13 Peripheral Select 13 1 read-write P14 Peripheral Select 14 1 read-write P15 Peripheral Select 15 1 read-write P16 Peripheral Select 16 1 read-write P17 Peripheral Select 17 1 read-write P18 Peripheral Select 18 1 read-write P19 Peripheral Select 19 1 read-write P2 Peripheral Select 2 1 read-write P20 Peripheral Select 20 1 read-write P21 Peripheral Select 21 1 read-write P22 Peripheral Select 22 1 read-write P23 Peripheral Select 23 1 read-write P24 Peripheral Select 24 1 read-write P25 Peripheral Select 25 1 read-write P26 Peripheral Select 26 1 read-write P27 Peripheral Select 27 1 read-write P28 Peripheral Select 28 1 read-write P29 Peripheral Select 29 1 read-write P3 Peripheral Select 3 1 read-write P30 Peripheral Select 30 1 read-write P31 Peripheral Select 31 1 read-write P4 Peripheral Select 4 1 read-write P5 Peripheral Select 5 1 read-write P6 Peripheral Select 6 1 read-write P7 Peripheral Select 7 1 read-write P8 Peripheral Select 8 1 read-write P9 Peripheral Select 9 1 read-write ABCDSR1 Peripheral ABCD Select Register 0x74 32 read-write n P0 Peripheral Select 0 1 read-write P1 Peripheral Select 1 1 read-write P10 Peripheral Select 10 1 read-write P11 Peripheral Select 11 1 read-write P12 Peripheral Select 12 1 read-write P13 Peripheral Select 13 1 read-write P14 Peripheral Select 14 1 read-write P15 Peripheral Select 15 1 read-write P16 Peripheral Select 16 1 read-write P17 Peripheral Select 17 1 read-write P18 Peripheral Select 18 1 read-write P19 Peripheral Select 19 1 read-write P2 Peripheral Select 2 1 read-write P20 Peripheral Select 20 1 read-write P21 Peripheral Select 21 1 read-write P22 Peripheral Select 22 1 read-write P23 Peripheral Select 23 1 read-write P24 Peripheral Select 24 1 read-write P25 Peripheral Select 25 1 read-write P26 Peripheral Select 26 1 read-write P27 Peripheral Select 27 1 read-write P28 Peripheral Select 28 1 read-write P29 Peripheral Select 29 1 read-write P3 Peripheral Select 3 1 read-write P30 Peripheral Select 30 1 read-write P31 Peripheral Select 31 1 read-write P4 Peripheral Select 4 1 read-write P5 Peripheral Select 5 1 read-write P6 Peripheral Select 6 1 read-write P7 Peripheral Select 7 1 read-write P8 Peripheral Select 8 1 read-write P9 Peripheral Select 9 1 read-write ABCDSR[0] Peripheral ABCD Select Register 0xE0 32 read-write n 0x0 0x0 P0 Peripheral Select 0 1 read-write P1 Peripheral Select 1 1 read-write P10 Peripheral Select 10 1 read-write P11 Peripheral Select 11 1 read-write P12 Peripheral Select 12 1 read-write P13 Peripheral Select 13 1 read-write P14 Peripheral Select 14 1 read-write P15 Peripheral Select 15 1 read-write P16 Peripheral Select 16 1 read-write P17 Peripheral Select 17 1 read-write P18 Peripheral Select 18 1 read-write P19 Peripheral Select 19 1 read-write P2 Peripheral Select 2 1 read-write P20 Peripheral Select 20 1 read-write P21 Peripheral Select 21 1 read-write P22 Peripheral Select 22 1 read-write P23 Peripheral Select 23 1 read-write P24 Peripheral Select 24 1 read-write P25 Peripheral Select 25 1 read-write P26 Peripheral Select 26 1 read-write P27 Peripheral Select 27 1 read-write P28 Peripheral Select 28 1 read-write P29 Peripheral Select 29 1 read-write P3 Peripheral Select 3 1 read-write P30 Peripheral Select 30 1 read-write P31 Peripheral Select 31 1 read-write P4 Peripheral Select 4 1 read-write P5 Peripheral Select 5 1 read-write P6 Peripheral Select 6 1 read-write P7 Peripheral Select 7 1 read-write P8 Peripheral Select 8 1 read-write P9 Peripheral Select 9 1 read-write ABCDSR[1] Peripheral ABCD Select Register 0x154 32 read-write n 0x0 0x0 P0 Peripheral Select 0 1 read-write P1 Peripheral Select 1 1 read-write P10 Peripheral Select 10 1 read-write P11 Peripheral Select 11 1 read-write P12 Peripheral Select 12 1 read-write P13 Peripheral Select 13 1 read-write P14 Peripheral Select 14 1 read-write P15 Peripheral Select 15 1 read-write P16 Peripheral Select 16 1 read-write P17 Peripheral Select 17 1 read-write P18 Peripheral Select 18 1 read-write P19 Peripheral Select 19 1 read-write P2 Peripheral Select 2 1 read-write P20 Peripheral Select 20 1 read-write P21 Peripheral Select 21 1 read-write P22 Peripheral Select 22 1 read-write P23 Peripheral Select 23 1 read-write P24 Peripheral Select 24 1 read-write P25 Peripheral Select 25 1 read-write P26 Peripheral Select 26 1 read-write P27 Peripheral Select 27 1 read-write P28 Peripheral Select 28 1 read-write P29 Peripheral Select 29 1 read-write P3 Peripheral Select 3 1 read-write P30 Peripheral Select 30 1 read-write P31 Peripheral Select 31 1 read-write P4 Peripheral Select 4 1 read-write P5 Peripheral Select 5 1 read-write P6 Peripheral Select 6 1 read-write P7 Peripheral Select 7 1 read-write P8 Peripheral Select 8 1 read-write P9 Peripheral Select 9 1 read-write AIMDR Additional Interrupt Modes Disable Register 0xB4 32 write-only n 0x0 0x0 P0 Additional Interrupt Modes Disable 0 1 write-only P1 Additional Interrupt Modes Disable 1 1 write-only P10 Additional Interrupt Modes Disable 10 1 write-only P11 Additional Interrupt Modes Disable 11 1 write-only P12 Additional Interrupt Modes Disable 12 1 write-only P13 Additional Interrupt Modes Disable 13 1 write-only P14 Additional Interrupt Modes Disable 14 1 write-only P15 Additional Interrupt Modes Disable 15 1 write-only P16 Additional Interrupt Modes Disable 16 1 write-only P17 Additional Interrupt Modes Disable 17 1 write-only P18 Additional Interrupt Modes Disable 18 1 write-only P19 Additional Interrupt Modes Disable 19 1 write-only P2 Additional Interrupt Modes Disable 2 1 write-only P20 Additional Interrupt Modes Disable 20 1 write-only P21 Additional Interrupt Modes Disable 21 1 write-only P22 Additional Interrupt Modes Disable 22 1 write-only P23 Additional Interrupt Modes Disable 23 1 write-only P24 Additional Interrupt Modes Disable 24 1 write-only P25 Additional Interrupt Modes Disable 25 1 write-only P26 Additional Interrupt Modes Disable 26 1 write-only P27 Additional Interrupt Modes Disable 27 1 write-only P28 Additional Interrupt Modes Disable 28 1 write-only P29 Additional Interrupt Modes Disable 29 1 write-only P3 Additional Interrupt Modes Disable 3 1 write-only P30 Additional Interrupt Modes Disable 30 1 write-only P31 Additional Interrupt Modes Disable 31 1 write-only P4 Additional Interrupt Modes Disable 4 1 write-only P5 Additional Interrupt Modes Disable 5 1 write-only P6 Additional Interrupt Modes Disable 6 1 write-only P7 Additional Interrupt Modes Disable 7 1 write-only P8 Additional Interrupt Modes Disable 8 1 write-only P9 Additional Interrupt Modes Disable 9 1 write-only AIMER Additional Interrupt Modes Enable Register 0xB0 32 write-only n 0x0 0x0 P0 Additional Interrupt Modes Enable 0 1 write-only P1 Additional Interrupt Modes Enable 1 1 write-only P10 Additional Interrupt Modes Enable 10 1 write-only P11 Additional Interrupt Modes Enable 11 1 write-only P12 Additional Interrupt Modes Enable 12 1 write-only P13 Additional Interrupt Modes Enable 13 1 write-only P14 Additional Interrupt Modes Enable 14 1 write-only P15 Additional Interrupt Modes Enable 15 1 write-only P16 Additional Interrupt Modes Enable 16 1 write-only P17 Additional Interrupt Modes Enable 17 1 write-only P18 Additional Interrupt Modes Enable 18 1 write-only P19 Additional Interrupt Modes Enable 19 1 write-only P2 Additional Interrupt Modes Enable 2 1 write-only P20 Additional Interrupt Modes Enable 20 1 write-only P21 Additional Interrupt Modes Enable 21 1 write-only P22 Additional Interrupt Modes Enable 22 1 write-only P23 Additional Interrupt Modes Enable 23 1 write-only P24 Additional Interrupt Modes Enable 24 1 write-only P25 Additional Interrupt Modes Enable 25 1 write-only P26 Additional Interrupt Modes Enable 26 1 write-only P27 Additional Interrupt Modes Enable 27 1 write-only P28 Additional Interrupt Modes Enable 28 1 write-only P29 Additional Interrupt Modes Enable 29 1 write-only P3 Additional Interrupt Modes Enable 3 1 write-only P30 Additional Interrupt Modes Enable 30 1 write-only P31 Additional Interrupt Modes Enable 31 1 write-only P4 Additional Interrupt Modes Enable 4 1 write-only P5 Additional Interrupt Modes Enable 5 1 write-only P6 Additional Interrupt Modes Enable 6 1 write-only P7 Additional Interrupt Modes Enable 7 1 write-only P8 Additional Interrupt Modes Enable 8 1 write-only P9 Additional Interrupt Modes Enable 9 1 write-only AIMMR Additional Interrupt Modes Mask Register 0xB8 32 read-only n 0x0 0x0 P0 IO Line Index 0 1 read-only P1 IO Line Index 1 1 read-only P10 IO Line Index 10 1 read-only P11 IO Line Index 11 1 read-only P12 IO Line Index 12 1 read-only P13 IO Line Index 13 1 read-only P14 IO Line Index 14 1 read-only P15 IO Line Index 15 1 read-only P16 IO Line Index 16 1 read-only P17 IO Line Index 17 1 read-only P18 IO Line Index 18 1 read-only P19 IO Line Index 19 1 read-only P2 IO Line Index 2 1 read-only P20 IO Line Index 20 1 read-only P21 IO Line Index 21 1 read-only P22 IO Line Index 22 1 read-only P23 IO Line Index 23 1 read-only P24 IO Line Index 24 1 read-only P25 IO Line Index 25 1 read-only P26 IO Line Index 26 1 read-only P27 IO Line Index 27 1 read-only P28 IO Line Index 28 1 read-only P29 IO Line Index 29 1 read-only P3 IO Line Index 3 1 read-only P30 IO Line Index 30 1 read-only P31 IO Line Index 31 1 read-only P4 IO Line Index 4 1 read-only P5 IO Line Index 5 1 read-only P6 IO Line Index 6 1 read-only P7 IO Line Index 7 1 read-only P8 IO Line Index 8 1 read-only P9 IO Line Index 9 1 read-only CODR Clear Output Data Register 0x34 32 write-only n 0x0 0x0 P0 Clear Output Data 0 1 write-only P1 Clear Output Data 1 1 write-only P10 Clear Output Data 10 1 write-only P11 Clear Output Data 11 1 write-only P12 Clear Output Data 12 1 write-only P13 Clear Output Data 13 1 write-only P14 Clear Output Data 14 1 write-only P15 Clear Output Data 15 1 write-only P16 Clear Output Data 16 1 write-only P17 Clear Output Data 17 1 write-only P18 Clear Output Data 18 1 write-only P19 Clear Output Data 19 1 write-only P2 Clear Output Data 2 1 write-only P20 Clear Output Data 20 1 write-only P21 Clear Output Data 21 1 write-only P22 Clear Output Data 22 1 write-only P23 Clear Output Data 23 1 write-only P24 Clear Output Data 24 1 write-only P25 Clear Output Data 25 1 write-only P26 Clear Output Data 26 1 write-only P27 Clear Output Data 27 1 write-only P28 Clear Output Data 28 1 write-only P29 Clear Output Data 29 1 write-only P3 Clear Output Data 3 1 write-only P30 Clear Output Data 30 1 write-only P31 Clear Output Data 31 1 write-only P4 Clear Output Data 4 1 write-only P5 Clear Output Data 5 1 write-only P6 Clear Output Data 6 1 write-only P7 Clear Output Data 7 1 write-only P8 Clear Output Data 8 1 write-only P9 Clear Output Data 9 1 write-only DRIVER1 I/O Drive Register 1 0x118 32 read-write n 0x0 0x0 LINE0 Drive of PIO Line 0 0 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE1 Drive of PIO Line 1 2 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE10 Drive of PIO Line 10 20 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE11 Drive of PIO Line 11 22 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE12 Drive of PIO Line 12 24 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE13 Drive of PIO Line 13 26 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE14 Drive of PIO Line 14 28 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE15 Drive of PIO Line 15 30 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE2 Drive of PIO Line 2 4 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE3 Drive of PIO Line 3 6 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE4 Drive of PIO Line 4 8 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE5 Drive of PIO Line 5 10 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE6 Drive of PIO Line 6 12 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE7 Drive of PIO Line 7 14 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE8 Drive of PIO Line 8 16 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE9 Drive of PIO Line 9 18 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 DRIVER2 I/O Drive Register 2 0x11C 32 read-write n 0x0 0x0 LINE16 Drive of PIO line 16 0 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE17 Drive of PIO line 17 2 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE18 Drive of PIO line 18 4 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE19 Drive of PIO line 19 6 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE20 Drive of PIO line 20 8 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE21 Drive of PIO line 21 10 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE22 Drive of PIO line 22 12 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE23 Drive of PIO line 23 14 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE24 Drive of PIO line 24 16 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE25 Drive of PIO line 25 18 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE26 Drive of PIO line 26 20 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE27 Drive of PIO line 27 22 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE28 Drive of PIO line 28 24 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE29 Drive of PIO line 29 26 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE30 Drive of PIO line 30 28 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE31 Drive of PIO line 31 30 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 ELSR Edge/Level Status Register 0xC8 32 read-only n 0x0 0x0 P0 Edge/Level Interrupt Source Selection 0 1 read-only P1 Edge/Level Interrupt Source Selection 1 1 read-only P10 Edge/Level Interrupt Source Selection 10 1 read-only P11 Edge/Level Interrupt Source Selection 11 1 read-only P12 Edge/Level Interrupt Source Selection 12 1 read-only P13 Edge/Level Interrupt Source Selection 13 1 read-only P14 Edge/Level Interrupt Source Selection 14 1 read-only P15 Edge/Level Interrupt Source Selection 15 1 read-only P16 Edge/Level Interrupt Source Selection 16 1 read-only P17 Edge/Level Interrupt Source Selection 17 1 read-only P18 Edge/Level Interrupt Source Selection 18 1 read-only P19 Edge/Level Interrupt Source Selection 19 1 read-only P2 Edge/Level Interrupt Source Selection 2 1 read-only P20 Edge/Level Interrupt Source Selection 20 1 read-only P21 Edge/Level Interrupt Source Selection 21 1 read-only P22 Edge/Level Interrupt Source Selection 22 1 read-only P23 Edge/Level Interrupt Source Selection 23 1 read-only P24 Edge/Level Interrupt Source Selection 24 1 read-only P25 Edge/Level Interrupt Source Selection 25 1 read-only P26 Edge/Level Interrupt Source Selection 26 1 read-only P27 Edge/Level Interrupt Source Selection 27 1 read-only P28 Edge/Level Interrupt Source Selection 28 1 read-only P29 Edge/Level Interrupt Source Selection 29 1 read-only P3 Edge/Level Interrupt Source Selection 3 1 read-only P30 Edge/Level Interrupt Source Selection 30 1 read-only P31 Edge/Level Interrupt Source Selection 31 1 read-only P4 Edge/Level Interrupt Source Selection 4 1 read-only P5 Edge/Level Interrupt Source Selection 5 1 read-only P6 Edge/Level Interrupt Source Selection 6 1 read-only P7 Edge/Level Interrupt Source Selection 7 1 read-only P8 Edge/Level Interrupt Source Selection 8 1 read-only P9 Edge/Level Interrupt Source Selection 9 1 read-only ESR Edge Select Register 0xC0 32 write-only n 0x0 0x0 P0 Edge Interrupt Selection 0 1 write-only P1 Edge Interrupt Selection 1 1 write-only P10 Edge Interrupt Selection 10 1 write-only P11 Edge Interrupt Selection 11 1 write-only P12 Edge Interrupt Selection 12 1 write-only P13 Edge Interrupt Selection 13 1 write-only P14 Edge Interrupt Selection 14 1 write-only P15 Edge Interrupt Selection 15 1 write-only P16 Edge Interrupt Selection 16 1 write-only P17 Edge Interrupt Selection 17 1 write-only P18 Edge Interrupt Selection 18 1 write-only P19 Edge Interrupt Selection 19 1 write-only P2 Edge Interrupt Selection 2 1 write-only P20 Edge Interrupt Selection 20 1 write-only P21 Edge Interrupt Selection 21 1 write-only P22 Edge Interrupt Selection 22 1 write-only P23 Edge Interrupt Selection 23 1 write-only P24 Edge Interrupt Selection 24 1 write-only P25 Edge Interrupt Selection 25 1 write-only P26 Edge Interrupt Selection 26 1 write-only P27 Edge Interrupt Selection 27 1 write-only P28 Edge Interrupt Selection 28 1 write-only P29 Edge Interrupt Selection 29 1 write-only P3 Edge Interrupt Selection 3 1 write-only P30 Edge Interrupt Selection 30 1 write-only P31 Edge Interrupt Selection 31 1 write-only P4 Edge Interrupt Selection 4 1 write-only P5 Edge Interrupt Selection 5 1 write-only P6 Edge Interrupt Selection 6 1 write-only P7 Edge Interrupt Selection 7 1 write-only P8 Edge Interrupt Selection 8 1 write-only P9 Edge Interrupt Selection 9 1 write-only FELLSR Falling Edge/Low-Level Select Register 0xD0 32 write-only n 0x0 0x0 P0 Falling Edge/Low-Level Interrupt Selection 0 1 write-only P1 Falling Edge/Low-Level Interrupt Selection 1 1 write-only P10 Falling Edge/Low-Level Interrupt Selection 10 1 write-only P11 Falling Edge/Low-Level Interrupt Selection 11 1 write-only P12 Falling Edge/Low-Level Interrupt Selection 12 1 write-only P13 Falling Edge/Low-Level Interrupt Selection 13 1 write-only P14 Falling Edge/Low-Level Interrupt Selection 14 1 write-only P15 Falling Edge/Low-Level Interrupt Selection 15 1 write-only P16 Falling Edge/Low-Level Interrupt Selection 16 1 write-only P17 Falling Edge/Low-Level Interrupt Selection 17 1 write-only P18 Falling Edge/Low-Level Interrupt Selection 18 1 write-only P19 Falling Edge/Low-Level Interrupt Selection 19 1 write-only P2 Falling Edge/Low-Level Interrupt Selection 2 1 write-only P20 Falling Edge/Low-Level Interrupt Selection 20 1 write-only P21 Falling Edge/Low-Level Interrupt Selection 21 1 write-only P22 Falling Edge/Low-Level Interrupt Selection 22 1 write-only P23 Falling Edge/Low-Level Interrupt Selection 23 1 write-only P24 Falling Edge/Low-Level Interrupt Selection 24 1 write-only P25 Falling Edge/Low-Level Interrupt Selection 25 1 write-only P26 Falling Edge/Low-Level Interrupt Selection 26 1 write-only P27 Falling Edge/Low-Level Interrupt Selection 27 1 write-only P28 Falling Edge/Low-Level Interrupt Selection 28 1 write-only P29 Falling Edge/Low-Level Interrupt Selection 29 1 write-only P3 Falling Edge/Low-Level Interrupt Selection 3 1 write-only P30 Falling Edge/Low-Level Interrupt Selection 30 1 write-only P31 Falling Edge/Low-Level Interrupt Selection 31 1 write-only P4 Falling Edge/Low-Level Interrupt Selection 4 1 write-only P5 Falling Edge/Low-Level Interrupt Selection 5 1 write-only P6 Falling Edge/Low-Level Interrupt Selection 6 1 write-only P7 Falling Edge/Low-Level Interrupt Selection 7 1 write-only P8 Falling Edge/Low-Level Interrupt Selection 8 1 write-only P9 Falling Edge/Low-Level Interrupt Selection 9 1 write-only FRLHSR Fall/Rise - Low/High Status Register 0xD8 32 read-only n 0x0 0x0 P0 Edge/Level Interrupt Source Selection 0 1 read-only P1 Edge/Level Interrupt Source Selection 1 1 read-only P10 Edge/Level Interrupt Source Selection 10 1 read-only P11 Edge/Level Interrupt Source Selection 11 1 read-only P12 Edge/Level Interrupt Source Selection 12 1 read-only P13 Edge/Level Interrupt Source Selection 13 1 read-only P14 Edge/Level Interrupt Source Selection 14 1 read-only P15 Edge/Level Interrupt Source Selection 15 1 read-only P16 Edge/Level Interrupt Source Selection 16 1 read-only P17 Edge/Level Interrupt Source Selection 17 1 read-only P18 Edge/Level Interrupt Source Selection 18 1 read-only P19 Edge/Level Interrupt Source Selection 19 1 read-only P2 Edge/Level Interrupt Source Selection 2 1 read-only P20 Edge/Level Interrupt Source Selection 20 1 read-only P21 Edge/Level Interrupt Source Selection 21 1 read-only P22 Edge/Level Interrupt Source Selection 22 1 read-only P23 Edge/Level Interrupt Source Selection 23 1 read-only P24 Edge/Level Interrupt Source Selection 24 1 read-only P25 Edge/Level Interrupt Source Selection 25 1 read-only P26 Edge/Level Interrupt Source Selection 26 1 read-only P27 Edge/Level Interrupt Source Selection 27 1 read-only P28 Edge/Level Interrupt Source Selection 28 1 read-only P29 Edge/Level Interrupt Source Selection 29 1 read-only P3 Edge/Level Interrupt Source Selection 3 1 read-only P30 Edge/Level Interrupt Source Selection 30 1 read-only P31 Edge/Level Interrupt Source Selection 31 1 read-only P4 Edge/Level Interrupt Source Selection 4 1 read-only P5 Edge/Level Interrupt Source Selection 5 1 read-only P6 Edge/Level Interrupt Source Selection 6 1 read-only P7 Edge/Level Interrupt Source Selection 7 1 read-only P8 Edge/Level Interrupt Source Selection 8 1 read-only P9 Edge/Level Interrupt Source Selection 9 1 read-only IDR Interrupt Disable Register 0x44 32 write-only n 0x0 0x0 P0 Input Change Interrupt Disable 0 1 write-only P1 Input Change Interrupt Disable 1 1 write-only P10 Input Change Interrupt Disable 10 1 write-only P11 Input Change Interrupt Disable 11 1 write-only P12 Input Change Interrupt Disable 12 1 write-only P13 Input Change Interrupt Disable 13 1 write-only P14 Input Change Interrupt Disable 14 1 write-only P15 Input Change Interrupt Disable 15 1 write-only P16 Input Change Interrupt Disable 16 1 write-only P17 Input Change Interrupt Disable 17 1 write-only P18 Input Change Interrupt Disable 18 1 write-only P19 Input Change Interrupt Disable 19 1 write-only P2 Input Change Interrupt Disable 2 1 write-only P20 Input Change Interrupt Disable 20 1 write-only P21 Input Change Interrupt Disable 21 1 write-only P22 Input Change Interrupt Disable 22 1 write-only P23 Input Change Interrupt Disable 23 1 write-only P24 Input Change Interrupt Disable 24 1 write-only P25 Input Change Interrupt Disable 25 1 write-only P26 Input Change Interrupt Disable 26 1 write-only P27 Input Change Interrupt Disable 27 1 write-only P28 Input Change Interrupt Disable 28 1 write-only P29 Input Change Interrupt Disable 29 1 write-only P3 Input Change Interrupt Disable 3 1 write-only P30 Input Change Interrupt Disable 30 1 write-only P31 Input Change Interrupt Disable 31 1 write-only P4 Input Change Interrupt Disable 4 1 write-only P5 Input Change Interrupt Disable 5 1 write-only P6 Input Change Interrupt Disable 6 1 write-only P7 Input Change Interrupt Disable 7 1 write-only P8 Input Change Interrupt Disable 8 1 write-only P9 Input Change Interrupt Disable 9 1 write-only IER Interrupt Enable Register 0x40 32 write-only n 0x0 0x0 P0 Input Change Interrupt Enable 0 1 write-only P1 Input Change Interrupt Enable 1 1 write-only P10 Input Change Interrupt Enable 10 1 write-only P11 Input Change Interrupt Enable 11 1 write-only P12 Input Change Interrupt Enable 12 1 write-only P13 Input Change Interrupt Enable 13 1 write-only P14 Input Change Interrupt Enable 14 1 write-only P15 Input Change Interrupt Enable 15 1 write-only P16 Input Change Interrupt Enable 16 1 write-only P17 Input Change Interrupt Enable 17 1 write-only P18 Input Change Interrupt Enable 18 1 write-only P19 Input Change Interrupt Enable 19 1 write-only P2 Input Change Interrupt Enable 2 1 write-only P20 Input Change Interrupt Enable 20 1 write-only P21 Input Change Interrupt Enable 21 1 write-only P22 Input Change Interrupt Enable 22 1 write-only P23 Input Change Interrupt Enable 23 1 write-only P24 Input Change Interrupt Enable 24 1 write-only P25 Input Change Interrupt Enable 25 1 write-only P26 Input Change Interrupt Enable 26 1 write-only P27 Input Change Interrupt Enable 27 1 write-only P28 Input Change Interrupt Enable 28 1 write-only P29 Input Change Interrupt Enable 29 1 write-only P3 Input Change Interrupt Enable 3 1 write-only P30 Input Change Interrupt Enable 30 1 write-only P31 Input Change Interrupt Enable 31 1 write-only P4 Input Change Interrupt Enable 4 1 write-only P5 Input Change Interrupt Enable 5 1 write-only P6 Input Change Interrupt Enable 6 1 write-only P7 Input Change Interrupt Enable 7 1 write-only P8 Input Change Interrupt Enable 8 1 write-only P9 Input Change Interrupt Enable 9 1 write-only IFDR Glitch Input Filter Disable Register 0x24 32 write-only n 0x0 0x0 P0 Input Filter Disable 0 1 write-only P1 Input Filter Disable 1 1 write-only P10 Input Filter Disable 10 1 write-only P11 Input Filter Disable 11 1 write-only P12 Input Filter Disable 12 1 write-only P13 Input Filter Disable 13 1 write-only P14 Input Filter Disable 14 1 write-only P15 Input Filter Disable 15 1 write-only P16 Input Filter Disable 16 1 write-only P17 Input Filter Disable 17 1 write-only P18 Input Filter Disable 18 1 write-only P19 Input Filter Disable 19 1 write-only P2 Input Filter Disable 2 1 write-only P20 Input Filter Disable 20 1 write-only P21 Input Filter Disable 21 1 write-only P22 Input Filter Disable 22 1 write-only P23 Input Filter Disable 23 1 write-only P24 Input Filter Disable 24 1 write-only P25 Input Filter Disable 25 1 write-only P26 Input Filter Disable 26 1 write-only P27 Input Filter Disable 27 1 write-only P28 Input Filter Disable 28 1 write-only P29 Input Filter Disable 29 1 write-only P3 Input Filter Disable 3 1 write-only P30 Input Filter Disable 30 1 write-only P31 Input Filter Disable 31 1 write-only P4 Input Filter Disable 4 1 write-only P5 Input Filter Disable 5 1 write-only P6 Input Filter Disable 6 1 write-only P7 Input Filter Disable 7 1 write-only P8 Input Filter Disable 8 1 write-only P9 Input Filter Disable 9 1 write-only IFER Glitch Input Filter Enable Register 0x20 32 write-only n 0x0 0x0 P0 Input Filter Enable 0 1 write-only P1 Input Filter Enable 1 1 write-only P10 Input Filter Enable 10 1 write-only P11 Input Filter Enable 11 1 write-only P12 Input Filter Enable 12 1 write-only P13 Input Filter Enable 13 1 write-only P14 Input Filter Enable 14 1 write-only P15 Input Filter Enable 15 1 write-only P16 Input Filter Enable 16 1 write-only P17 Input Filter Enable 17 1 write-only P18 Input Filter Enable 18 1 write-only P19 Input Filter Enable 19 1 write-only P2 Input Filter Enable 2 1 write-only P20 Input Filter Enable 20 1 write-only P21 Input Filter Enable 21 1 write-only P22 Input Filter Enable 22 1 write-only P23 Input Filter Enable 23 1 write-only P24 Input Filter Enable 24 1 write-only P25 Input Filter Enable 25 1 write-only P26 Input Filter Enable 26 1 write-only P27 Input Filter Enable 27 1 write-only P28 Input Filter Enable 28 1 write-only P29 Input Filter Enable 29 1 write-only P3 Input Filter Enable 3 1 write-only P30 Input Filter Enable 30 1 write-only P31 Input Filter Enable 31 1 write-only P4 Input Filter Enable 4 1 write-only P5 Input Filter Enable 5 1 write-only P6 Input Filter Enable 6 1 write-only P7 Input Filter Enable 7 1 write-only P8 Input Filter Enable 8 1 write-only P9 Input Filter Enable 9 1 write-only IFSCDR Input Filter Slow Clock Disable Register 0x80 32 write-only n 0x0 0x0 P0 Peripheral Clock Glitch Filtering Select 0 1 write-only P1 Peripheral Clock Glitch Filtering Select 1 1 write-only P10 Peripheral Clock Glitch Filtering Select 10 1 write-only P11 Peripheral Clock Glitch Filtering Select 11 1 write-only P12 Peripheral Clock Glitch Filtering Select 12 1 write-only P13 Peripheral Clock Glitch Filtering Select 13 1 write-only P14 Peripheral Clock Glitch Filtering Select 14 1 write-only P15 Peripheral Clock Glitch Filtering Select 15 1 write-only P16 Peripheral Clock Glitch Filtering Select 16 1 write-only P17 Peripheral Clock Glitch Filtering Select 17 1 write-only P18 Peripheral Clock Glitch Filtering Select 18 1 write-only P19 Peripheral Clock Glitch Filtering Select 19 1 write-only P2 Peripheral Clock Glitch Filtering Select 2 1 write-only P20 Peripheral Clock Glitch Filtering Select 20 1 write-only P21 Peripheral Clock Glitch Filtering Select 21 1 write-only P22 Peripheral Clock Glitch Filtering Select 22 1 write-only P23 Peripheral Clock Glitch Filtering Select 23 1 write-only P24 Peripheral Clock Glitch Filtering Select 24 1 write-only P25 Peripheral Clock Glitch Filtering Select 25 1 write-only P26 Peripheral Clock Glitch Filtering Select 26 1 write-only P27 Peripheral Clock Glitch Filtering Select 27 1 write-only P28 Peripheral Clock Glitch Filtering Select 28 1 write-only P29 Peripheral Clock Glitch Filtering Select 29 1 write-only P3 Peripheral Clock Glitch Filtering Select 3 1 write-only P30 Peripheral Clock Glitch Filtering Select 30 1 write-only P31 Peripheral Clock Glitch Filtering Select 31 1 write-only P4 Peripheral Clock Glitch Filtering Select 4 1 write-only P5 Peripheral Clock Glitch Filtering Select 5 1 write-only P6 Peripheral Clock Glitch Filtering Select 6 1 write-only P7 Peripheral Clock Glitch Filtering Select 7 1 write-only P8 Peripheral Clock Glitch Filtering Select 8 1 write-only P9 Peripheral Clock Glitch Filtering Select 9 1 write-only IFSCER Input Filter Slow Clock Enable Register 0x84 32 write-only n 0x0 0x0 P0 Slow Clock Debouncing Filtering Select 0 1 write-only P1 Slow Clock Debouncing Filtering Select 1 1 write-only P10 Slow Clock Debouncing Filtering Select 10 1 write-only P11 Slow Clock Debouncing Filtering Select 11 1 write-only P12 Slow Clock Debouncing Filtering Select 12 1 write-only P13 Slow Clock Debouncing Filtering Select 13 1 write-only P14 Slow Clock Debouncing Filtering Select 14 1 write-only P15 Slow Clock Debouncing Filtering Select 15 1 write-only P16 Slow Clock Debouncing Filtering Select 16 1 write-only P17 Slow Clock Debouncing Filtering Select 17 1 write-only P18 Slow Clock Debouncing Filtering Select 18 1 write-only P19 Slow Clock Debouncing Filtering Select 19 1 write-only P2 Slow Clock Debouncing Filtering Select 2 1 write-only P20 Slow Clock Debouncing Filtering Select 20 1 write-only P21 Slow Clock Debouncing Filtering Select 21 1 write-only P22 Slow Clock Debouncing Filtering Select 22 1 write-only P23 Slow Clock Debouncing Filtering Select 23 1 write-only P24 Slow Clock Debouncing Filtering Select 24 1 write-only P25 Slow Clock Debouncing Filtering Select 25 1 write-only P26 Slow Clock Debouncing Filtering Select 26 1 write-only P27 Slow Clock Debouncing Filtering Select 27 1 write-only P28 Slow Clock Debouncing Filtering Select 28 1 write-only P29 Slow Clock Debouncing Filtering Select 29 1 write-only P3 Slow Clock Debouncing Filtering Select 3 1 write-only P30 Slow Clock Debouncing Filtering Select 30 1 write-only P31 Slow Clock Debouncing Filtering Select 31 1 write-only P4 Slow Clock Debouncing Filtering Select 4 1 write-only P5 Slow Clock Debouncing Filtering Select 5 1 write-only P6 Slow Clock Debouncing Filtering Select 6 1 write-only P7 Slow Clock Debouncing Filtering Select 7 1 write-only P8 Slow Clock Debouncing Filtering Select 8 1 write-only P9 Slow Clock Debouncing Filtering Select 9 1 write-only IFSCSR Input Filter Slow Clock Status Register 0x88 32 read-only n 0x0 0x0 P0 Glitch or Debouncing Filter Selection Status 0 1 read-only P1 Glitch or Debouncing Filter Selection Status 1 1 read-only P10 Glitch or Debouncing Filter Selection Status 10 1 read-only P11 Glitch or Debouncing Filter Selection Status 11 1 read-only P12 Glitch or Debouncing Filter Selection Status 12 1 read-only P13 Glitch or Debouncing Filter Selection Status 13 1 read-only P14 Glitch or Debouncing Filter Selection Status 14 1 read-only P15 Glitch or Debouncing Filter Selection Status 15 1 read-only P16 Glitch or Debouncing Filter Selection Status 16 1 read-only P17 Glitch or Debouncing Filter Selection Status 17 1 read-only P18 Glitch or Debouncing Filter Selection Status 18 1 read-only P19 Glitch or Debouncing Filter Selection Status 19 1 read-only P2 Glitch or Debouncing Filter Selection Status 2 1 read-only P20 Glitch or Debouncing Filter Selection Status 20 1 read-only P21 Glitch or Debouncing Filter Selection Status 21 1 read-only P22 Glitch or Debouncing Filter Selection Status 22 1 read-only P23 Glitch or Debouncing Filter Selection Status 23 1 read-only P24 Glitch or Debouncing Filter Selection Status 24 1 read-only P25 Glitch or Debouncing Filter Selection Status 25 1 read-only P26 Glitch or Debouncing Filter Selection Status 26 1 read-only P27 Glitch or Debouncing Filter Selection Status 27 1 read-only P28 Glitch or Debouncing Filter Selection Status 28 1 read-only P29 Glitch or Debouncing Filter Selection Status 29 1 read-only P3 Glitch or Debouncing Filter Selection Status 3 1 read-only P30 Glitch or Debouncing Filter Selection Status 30 1 read-only P31 Glitch or Debouncing Filter Selection Status 31 1 read-only P4 Glitch or Debouncing Filter Selection Status 4 1 read-only P5 Glitch or Debouncing Filter Selection Status 5 1 read-only P6 Glitch or Debouncing Filter Selection Status 6 1 read-only P7 Glitch or Debouncing Filter Selection Status 7 1 read-only P8 Glitch or Debouncing Filter Selection Status 8 1 read-only P9 Glitch or Debouncing Filter Selection Status 9 1 read-only IFSR Glitch Input Filter Status Register 0x28 32 read-only n 0x0 0x0 P0 Input Filter Status 0 1 read-only P1 Input Filter Status 1 1 read-only P10 Input Filter Status 10 1 read-only P11 Input Filter Status 11 1 read-only P12 Input Filter Status 12 1 read-only P13 Input Filter Status 13 1 read-only P14 Input Filter Status 14 1 read-only P15 Input Filter Status 15 1 read-only P16 Input Filter Status 16 1 read-only P17 Input Filter Status 17 1 read-only P18 Input Filter Status 18 1 read-only P19 Input Filter Status 19 1 read-only P2 Input Filter Status 2 1 read-only P20 Input Filter Status 20 1 read-only P21 Input Filter Status 21 1 read-only P22 Input Filter Status 22 1 read-only P23 Input Filter Status 23 1 read-only P24 Input Filter Status 24 1 read-only P25 Input Filter Status 25 1 read-only P26 Input Filter Status 26 1 read-only P27 Input Filter Status 27 1 read-only P28 Input Filter Status 28 1 read-only P29 Input Filter Status 29 1 read-only P3 Input Filter Status 3 1 read-only P30 Input Filter Status 30 1 read-only P31 Input Filter Status 31 1 read-only P4 Input Filter Status 4 1 read-only P5 Input Filter Status 5 1 read-only P6 Input Filter Status 6 1 read-only P7 Input Filter Status 7 1 read-only P8 Input Filter Status 8 1 read-only P9 Input Filter Status 9 1 read-only IMR Interrupt Mask Register 0x48 32 read-only n 0x0 0x0 P0 Input Change Interrupt Mask 0 1 read-only P1 Input Change Interrupt Mask 1 1 read-only P10 Input Change Interrupt Mask 10 1 read-only P11 Input Change Interrupt Mask 11 1 read-only P12 Input Change Interrupt Mask 12 1 read-only P13 Input Change Interrupt Mask 13 1 read-only P14 Input Change Interrupt Mask 14 1 read-only P15 Input Change Interrupt Mask 15 1 read-only P16 Input Change Interrupt Mask 16 1 read-only P17 Input Change Interrupt Mask 17 1 read-only P18 Input Change Interrupt Mask 18 1 read-only P19 Input Change Interrupt Mask 19 1 read-only P2 Input Change Interrupt Mask 2 1 read-only P20 Input Change Interrupt Mask 20 1 read-only P21 Input Change Interrupt Mask 21 1 read-only P22 Input Change Interrupt Mask 22 1 read-only P23 Input Change Interrupt Mask 23 1 read-only P24 Input Change Interrupt Mask 24 1 read-only P25 Input Change Interrupt Mask 25 1 read-only P26 Input Change Interrupt Mask 26 1 read-only P27 Input Change Interrupt Mask 27 1 read-only P28 Input Change Interrupt Mask 28 1 read-only P29 Input Change Interrupt Mask 29 1 read-only P3 Input Change Interrupt Mask 3 1 read-only P30 Input Change Interrupt Mask 30 1 read-only P31 Input Change Interrupt Mask 31 1 read-only P4 Input Change Interrupt Mask 4 1 read-only P5 Input Change Interrupt Mask 5 1 read-only P6 Input Change Interrupt Mask 6 1 read-only P7 Input Change Interrupt Mask 7 1 read-only P8 Input Change Interrupt Mask 8 1 read-only P9 Input Change Interrupt Mask 9 1 read-only ISLR PIO Interrupt Security Level Register 0xC 32 read-write n 0x0 0x0 P0 PIO Interrupt Security Level 0 1 read-write P1 PIO Interrupt Security Level 1 1 read-write P10 PIO Interrupt Security Level 10 1 read-write P11 PIO Interrupt Security Level 11 1 read-write P12 PIO Interrupt Security Level 12 1 read-write P13 PIO Interrupt Security Level 13 1 read-write P14 PIO Interrupt Security Level 14 1 read-write P15 PIO Interrupt Security Level 15 1 read-write P16 PIO Interrupt Security Level 16 1 read-write P17 PIO Interrupt Security Level 17 1 read-write P18 PIO Interrupt Security Level 18 1 read-write P19 PIO Interrupt Security Level 19 1 read-write P2 PIO Interrupt Security Level 2 1 read-write P20 PIO Interrupt Security Level 20 1 read-write P21 PIO Interrupt Security Level 21 1 read-write P22 PIO Interrupt Security Level 22 1 read-write P23 PIO Interrupt Security Level 23 1 read-write P24 PIO Interrupt Security Level 24 1 read-write P25 PIO Interrupt Security Level 25 1 read-write P26 PIO Interrupt Security Level 26 1 read-write P27 PIO Interrupt Security Level 27 1 read-write P28 PIO Interrupt Security Level 28 1 read-write P29 PIO Interrupt Security Level 29 1 read-write P3 PIO Interrupt Security Level 3 1 read-write P30 PIO Interrupt Security Level 30 1 read-write P31 PIO Interrupt Security Level 31 1 read-write P4 PIO Interrupt Security Level 4 1 read-write P5 PIO Interrupt Security Level 5 1 read-write P6 PIO Interrupt Security Level 6 1 read-write P7 PIO Interrupt Security Level 7 1 read-write P8 PIO Interrupt Security Level 8 1 read-write P9 PIO Interrupt Security Level 9 1 read-write ISR Interrupt Status Register 0x4C 32 read-only n 0x0 0x0 P0 Input Change Interrupt Status 0 1 read-only P1 Input Change Interrupt Status 1 1 read-only P10 Input Change Interrupt Status 10 1 read-only P11 Input Change Interrupt Status 11 1 read-only P12 Input Change Interrupt Status 12 1 read-only P13 Input Change Interrupt Status 13 1 read-only P14 Input Change Interrupt Status 14 1 read-only P15 Input Change Interrupt Status 15 1 read-only P16 Input Change Interrupt Status 16 1 read-only P17 Input Change Interrupt Status 17 1 read-only P18 Input Change Interrupt Status 18 1 read-only P19 Input Change Interrupt Status 19 1 read-only P2 Input Change Interrupt Status 2 1 read-only P20 Input Change Interrupt Status 20 1 read-only P21 Input Change Interrupt Status 21 1 read-only P22 Input Change Interrupt Status 22 1 read-only P23 Input Change Interrupt Status 23 1 read-only P24 Input Change Interrupt Status 24 1 read-only P25 Input Change Interrupt Status 25 1 read-only P26 Input Change Interrupt Status 26 1 read-only P27 Input Change Interrupt Status 27 1 read-only P28 Input Change Interrupt Status 28 1 read-only P29 Input Change Interrupt Status 29 1 read-only P3 Input Change Interrupt Status 3 1 read-only P30 Input Change Interrupt Status 30 1 read-only P31 Input Change Interrupt Status 31 1 read-only P4 Input Change Interrupt Status 4 1 read-only P5 Input Change Interrupt Status 5 1 read-only P6 Input Change Interrupt Status 6 1 read-only P7 Input Change Interrupt Status 7 1 read-only P8 Input Change Interrupt Status 8 1 read-only P9 Input Change Interrupt Status 9 1 read-only LSR Level Select Register 0xC4 32 write-only n 0x0 0x0 P0 Level Interrupt Selection 0 1 write-only P1 Level Interrupt Selection 1 1 write-only P10 Level Interrupt Selection 10 1 write-only P11 Level Interrupt Selection 11 1 write-only P12 Level Interrupt Selection 12 1 write-only P13 Level Interrupt Selection 13 1 write-only P14 Level Interrupt Selection 14 1 write-only P15 Level Interrupt Selection 15 1 write-only P16 Level Interrupt Selection 16 1 write-only P17 Level Interrupt Selection 17 1 write-only P18 Level Interrupt Selection 18 1 write-only P19 Level Interrupt Selection 19 1 write-only P2 Level Interrupt Selection 2 1 write-only P20 Level Interrupt Selection 20 1 write-only P21 Level Interrupt Selection 21 1 write-only P22 Level Interrupt Selection 22 1 write-only P23 Level Interrupt Selection 23 1 write-only P24 Level Interrupt Selection 24 1 write-only P25 Level Interrupt Selection 25 1 write-only P26 Level Interrupt Selection 26 1 write-only P27 Level Interrupt Selection 27 1 write-only P28 Level Interrupt Selection 28 1 write-only P29 Level Interrupt Selection 29 1 write-only P3 Level Interrupt Selection 3 1 write-only P30 Level Interrupt Selection 30 1 write-only P31 Level Interrupt Selection 31 1 write-only P4 Level Interrupt Selection 4 1 write-only P5 Level Interrupt Selection 5 1 write-only P6 Level Interrupt Selection 6 1 write-only P7 Level Interrupt Selection 7 1 write-only P8 Level Interrupt Selection 8 1 write-only P9 Level Interrupt Selection 9 1 write-only MDDR Multi-driver Disable Register 0x54 32 write-only n 0x0 0x0 P0 Multi-drive Disable 0 1 write-only P1 Multi-drive Disable 1 1 write-only P10 Multi-drive Disable 10 1 write-only P11 Multi-drive Disable 11 1 write-only P12 Multi-drive Disable 12 1 write-only P13 Multi-drive Disable 13 1 write-only P14 Multi-drive Disable 14 1 write-only P15 Multi-drive Disable 15 1 write-only P16 Multi-drive Disable 16 1 write-only P17 Multi-drive Disable 17 1 write-only P18 Multi-drive Disable 18 1 write-only P19 Multi-drive Disable 19 1 write-only P2 Multi-drive Disable 2 1 write-only P20 Multi-drive Disable 20 1 write-only P21 Multi-drive Disable 21 1 write-only P22 Multi-drive Disable 22 1 write-only P23 Multi-drive Disable 23 1 write-only P24 Multi-drive Disable 24 1 write-only P25 Multi-drive Disable 25 1 write-only P26 Multi-drive Disable 26 1 write-only P27 Multi-drive Disable 27 1 write-only P28 Multi-drive Disable 28 1 write-only P29 Multi-drive Disable 29 1 write-only P3 Multi-drive Disable 3 1 write-only P30 Multi-drive Disable 30 1 write-only P31 Multi-drive Disable 31 1 write-only P4 Multi-drive Disable 4 1 write-only P5 Multi-drive Disable 5 1 write-only P6 Multi-drive Disable 6 1 write-only P7 Multi-drive Disable 7 1 write-only P8 Multi-drive Disable 8 1 write-only P9 Multi-drive Disable 9 1 write-only MDER Multi-driver Enable Register 0x50 32 write-only n 0x0 0x0 P0 Multi-drive Enable 0 1 write-only P1 Multi-drive Enable 1 1 write-only P10 Multi-drive Enable 10 1 write-only P11 Multi-drive Enable 11 1 write-only P12 Multi-drive Enable 12 1 write-only P13 Multi-drive Enable 13 1 write-only P14 Multi-drive Enable 14 1 write-only P15 Multi-drive Enable 15 1 write-only P16 Multi-drive Enable 16 1 write-only P17 Multi-drive Enable 17 1 write-only P18 Multi-drive Enable 18 1 write-only P19 Multi-drive Enable 19 1 write-only P2 Multi-drive Enable 2 1 write-only P20 Multi-drive Enable 20 1 write-only P21 Multi-drive Enable 21 1 write-only P22 Multi-drive Enable 22 1 write-only P23 Multi-drive Enable 23 1 write-only P24 Multi-drive Enable 24 1 write-only P25 Multi-drive Enable 25 1 write-only P26 Multi-drive Enable 26 1 write-only P27 Multi-drive Enable 27 1 write-only P28 Multi-drive Enable 28 1 write-only P29 Multi-drive Enable 29 1 write-only P3 Multi-drive Enable 3 1 write-only P30 Multi-drive Enable 30 1 write-only P31 Multi-drive Enable 31 1 write-only P4 Multi-drive Enable 4 1 write-only P5 Multi-drive Enable 5 1 write-only P6 Multi-drive Enable 6 1 write-only P7 Multi-drive Enable 7 1 write-only P8 Multi-drive Enable 8 1 write-only P9 Multi-drive Enable 9 1 write-only MDSR Multi-driver Status Register 0x58 32 read-only n 0x0 0x0 P0 Multi-drive Status 0 1 read-only P1 Multi-drive Status 1 1 read-only P10 Multi-drive Status 10 1 read-only P11 Multi-drive Status 11 1 read-only P12 Multi-drive Status 12 1 read-only P13 Multi-drive Status 13 1 read-only P14 Multi-drive Status 14 1 read-only P15 Multi-drive Status 15 1 read-only P16 Multi-drive Status 16 1 read-only P17 Multi-drive Status 17 1 read-only P18 Multi-drive Status 18 1 read-only P19 Multi-drive Status 19 1 read-only P2 Multi-drive Status 2 1 read-only P20 Multi-drive Status 20 1 read-only P21 Multi-drive Status 21 1 read-only P22 Multi-drive Status 22 1 read-only P23 Multi-drive Status 23 1 read-only P24 Multi-drive Status 24 1 read-only P25 Multi-drive Status 25 1 read-only P26 Multi-drive Status 26 1 read-only P27 Multi-drive Status 27 1 read-only P28 Multi-drive Status 28 1 read-only P29 Multi-drive Status 29 1 read-only P3 Multi-drive Status 3 1 read-only P30 Multi-drive Status 30 1 read-only P31 Multi-drive Status 31 1 read-only P4 Multi-drive Status 4 1 read-only P5 Multi-drive Status 5 1 read-only P6 Multi-drive Status 6 1 read-only P7 Multi-drive Status 7 1 read-only P8 Multi-drive Status 8 1 read-only P9 Multi-drive Status 9 1 read-only ODR Output Disable Register 0x14 32 write-only n 0x0 0x0 P0 Output Disable 0 1 write-only P1 Output Disable 1 1 write-only P10 Output Disable 10 1 write-only P11 Output Disable 11 1 write-only P12 Output Disable 12 1 write-only P13 Output Disable 13 1 write-only P14 Output Disable 14 1 write-only P15 Output Disable 15 1 write-only P16 Output Disable 16 1 write-only P17 Output Disable 17 1 write-only P18 Output Disable 18 1 write-only P19 Output Disable 19 1 write-only P2 Output Disable 2 1 write-only P20 Output Disable 20 1 write-only P21 Output Disable 21 1 write-only P22 Output Disable 22 1 write-only P23 Output Disable 23 1 write-only P24 Output Disable 24 1 write-only P25 Output Disable 25 1 write-only P26 Output Disable 26 1 write-only P27 Output Disable 27 1 write-only P28 Output Disable 28 1 write-only P29 Output Disable 29 1 write-only P3 Output Disable 3 1 write-only P30 Output Disable 30 1 write-only P31 Output Disable 31 1 write-only P4 Output Disable 4 1 write-only P5 Output Disable 5 1 write-only P6 Output Disable 6 1 write-only P7 Output Disable 7 1 write-only P8 Output Disable 8 1 write-only P9 Output Disable 9 1 write-only ODSR Output Data Status Register 0x38 32 read-write n 0x0 0x0 P0 Output Data Status 0 1 read-write P1 Output Data Status 1 1 read-write P10 Output Data Status 10 1 read-write P11 Output Data Status 11 1 read-write P12 Output Data Status 12 1 read-write P13 Output Data Status 13 1 read-write P14 Output Data Status 14 1 read-write P15 Output Data Status 15 1 read-write P16 Output Data Status 16 1 read-write P17 Output Data Status 17 1 read-write P18 Output Data Status 18 1 read-write P19 Output Data Status 19 1 read-write P2 Output Data Status 2 1 read-write P20 Output Data Status 20 1 read-write P21 Output Data Status 21 1 read-write P22 Output Data Status 22 1 read-write P23 Output Data Status 23 1 read-write P24 Output Data Status 24 1 read-write P25 Output Data Status 25 1 read-write P26 Output Data Status 26 1 read-write P27 Output Data Status 27 1 read-write P28 Output Data Status 28 1 read-write P29 Output Data Status 29 1 read-write P3 Output Data Status 3 1 read-write P30 Output Data Status 30 1 read-write P31 Output Data Status 31 1 read-write P4 Output Data Status 4 1 read-write P5 Output Data Status 5 1 read-write P6 Output Data Status 6 1 read-write P7 Output Data Status 7 1 read-write P8 Output Data Status 8 1 read-write P9 Output Data Status 9 1 read-write OER Output Enable Register 0x10 32 write-only n 0x0 0x0 P0 Output Enable 0 1 write-only P1 Output Enable 1 1 write-only P10 Output Enable 10 1 write-only P11 Output Enable 11 1 write-only P12 Output Enable 12 1 write-only P13 Output Enable 13 1 write-only P14 Output Enable 14 1 write-only P15 Output Enable 15 1 write-only P16 Output Enable 16 1 write-only P17 Output Enable 17 1 write-only P18 Output Enable 18 1 write-only P19 Output Enable 19 1 write-only P2 Output Enable 2 1 write-only P20 Output Enable 20 1 write-only P21 Output Enable 21 1 write-only P22 Output Enable 22 1 write-only P23 Output Enable 23 1 write-only P24 Output Enable 24 1 write-only P25 Output Enable 25 1 write-only P26 Output Enable 26 1 write-only P27 Output Enable 27 1 write-only P28 Output Enable 28 1 write-only P29 Output Enable 29 1 write-only P3 Output Enable 3 1 write-only P30 Output Enable 30 1 write-only P31 Output Enable 31 1 write-only P4 Output Enable 4 1 write-only P5 Output Enable 5 1 write-only P6 Output Enable 6 1 write-only P7 Output Enable 7 1 write-only P8 Output Enable 8 1 write-only P9 Output Enable 9 1 write-only OSR Output Status Register 0x18 32 read-only n 0x0 0x0 P0 Output Status 0 1 read-only P1 Output Status 1 1 read-only P10 Output Status 10 1 read-only P11 Output Status 11 1 read-only P12 Output Status 12 1 read-only P13 Output Status 13 1 read-only P14 Output Status 14 1 read-only P15 Output Status 15 1 read-only P16 Output Status 16 1 read-only P17 Output Status 17 1 read-only P18 Output Status 18 1 read-only P19 Output Status 19 1 read-only P2 Output Status 2 1 read-only P20 Output Status 20 1 read-only P21 Output Status 21 1 read-only P22 Output Status 22 1 read-only P23 Output Status 23 1 read-only P24 Output Status 24 1 read-only P25 Output Status 25 1 read-only P26 Output Status 26 1 read-only P27 Output Status 27 1 read-only P28 Output Status 28 1 read-only P29 Output Status 29 1 read-only P3 Output Status 3 1 read-only P30 Output Status 30 1 read-only P31 Output Status 31 1 read-only P4 Output Status 4 1 read-only P5 Output Status 5 1 read-only P6 Output Status 6 1 read-only P7 Output Status 7 1 read-only P8 Output Status 8 1 read-only P9 Output Status 9 1 read-only OWDR Output Write Disable 0xA4 32 write-only n 0x0 0x0 P0 Output Write Disable 0 1 write-only P1 Output Write Disable 1 1 write-only P10 Output Write Disable 10 1 write-only P11 Output Write Disable 11 1 write-only P12 Output Write Disable 12 1 write-only P13 Output Write Disable 13 1 write-only P14 Output Write Disable 14 1 write-only P15 Output Write Disable 15 1 write-only P16 Output Write Disable 16 1 write-only P17 Output Write Disable 17 1 write-only P18 Output Write Disable 18 1 write-only P19 Output Write Disable 19 1 write-only P2 Output Write Disable 2 1 write-only P20 Output Write Disable 20 1 write-only P21 Output Write Disable 21 1 write-only P22 Output Write Disable 22 1 write-only P23 Output Write Disable 23 1 write-only P24 Output Write Disable 24 1 write-only P25 Output Write Disable 25 1 write-only P26 Output Write Disable 26 1 write-only P27 Output Write Disable 27 1 write-only P28 Output Write Disable 28 1 write-only P29 Output Write Disable 29 1 write-only P3 Output Write Disable 3 1 write-only P30 Output Write Disable 30 1 write-only P31 Output Write Disable 31 1 write-only P4 Output Write Disable 4 1 write-only P5 Output Write Disable 5 1 write-only P6 Output Write Disable 6 1 write-only P7 Output Write Disable 7 1 write-only P8 Output Write Disable 8 1 write-only P9 Output Write Disable 9 1 write-only OWER Output Write Enable 0xA0 32 write-only n 0x0 0x0 P0 Output Write Enable 0 1 write-only P1 Output Write Enable 1 1 write-only P10 Output Write Enable 10 1 write-only P11 Output Write Enable 11 1 write-only P12 Output Write Enable 12 1 write-only P13 Output Write Enable 13 1 write-only P14 Output Write Enable 14 1 write-only P15 Output Write Enable 15 1 write-only P16 Output Write Enable 16 1 write-only P17 Output Write Enable 17 1 write-only P18 Output Write Enable 18 1 write-only P19 Output Write Enable 19 1 write-only P2 Output Write Enable 2 1 write-only P20 Output Write Enable 20 1 write-only P21 Output Write Enable 21 1 write-only P22 Output Write Enable 22 1 write-only P23 Output Write Enable 23 1 write-only P24 Output Write Enable 24 1 write-only P25 Output Write Enable 25 1 write-only P26 Output Write Enable 26 1 write-only P27 Output Write Enable 27 1 write-only P28 Output Write Enable 28 1 write-only P29 Output Write Enable 29 1 write-only P3 Output Write Enable 3 1 write-only P30 Output Write Enable 30 1 write-only P31 Output Write Enable 31 1 write-only P4 Output Write Enable 4 1 write-only P5 Output Write Enable 5 1 write-only P6 Output Write Enable 6 1 write-only P7 Output Write Enable 7 1 write-only P8 Output Write Enable 8 1 write-only P9 Output Write Enable 9 1 write-only OWSR Output Write Status Register 0xA8 32 read-only n 0x0 0x0 P0 Output Write Status 0 1 read-only P1 Output Write Status 1 1 read-only P10 Output Write Status 10 1 read-only P11 Output Write Status 11 1 read-only P12 Output Write Status 12 1 read-only P13 Output Write Status 13 1 read-only P14 Output Write Status 14 1 read-only P15 Output Write Status 15 1 read-only P16 Output Write Status 16 1 read-only P17 Output Write Status 17 1 read-only P18 Output Write Status 18 1 read-only P19 Output Write Status 19 1 read-only P2 Output Write Status 2 1 read-only P20 Output Write Status 20 1 read-only P21 Output Write Status 21 1 read-only P22 Output Write Status 22 1 read-only P23 Output Write Status 23 1 read-only P24 Output Write Status 24 1 read-only P25 Output Write Status 25 1 read-only P26 Output Write Status 26 1 read-only P27 Output Write Status 27 1 read-only P28 Output Write Status 28 1 read-only P29 Output Write Status 29 1 read-only P3 Output Write Status 3 1 read-only P30 Output Write Status 30 1 read-only P31 Output Write Status 31 1 read-only P4 Output Write Status 4 1 read-only P5 Output Write Status 5 1 read-only P6 Output Write Status 6 1 read-only P7 Output Write Status 7 1 read-only P8 Output Write Status 8 1 read-only P9 Output Write Status 9 1 read-only PDR PIO Disable Register 0x4 32 write-only n 0x0 0x0 P0 PIO Disable 0 1 write-only P1 PIO Disable 1 1 write-only P10 PIO Disable 10 1 write-only P11 PIO Disable 11 1 write-only P12 PIO Disable 12 1 write-only P13 PIO Disable 13 1 write-only P14 PIO Disable 14 1 write-only P15 PIO Disable 15 1 write-only P16 PIO Disable 16 1 write-only P17 PIO Disable 17 1 write-only P18 PIO Disable 18 1 write-only P19 PIO Disable 19 1 write-only P2 PIO Disable 2 1 write-only P20 PIO Disable 20 1 write-only P21 PIO Disable 21 1 write-only P22 PIO Disable 22 1 write-only P23 PIO Disable 23 1 write-only P24 PIO Disable 24 1 write-only P25 PIO Disable 25 1 write-only P26 PIO Disable 26 1 write-only P27 PIO Disable 27 1 write-only P28 PIO Disable 28 1 write-only P29 PIO Disable 29 1 write-only P3 PIO Disable 3 1 write-only P30 PIO Disable 30 1 write-only P31 PIO Disable 31 1 write-only P4 PIO Disable 4 1 write-only P5 PIO Disable 5 1 write-only P6 PIO Disable 6 1 write-only P7 PIO Disable 7 1 write-only P8 PIO Disable 8 1 write-only P9 PIO Disable 9 1 write-only PDSR Pin Data Status Register 0x3C 32 read-only n 0x0 0x0 P0 Output Data Status 0 1 read-only P1 Output Data Status 1 1 read-only P10 Output Data Status 10 1 read-only P11 Output Data Status 11 1 read-only P12 Output Data Status 12 1 read-only P13 Output Data Status 13 1 read-only P14 Output Data Status 14 1 read-only P15 Output Data Status 15 1 read-only P16 Output Data Status 16 1 read-only P17 Output Data Status 17 1 read-only P18 Output Data Status 18 1 read-only P19 Output Data Status 19 1 read-only P2 Output Data Status 2 1 read-only P20 Output Data Status 20 1 read-only P21 Output Data Status 21 1 read-only P22 Output Data Status 22 1 read-only P23 Output Data Status 23 1 read-only P24 Output Data Status 24 1 read-only P25 Output Data Status 25 1 read-only P26 Output Data Status 26 1 read-only P27 Output Data Status 27 1 read-only P28 Output Data Status 28 1 read-only P29 Output Data Status 29 1 read-only P3 Output Data Status 3 1 read-only P30 Output Data Status 30 1 read-only P31 Output Data Status 31 1 read-only P4 Output Data Status 4 1 read-only P5 Output Data Status 5 1 read-only P6 Output Data Status 6 1 read-only P7 Output Data Status 7 1 read-only P8 Output Data Status 8 1 read-only P9 Output Data Status 9 1 read-only PER PIO Enable Register 0x0 32 write-only n 0x0 0x0 P0 PIO Enable 0 1 write-only P1 PIO Enable 1 1 write-only P10 PIO Enable 10 1 write-only P11 PIO Enable 11 1 write-only P12 PIO Enable 12 1 write-only P13 PIO Enable 13 1 write-only P14 PIO Enable 14 1 write-only P15 PIO Enable 15 1 write-only P16 PIO Enable 16 1 write-only P17 PIO Enable 17 1 write-only P18 PIO Enable 18 1 write-only P19 PIO Enable 19 1 write-only P2 PIO Enable 2 1 write-only P20 PIO Enable 20 1 write-only P21 PIO Enable 21 1 write-only P22 PIO Enable 22 1 write-only P23 PIO Enable 23 1 write-only P24 PIO Enable 24 1 write-only P25 PIO Enable 25 1 write-only P26 PIO Enable 26 1 write-only P27 PIO Enable 27 1 write-only P28 PIO Enable 28 1 write-only P29 PIO Enable 29 1 write-only P3 PIO Enable 3 1 write-only P30 PIO Enable 30 1 write-only P31 PIO Enable 31 1 write-only P4 PIO Enable 4 1 write-only P5 PIO Enable 5 1 write-only P6 PIO Enable 6 1 write-only P7 PIO Enable 7 1 write-only P8 PIO Enable 8 1 write-only P9 PIO Enable 9 1 write-only PPDDR Pad Pull-Down Disable Register 0x90 32 write-only n 0x0 0x0 P0 Pull-Down Disable 0 1 write-only P1 Pull-Down Disable 1 1 write-only P10 Pull-Down Disable 10 1 write-only P11 Pull-Down Disable 11 1 write-only P12 Pull-Down Disable 12 1 write-only P13 Pull-Down Disable 13 1 write-only P14 Pull-Down Disable 14 1 write-only P15 Pull-Down Disable 15 1 write-only P16 Pull-Down Disable 16 1 write-only P17 Pull-Down Disable 17 1 write-only P18 Pull-Down Disable 18 1 write-only P19 Pull-Down Disable 19 1 write-only P2 Pull-Down Disable 2 1 write-only P20 Pull-Down Disable 20 1 write-only P21 Pull-Down Disable 21 1 write-only P22 Pull-Down Disable 22 1 write-only P23 Pull-Down Disable 23 1 write-only P24 Pull-Down Disable 24 1 write-only P25 Pull-Down Disable 25 1 write-only P26 Pull-Down Disable 26 1 write-only P27 Pull-Down Disable 27 1 write-only P28 Pull-Down Disable 28 1 write-only P29 Pull-Down Disable 29 1 write-only P3 Pull-Down Disable 3 1 write-only P30 Pull-Down Disable 30 1 write-only P31 Pull-Down Disable 31 1 write-only P4 Pull-Down Disable 4 1 write-only P5 Pull-Down Disable 5 1 write-only P6 Pull-Down Disable 6 1 write-only P7 Pull-Down Disable 7 1 write-only P8 Pull-Down Disable 8 1 write-only P9 Pull-Down Disable 9 1 write-only PPDER Pad Pull-Down Enable Register 0x94 32 write-only n 0x0 0x0 P0 Pull-Down Enable 0 1 write-only P1 Pull-Down Enable 1 1 write-only P10 Pull-Down Enable 10 1 write-only P11 Pull-Down Enable 11 1 write-only P12 Pull-Down Enable 12 1 write-only P13 Pull-Down Enable 13 1 write-only P14 Pull-Down Enable 14 1 write-only P15 Pull-Down Enable 15 1 write-only P16 Pull-Down Enable 16 1 write-only P17 Pull-Down Enable 17 1 write-only P18 Pull-Down Enable 18 1 write-only P19 Pull-Down Enable 19 1 write-only P2 Pull-Down Enable 2 1 write-only P20 Pull-Down Enable 20 1 write-only P21 Pull-Down Enable 21 1 write-only P22 Pull-Down Enable 22 1 write-only P23 Pull-Down Enable 23 1 write-only P24 Pull-Down Enable 24 1 write-only P25 Pull-Down Enable 25 1 write-only P26 Pull-Down Enable 26 1 write-only P27 Pull-Down Enable 27 1 write-only P28 Pull-Down Enable 28 1 write-only P29 Pull-Down Enable 29 1 write-only P3 Pull-Down Enable 3 1 write-only P30 Pull-Down Enable 30 1 write-only P31 Pull-Down Enable 31 1 write-only P4 Pull-Down Enable 4 1 write-only P5 Pull-Down Enable 5 1 write-only P6 Pull-Down Enable 6 1 write-only P7 Pull-Down Enable 7 1 write-only P8 Pull-Down Enable 8 1 write-only P9 Pull-Down Enable 9 1 write-only PPDSR Pad Pull-Down Status Register 0x98 32 read-only n 0x0 0x0 P0 Pull-Down Status 0 1 read-only P1 Pull-Down Status 1 1 read-only P10 Pull-Down Status 10 1 read-only P11 Pull-Down Status 11 1 read-only P12 Pull-Down Status 12 1 read-only P13 Pull-Down Status 13 1 read-only P14 Pull-Down Status 14 1 read-only P15 Pull-Down Status 15 1 read-only P16 Pull-Down Status 16 1 read-only P17 Pull-Down Status 17 1 read-only P18 Pull-Down Status 18 1 read-only P19 Pull-Down Status 19 1 read-only P2 Pull-Down Status 2 1 read-only P20 Pull-Down Status 20 1 read-only P21 Pull-Down Status 21 1 read-only P22 Pull-Down Status 22 1 read-only P23 Pull-Down Status 23 1 read-only P24 Pull-Down Status 24 1 read-only P25 Pull-Down Status 25 1 read-only P26 Pull-Down Status 26 1 read-only P27 Pull-Down Status 27 1 read-only P28 Pull-Down Status 28 1 read-only P29 Pull-Down Status 29 1 read-only P3 Pull-Down Status 3 1 read-only P30 Pull-Down Status 30 1 read-only P31 Pull-Down Status 31 1 read-only P4 Pull-Down Status 4 1 read-only P5 Pull-Down Status 5 1 read-only P6 Pull-Down Status 6 1 read-only P7 Pull-Down Status 7 1 read-only P8 Pull-Down Status 8 1 read-only P9 Pull-Down Status 9 1 read-only PSR PIO Status Register 0x8 32 read-only n 0x0 0x0 P0 PIO Status 0 1 read-only P1 PIO Status 1 1 read-only P10 PIO Status 10 1 read-only P11 PIO Status 11 1 read-only P12 PIO Status 12 1 read-only P13 PIO Status 13 1 read-only P14 PIO Status 14 1 read-only P15 PIO Status 15 1 read-only P16 PIO Status 16 1 read-only P17 PIO Status 17 1 read-only P18 PIO Status 18 1 read-only P19 PIO Status 19 1 read-only P2 PIO Status 2 1 read-only P20 PIO Status 20 1 read-only P21 PIO Status 21 1 read-only P22 PIO Status 22 1 read-only P23 PIO Status 23 1 read-only P24 PIO Status 24 1 read-only P25 PIO Status 25 1 read-only P26 PIO Status 26 1 read-only P27 PIO Status 27 1 read-only P28 PIO Status 28 1 read-only P29 PIO Status 29 1 read-only P3 PIO Status 3 1 read-only P30 PIO Status 30 1 read-only P31 PIO Status 31 1 read-only P4 PIO Status 4 1 read-only P5 PIO Status 5 1 read-only P6 PIO Status 6 1 read-only P7 PIO Status 7 1 read-only P8 PIO Status 8 1 read-only P9 PIO Status 9 1 read-only PUDR Pull-Up Disable Register 0x60 32 write-only n 0x0 0x0 P0 Pull-Up Disable 0 1 write-only P1 Pull-Up Disable 1 1 write-only P10 Pull-Up Disable 10 1 write-only P11 Pull-Up Disable 11 1 write-only P12 Pull-Up Disable 12 1 write-only P13 Pull-Up Disable 13 1 write-only P14 Pull-Up Disable 14 1 write-only P15 Pull-Up Disable 15 1 write-only P16 Pull-Up Disable 16 1 write-only P17 Pull-Up Disable 17 1 write-only P18 Pull-Up Disable 18 1 write-only P19 Pull-Up Disable 19 1 write-only P2 Pull-Up Disable 2 1 write-only P20 Pull-Up Disable 20 1 write-only P21 Pull-Up Disable 21 1 write-only P22 Pull-Up Disable 22 1 write-only P23 Pull-Up Disable 23 1 write-only P24 Pull-Up Disable 24 1 write-only P25 Pull-Up Disable 25 1 write-only P26 Pull-Up Disable 26 1 write-only P27 Pull-Up Disable 27 1 write-only P28 Pull-Up Disable 28 1 write-only P29 Pull-Up Disable 29 1 write-only P3 Pull-Up Disable 3 1 write-only P30 Pull-Up Disable 30 1 write-only P31 Pull-Up Disable 31 1 write-only P4 Pull-Up Disable 4 1 write-only P5 Pull-Up Disable 5 1 write-only P6 Pull-Up Disable 6 1 write-only P7 Pull-Up Disable 7 1 write-only P8 Pull-Up Disable 8 1 write-only P9 Pull-Up Disable 9 1 write-only PUER Pull-Up Enable Register 0x64 32 write-only n 0x0 0x0 P0 Pull-Up Enable 0 1 write-only P1 Pull-Up Enable 1 1 write-only P10 Pull-Up Enable 10 1 write-only P11 Pull-Up Enable 11 1 write-only P12 Pull-Up Enable 12 1 write-only P13 Pull-Up Enable 13 1 write-only P14 Pull-Up Enable 14 1 write-only P15 Pull-Up Enable 15 1 write-only P16 Pull-Up Enable 16 1 write-only P17 Pull-Up Enable 17 1 write-only P18 Pull-Up Enable 18 1 write-only P19 Pull-Up Enable 19 1 write-only P2 Pull-Up Enable 2 1 write-only P20 Pull-Up Enable 20 1 write-only P21 Pull-Up Enable 21 1 write-only P22 Pull-Up Enable 22 1 write-only P23 Pull-Up Enable 23 1 write-only P24 Pull-Up Enable 24 1 write-only P25 Pull-Up Enable 25 1 write-only P26 Pull-Up Enable 26 1 write-only P27 Pull-Up Enable 27 1 write-only P28 Pull-Up Enable 28 1 write-only P29 Pull-Up Enable 29 1 write-only P3 Pull-Up Enable 3 1 write-only P30 Pull-Up Enable 30 1 write-only P31 Pull-Up Enable 31 1 write-only P4 Pull-Up Enable 4 1 write-only P5 Pull-Up Enable 5 1 write-only P6 Pull-Up Enable 6 1 write-only P7 Pull-Up Enable 7 1 write-only P8 Pull-Up Enable 8 1 write-only P9 Pull-Up Enable 9 1 write-only PUSR Pad Pull-Up Status Register 0x68 32 read-only n 0x0 0x0 P0 Pull-Up Status 0 1 read-only P1 Pull-Up Status 1 1 read-only P10 Pull-Up Status 10 1 read-only P11 Pull-Up Status 11 1 read-only P12 Pull-Up Status 12 1 read-only P13 Pull-Up Status 13 1 read-only P14 Pull-Up Status 14 1 read-only P15 Pull-Up Status 15 1 read-only P16 Pull-Up Status 16 1 read-only P17 Pull-Up Status 17 1 read-only P18 Pull-Up Status 18 1 read-only P19 Pull-Up Status 19 1 read-only P2 Pull-Up Status 2 1 read-only P20 Pull-Up Status 20 1 read-only P21 Pull-Up Status 21 1 read-only P22 Pull-Up Status 22 1 read-only P23 Pull-Up Status 23 1 read-only P24 Pull-Up Status 24 1 read-only P25 Pull-Up Status 25 1 read-only P26 Pull-Up Status 26 1 read-only P27 Pull-Up Status 27 1 read-only P28 Pull-Up Status 28 1 read-only P29 Pull-Up Status 29 1 read-only P3 Pull-Up Status 3 1 read-only P30 Pull-Up Status 30 1 read-only P31 Pull-Up Status 31 1 read-only P4 Pull-Up Status 4 1 read-only P5 Pull-Up Status 5 1 read-only P6 Pull-Up Status 6 1 read-only P7 Pull-Up Status 7 1 read-only P8 Pull-Up Status 8 1 read-only P9 Pull-Up Status 9 1 read-only REHLSR Rising Edge/High-Level Select Register 0xD4 32 write-only n 0x0 0x0 P0 Rising Edge/High-Level Interrupt Selection 0 1 write-only P1 Rising Edge/High-Level Interrupt Selection 1 1 write-only P10 Rising Edge/High-Level Interrupt Selection 10 1 write-only P11 Rising Edge/High-Level Interrupt Selection 11 1 write-only P12 Rising Edge/High-Level Interrupt Selection 12 1 write-only P13 Rising Edge/High-Level Interrupt Selection 13 1 write-only P14 Rising Edge/High-Level Interrupt Selection 14 1 write-only P15 Rising Edge/High-Level Interrupt Selection 15 1 write-only P16 Rising Edge/High-Level Interrupt Selection 16 1 write-only P17 Rising Edge/High-Level Interrupt Selection 17 1 write-only P18 Rising Edge/High-Level Interrupt Selection 18 1 write-only P19 Rising Edge/High-Level Interrupt Selection 19 1 write-only P2 Rising Edge/High-Level Interrupt Selection 2 1 write-only P20 Rising Edge/High-Level Interrupt Selection 20 1 write-only P21 Rising Edge/High-Level Interrupt Selection 21 1 write-only P22 Rising Edge/High-Level Interrupt Selection 22 1 write-only P23 Rising Edge/High-Level Interrupt Selection 23 1 write-only P24 Rising Edge/High-Level Interrupt Selection 24 1 write-only P25 Rising Edge/High-Level Interrupt Selection 25 1 write-only P26 Rising Edge/High-Level Interrupt Selection 26 1 write-only P27 Rising Edge/High-Level Interrupt Selection 27 1 write-only P28 Rising Edge/High-Level Interrupt Selection 28 1 write-only P29 Rising Edge/High-Level Interrupt Selection 29 1 write-only P3 Rising Edge/High-Level Interrupt Selection 3 1 write-only P30 Rising Edge/High-Level Interrupt Selection 30 1 write-only P31 Rising Edge/High-Level Interrupt Selection 31 1 write-only P4 Rising Edge/High-Level Interrupt Selection 4 1 write-only P5 Rising Edge/High-Level Interrupt Selection 5 1 write-only P6 Rising Edge/High-Level Interrupt Selection 6 1 write-only P7 Rising Edge/High-Level Interrupt Selection 7 1 write-only P8 Rising Edge/High-Level Interrupt Selection 8 1 write-only P9 Rising Edge/High-Level Interrupt Selection 9 1 write-only SCDR Slow Clock Divider Debouncing Register 0x8C 32 read-write n 0x0 0x0 DIV Slow Clock Divider Selection for Debouncing 0 14 read-write SCHMITT Schmitt Trigger Register 0x100 32 read-write n 0x0 0x0 SCHMITT0 Schmitt Trigger Control 0 1 read-write SCHMITT1 Schmitt Trigger Control 1 1 read-write SCHMITT10 Schmitt Trigger Control 10 1 read-write SCHMITT11 Schmitt Trigger Control 11 1 read-write SCHMITT12 Schmitt Trigger Control 12 1 read-write SCHMITT13 Schmitt Trigger Control 13 1 read-write SCHMITT14 Schmitt Trigger Control 14 1 read-write SCHMITT15 Schmitt Trigger Control 15 1 read-write SCHMITT16 Schmitt Trigger Control 16 1 read-write SCHMITT17 Schmitt Trigger Control 17 1 read-write SCHMITT18 Schmitt Trigger Control 18 1 read-write SCHMITT19 Schmitt Trigger Control 19 1 read-write SCHMITT2 Schmitt Trigger Control 2 1 read-write SCHMITT20 Schmitt Trigger Control 20 1 read-write SCHMITT21 Schmitt Trigger Control 21 1 read-write SCHMITT22 Schmitt Trigger Control 22 1 read-write SCHMITT23 Schmitt Trigger Control 23 1 read-write SCHMITT24 Schmitt Trigger Control 24 1 read-write SCHMITT25 Schmitt Trigger Control 25 1 read-write SCHMITT26 Schmitt Trigger Control 26 1 read-write SCHMITT27 Schmitt Trigger Control 27 1 read-write SCHMITT28 Schmitt Trigger Control 28 1 read-write SCHMITT29 Schmitt Trigger Control 29 1 read-write SCHMITT3 Schmitt Trigger Control 3 1 read-write SCHMITT30 Schmitt Trigger Control 30 1 read-write SCHMITT31 Schmitt Trigger Control 31 1 read-write SCHMITT4 Schmitt Trigger Control 4 1 read-write SCHMITT5 Schmitt Trigger Control 5 1 read-write SCHMITT6 Schmitt Trigger Control 6 1 read-write SCHMITT7 Schmitt Trigger Control 7 1 read-write SCHMITT8 Schmitt Trigger Control 8 1 read-write SCHMITT9 Schmitt Trigger Control 9 1 read-write SODR Set Output Data Register 0x30 32 write-only n 0x0 0x0 P0 Set Output Data 0 1 write-only P1 Set Output Data 1 1 write-only P10 Set Output Data 10 1 write-only P11 Set Output Data 11 1 write-only P12 Set Output Data 12 1 write-only P13 Set Output Data 13 1 write-only P14 Set Output Data 14 1 write-only P15 Set Output Data 15 1 write-only P16 Set Output Data 16 1 write-only P17 Set Output Data 17 1 write-only P18 Set Output Data 18 1 write-only P19 Set Output Data 19 1 write-only P2 Set Output Data 2 1 write-only P20 Set Output Data 20 1 write-only P21 Set Output Data 21 1 write-only P22 Set Output Data 22 1 write-only P23 Set Output Data 23 1 write-only P24 Set Output Data 24 1 write-only P25 Set Output Data 25 1 write-only P26 Set Output Data 26 1 write-only P27 Set Output Data 27 1 write-only P28 Set Output Data 28 1 write-only P29 Set Output Data 29 1 write-only P3 Set Output Data 3 1 write-only P30 Set Output Data 30 1 write-only P31 Set Output Data 31 1 write-only P4 Set Output Data 4 1 write-only P5 Set Output Data 5 1 write-only P6 Set Output Data 6 1 write-only P7 Set Output Data 7 1 write-only P8 Set Output Data 8 1 write-only P9 Set Output Data 9 1 write-only WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 read-write WPKEY Write Protection Key 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 0x50494F WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 read-only WPVSRC Write Protection Violation Source 8 16 read-only PIOB Parallel Input/Output Controller B PIO 0x0 0x0 0x1000 registers n PIOB 24 ABCDSR0 Peripheral ABCD Select Register 0x70 32 read-write n P0 Peripheral Select 0 1 read-write P1 Peripheral Select 1 1 read-write P10 Peripheral Select 10 1 read-write P11 Peripheral Select 11 1 read-write P12 Peripheral Select 12 1 read-write P13 Peripheral Select 13 1 read-write P14 Peripheral Select 14 1 read-write P15 Peripheral Select 15 1 read-write P16 Peripheral Select 16 1 read-write P17 Peripheral Select 17 1 read-write P18 Peripheral Select 18 1 read-write P19 Peripheral Select 19 1 read-write P2 Peripheral Select 2 1 read-write P20 Peripheral Select 20 1 read-write P21 Peripheral Select 21 1 read-write P22 Peripheral Select 22 1 read-write P23 Peripheral Select 23 1 read-write P24 Peripheral Select 24 1 read-write P25 Peripheral Select 25 1 read-write P26 Peripheral Select 26 1 read-write P27 Peripheral Select 27 1 read-write P28 Peripheral Select 28 1 read-write P29 Peripheral Select 29 1 read-write P3 Peripheral Select 3 1 read-write P30 Peripheral Select 30 1 read-write P31 Peripheral Select 31 1 read-write P4 Peripheral Select 4 1 read-write P5 Peripheral Select 5 1 read-write P6 Peripheral Select 6 1 read-write P7 Peripheral Select 7 1 read-write P8 Peripheral Select 8 1 read-write P9 Peripheral Select 9 1 read-write ABCDSR1 Peripheral ABCD Select Register 0x74 32 read-write n P0 Peripheral Select 0 1 read-write P1 Peripheral Select 1 1 read-write P10 Peripheral Select 10 1 read-write P11 Peripheral Select 11 1 read-write P12 Peripheral Select 12 1 read-write P13 Peripheral Select 13 1 read-write P14 Peripheral Select 14 1 read-write P15 Peripheral Select 15 1 read-write P16 Peripheral Select 16 1 read-write P17 Peripheral Select 17 1 read-write P18 Peripheral Select 18 1 read-write P19 Peripheral Select 19 1 read-write P2 Peripheral Select 2 1 read-write P20 Peripheral Select 20 1 read-write P21 Peripheral Select 21 1 read-write P22 Peripheral Select 22 1 read-write P23 Peripheral Select 23 1 read-write P24 Peripheral Select 24 1 read-write P25 Peripheral Select 25 1 read-write P26 Peripheral Select 26 1 read-write P27 Peripheral Select 27 1 read-write P28 Peripheral Select 28 1 read-write P29 Peripheral Select 29 1 read-write P3 Peripheral Select 3 1 read-write P30 Peripheral Select 30 1 read-write P31 Peripheral Select 31 1 read-write P4 Peripheral Select 4 1 read-write P5 Peripheral Select 5 1 read-write P6 Peripheral Select 6 1 read-write P7 Peripheral Select 7 1 read-write P8 Peripheral Select 8 1 read-write P9 Peripheral Select 9 1 read-write ABCDSR[0] Peripheral ABCD Select Register 0xE0 32 read-write n 0x0 0x0 P0 Peripheral Select 0 1 read-write P1 Peripheral Select 1 1 read-write P10 Peripheral Select 10 1 read-write P11 Peripheral Select 11 1 read-write P12 Peripheral Select 12 1 read-write P13 Peripheral Select 13 1 read-write P14 Peripheral Select 14 1 read-write P15 Peripheral Select 15 1 read-write P16 Peripheral Select 16 1 read-write P17 Peripheral Select 17 1 read-write P18 Peripheral Select 18 1 read-write P19 Peripheral Select 19 1 read-write P2 Peripheral Select 2 1 read-write P20 Peripheral Select 20 1 read-write P21 Peripheral Select 21 1 read-write P22 Peripheral Select 22 1 read-write P23 Peripheral Select 23 1 read-write P24 Peripheral Select 24 1 read-write P25 Peripheral Select 25 1 read-write P26 Peripheral Select 26 1 read-write P27 Peripheral Select 27 1 read-write P28 Peripheral Select 28 1 read-write P29 Peripheral Select 29 1 read-write P3 Peripheral Select 3 1 read-write P30 Peripheral Select 30 1 read-write P31 Peripheral Select 31 1 read-write P4 Peripheral Select 4 1 read-write P5 Peripheral Select 5 1 read-write P6 Peripheral Select 6 1 read-write P7 Peripheral Select 7 1 read-write P8 Peripheral Select 8 1 read-write P9 Peripheral Select 9 1 read-write ABCDSR[1] Peripheral ABCD Select Register 0x154 32 read-write n 0x0 0x0 P0 Peripheral Select 0 1 read-write P1 Peripheral Select 1 1 read-write P10 Peripheral Select 10 1 read-write P11 Peripheral Select 11 1 read-write P12 Peripheral Select 12 1 read-write P13 Peripheral Select 13 1 read-write P14 Peripheral Select 14 1 read-write P15 Peripheral Select 15 1 read-write P16 Peripheral Select 16 1 read-write P17 Peripheral Select 17 1 read-write P18 Peripheral Select 18 1 read-write P19 Peripheral Select 19 1 read-write P2 Peripheral Select 2 1 read-write P20 Peripheral Select 20 1 read-write P21 Peripheral Select 21 1 read-write P22 Peripheral Select 22 1 read-write P23 Peripheral Select 23 1 read-write P24 Peripheral Select 24 1 read-write P25 Peripheral Select 25 1 read-write P26 Peripheral Select 26 1 read-write P27 Peripheral Select 27 1 read-write P28 Peripheral Select 28 1 read-write P29 Peripheral Select 29 1 read-write P3 Peripheral Select 3 1 read-write P30 Peripheral Select 30 1 read-write P31 Peripheral Select 31 1 read-write P4 Peripheral Select 4 1 read-write P5 Peripheral Select 5 1 read-write P6 Peripheral Select 6 1 read-write P7 Peripheral Select 7 1 read-write P8 Peripheral Select 8 1 read-write P9 Peripheral Select 9 1 read-write AIMDR Additional Interrupt Modes Disable Register 0xB4 32 write-only n 0x0 0x0 P0 Additional Interrupt Modes Disable 0 1 write-only P1 Additional Interrupt Modes Disable 1 1 write-only P10 Additional Interrupt Modes Disable 10 1 write-only P11 Additional Interrupt Modes Disable 11 1 write-only P12 Additional Interrupt Modes Disable 12 1 write-only P13 Additional Interrupt Modes Disable 13 1 write-only P14 Additional Interrupt Modes Disable 14 1 write-only P15 Additional Interrupt Modes Disable 15 1 write-only P16 Additional Interrupt Modes Disable 16 1 write-only P17 Additional Interrupt Modes Disable 17 1 write-only P18 Additional Interrupt Modes Disable 18 1 write-only P19 Additional Interrupt Modes Disable 19 1 write-only P2 Additional Interrupt Modes Disable 2 1 write-only P20 Additional Interrupt Modes Disable 20 1 write-only P21 Additional Interrupt Modes Disable 21 1 write-only P22 Additional Interrupt Modes Disable 22 1 write-only P23 Additional Interrupt Modes Disable 23 1 write-only P24 Additional Interrupt Modes Disable 24 1 write-only P25 Additional Interrupt Modes Disable 25 1 write-only P26 Additional Interrupt Modes Disable 26 1 write-only P27 Additional Interrupt Modes Disable 27 1 write-only P28 Additional Interrupt Modes Disable 28 1 write-only P29 Additional Interrupt Modes Disable 29 1 write-only P3 Additional Interrupt Modes Disable 3 1 write-only P30 Additional Interrupt Modes Disable 30 1 write-only P31 Additional Interrupt Modes Disable 31 1 write-only P4 Additional Interrupt Modes Disable 4 1 write-only P5 Additional Interrupt Modes Disable 5 1 write-only P6 Additional Interrupt Modes Disable 6 1 write-only P7 Additional Interrupt Modes Disable 7 1 write-only P8 Additional Interrupt Modes Disable 8 1 write-only P9 Additional Interrupt Modes Disable 9 1 write-only AIMER Additional Interrupt Modes Enable Register 0xB0 32 write-only n 0x0 0x0 P0 Additional Interrupt Modes Enable 0 1 write-only P1 Additional Interrupt Modes Enable 1 1 write-only P10 Additional Interrupt Modes Enable 10 1 write-only P11 Additional Interrupt Modes Enable 11 1 write-only P12 Additional Interrupt Modes Enable 12 1 write-only P13 Additional Interrupt Modes Enable 13 1 write-only P14 Additional Interrupt Modes Enable 14 1 write-only P15 Additional Interrupt Modes Enable 15 1 write-only P16 Additional Interrupt Modes Enable 16 1 write-only P17 Additional Interrupt Modes Enable 17 1 write-only P18 Additional Interrupt Modes Enable 18 1 write-only P19 Additional Interrupt Modes Enable 19 1 write-only P2 Additional Interrupt Modes Enable 2 1 write-only P20 Additional Interrupt Modes Enable 20 1 write-only P21 Additional Interrupt Modes Enable 21 1 write-only P22 Additional Interrupt Modes Enable 22 1 write-only P23 Additional Interrupt Modes Enable 23 1 write-only P24 Additional Interrupt Modes Enable 24 1 write-only P25 Additional Interrupt Modes Enable 25 1 write-only P26 Additional Interrupt Modes Enable 26 1 write-only P27 Additional Interrupt Modes Enable 27 1 write-only P28 Additional Interrupt Modes Enable 28 1 write-only P29 Additional Interrupt Modes Enable 29 1 write-only P3 Additional Interrupt Modes Enable 3 1 write-only P30 Additional Interrupt Modes Enable 30 1 write-only P31 Additional Interrupt Modes Enable 31 1 write-only P4 Additional Interrupt Modes Enable 4 1 write-only P5 Additional Interrupt Modes Enable 5 1 write-only P6 Additional Interrupt Modes Enable 6 1 write-only P7 Additional Interrupt Modes Enable 7 1 write-only P8 Additional Interrupt Modes Enable 8 1 write-only P9 Additional Interrupt Modes Enable 9 1 write-only AIMMR Additional Interrupt Modes Mask Register 0xB8 32 read-only n 0x0 0x0 P0 IO Line Index 0 1 read-only P1 IO Line Index 1 1 read-only P10 IO Line Index 10 1 read-only P11 IO Line Index 11 1 read-only P12 IO Line Index 12 1 read-only P13 IO Line Index 13 1 read-only P14 IO Line Index 14 1 read-only P15 IO Line Index 15 1 read-only P16 IO Line Index 16 1 read-only P17 IO Line Index 17 1 read-only P18 IO Line Index 18 1 read-only P19 IO Line Index 19 1 read-only P2 IO Line Index 2 1 read-only P20 IO Line Index 20 1 read-only P21 IO Line Index 21 1 read-only P22 IO Line Index 22 1 read-only P23 IO Line Index 23 1 read-only P24 IO Line Index 24 1 read-only P25 IO Line Index 25 1 read-only P26 IO Line Index 26 1 read-only P27 IO Line Index 27 1 read-only P28 IO Line Index 28 1 read-only P29 IO Line Index 29 1 read-only P3 IO Line Index 3 1 read-only P30 IO Line Index 30 1 read-only P31 IO Line Index 31 1 read-only P4 IO Line Index 4 1 read-only P5 IO Line Index 5 1 read-only P6 IO Line Index 6 1 read-only P7 IO Line Index 7 1 read-only P8 IO Line Index 8 1 read-only P9 IO Line Index 9 1 read-only CODR Clear Output Data Register 0x34 32 write-only n 0x0 0x0 P0 Clear Output Data 0 1 write-only P1 Clear Output Data 1 1 write-only P10 Clear Output Data 10 1 write-only P11 Clear Output Data 11 1 write-only P12 Clear Output Data 12 1 write-only P13 Clear Output Data 13 1 write-only P14 Clear Output Data 14 1 write-only P15 Clear Output Data 15 1 write-only P16 Clear Output Data 16 1 write-only P17 Clear Output Data 17 1 write-only P18 Clear Output Data 18 1 write-only P19 Clear Output Data 19 1 write-only P2 Clear Output Data 2 1 write-only P20 Clear Output Data 20 1 write-only P21 Clear Output Data 21 1 write-only P22 Clear Output Data 22 1 write-only P23 Clear Output Data 23 1 write-only P24 Clear Output Data 24 1 write-only P25 Clear Output Data 25 1 write-only P26 Clear Output Data 26 1 write-only P27 Clear Output Data 27 1 write-only P28 Clear Output Data 28 1 write-only P29 Clear Output Data 29 1 write-only P3 Clear Output Data 3 1 write-only P30 Clear Output Data 30 1 write-only P31 Clear Output Data 31 1 write-only P4 Clear Output Data 4 1 write-only P5 Clear Output Data 5 1 write-only P6 Clear Output Data 6 1 write-only P7 Clear Output Data 7 1 write-only P8 Clear Output Data 8 1 write-only P9 Clear Output Data 9 1 write-only DRIVER1 I/O Drive Register 1 0x118 32 read-write n 0x0 0x0 LINE0 Drive of PIO Line 0 0 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE1 Drive of PIO Line 1 2 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE10 Drive of PIO Line 10 20 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE11 Drive of PIO Line 11 22 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE12 Drive of PIO Line 12 24 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE13 Drive of PIO Line 13 26 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE14 Drive of PIO Line 14 28 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE15 Drive of PIO Line 15 30 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE2 Drive of PIO Line 2 4 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE3 Drive of PIO Line 3 6 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE4 Drive of PIO Line 4 8 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE5 Drive of PIO Line 5 10 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE6 Drive of PIO Line 6 12 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE7 Drive of PIO Line 7 14 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE8 Drive of PIO Line 8 16 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE9 Drive of PIO Line 9 18 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 DRIVER2 I/O Drive Register 2 0x11C 32 read-write n 0x0 0x0 LINE16 Drive of PIO line 16 0 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE17 Drive of PIO line 17 2 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE18 Drive of PIO line 18 4 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE19 Drive of PIO line 19 6 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE20 Drive of PIO line 20 8 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE21 Drive of PIO line 21 10 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE22 Drive of PIO line 22 12 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE23 Drive of PIO line 23 14 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE24 Drive of PIO line 24 16 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE25 Drive of PIO line 25 18 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE26 Drive of PIO line 26 20 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE27 Drive of PIO line 27 22 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE28 Drive of PIO line 28 24 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE29 Drive of PIO line 29 26 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE30 Drive of PIO line 30 28 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE31 Drive of PIO line 31 30 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 ELSR Edge/Level Status Register 0xC8 32 read-only n 0x0 0x0 P0 Edge/Level Interrupt Source Selection 0 1 read-only P1 Edge/Level Interrupt Source Selection 1 1 read-only P10 Edge/Level Interrupt Source Selection 10 1 read-only P11 Edge/Level Interrupt Source Selection 11 1 read-only P12 Edge/Level Interrupt Source Selection 12 1 read-only P13 Edge/Level Interrupt Source Selection 13 1 read-only P14 Edge/Level Interrupt Source Selection 14 1 read-only P15 Edge/Level Interrupt Source Selection 15 1 read-only P16 Edge/Level Interrupt Source Selection 16 1 read-only P17 Edge/Level Interrupt Source Selection 17 1 read-only P18 Edge/Level Interrupt Source Selection 18 1 read-only P19 Edge/Level Interrupt Source Selection 19 1 read-only P2 Edge/Level Interrupt Source Selection 2 1 read-only P20 Edge/Level Interrupt Source Selection 20 1 read-only P21 Edge/Level Interrupt Source Selection 21 1 read-only P22 Edge/Level Interrupt Source Selection 22 1 read-only P23 Edge/Level Interrupt Source Selection 23 1 read-only P24 Edge/Level Interrupt Source Selection 24 1 read-only P25 Edge/Level Interrupt Source Selection 25 1 read-only P26 Edge/Level Interrupt Source Selection 26 1 read-only P27 Edge/Level Interrupt Source Selection 27 1 read-only P28 Edge/Level Interrupt Source Selection 28 1 read-only P29 Edge/Level Interrupt Source Selection 29 1 read-only P3 Edge/Level Interrupt Source Selection 3 1 read-only P30 Edge/Level Interrupt Source Selection 30 1 read-only P31 Edge/Level Interrupt Source Selection 31 1 read-only P4 Edge/Level Interrupt Source Selection 4 1 read-only P5 Edge/Level Interrupt Source Selection 5 1 read-only P6 Edge/Level Interrupt Source Selection 6 1 read-only P7 Edge/Level Interrupt Source Selection 7 1 read-only P8 Edge/Level Interrupt Source Selection 8 1 read-only P9 Edge/Level Interrupt Source Selection 9 1 read-only ESR Edge Select Register 0xC0 32 write-only n 0x0 0x0 P0 Edge Interrupt Selection 0 1 write-only P1 Edge Interrupt Selection 1 1 write-only P10 Edge Interrupt Selection 10 1 write-only P11 Edge Interrupt Selection 11 1 write-only P12 Edge Interrupt Selection 12 1 write-only P13 Edge Interrupt Selection 13 1 write-only P14 Edge Interrupt Selection 14 1 write-only P15 Edge Interrupt Selection 15 1 write-only P16 Edge Interrupt Selection 16 1 write-only P17 Edge Interrupt Selection 17 1 write-only P18 Edge Interrupt Selection 18 1 write-only P19 Edge Interrupt Selection 19 1 write-only P2 Edge Interrupt Selection 2 1 write-only P20 Edge Interrupt Selection 20 1 write-only P21 Edge Interrupt Selection 21 1 write-only P22 Edge Interrupt Selection 22 1 write-only P23 Edge Interrupt Selection 23 1 write-only P24 Edge Interrupt Selection 24 1 write-only P25 Edge Interrupt Selection 25 1 write-only P26 Edge Interrupt Selection 26 1 write-only P27 Edge Interrupt Selection 27 1 write-only P28 Edge Interrupt Selection 28 1 write-only P29 Edge Interrupt Selection 29 1 write-only P3 Edge Interrupt Selection 3 1 write-only P30 Edge Interrupt Selection 30 1 write-only P31 Edge Interrupt Selection 31 1 write-only P4 Edge Interrupt Selection 4 1 write-only P5 Edge Interrupt Selection 5 1 write-only P6 Edge Interrupt Selection 6 1 write-only P7 Edge Interrupt Selection 7 1 write-only P8 Edge Interrupt Selection 8 1 write-only P9 Edge Interrupt Selection 9 1 write-only FELLSR Falling Edge/Low-Level Select Register 0xD0 32 write-only n 0x0 0x0 P0 Falling Edge/Low-Level Interrupt Selection 0 1 write-only P1 Falling Edge/Low-Level Interrupt Selection 1 1 write-only P10 Falling Edge/Low-Level Interrupt Selection 10 1 write-only P11 Falling Edge/Low-Level Interrupt Selection 11 1 write-only P12 Falling Edge/Low-Level Interrupt Selection 12 1 write-only P13 Falling Edge/Low-Level Interrupt Selection 13 1 write-only P14 Falling Edge/Low-Level Interrupt Selection 14 1 write-only P15 Falling Edge/Low-Level Interrupt Selection 15 1 write-only P16 Falling Edge/Low-Level Interrupt Selection 16 1 write-only P17 Falling Edge/Low-Level Interrupt Selection 17 1 write-only P18 Falling Edge/Low-Level Interrupt Selection 18 1 write-only P19 Falling Edge/Low-Level Interrupt Selection 19 1 write-only P2 Falling Edge/Low-Level Interrupt Selection 2 1 write-only P20 Falling Edge/Low-Level Interrupt Selection 20 1 write-only P21 Falling Edge/Low-Level Interrupt Selection 21 1 write-only P22 Falling Edge/Low-Level Interrupt Selection 22 1 write-only P23 Falling Edge/Low-Level Interrupt Selection 23 1 write-only P24 Falling Edge/Low-Level Interrupt Selection 24 1 write-only P25 Falling Edge/Low-Level Interrupt Selection 25 1 write-only P26 Falling Edge/Low-Level Interrupt Selection 26 1 write-only P27 Falling Edge/Low-Level Interrupt Selection 27 1 write-only P28 Falling Edge/Low-Level Interrupt Selection 28 1 write-only P29 Falling Edge/Low-Level Interrupt Selection 29 1 write-only P3 Falling Edge/Low-Level Interrupt Selection 3 1 write-only P30 Falling Edge/Low-Level Interrupt Selection 30 1 write-only P31 Falling Edge/Low-Level Interrupt Selection 31 1 write-only P4 Falling Edge/Low-Level Interrupt Selection 4 1 write-only P5 Falling Edge/Low-Level Interrupt Selection 5 1 write-only P6 Falling Edge/Low-Level Interrupt Selection 6 1 write-only P7 Falling Edge/Low-Level Interrupt Selection 7 1 write-only P8 Falling Edge/Low-Level Interrupt Selection 8 1 write-only P9 Falling Edge/Low-Level Interrupt Selection 9 1 write-only FRLHSR Fall/Rise - Low/High Status Register 0xD8 32 read-only n 0x0 0x0 P0 Edge/Level Interrupt Source Selection 0 1 read-only P1 Edge/Level Interrupt Source Selection 1 1 read-only P10 Edge/Level Interrupt Source Selection 10 1 read-only P11 Edge/Level Interrupt Source Selection 11 1 read-only P12 Edge/Level Interrupt Source Selection 12 1 read-only P13 Edge/Level Interrupt Source Selection 13 1 read-only P14 Edge/Level Interrupt Source Selection 14 1 read-only P15 Edge/Level Interrupt Source Selection 15 1 read-only P16 Edge/Level Interrupt Source Selection 16 1 read-only P17 Edge/Level Interrupt Source Selection 17 1 read-only P18 Edge/Level Interrupt Source Selection 18 1 read-only P19 Edge/Level Interrupt Source Selection 19 1 read-only P2 Edge/Level Interrupt Source Selection 2 1 read-only P20 Edge/Level Interrupt Source Selection 20 1 read-only P21 Edge/Level Interrupt Source Selection 21 1 read-only P22 Edge/Level Interrupt Source Selection 22 1 read-only P23 Edge/Level Interrupt Source Selection 23 1 read-only P24 Edge/Level Interrupt Source Selection 24 1 read-only P25 Edge/Level Interrupt Source Selection 25 1 read-only P26 Edge/Level Interrupt Source Selection 26 1 read-only P27 Edge/Level Interrupt Source Selection 27 1 read-only P28 Edge/Level Interrupt Source Selection 28 1 read-only P29 Edge/Level Interrupt Source Selection 29 1 read-only P3 Edge/Level Interrupt Source Selection 3 1 read-only P30 Edge/Level Interrupt Source Selection 30 1 read-only P31 Edge/Level Interrupt Source Selection 31 1 read-only P4 Edge/Level Interrupt Source Selection 4 1 read-only P5 Edge/Level Interrupt Source Selection 5 1 read-only P6 Edge/Level Interrupt Source Selection 6 1 read-only P7 Edge/Level Interrupt Source Selection 7 1 read-only P8 Edge/Level Interrupt Source Selection 8 1 read-only P9 Edge/Level Interrupt Source Selection 9 1 read-only IDR Interrupt Disable Register 0x44 32 write-only n 0x0 0x0 P0 Input Change Interrupt Disable 0 1 write-only P1 Input Change Interrupt Disable 1 1 write-only P10 Input Change Interrupt Disable 10 1 write-only P11 Input Change Interrupt Disable 11 1 write-only P12 Input Change Interrupt Disable 12 1 write-only P13 Input Change Interrupt Disable 13 1 write-only P14 Input Change Interrupt Disable 14 1 write-only P15 Input Change Interrupt Disable 15 1 write-only P16 Input Change Interrupt Disable 16 1 write-only P17 Input Change Interrupt Disable 17 1 write-only P18 Input Change Interrupt Disable 18 1 write-only P19 Input Change Interrupt Disable 19 1 write-only P2 Input Change Interrupt Disable 2 1 write-only P20 Input Change Interrupt Disable 20 1 write-only P21 Input Change Interrupt Disable 21 1 write-only P22 Input Change Interrupt Disable 22 1 write-only P23 Input Change Interrupt Disable 23 1 write-only P24 Input Change Interrupt Disable 24 1 write-only P25 Input Change Interrupt Disable 25 1 write-only P26 Input Change Interrupt Disable 26 1 write-only P27 Input Change Interrupt Disable 27 1 write-only P28 Input Change Interrupt Disable 28 1 write-only P29 Input Change Interrupt Disable 29 1 write-only P3 Input Change Interrupt Disable 3 1 write-only P30 Input Change Interrupt Disable 30 1 write-only P31 Input Change Interrupt Disable 31 1 write-only P4 Input Change Interrupt Disable 4 1 write-only P5 Input Change Interrupt Disable 5 1 write-only P6 Input Change Interrupt Disable 6 1 write-only P7 Input Change Interrupt Disable 7 1 write-only P8 Input Change Interrupt Disable 8 1 write-only P9 Input Change Interrupt Disable 9 1 write-only IER Interrupt Enable Register 0x40 32 write-only n 0x0 0x0 P0 Input Change Interrupt Enable 0 1 write-only P1 Input Change Interrupt Enable 1 1 write-only P10 Input Change Interrupt Enable 10 1 write-only P11 Input Change Interrupt Enable 11 1 write-only P12 Input Change Interrupt Enable 12 1 write-only P13 Input Change Interrupt Enable 13 1 write-only P14 Input Change Interrupt Enable 14 1 write-only P15 Input Change Interrupt Enable 15 1 write-only P16 Input Change Interrupt Enable 16 1 write-only P17 Input Change Interrupt Enable 17 1 write-only P18 Input Change Interrupt Enable 18 1 write-only P19 Input Change Interrupt Enable 19 1 write-only P2 Input Change Interrupt Enable 2 1 write-only P20 Input Change Interrupt Enable 20 1 write-only P21 Input Change Interrupt Enable 21 1 write-only P22 Input Change Interrupt Enable 22 1 write-only P23 Input Change Interrupt Enable 23 1 write-only P24 Input Change Interrupt Enable 24 1 write-only P25 Input Change Interrupt Enable 25 1 write-only P26 Input Change Interrupt Enable 26 1 write-only P27 Input Change Interrupt Enable 27 1 write-only P28 Input Change Interrupt Enable 28 1 write-only P29 Input Change Interrupt Enable 29 1 write-only P3 Input Change Interrupt Enable 3 1 write-only P30 Input Change Interrupt Enable 30 1 write-only P31 Input Change Interrupt Enable 31 1 write-only P4 Input Change Interrupt Enable 4 1 write-only P5 Input Change Interrupt Enable 5 1 write-only P6 Input Change Interrupt Enable 6 1 write-only P7 Input Change Interrupt Enable 7 1 write-only P8 Input Change Interrupt Enable 8 1 write-only P9 Input Change Interrupt Enable 9 1 write-only IFDR Glitch Input Filter Disable Register 0x24 32 write-only n 0x0 0x0 P0 Input Filter Disable 0 1 write-only P1 Input Filter Disable 1 1 write-only P10 Input Filter Disable 10 1 write-only P11 Input Filter Disable 11 1 write-only P12 Input Filter Disable 12 1 write-only P13 Input Filter Disable 13 1 write-only P14 Input Filter Disable 14 1 write-only P15 Input Filter Disable 15 1 write-only P16 Input Filter Disable 16 1 write-only P17 Input Filter Disable 17 1 write-only P18 Input Filter Disable 18 1 write-only P19 Input Filter Disable 19 1 write-only P2 Input Filter Disable 2 1 write-only P20 Input Filter Disable 20 1 write-only P21 Input Filter Disable 21 1 write-only P22 Input Filter Disable 22 1 write-only P23 Input Filter Disable 23 1 write-only P24 Input Filter Disable 24 1 write-only P25 Input Filter Disable 25 1 write-only P26 Input Filter Disable 26 1 write-only P27 Input Filter Disable 27 1 write-only P28 Input Filter Disable 28 1 write-only P29 Input Filter Disable 29 1 write-only P3 Input Filter Disable 3 1 write-only P30 Input Filter Disable 30 1 write-only P31 Input Filter Disable 31 1 write-only P4 Input Filter Disable 4 1 write-only P5 Input Filter Disable 5 1 write-only P6 Input Filter Disable 6 1 write-only P7 Input Filter Disable 7 1 write-only P8 Input Filter Disable 8 1 write-only P9 Input Filter Disable 9 1 write-only IFER Glitch Input Filter Enable Register 0x20 32 write-only n 0x0 0x0 P0 Input Filter Enable 0 1 write-only P1 Input Filter Enable 1 1 write-only P10 Input Filter Enable 10 1 write-only P11 Input Filter Enable 11 1 write-only P12 Input Filter Enable 12 1 write-only P13 Input Filter Enable 13 1 write-only P14 Input Filter Enable 14 1 write-only P15 Input Filter Enable 15 1 write-only P16 Input Filter Enable 16 1 write-only P17 Input Filter Enable 17 1 write-only P18 Input Filter Enable 18 1 write-only P19 Input Filter Enable 19 1 write-only P2 Input Filter Enable 2 1 write-only P20 Input Filter Enable 20 1 write-only P21 Input Filter Enable 21 1 write-only P22 Input Filter Enable 22 1 write-only P23 Input Filter Enable 23 1 write-only P24 Input Filter Enable 24 1 write-only P25 Input Filter Enable 25 1 write-only P26 Input Filter Enable 26 1 write-only P27 Input Filter Enable 27 1 write-only P28 Input Filter Enable 28 1 write-only P29 Input Filter Enable 29 1 write-only P3 Input Filter Enable 3 1 write-only P30 Input Filter Enable 30 1 write-only P31 Input Filter Enable 31 1 write-only P4 Input Filter Enable 4 1 write-only P5 Input Filter Enable 5 1 write-only P6 Input Filter Enable 6 1 write-only P7 Input Filter Enable 7 1 write-only P8 Input Filter Enable 8 1 write-only P9 Input Filter Enable 9 1 write-only IFSCDR Input Filter Slow Clock Disable Register 0x80 32 write-only n 0x0 0x0 P0 Peripheral Clock Glitch Filtering Select 0 1 write-only P1 Peripheral Clock Glitch Filtering Select 1 1 write-only P10 Peripheral Clock Glitch Filtering Select 10 1 write-only P11 Peripheral Clock Glitch Filtering Select 11 1 write-only P12 Peripheral Clock Glitch Filtering Select 12 1 write-only P13 Peripheral Clock Glitch Filtering Select 13 1 write-only P14 Peripheral Clock Glitch Filtering Select 14 1 write-only P15 Peripheral Clock Glitch Filtering Select 15 1 write-only P16 Peripheral Clock Glitch Filtering Select 16 1 write-only P17 Peripheral Clock Glitch Filtering Select 17 1 write-only P18 Peripheral Clock Glitch Filtering Select 18 1 write-only P19 Peripheral Clock Glitch Filtering Select 19 1 write-only P2 Peripheral Clock Glitch Filtering Select 2 1 write-only P20 Peripheral Clock Glitch Filtering Select 20 1 write-only P21 Peripheral Clock Glitch Filtering Select 21 1 write-only P22 Peripheral Clock Glitch Filtering Select 22 1 write-only P23 Peripheral Clock Glitch Filtering Select 23 1 write-only P24 Peripheral Clock Glitch Filtering Select 24 1 write-only P25 Peripheral Clock Glitch Filtering Select 25 1 write-only P26 Peripheral Clock Glitch Filtering Select 26 1 write-only P27 Peripheral Clock Glitch Filtering Select 27 1 write-only P28 Peripheral Clock Glitch Filtering Select 28 1 write-only P29 Peripheral Clock Glitch Filtering Select 29 1 write-only P3 Peripheral Clock Glitch Filtering Select 3 1 write-only P30 Peripheral Clock Glitch Filtering Select 30 1 write-only P31 Peripheral Clock Glitch Filtering Select 31 1 write-only P4 Peripheral Clock Glitch Filtering Select 4 1 write-only P5 Peripheral Clock Glitch Filtering Select 5 1 write-only P6 Peripheral Clock Glitch Filtering Select 6 1 write-only P7 Peripheral Clock Glitch Filtering Select 7 1 write-only P8 Peripheral Clock Glitch Filtering Select 8 1 write-only P9 Peripheral Clock Glitch Filtering Select 9 1 write-only IFSCER Input Filter Slow Clock Enable Register 0x84 32 write-only n 0x0 0x0 P0 Slow Clock Debouncing Filtering Select 0 1 write-only P1 Slow Clock Debouncing Filtering Select 1 1 write-only P10 Slow Clock Debouncing Filtering Select 10 1 write-only P11 Slow Clock Debouncing Filtering Select 11 1 write-only P12 Slow Clock Debouncing Filtering Select 12 1 write-only P13 Slow Clock Debouncing Filtering Select 13 1 write-only P14 Slow Clock Debouncing Filtering Select 14 1 write-only P15 Slow Clock Debouncing Filtering Select 15 1 write-only P16 Slow Clock Debouncing Filtering Select 16 1 write-only P17 Slow Clock Debouncing Filtering Select 17 1 write-only P18 Slow Clock Debouncing Filtering Select 18 1 write-only P19 Slow Clock Debouncing Filtering Select 19 1 write-only P2 Slow Clock Debouncing Filtering Select 2 1 write-only P20 Slow Clock Debouncing Filtering Select 20 1 write-only P21 Slow Clock Debouncing Filtering Select 21 1 write-only P22 Slow Clock Debouncing Filtering Select 22 1 write-only P23 Slow Clock Debouncing Filtering Select 23 1 write-only P24 Slow Clock Debouncing Filtering Select 24 1 write-only P25 Slow Clock Debouncing Filtering Select 25 1 write-only P26 Slow Clock Debouncing Filtering Select 26 1 write-only P27 Slow Clock Debouncing Filtering Select 27 1 write-only P28 Slow Clock Debouncing Filtering Select 28 1 write-only P29 Slow Clock Debouncing Filtering Select 29 1 write-only P3 Slow Clock Debouncing Filtering Select 3 1 write-only P30 Slow Clock Debouncing Filtering Select 30 1 write-only P31 Slow Clock Debouncing Filtering Select 31 1 write-only P4 Slow Clock Debouncing Filtering Select 4 1 write-only P5 Slow Clock Debouncing Filtering Select 5 1 write-only P6 Slow Clock Debouncing Filtering Select 6 1 write-only P7 Slow Clock Debouncing Filtering Select 7 1 write-only P8 Slow Clock Debouncing Filtering Select 8 1 write-only P9 Slow Clock Debouncing Filtering Select 9 1 write-only IFSCSR Input Filter Slow Clock Status Register 0x88 32 read-only n 0x0 0x0 P0 Glitch or Debouncing Filter Selection Status 0 1 read-only P1 Glitch or Debouncing Filter Selection Status 1 1 read-only P10 Glitch or Debouncing Filter Selection Status 10 1 read-only P11 Glitch or Debouncing Filter Selection Status 11 1 read-only P12 Glitch or Debouncing Filter Selection Status 12 1 read-only P13 Glitch or Debouncing Filter Selection Status 13 1 read-only P14 Glitch or Debouncing Filter Selection Status 14 1 read-only P15 Glitch or Debouncing Filter Selection Status 15 1 read-only P16 Glitch or Debouncing Filter Selection Status 16 1 read-only P17 Glitch or Debouncing Filter Selection Status 17 1 read-only P18 Glitch or Debouncing Filter Selection Status 18 1 read-only P19 Glitch or Debouncing Filter Selection Status 19 1 read-only P2 Glitch or Debouncing Filter Selection Status 2 1 read-only P20 Glitch or Debouncing Filter Selection Status 20 1 read-only P21 Glitch or Debouncing Filter Selection Status 21 1 read-only P22 Glitch or Debouncing Filter Selection Status 22 1 read-only P23 Glitch or Debouncing Filter Selection Status 23 1 read-only P24 Glitch or Debouncing Filter Selection Status 24 1 read-only P25 Glitch or Debouncing Filter Selection Status 25 1 read-only P26 Glitch or Debouncing Filter Selection Status 26 1 read-only P27 Glitch or Debouncing Filter Selection Status 27 1 read-only P28 Glitch or Debouncing Filter Selection Status 28 1 read-only P29 Glitch or Debouncing Filter Selection Status 29 1 read-only P3 Glitch or Debouncing Filter Selection Status 3 1 read-only P30 Glitch or Debouncing Filter Selection Status 30 1 read-only P31 Glitch or Debouncing Filter Selection Status 31 1 read-only P4 Glitch or Debouncing Filter Selection Status 4 1 read-only P5 Glitch or Debouncing Filter Selection Status 5 1 read-only P6 Glitch or Debouncing Filter Selection Status 6 1 read-only P7 Glitch or Debouncing Filter Selection Status 7 1 read-only P8 Glitch or Debouncing Filter Selection Status 8 1 read-only P9 Glitch or Debouncing Filter Selection Status 9 1 read-only IFSR Glitch Input Filter Status Register 0x28 32 read-only n 0x0 0x0 P0 Input Filter Status 0 1 read-only P1 Input Filter Status 1 1 read-only P10 Input Filter Status 10 1 read-only P11 Input Filter Status 11 1 read-only P12 Input Filter Status 12 1 read-only P13 Input Filter Status 13 1 read-only P14 Input Filter Status 14 1 read-only P15 Input Filter Status 15 1 read-only P16 Input Filter Status 16 1 read-only P17 Input Filter Status 17 1 read-only P18 Input Filter Status 18 1 read-only P19 Input Filter Status 19 1 read-only P2 Input Filter Status 2 1 read-only P20 Input Filter Status 20 1 read-only P21 Input Filter Status 21 1 read-only P22 Input Filter Status 22 1 read-only P23 Input Filter Status 23 1 read-only P24 Input Filter Status 24 1 read-only P25 Input Filter Status 25 1 read-only P26 Input Filter Status 26 1 read-only P27 Input Filter Status 27 1 read-only P28 Input Filter Status 28 1 read-only P29 Input Filter Status 29 1 read-only P3 Input Filter Status 3 1 read-only P30 Input Filter Status 30 1 read-only P31 Input Filter Status 31 1 read-only P4 Input Filter Status 4 1 read-only P5 Input Filter Status 5 1 read-only P6 Input Filter Status 6 1 read-only P7 Input Filter Status 7 1 read-only P8 Input Filter Status 8 1 read-only P9 Input Filter Status 9 1 read-only IMR Interrupt Mask Register 0x48 32 read-only n 0x0 0x0 P0 Input Change Interrupt Mask 0 1 read-only P1 Input Change Interrupt Mask 1 1 read-only P10 Input Change Interrupt Mask 10 1 read-only P11 Input Change Interrupt Mask 11 1 read-only P12 Input Change Interrupt Mask 12 1 read-only P13 Input Change Interrupt Mask 13 1 read-only P14 Input Change Interrupt Mask 14 1 read-only P15 Input Change Interrupt Mask 15 1 read-only P16 Input Change Interrupt Mask 16 1 read-only P17 Input Change Interrupt Mask 17 1 read-only P18 Input Change Interrupt Mask 18 1 read-only P19 Input Change Interrupt Mask 19 1 read-only P2 Input Change Interrupt Mask 2 1 read-only P20 Input Change Interrupt Mask 20 1 read-only P21 Input Change Interrupt Mask 21 1 read-only P22 Input Change Interrupt Mask 22 1 read-only P23 Input Change Interrupt Mask 23 1 read-only P24 Input Change Interrupt Mask 24 1 read-only P25 Input Change Interrupt Mask 25 1 read-only P26 Input Change Interrupt Mask 26 1 read-only P27 Input Change Interrupt Mask 27 1 read-only P28 Input Change Interrupt Mask 28 1 read-only P29 Input Change Interrupt Mask 29 1 read-only P3 Input Change Interrupt Mask 3 1 read-only P30 Input Change Interrupt Mask 30 1 read-only P31 Input Change Interrupt Mask 31 1 read-only P4 Input Change Interrupt Mask 4 1 read-only P5 Input Change Interrupt Mask 5 1 read-only P6 Input Change Interrupt Mask 6 1 read-only P7 Input Change Interrupt Mask 7 1 read-only P8 Input Change Interrupt Mask 8 1 read-only P9 Input Change Interrupt Mask 9 1 read-only ISLR PIO Interrupt Security Level Register 0xC 32 read-write n 0x0 0x0 P0 PIO Interrupt Security Level 0 1 read-write P1 PIO Interrupt Security Level 1 1 read-write P10 PIO Interrupt Security Level 10 1 read-write P11 PIO Interrupt Security Level 11 1 read-write P12 PIO Interrupt Security Level 12 1 read-write P13 PIO Interrupt Security Level 13 1 read-write P14 PIO Interrupt Security Level 14 1 read-write P15 PIO Interrupt Security Level 15 1 read-write P16 PIO Interrupt Security Level 16 1 read-write P17 PIO Interrupt Security Level 17 1 read-write P18 PIO Interrupt Security Level 18 1 read-write P19 PIO Interrupt Security Level 19 1 read-write P2 PIO Interrupt Security Level 2 1 read-write P20 PIO Interrupt Security Level 20 1 read-write P21 PIO Interrupt Security Level 21 1 read-write P22 PIO Interrupt Security Level 22 1 read-write P23 PIO Interrupt Security Level 23 1 read-write P24 PIO Interrupt Security Level 24 1 read-write P25 PIO Interrupt Security Level 25 1 read-write P26 PIO Interrupt Security Level 26 1 read-write P27 PIO Interrupt Security Level 27 1 read-write P28 PIO Interrupt Security Level 28 1 read-write P29 PIO Interrupt Security Level 29 1 read-write P3 PIO Interrupt Security Level 3 1 read-write P30 PIO Interrupt Security Level 30 1 read-write P31 PIO Interrupt Security Level 31 1 read-write P4 PIO Interrupt Security Level 4 1 read-write P5 PIO Interrupt Security Level 5 1 read-write P6 PIO Interrupt Security Level 6 1 read-write P7 PIO Interrupt Security Level 7 1 read-write P8 PIO Interrupt Security Level 8 1 read-write P9 PIO Interrupt Security Level 9 1 read-write ISR Interrupt Status Register 0x4C 32 read-only n 0x0 0x0 P0 Input Change Interrupt Status 0 1 read-only P1 Input Change Interrupt Status 1 1 read-only P10 Input Change Interrupt Status 10 1 read-only P11 Input Change Interrupt Status 11 1 read-only P12 Input Change Interrupt Status 12 1 read-only P13 Input Change Interrupt Status 13 1 read-only P14 Input Change Interrupt Status 14 1 read-only P15 Input Change Interrupt Status 15 1 read-only P16 Input Change Interrupt Status 16 1 read-only P17 Input Change Interrupt Status 17 1 read-only P18 Input Change Interrupt Status 18 1 read-only P19 Input Change Interrupt Status 19 1 read-only P2 Input Change Interrupt Status 2 1 read-only P20 Input Change Interrupt Status 20 1 read-only P21 Input Change Interrupt Status 21 1 read-only P22 Input Change Interrupt Status 22 1 read-only P23 Input Change Interrupt Status 23 1 read-only P24 Input Change Interrupt Status 24 1 read-only P25 Input Change Interrupt Status 25 1 read-only P26 Input Change Interrupt Status 26 1 read-only P27 Input Change Interrupt Status 27 1 read-only P28 Input Change Interrupt Status 28 1 read-only P29 Input Change Interrupt Status 29 1 read-only P3 Input Change Interrupt Status 3 1 read-only P30 Input Change Interrupt Status 30 1 read-only P31 Input Change Interrupt Status 31 1 read-only P4 Input Change Interrupt Status 4 1 read-only P5 Input Change Interrupt Status 5 1 read-only P6 Input Change Interrupt Status 6 1 read-only P7 Input Change Interrupt Status 7 1 read-only P8 Input Change Interrupt Status 8 1 read-only P9 Input Change Interrupt Status 9 1 read-only LSR Level Select Register 0xC4 32 write-only n 0x0 0x0 P0 Level Interrupt Selection 0 1 write-only P1 Level Interrupt Selection 1 1 write-only P10 Level Interrupt Selection 10 1 write-only P11 Level Interrupt Selection 11 1 write-only P12 Level Interrupt Selection 12 1 write-only P13 Level Interrupt Selection 13 1 write-only P14 Level Interrupt Selection 14 1 write-only P15 Level Interrupt Selection 15 1 write-only P16 Level Interrupt Selection 16 1 write-only P17 Level Interrupt Selection 17 1 write-only P18 Level Interrupt Selection 18 1 write-only P19 Level Interrupt Selection 19 1 write-only P2 Level Interrupt Selection 2 1 write-only P20 Level Interrupt Selection 20 1 write-only P21 Level Interrupt Selection 21 1 write-only P22 Level Interrupt Selection 22 1 write-only P23 Level Interrupt Selection 23 1 write-only P24 Level Interrupt Selection 24 1 write-only P25 Level Interrupt Selection 25 1 write-only P26 Level Interrupt Selection 26 1 write-only P27 Level Interrupt Selection 27 1 write-only P28 Level Interrupt Selection 28 1 write-only P29 Level Interrupt Selection 29 1 write-only P3 Level Interrupt Selection 3 1 write-only P30 Level Interrupt Selection 30 1 write-only P31 Level Interrupt Selection 31 1 write-only P4 Level Interrupt Selection 4 1 write-only P5 Level Interrupt Selection 5 1 write-only P6 Level Interrupt Selection 6 1 write-only P7 Level Interrupt Selection 7 1 write-only P8 Level Interrupt Selection 8 1 write-only P9 Level Interrupt Selection 9 1 write-only MDDR Multi-driver Disable Register 0x54 32 write-only n 0x0 0x0 P0 Multi-drive Disable 0 1 write-only P1 Multi-drive Disable 1 1 write-only P10 Multi-drive Disable 10 1 write-only P11 Multi-drive Disable 11 1 write-only P12 Multi-drive Disable 12 1 write-only P13 Multi-drive Disable 13 1 write-only P14 Multi-drive Disable 14 1 write-only P15 Multi-drive Disable 15 1 write-only P16 Multi-drive Disable 16 1 write-only P17 Multi-drive Disable 17 1 write-only P18 Multi-drive Disable 18 1 write-only P19 Multi-drive Disable 19 1 write-only P2 Multi-drive Disable 2 1 write-only P20 Multi-drive Disable 20 1 write-only P21 Multi-drive Disable 21 1 write-only P22 Multi-drive Disable 22 1 write-only P23 Multi-drive Disable 23 1 write-only P24 Multi-drive Disable 24 1 write-only P25 Multi-drive Disable 25 1 write-only P26 Multi-drive Disable 26 1 write-only P27 Multi-drive Disable 27 1 write-only P28 Multi-drive Disable 28 1 write-only P29 Multi-drive Disable 29 1 write-only P3 Multi-drive Disable 3 1 write-only P30 Multi-drive Disable 30 1 write-only P31 Multi-drive Disable 31 1 write-only P4 Multi-drive Disable 4 1 write-only P5 Multi-drive Disable 5 1 write-only P6 Multi-drive Disable 6 1 write-only P7 Multi-drive Disable 7 1 write-only P8 Multi-drive Disable 8 1 write-only P9 Multi-drive Disable 9 1 write-only MDER Multi-driver Enable Register 0x50 32 write-only n 0x0 0x0 P0 Multi-drive Enable 0 1 write-only P1 Multi-drive Enable 1 1 write-only P10 Multi-drive Enable 10 1 write-only P11 Multi-drive Enable 11 1 write-only P12 Multi-drive Enable 12 1 write-only P13 Multi-drive Enable 13 1 write-only P14 Multi-drive Enable 14 1 write-only P15 Multi-drive Enable 15 1 write-only P16 Multi-drive Enable 16 1 write-only P17 Multi-drive Enable 17 1 write-only P18 Multi-drive Enable 18 1 write-only P19 Multi-drive Enable 19 1 write-only P2 Multi-drive Enable 2 1 write-only P20 Multi-drive Enable 20 1 write-only P21 Multi-drive Enable 21 1 write-only P22 Multi-drive Enable 22 1 write-only P23 Multi-drive Enable 23 1 write-only P24 Multi-drive Enable 24 1 write-only P25 Multi-drive Enable 25 1 write-only P26 Multi-drive Enable 26 1 write-only P27 Multi-drive Enable 27 1 write-only P28 Multi-drive Enable 28 1 write-only P29 Multi-drive Enable 29 1 write-only P3 Multi-drive Enable 3 1 write-only P30 Multi-drive Enable 30 1 write-only P31 Multi-drive Enable 31 1 write-only P4 Multi-drive Enable 4 1 write-only P5 Multi-drive Enable 5 1 write-only P6 Multi-drive Enable 6 1 write-only P7 Multi-drive Enable 7 1 write-only P8 Multi-drive Enable 8 1 write-only P9 Multi-drive Enable 9 1 write-only MDSR Multi-driver Status Register 0x58 32 read-only n 0x0 0x0 P0 Multi-drive Status 0 1 read-only P1 Multi-drive Status 1 1 read-only P10 Multi-drive Status 10 1 read-only P11 Multi-drive Status 11 1 read-only P12 Multi-drive Status 12 1 read-only P13 Multi-drive Status 13 1 read-only P14 Multi-drive Status 14 1 read-only P15 Multi-drive Status 15 1 read-only P16 Multi-drive Status 16 1 read-only P17 Multi-drive Status 17 1 read-only P18 Multi-drive Status 18 1 read-only P19 Multi-drive Status 19 1 read-only P2 Multi-drive Status 2 1 read-only P20 Multi-drive Status 20 1 read-only P21 Multi-drive Status 21 1 read-only P22 Multi-drive Status 22 1 read-only P23 Multi-drive Status 23 1 read-only P24 Multi-drive Status 24 1 read-only P25 Multi-drive Status 25 1 read-only P26 Multi-drive Status 26 1 read-only P27 Multi-drive Status 27 1 read-only P28 Multi-drive Status 28 1 read-only P29 Multi-drive Status 29 1 read-only P3 Multi-drive Status 3 1 read-only P30 Multi-drive Status 30 1 read-only P31 Multi-drive Status 31 1 read-only P4 Multi-drive Status 4 1 read-only P5 Multi-drive Status 5 1 read-only P6 Multi-drive Status 6 1 read-only P7 Multi-drive Status 7 1 read-only P8 Multi-drive Status 8 1 read-only P9 Multi-drive Status 9 1 read-only ODR Output Disable Register 0x14 32 write-only n 0x0 0x0 P0 Output Disable 0 1 write-only P1 Output Disable 1 1 write-only P10 Output Disable 10 1 write-only P11 Output Disable 11 1 write-only P12 Output Disable 12 1 write-only P13 Output Disable 13 1 write-only P14 Output Disable 14 1 write-only P15 Output Disable 15 1 write-only P16 Output Disable 16 1 write-only P17 Output Disable 17 1 write-only P18 Output Disable 18 1 write-only P19 Output Disable 19 1 write-only P2 Output Disable 2 1 write-only P20 Output Disable 20 1 write-only P21 Output Disable 21 1 write-only P22 Output Disable 22 1 write-only P23 Output Disable 23 1 write-only P24 Output Disable 24 1 write-only P25 Output Disable 25 1 write-only P26 Output Disable 26 1 write-only P27 Output Disable 27 1 write-only P28 Output Disable 28 1 write-only P29 Output Disable 29 1 write-only P3 Output Disable 3 1 write-only P30 Output Disable 30 1 write-only P31 Output Disable 31 1 write-only P4 Output Disable 4 1 write-only P5 Output Disable 5 1 write-only P6 Output Disable 6 1 write-only P7 Output Disable 7 1 write-only P8 Output Disable 8 1 write-only P9 Output Disable 9 1 write-only ODSR Output Data Status Register 0x38 32 read-write n 0x0 0x0 P0 Output Data Status 0 1 read-write P1 Output Data Status 1 1 read-write P10 Output Data Status 10 1 read-write P11 Output Data Status 11 1 read-write P12 Output Data Status 12 1 read-write P13 Output Data Status 13 1 read-write P14 Output Data Status 14 1 read-write P15 Output Data Status 15 1 read-write P16 Output Data Status 16 1 read-write P17 Output Data Status 17 1 read-write P18 Output Data Status 18 1 read-write P19 Output Data Status 19 1 read-write P2 Output Data Status 2 1 read-write P20 Output Data Status 20 1 read-write P21 Output Data Status 21 1 read-write P22 Output Data Status 22 1 read-write P23 Output Data Status 23 1 read-write P24 Output Data Status 24 1 read-write P25 Output Data Status 25 1 read-write P26 Output Data Status 26 1 read-write P27 Output Data Status 27 1 read-write P28 Output Data Status 28 1 read-write P29 Output Data Status 29 1 read-write P3 Output Data Status 3 1 read-write P30 Output Data Status 30 1 read-write P31 Output Data Status 31 1 read-write P4 Output Data Status 4 1 read-write P5 Output Data Status 5 1 read-write P6 Output Data Status 6 1 read-write P7 Output Data Status 7 1 read-write P8 Output Data Status 8 1 read-write P9 Output Data Status 9 1 read-write OER Output Enable Register 0x10 32 write-only n 0x0 0x0 P0 Output Enable 0 1 write-only P1 Output Enable 1 1 write-only P10 Output Enable 10 1 write-only P11 Output Enable 11 1 write-only P12 Output Enable 12 1 write-only P13 Output Enable 13 1 write-only P14 Output Enable 14 1 write-only P15 Output Enable 15 1 write-only P16 Output Enable 16 1 write-only P17 Output Enable 17 1 write-only P18 Output Enable 18 1 write-only P19 Output Enable 19 1 write-only P2 Output Enable 2 1 write-only P20 Output Enable 20 1 write-only P21 Output Enable 21 1 write-only P22 Output Enable 22 1 write-only P23 Output Enable 23 1 write-only P24 Output Enable 24 1 write-only P25 Output Enable 25 1 write-only P26 Output Enable 26 1 write-only P27 Output Enable 27 1 write-only P28 Output Enable 28 1 write-only P29 Output Enable 29 1 write-only P3 Output Enable 3 1 write-only P30 Output Enable 30 1 write-only P31 Output Enable 31 1 write-only P4 Output Enable 4 1 write-only P5 Output Enable 5 1 write-only P6 Output Enable 6 1 write-only P7 Output Enable 7 1 write-only P8 Output Enable 8 1 write-only P9 Output Enable 9 1 write-only OSR Output Status Register 0x18 32 read-only n 0x0 0x0 P0 Output Status 0 1 read-only P1 Output Status 1 1 read-only P10 Output Status 10 1 read-only P11 Output Status 11 1 read-only P12 Output Status 12 1 read-only P13 Output Status 13 1 read-only P14 Output Status 14 1 read-only P15 Output Status 15 1 read-only P16 Output Status 16 1 read-only P17 Output Status 17 1 read-only P18 Output Status 18 1 read-only P19 Output Status 19 1 read-only P2 Output Status 2 1 read-only P20 Output Status 20 1 read-only P21 Output Status 21 1 read-only P22 Output Status 22 1 read-only P23 Output Status 23 1 read-only P24 Output Status 24 1 read-only P25 Output Status 25 1 read-only P26 Output Status 26 1 read-only P27 Output Status 27 1 read-only P28 Output Status 28 1 read-only P29 Output Status 29 1 read-only P3 Output Status 3 1 read-only P30 Output Status 30 1 read-only P31 Output Status 31 1 read-only P4 Output Status 4 1 read-only P5 Output Status 5 1 read-only P6 Output Status 6 1 read-only P7 Output Status 7 1 read-only P8 Output Status 8 1 read-only P9 Output Status 9 1 read-only OWDR Output Write Disable 0xA4 32 write-only n 0x0 0x0 P0 Output Write Disable 0 1 write-only P1 Output Write Disable 1 1 write-only P10 Output Write Disable 10 1 write-only P11 Output Write Disable 11 1 write-only P12 Output Write Disable 12 1 write-only P13 Output Write Disable 13 1 write-only P14 Output Write Disable 14 1 write-only P15 Output Write Disable 15 1 write-only P16 Output Write Disable 16 1 write-only P17 Output Write Disable 17 1 write-only P18 Output Write Disable 18 1 write-only P19 Output Write Disable 19 1 write-only P2 Output Write Disable 2 1 write-only P20 Output Write Disable 20 1 write-only P21 Output Write Disable 21 1 write-only P22 Output Write Disable 22 1 write-only P23 Output Write Disable 23 1 write-only P24 Output Write Disable 24 1 write-only P25 Output Write Disable 25 1 write-only P26 Output Write Disable 26 1 write-only P27 Output Write Disable 27 1 write-only P28 Output Write Disable 28 1 write-only P29 Output Write Disable 29 1 write-only P3 Output Write Disable 3 1 write-only P30 Output Write Disable 30 1 write-only P31 Output Write Disable 31 1 write-only P4 Output Write Disable 4 1 write-only P5 Output Write Disable 5 1 write-only P6 Output Write Disable 6 1 write-only P7 Output Write Disable 7 1 write-only P8 Output Write Disable 8 1 write-only P9 Output Write Disable 9 1 write-only OWER Output Write Enable 0xA0 32 write-only n 0x0 0x0 P0 Output Write Enable 0 1 write-only P1 Output Write Enable 1 1 write-only P10 Output Write Enable 10 1 write-only P11 Output Write Enable 11 1 write-only P12 Output Write Enable 12 1 write-only P13 Output Write Enable 13 1 write-only P14 Output Write Enable 14 1 write-only P15 Output Write Enable 15 1 write-only P16 Output Write Enable 16 1 write-only P17 Output Write Enable 17 1 write-only P18 Output Write Enable 18 1 write-only P19 Output Write Enable 19 1 write-only P2 Output Write Enable 2 1 write-only P20 Output Write Enable 20 1 write-only P21 Output Write Enable 21 1 write-only P22 Output Write Enable 22 1 write-only P23 Output Write Enable 23 1 write-only P24 Output Write Enable 24 1 write-only P25 Output Write Enable 25 1 write-only P26 Output Write Enable 26 1 write-only P27 Output Write Enable 27 1 write-only P28 Output Write Enable 28 1 write-only P29 Output Write Enable 29 1 write-only P3 Output Write Enable 3 1 write-only P30 Output Write Enable 30 1 write-only P31 Output Write Enable 31 1 write-only P4 Output Write Enable 4 1 write-only P5 Output Write Enable 5 1 write-only P6 Output Write Enable 6 1 write-only P7 Output Write Enable 7 1 write-only P8 Output Write Enable 8 1 write-only P9 Output Write Enable 9 1 write-only OWSR Output Write Status Register 0xA8 32 read-only n 0x0 0x0 P0 Output Write Status 0 1 read-only P1 Output Write Status 1 1 read-only P10 Output Write Status 10 1 read-only P11 Output Write Status 11 1 read-only P12 Output Write Status 12 1 read-only P13 Output Write Status 13 1 read-only P14 Output Write Status 14 1 read-only P15 Output Write Status 15 1 read-only P16 Output Write Status 16 1 read-only P17 Output Write Status 17 1 read-only P18 Output Write Status 18 1 read-only P19 Output Write Status 19 1 read-only P2 Output Write Status 2 1 read-only P20 Output Write Status 20 1 read-only P21 Output Write Status 21 1 read-only P22 Output Write Status 22 1 read-only P23 Output Write Status 23 1 read-only P24 Output Write Status 24 1 read-only P25 Output Write Status 25 1 read-only P26 Output Write Status 26 1 read-only P27 Output Write Status 27 1 read-only P28 Output Write Status 28 1 read-only P29 Output Write Status 29 1 read-only P3 Output Write Status 3 1 read-only P30 Output Write Status 30 1 read-only P31 Output Write Status 31 1 read-only P4 Output Write Status 4 1 read-only P5 Output Write Status 5 1 read-only P6 Output Write Status 6 1 read-only P7 Output Write Status 7 1 read-only P8 Output Write Status 8 1 read-only P9 Output Write Status 9 1 read-only PDR PIO Disable Register 0x4 32 write-only n 0x0 0x0 P0 PIO Disable 0 1 write-only P1 PIO Disable 1 1 write-only P10 PIO Disable 10 1 write-only P11 PIO Disable 11 1 write-only P12 PIO Disable 12 1 write-only P13 PIO Disable 13 1 write-only P14 PIO Disable 14 1 write-only P15 PIO Disable 15 1 write-only P16 PIO Disable 16 1 write-only P17 PIO Disable 17 1 write-only P18 PIO Disable 18 1 write-only P19 PIO Disable 19 1 write-only P2 PIO Disable 2 1 write-only P20 PIO Disable 20 1 write-only P21 PIO Disable 21 1 write-only P22 PIO Disable 22 1 write-only P23 PIO Disable 23 1 write-only P24 PIO Disable 24 1 write-only P25 PIO Disable 25 1 write-only P26 PIO Disable 26 1 write-only P27 PIO Disable 27 1 write-only P28 PIO Disable 28 1 write-only P29 PIO Disable 29 1 write-only P3 PIO Disable 3 1 write-only P30 PIO Disable 30 1 write-only P31 PIO Disable 31 1 write-only P4 PIO Disable 4 1 write-only P5 PIO Disable 5 1 write-only P6 PIO Disable 6 1 write-only P7 PIO Disable 7 1 write-only P8 PIO Disable 8 1 write-only P9 PIO Disable 9 1 write-only PDSR Pin Data Status Register 0x3C 32 read-only n 0x0 0x0 P0 Output Data Status 0 1 read-only P1 Output Data Status 1 1 read-only P10 Output Data Status 10 1 read-only P11 Output Data Status 11 1 read-only P12 Output Data Status 12 1 read-only P13 Output Data Status 13 1 read-only P14 Output Data Status 14 1 read-only P15 Output Data Status 15 1 read-only P16 Output Data Status 16 1 read-only P17 Output Data Status 17 1 read-only P18 Output Data Status 18 1 read-only P19 Output Data Status 19 1 read-only P2 Output Data Status 2 1 read-only P20 Output Data Status 20 1 read-only P21 Output Data Status 21 1 read-only P22 Output Data Status 22 1 read-only P23 Output Data Status 23 1 read-only P24 Output Data Status 24 1 read-only P25 Output Data Status 25 1 read-only P26 Output Data Status 26 1 read-only P27 Output Data Status 27 1 read-only P28 Output Data Status 28 1 read-only P29 Output Data Status 29 1 read-only P3 Output Data Status 3 1 read-only P30 Output Data Status 30 1 read-only P31 Output Data Status 31 1 read-only P4 Output Data Status 4 1 read-only P5 Output Data Status 5 1 read-only P6 Output Data Status 6 1 read-only P7 Output Data Status 7 1 read-only P8 Output Data Status 8 1 read-only P9 Output Data Status 9 1 read-only PER PIO Enable Register 0x0 32 write-only n 0x0 0x0 P0 PIO Enable 0 1 write-only P1 PIO Enable 1 1 write-only P10 PIO Enable 10 1 write-only P11 PIO Enable 11 1 write-only P12 PIO Enable 12 1 write-only P13 PIO Enable 13 1 write-only P14 PIO Enable 14 1 write-only P15 PIO Enable 15 1 write-only P16 PIO Enable 16 1 write-only P17 PIO Enable 17 1 write-only P18 PIO Enable 18 1 write-only P19 PIO Enable 19 1 write-only P2 PIO Enable 2 1 write-only P20 PIO Enable 20 1 write-only P21 PIO Enable 21 1 write-only P22 PIO Enable 22 1 write-only P23 PIO Enable 23 1 write-only P24 PIO Enable 24 1 write-only P25 PIO Enable 25 1 write-only P26 PIO Enable 26 1 write-only P27 PIO Enable 27 1 write-only P28 PIO Enable 28 1 write-only P29 PIO Enable 29 1 write-only P3 PIO Enable 3 1 write-only P30 PIO Enable 30 1 write-only P31 PIO Enable 31 1 write-only P4 PIO Enable 4 1 write-only P5 PIO Enable 5 1 write-only P6 PIO Enable 6 1 write-only P7 PIO Enable 7 1 write-only P8 PIO Enable 8 1 write-only P9 PIO Enable 9 1 write-only PPDDR Pad Pull-Down Disable Register 0x90 32 write-only n 0x0 0x0 P0 Pull-Down Disable 0 1 write-only P1 Pull-Down Disable 1 1 write-only P10 Pull-Down Disable 10 1 write-only P11 Pull-Down Disable 11 1 write-only P12 Pull-Down Disable 12 1 write-only P13 Pull-Down Disable 13 1 write-only P14 Pull-Down Disable 14 1 write-only P15 Pull-Down Disable 15 1 write-only P16 Pull-Down Disable 16 1 write-only P17 Pull-Down Disable 17 1 write-only P18 Pull-Down Disable 18 1 write-only P19 Pull-Down Disable 19 1 write-only P2 Pull-Down Disable 2 1 write-only P20 Pull-Down Disable 20 1 write-only P21 Pull-Down Disable 21 1 write-only P22 Pull-Down Disable 22 1 write-only P23 Pull-Down Disable 23 1 write-only P24 Pull-Down Disable 24 1 write-only P25 Pull-Down Disable 25 1 write-only P26 Pull-Down Disable 26 1 write-only P27 Pull-Down Disable 27 1 write-only P28 Pull-Down Disable 28 1 write-only P29 Pull-Down Disable 29 1 write-only P3 Pull-Down Disable 3 1 write-only P30 Pull-Down Disable 30 1 write-only P31 Pull-Down Disable 31 1 write-only P4 Pull-Down Disable 4 1 write-only P5 Pull-Down Disable 5 1 write-only P6 Pull-Down Disable 6 1 write-only P7 Pull-Down Disable 7 1 write-only P8 Pull-Down Disable 8 1 write-only P9 Pull-Down Disable 9 1 write-only PPDER Pad Pull-Down Enable Register 0x94 32 write-only n 0x0 0x0 P0 Pull-Down Enable 0 1 write-only P1 Pull-Down Enable 1 1 write-only P10 Pull-Down Enable 10 1 write-only P11 Pull-Down Enable 11 1 write-only P12 Pull-Down Enable 12 1 write-only P13 Pull-Down Enable 13 1 write-only P14 Pull-Down Enable 14 1 write-only P15 Pull-Down Enable 15 1 write-only P16 Pull-Down Enable 16 1 write-only P17 Pull-Down Enable 17 1 write-only P18 Pull-Down Enable 18 1 write-only P19 Pull-Down Enable 19 1 write-only P2 Pull-Down Enable 2 1 write-only P20 Pull-Down Enable 20 1 write-only P21 Pull-Down Enable 21 1 write-only P22 Pull-Down Enable 22 1 write-only P23 Pull-Down Enable 23 1 write-only P24 Pull-Down Enable 24 1 write-only P25 Pull-Down Enable 25 1 write-only P26 Pull-Down Enable 26 1 write-only P27 Pull-Down Enable 27 1 write-only P28 Pull-Down Enable 28 1 write-only P29 Pull-Down Enable 29 1 write-only P3 Pull-Down Enable 3 1 write-only P30 Pull-Down Enable 30 1 write-only P31 Pull-Down Enable 31 1 write-only P4 Pull-Down Enable 4 1 write-only P5 Pull-Down Enable 5 1 write-only P6 Pull-Down Enable 6 1 write-only P7 Pull-Down Enable 7 1 write-only P8 Pull-Down Enable 8 1 write-only P9 Pull-Down Enable 9 1 write-only PPDSR Pad Pull-Down Status Register 0x98 32 read-only n 0x0 0x0 P0 Pull-Down Status 0 1 read-only P1 Pull-Down Status 1 1 read-only P10 Pull-Down Status 10 1 read-only P11 Pull-Down Status 11 1 read-only P12 Pull-Down Status 12 1 read-only P13 Pull-Down Status 13 1 read-only P14 Pull-Down Status 14 1 read-only P15 Pull-Down Status 15 1 read-only P16 Pull-Down Status 16 1 read-only P17 Pull-Down Status 17 1 read-only P18 Pull-Down Status 18 1 read-only P19 Pull-Down Status 19 1 read-only P2 Pull-Down Status 2 1 read-only P20 Pull-Down Status 20 1 read-only P21 Pull-Down Status 21 1 read-only P22 Pull-Down Status 22 1 read-only P23 Pull-Down Status 23 1 read-only P24 Pull-Down Status 24 1 read-only P25 Pull-Down Status 25 1 read-only P26 Pull-Down Status 26 1 read-only P27 Pull-Down Status 27 1 read-only P28 Pull-Down Status 28 1 read-only P29 Pull-Down Status 29 1 read-only P3 Pull-Down Status 3 1 read-only P30 Pull-Down Status 30 1 read-only P31 Pull-Down Status 31 1 read-only P4 Pull-Down Status 4 1 read-only P5 Pull-Down Status 5 1 read-only P6 Pull-Down Status 6 1 read-only P7 Pull-Down Status 7 1 read-only P8 Pull-Down Status 8 1 read-only P9 Pull-Down Status 9 1 read-only PSR PIO Status Register 0x8 32 read-only n 0x0 0x0 P0 PIO Status 0 1 read-only P1 PIO Status 1 1 read-only P10 PIO Status 10 1 read-only P11 PIO Status 11 1 read-only P12 PIO Status 12 1 read-only P13 PIO Status 13 1 read-only P14 PIO Status 14 1 read-only P15 PIO Status 15 1 read-only P16 PIO Status 16 1 read-only P17 PIO Status 17 1 read-only P18 PIO Status 18 1 read-only P19 PIO Status 19 1 read-only P2 PIO Status 2 1 read-only P20 PIO Status 20 1 read-only P21 PIO Status 21 1 read-only P22 PIO Status 22 1 read-only P23 PIO Status 23 1 read-only P24 PIO Status 24 1 read-only P25 PIO Status 25 1 read-only P26 PIO Status 26 1 read-only P27 PIO Status 27 1 read-only P28 PIO Status 28 1 read-only P29 PIO Status 29 1 read-only P3 PIO Status 3 1 read-only P30 PIO Status 30 1 read-only P31 PIO Status 31 1 read-only P4 PIO Status 4 1 read-only P5 PIO Status 5 1 read-only P6 PIO Status 6 1 read-only P7 PIO Status 7 1 read-only P8 PIO Status 8 1 read-only P9 PIO Status 9 1 read-only PUDR Pull-Up Disable Register 0x60 32 write-only n 0x0 0x0 P0 Pull-Up Disable 0 1 write-only P1 Pull-Up Disable 1 1 write-only P10 Pull-Up Disable 10 1 write-only P11 Pull-Up Disable 11 1 write-only P12 Pull-Up Disable 12 1 write-only P13 Pull-Up Disable 13 1 write-only P14 Pull-Up Disable 14 1 write-only P15 Pull-Up Disable 15 1 write-only P16 Pull-Up Disable 16 1 write-only P17 Pull-Up Disable 17 1 write-only P18 Pull-Up Disable 18 1 write-only P19 Pull-Up Disable 19 1 write-only P2 Pull-Up Disable 2 1 write-only P20 Pull-Up Disable 20 1 write-only P21 Pull-Up Disable 21 1 write-only P22 Pull-Up Disable 22 1 write-only P23 Pull-Up Disable 23 1 write-only P24 Pull-Up Disable 24 1 write-only P25 Pull-Up Disable 25 1 write-only P26 Pull-Up Disable 26 1 write-only P27 Pull-Up Disable 27 1 write-only P28 Pull-Up Disable 28 1 write-only P29 Pull-Up Disable 29 1 write-only P3 Pull-Up Disable 3 1 write-only P30 Pull-Up Disable 30 1 write-only P31 Pull-Up Disable 31 1 write-only P4 Pull-Up Disable 4 1 write-only P5 Pull-Up Disable 5 1 write-only P6 Pull-Up Disable 6 1 write-only P7 Pull-Up Disable 7 1 write-only P8 Pull-Up Disable 8 1 write-only P9 Pull-Up Disable 9 1 write-only PUER Pull-Up Enable Register 0x64 32 write-only n 0x0 0x0 P0 Pull-Up Enable 0 1 write-only P1 Pull-Up Enable 1 1 write-only P10 Pull-Up Enable 10 1 write-only P11 Pull-Up Enable 11 1 write-only P12 Pull-Up Enable 12 1 write-only P13 Pull-Up Enable 13 1 write-only P14 Pull-Up Enable 14 1 write-only P15 Pull-Up Enable 15 1 write-only P16 Pull-Up Enable 16 1 write-only P17 Pull-Up Enable 17 1 write-only P18 Pull-Up Enable 18 1 write-only P19 Pull-Up Enable 19 1 write-only P2 Pull-Up Enable 2 1 write-only P20 Pull-Up Enable 20 1 write-only P21 Pull-Up Enable 21 1 write-only P22 Pull-Up Enable 22 1 write-only P23 Pull-Up Enable 23 1 write-only P24 Pull-Up Enable 24 1 write-only P25 Pull-Up Enable 25 1 write-only P26 Pull-Up Enable 26 1 write-only P27 Pull-Up Enable 27 1 write-only P28 Pull-Up Enable 28 1 write-only P29 Pull-Up Enable 29 1 write-only P3 Pull-Up Enable 3 1 write-only P30 Pull-Up Enable 30 1 write-only P31 Pull-Up Enable 31 1 write-only P4 Pull-Up Enable 4 1 write-only P5 Pull-Up Enable 5 1 write-only P6 Pull-Up Enable 6 1 write-only P7 Pull-Up Enable 7 1 write-only P8 Pull-Up Enable 8 1 write-only P9 Pull-Up Enable 9 1 write-only PUSR Pad Pull-Up Status Register 0x68 32 read-only n 0x0 0x0 P0 Pull-Up Status 0 1 read-only P1 Pull-Up Status 1 1 read-only P10 Pull-Up Status 10 1 read-only P11 Pull-Up Status 11 1 read-only P12 Pull-Up Status 12 1 read-only P13 Pull-Up Status 13 1 read-only P14 Pull-Up Status 14 1 read-only P15 Pull-Up Status 15 1 read-only P16 Pull-Up Status 16 1 read-only P17 Pull-Up Status 17 1 read-only P18 Pull-Up Status 18 1 read-only P19 Pull-Up Status 19 1 read-only P2 Pull-Up Status 2 1 read-only P20 Pull-Up Status 20 1 read-only P21 Pull-Up Status 21 1 read-only P22 Pull-Up Status 22 1 read-only P23 Pull-Up Status 23 1 read-only P24 Pull-Up Status 24 1 read-only P25 Pull-Up Status 25 1 read-only P26 Pull-Up Status 26 1 read-only P27 Pull-Up Status 27 1 read-only P28 Pull-Up Status 28 1 read-only P29 Pull-Up Status 29 1 read-only P3 Pull-Up Status 3 1 read-only P30 Pull-Up Status 30 1 read-only P31 Pull-Up Status 31 1 read-only P4 Pull-Up Status 4 1 read-only P5 Pull-Up Status 5 1 read-only P6 Pull-Up Status 6 1 read-only P7 Pull-Up Status 7 1 read-only P8 Pull-Up Status 8 1 read-only P9 Pull-Up Status 9 1 read-only REHLSR Rising Edge/High-Level Select Register 0xD4 32 write-only n 0x0 0x0 P0 Rising Edge/High-Level Interrupt Selection 0 1 write-only P1 Rising Edge/High-Level Interrupt Selection 1 1 write-only P10 Rising Edge/High-Level Interrupt Selection 10 1 write-only P11 Rising Edge/High-Level Interrupt Selection 11 1 write-only P12 Rising Edge/High-Level Interrupt Selection 12 1 write-only P13 Rising Edge/High-Level Interrupt Selection 13 1 write-only P14 Rising Edge/High-Level Interrupt Selection 14 1 write-only P15 Rising Edge/High-Level Interrupt Selection 15 1 write-only P16 Rising Edge/High-Level Interrupt Selection 16 1 write-only P17 Rising Edge/High-Level Interrupt Selection 17 1 write-only P18 Rising Edge/High-Level Interrupt Selection 18 1 write-only P19 Rising Edge/High-Level Interrupt Selection 19 1 write-only P2 Rising Edge/High-Level Interrupt Selection 2 1 write-only P20 Rising Edge/High-Level Interrupt Selection 20 1 write-only P21 Rising Edge/High-Level Interrupt Selection 21 1 write-only P22 Rising Edge/High-Level Interrupt Selection 22 1 write-only P23 Rising Edge/High-Level Interrupt Selection 23 1 write-only P24 Rising Edge/High-Level Interrupt Selection 24 1 write-only P25 Rising Edge/High-Level Interrupt Selection 25 1 write-only P26 Rising Edge/High-Level Interrupt Selection 26 1 write-only P27 Rising Edge/High-Level Interrupt Selection 27 1 write-only P28 Rising Edge/High-Level Interrupt Selection 28 1 write-only P29 Rising Edge/High-Level Interrupt Selection 29 1 write-only P3 Rising Edge/High-Level Interrupt Selection 3 1 write-only P30 Rising Edge/High-Level Interrupt Selection 30 1 write-only P31 Rising Edge/High-Level Interrupt Selection 31 1 write-only P4 Rising Edge/High-Level Interrupt Selection 4 1 write-only P5 Rising Edge/High-Level Interrupt Selection 5 1 write-only P6 Rising Edge/High-Level Interrupt Selection 6 1 write-only P7 Rising Edge/High-Level Interrupt Selection 7 1 write-only P8 Rising Edge/High-Level Interrupt Selection 8 1 write-only P9 Rising Edge/High-Level Interrupt Selection 9 1 write-only SCDR Slow Clock Divider Debouncing Register 0x8C 32 read-write n 0x0 0x0 DIV Slow Clock Divider Selection for Debouncing 0 14 read-write SCHMITT Schmitt Trigger Register 0x100 32 read-write n 0x0 0x0 SCHMITT0 Schmitt Trigger Control 0 1 read-write SCHMITT1 Schmitt Trigger Control 1 1 read-write SCHMITT10 Schmitt Trigger Control 10 1 read-write SCHMITT11 Schmitt Trigger Control 11 1 read-write SCHMITT12 Schmitt Trigger Control 12 1 read-write SCHMITT13 Schmitt Trigger Control 13 1 read-write SCHMITT14 Schmitt Trigger Control 14 1 read-write SCHMITT15 Schmitt Trigger Control 15 1 read-write SCHMITT16 Schmitt Trigger Control 16 1 read-write SCHMITT17 Schmitt Trigger Control 17 1 read-write SCHMITT18 Schmitt Trigger Control 18 1 read-write SCHMITT19 Schmitt Trigger Control 19 1 read-write SCHMITT2 Schmitt Trigger Control 2 1 read-write SCHMITT20 Schmitt Trigger Control 20 1 read-write SCHMITT21 Schmitt Trigger Control 21 1 read-write SCHMITT22 Schmitt Trigger Control 22 1 read-write SCHMITT23 Schmitt Trigger Control 23 1 read-write SCHMITT24 Schmitt Trigger Control 24 1 read-write SCHMITT25 Schmitt Trigger Control 25 1 read-write SCHMITT26 Schmitt Trigger Control 26 1 read-write SCHMITT27 Schmitt Trigger Control 27 1 read-write SCHMITT28 Schmitt Trigger Control 28 1 read-write SCHMITT29 Schmitt Trigger Control 29 1 read-write SCHMITT3 Schmitt Trigger Control 3 1 read-write SCHMITT30 Schmitt Trigger Control 30 1 read-write SCHMITT31 Schmitt Trigger Control 31 1 read-write SCHMITT4 Schmitt Trigger Control 4 1 read-write SCHMITT5 Schmitt Trigger Control 5 1 read-write SCHMITT6 Schmitt Trigger Control 6 1 read-write SCHMITT7 Schmitt Trigger Control 7 1 read-write SCHMITT8 Schmitt Trigger Control 8 1 read-write SCHMITT9 Schmitt Trigger Control 9 1 read-write SODR Set Output Data Register 0x30 32 write-only n 0x0 0x0 P0 Set Output Data 0 1 write-only P1 Set Output Data 1 1 write-only P10 Set Output Data 10 1 write-only P11 Set Output Data 11 1 write-only P12 Set Output Data 12 1 write-only P13 Set Output Data 13 1 write-only P14 Set Output Data 14 1 write-only P15 Set Output Data 15 1 write-only P16 Set Output Data 16 1 write-only P17 Set Output Data 17 1 write-only P18 Set Output Data 18 1 write-only P19 Set Output Data 19 1 write-only P2 Set Output Data 2 1 write-only P20 Set Output Data 20 1 write-only P21 Set Output Data 21 1 write-only P22 Set Output Data 22 1 write-only P23 Set Output Data 23 1 write-only P24 Set Output Data 24 1 write-only P25 Set Output Data 25 1 write-only P26 Set Output Data 26 1 write-only P27 Set Output Data 27 1 write-only P28 Set Output Data 28 1 write-only P29 Set Output Data 29 1 write-only P3 Set Output Data 3 1 write-only P30 Set Output Data 30 1 write-only P31 Set Output Data 31 1 write-only P4 Set Output Data 4 1 write-only P5 Set Output Data 5 1 write-only P6 Set Output Data 6 1 write-only P7 Set Output Data 7 1 write-only P8 Set Output Data 8 1 write-only P9 Set Output Data 9 1 write-only WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 read-write WPKEY Write Protection Key 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 0x50494F WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 read-only WPVSRC Write Protection Violation Source 8 16 read-only PIOC Parallel Input/Output Controller C PIO 0x0 0x0 0x1000 registers n PIOC 25 ABCDSR0 Peripheral ABCD Select Register 0x70 32 read-write n P0 Peripheral Select 0 1 read-write P1 Peripheral Select 1 1 read-write P10 Peripheral Select 10 1 read-write P11 Peripheral Select 11 1 read-write P12 Peripheral Select 12 1 read-write P13 Peripheral Select 13 1 read-write P14 Peripheral Select 14 1 read-write P15 Peripheral Select 15 1 read-write P16 Peripheral Select 16 1 read-write P17 Peripheral Select 17 1 read-write P18 Peripheral Select 18 1 read-write P19 Peripheral Select 19 1 read-write P2 Peripheral Select 2 1 read-write P20 Peripheral Select 20 1 read-write P21 Peripheral Select 21 1 read-write P22 Peripheral Select 22 1 read-write P23 Peripheral Select 23 1 read-write P24 Peripheral Select 24 1 read-write P25 Peripheral Select 25 1 read-write P26 Peripheral Select 26 1 read-write P27 Peripheral Select 27 1 read-write P28 Peripheral Select 28 1 read-write P29 Peripheral Select 29 1 read-write P3 Peripheral Select 3 1 read-write P30 Peripheral Select 30 1 read-write P31 Peripheral Select 31 1 read-write P4 Peripheral Select 4 1 read-write P5 Peripheral Select 5 1 read-write P6 Peripheral Select 6 1 read-write P7 Peripheral Select 7 1 read-write P8 Peripheral Select 8 1 read-write P9 Peripheral Select 9 1 read-write ABCDSR1 Peripheral ABCD Select Register 0x74 32 read-write n P0 Peripheral Select 0 1 read-write P1 Peripheral Select 1 1 read-write P10 Peripheral Select 10 1 read-write P11 Peripheral Select 11 1 read-write P12 Peripheral Select 12 1 read-write P13 Peripheral Select 13 1 read-write P14 Peripheral Select 14 1 read-write P15 Peripheral Select 15 1 read-write P16 Peripheral Select 16 1 read-write P17 Peripheral Select 17 1 read-write P18 Peripheral Select 18 1 read-write P19 Peripheral Select 19 1 read-write P2 Peripheral Select 2 1 read-write P20 Peripheral Select 20 1 read-write P21 Peripheral Select 21 1 read-write P22 Peripheral Select 22 1 read-write P23 Peripheral Select 23 1 read-write P24 Peripheral Select 24 1 read-write P25 Peripheral Select 25 1 read-write P26 Peripheral Select 26 1 read-write P27 Peripheral Select 27 1 read-write P28 Peripheral Select 28 1 read-write P29 Peripheral Select 29 1 read-write P3 Peripheral Select 3 1 read-write P30 Peripheral Select 30 1 read-write P31 Peripheral Select 31 1 read-write P4 Peripheral Select 4 1 read-write P5 Peripheral Select 5 1 read-write P6 Peripheral Select 6 1 read-write P7 Peripheral Select 7 1 read-write P8 Peripheral Select 8 1 read-write P9 Peripheral Select 9 1 read-write ABCDSR[0] Peripheral ABCD Select Register 0xE0 32 read-write n 0x0 0x0 P0 Peripheral Select 0 1 read-write P1 Peripheral Select 1 1 read-write P10 Peripheral Select 10 1 read-write P11 Peripheral Select 11 1 read-write P12 Peripheral Select 12 1 read-write P13 Peripheral Select 13 1 read-write P14 Peripheral Select 14 1 read-write P15 Peripheral Select 15 1 read-write P16 Peripheral Select 16 1 read-write P17 Peripheral Select 17 1 read-write P18 Peripheral Select 18 1 read-write P19 Peripheral Select 19 1 read-write P2 Peripheral Select 2 1 read-write P20 Peripheral Select 20 1 read-write P21 Peripheral Select 21 1 read-write P22 Peripheral Select 22 1 read-write P23 Peripheral Select 23 1 read-write P24 Peripheral Select 24 1 read-write P25 Peripheral Select 25 1 read-write P26 Peripheral Select 26 1 read-write P27 Peripheral Select 27 1 read-write P28 Peripheral Select 28 1 read-write P29 Peripheral Select 29 1 read-write P3 Peripheral Select 3 1 read-write P30 Peripheral Select 30 1 read-write P31 Peripheral Select 31 1 read-write P4 Peripheral Select 4 1 read-write P5 Peripheral Select 5 1 read-write P6 Peripheral Select 6 1 read-write P7 Peripheral Select 7 1 read-write P8 Peripheral Select 8 1 read-write P9 Peripheral Select 9 1 read-write ABCDSR[1] Peripheral ABCD Select Register 0x154 32 read-write n 0x0 0x0 P0 Peripheral Select 0 1 read-write P1 Peripheral Select 1 1 read-write P10 Peripheral Select 10 1 read-write P11 Peripheral Select 11 1 read-write P12 Peripheral Select 12 1 read-write P13 Peripheral Select 13 1 read-write P14 Peripheral Select 14 1 read-write P15 Peripheral Select 15 1 read-write P16 Peripheral Select 16 1 read-write P17 Peripheral Select 17 1 read-write P18 Peripheral Select 18 1 read-write P19 Peripheral Select 19 1 read-write P2 Peripheral Select 2 1 read-write P20 Peripheral Select 20 1 read-write P21 Peripheral Select 21 1 read-write P22 Peripheral Select 22 1 read-write P23 Peripheral Select 23 1 read-write P24 Peripheral Select 24 1 read-write P25 Peripheral Select 25 1 read-write P26 Peripheral Select 26 1 read-write P27 Peripheral Select 27 1 read-write P28 Peripheral Select 28 1 read-write P29 Peripheral Select 29 1 read-write P3 Peripheral Select 3 1 read-write P30 Peripheral Select 30 1 read-write P31 Peripheral Select 31 1 read-write P4 Peripheral Select 4 1 read-write P5 Peripheral Select 5 1 read-write P6 Peripheral Select 6 1 read-write P7 Peripheral Select 7 1 read-write P8 Peripheral Select 8 1 read-write P9 Peripheral Select 9 1 read-write AIMDR Additional Interrupt Modes Disable Register 0xB4 32 write-only n 0x0 0x0 P0 Additional Interrupt Modes Disable 0 1 write-only P1 Additional Interrupt Modes Disable 1 1 write-only P10 Additional Interrupt Modes Disable 10 1 write-only P11 Additional Interrupt Modes Disable 11 1 write-only P12 Additional Interrupt Modes Disable 12 1 write-only P13 Additional Interrupt Modes Disable 13 1 write-only P14 Additional Interrupt Modes Disable 14 1 write-only P15 Additional Interrupt Modes Disable 15 1 write-only P16 Additional Interrupt Modes Disable 16 1 write-only P17 Additional Interrupt Modes Disable 17 1 write-only P18 Additional Interrupt Modes Disable 18 1 write-only P19 Additional Interrupt Modes Disable 19 1 write-only P2 Additional Interrupt Modes Disable 2 1 write-only P20 Additional Interrupt Modes Disable 20 1 write-only P21 Additional Interrupt Modes Disable 21 1 write-only P22 Additional Interrupt Modes Disable 22 1 write-only P23 Additional Interrupt Modes Disable 23 1 write-only P24 Additional Interrupt Modes Disable 24 1 write-only P25 Additional Interrupt Modes Disable 25 1 write-only P26 Additional Interrupt Modes Disable 26 1 write-only P27 Additional Interrupt Modes Disable 27 1 write-only P28 Additional Interrupt Modes Disable 28 1 write-only P29 Additional Interrupt Modes Disable 29 1 write-only P3 Additional Interrupt Modes Disable 3 1 write-only P30 Additional Interrupt Modes Disable 30 1 write-only P31 Additional Interrupt Modes Disable 31 1 write-only P4 Additional Interrupt Modes Disable 4 1 write-only P5 Additional Interrupt Modes Disable 5 1 write-only P6 Additional Interrupt Modes Disable 6 1 write-only P7 Additional Interrupt Modes Disable 7 1 write-only P8 Additional Interrupt Modes Disable 8 1 write-only P9 Additional Interrupt Modes Disable 9 1 write-only AIMER Additional Interrupt Modes Enable Register 0xB0 32 write-only n 0x0 0x0 P0 Additional Interrupt Modes Enable 0 1 write-only P1 Additional Interrupt Modes Enable 1 1 write-only P10 Additional Interrupt Modes Enable 10 1 write-only P11 Additional Interrupt Modes Enable 11 1 write-only P12 Additional Interrupt Modes Enable 12 1 write-only P13 Additional Interrupt Modes Enable 13 1 write-only P14 Additional Interrupt Modes Enable 14 1 write-only P15 Additional Interrupt Modes Enable 15 1 write-only P16 Additional Interrupt Modes Enable 16 1 write-only P17 Additional Interrupt Modes Enable 17 1 write-only P18 Additional Interrupt Modes Enable 18 1 write-only P19 Additional Interrupt Modes Enable 19 1 write-only P2 Additional Interrupt Modes Enable 2 1 write-only P20 Additional Interrupt Modes Enable 20 1 write-only P21 Additional Interrupt Modes Enable 21 1 write-only P22 Additional Interrupt Modes Enable 22 1 write-only P23 Additional Interrupt Modes Enable 23 1 write-only P24 Additional Interrupt Modes Enable 24 1 write-only P25 Additional Interrupt Modes Enable 25 1 write-only P26 Additional Interrupt Modes Enable 26 1 write-only P27 Additional Interrupt Modes Enable 27 1 write-only P28 Additional Interrupt Modes Enable 28 1 write-only P29 Additional Interrupt Modes Enable 29 1 write-only P3 Additional Interrupt Modes Enable 3 1 write-only P30 Additional Interrupt Modes Enable 30 1 write-only P31 Additional Interrupt Modes Enable 31 1 write-only P4 Additional Interrupt Modes Enable 4 1 write-only P5 Additional Interrupt Modes Enable 5 1 write-only P6 Additional Interrupt Modes Enable 6 1 write-only P7 Additional Interrupt Modes Enable 7 1 write-only P8 Additional Interrupt Modes Enable 8 1 write-only P9 Additional Interrupt Modes Enable 9 1 write-only AIMMR Additional Interrupt Modes Mask Register 0xB8 32 read-only n 0x0 0x0 P0 IO Line Index 0 1 read-only P1 IO Line Index 1 1 read-only P10 IO Line Index 10 1 read-only P11 IO Line Index 11 1 read-only P12 IO Line Index 12 1 read-only P13 IO Line Index 13 1 read-only P14 IO Line Index 14 1 read-only P15 IO Line Index 15 1 read-only P16 IO Line Index 16 1 read-only P17 IO Line Index 17 1 read-only P18 IO Line Index 18 1 read-only P19 IO Line Index 19 1 read-only P2 IO Line Index 2 1 read-only P20 IO Line Index 20 1 read-only P21 IO Line Index 21 1 read-only P22 IO Line Index 22 1 read-only P23 IO Line Index 23 1 read-only P24 IO Line Index 24 1 read-only P25 IO Line Index 25 1 read-only P26 IO Line Index 26 1 read-only P27 IO Line Index 27 1 read-only P28 IO Line Index 28 1 read-only P29 IO Line Index 29 1 read-only P3 IO Line Index 3 1 read-only P30 IO Line Index 30 1 read-only P31 IO Line Index 31 1 read-only P4 IO Line Index 4 1 read-only P5 IO Line Index 5 1 read-only P6 IO Line Index 6 1 read-only P7 IO Line Index 7 1 read-only P8 IO Line Index 8 1 read-only P9 IO Line Index 9 1 read-only CODR Clear Output Data Register 0x34 32 write-only n 0x0 0x0 P0 Clear Output Data 0 1 write-only P1 Clear Output Data 1 1 write-only P10 Clear Output Data 10 1 write-only P11 Clear Output Data 11 1 write-only P12 Clear Output Data 12 1 write-only P13 Clear Output Data 13 1 write-only P14 Clear Output Data 14 1 write-only P15 Clear Output Data 15 1 write-only P16 Clear Output Data 16 1 write-only P17 Clear Output Data 17 1 write-only P18 Clear Output Data 18 1 write-only P19 Clear Output Data 19 1 write-only P2 Clear Output Data 2 1 write-only P20 Clear Output Data 20 1 write-only P21 Clear Output Data 21 1 write-only P22 Clear Output Data 22 1 write-only P23 Clear Output Data 23 1 write-only P24 Clear Output Data 24 1 write-only P25 Clear Output Data 25 1 write-only P26 Clear Output Data 26 1 write-only P27 Clear Output Data 27 1 write-only P28 Clear Output Data 28 1 write-only P29 Clear Output Data 29 1 write-only P3 Clear Output Data 3 1 write-only P30 Clear Output Data 30 1 write-only P31 Clear Output Data 31 1 write-only P4 Clear Output Data 4 1 write-only P5 Clear Output Data 5 1 write-only P6 Clear Output Data 6 1 write-only P7 Clear Output Data 7 1 write-only P8 Clear Output Data 8 1 write-only P9 Clear Output Data 9 1 write-only DRIVER1 I/O Drive Register 1 0x118 32 read-write n 0x0 0x0 LINE0 Drive of PIO Line 0 0 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE1 Drive of PIO Line 1 2 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE10 Drive of PIO Line 10 20 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE11 Drive of PIO Line 11 22 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE12 Drive of PIO Line 12 24 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE13 Drive of PIO Line 13 26 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE14 Drive of PIO Line 14 28 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE15 Drive of PIO Line 15 30 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE2 Drive of PIO Line 2 4 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE3 Drive of PIO Line 3 6 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE4 Drive of PIO Line 4 8 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE5 Drive of PIO Line 5 10 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE6 Drive of PIO Line 6 12 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE7 Drive of PIO Line 7 14 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE8 Drive of PIO Line 8 16 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE9 Drive of PIO Line 9 18 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 DRIVER2 I/O Drive Register 2 0x11C 32 read-write n 0x0 0x0 LINE16 Drive of PIO line 16 0 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE17 Drive of PIO line 17 2 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE18 Drive of PIO line 18 4 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE19 Drive of PIO line 19 6 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE20 Drive of PIO line 20 8 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE21 Drive of PIO line 21 10 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE22 Drive of PIO line 22 12 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE23 Drive of PIO line 23 14 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE24 Drive of PIO line 24 16 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE25 Drive of PIO line 25 18 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE26 Drive of PIO line 26 20 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE27 Drive of PIO line 27 22 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE28 Drive of PIO line 28 24 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE29 Drive of PIO line 29 26 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE30 Drive of PIO line 30 28 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE31 Drive of PIO line 31 30 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 ELSR Edge/Level Status Register 0xC8 32 read-only n 0x0 0x0 P0 Edge/Level Interrupt Source Selection 0 1 read-only P1 Edge/Level Interrupt Source Selection 1 1 read-only P10 Edge/Level Interrupt Source Selection 10 1 read-only P11 Edge/Level Interrupt Source Selection 11 1 read-only P12 Edge/Level Interrupt Source Selection 12 1 read-only P13 Edge/Level Interrupt Source Selection 13 1 read-only P14 Edge/Level Interrupt Source Selection 14 1 read-only P15 Edge/Level Interrupt Source Selection 15 1 read-only P16 Edge/Level Interrupt Source Selection 16 1 read-only P17 Edge/Level Interrupt Source Selection 17 1 read-only P18 Edge/Level Interrupt Source Selection 18 1 read-only P19 Edge/Level Interrupt Source Selection 19 1 read-only P2 Edge/Level Interrupt Source Selection 2 1 read-only P20 Edge/Level Interrupt Source Selection 20 1 read-only P21 Edge/Level Interrupt Source Selection 21 1 read-only P22 Edge/Level Interrupt Source Selection 22 1 read-only P23 Edge/Level Interrupt Source Selection 23 1 read-only P24 Edge/Level Interrupt Source Selection 24 1 read-only P25 Edge/Level Interrupt Source Selection 25 1 read-only P26 Edge/Level Interrupt Source Selection 26 1 read-only P27 Edge/Level Interrupt Source Selection 27 1 read-only P28 Edge/Level Interrupt Source Selection 28 1 read-only P29 Edge/Level Interrupt Source Selection 29 1 read-only P3 Edge/Level Interrupt Source Selection 3 1 read-only P30 Edge/Level Interrupt Source Selection 30 1 read-only P31 Edge/Level Interrupt Source Selection 31 1 read-only P4 Edge/Level Interrupt Source Selection 4 1 read-only P5 Edge/Level Interrupt Source Selection 5 1 read-only P6 Edge/Level Interrupt Source Selection 6 1 read-only P7 Edge/Level Interrupt Source Selection 7 1 read-only P8 Edge/Level Interrupt Source Selection 8 1 read-only P9 Edge/Level Interrupt Source Selection 9 1 read-only ESR Edge Select Register 0xC0 32 write-only n 0x0 0x0 P0 Edge Interrupt Selection 0 1 write-only P1 Edge Interrupt Selection 1 1 write-only P10 Edge Interrupt Selection 10 1 write-only P11 Edge Interrupt Selection 11 1 write-only P12 Edge Interrupt Selection 12 1 write-only P13 Edge Interrupt Selection 13 1 write-only P14 Edge Interrupt Selection 14 1 write-only P15 Edge Interrupt Selection 15 1 write-only P16 Edge Interrupt Selection 16 1 write-only P17 Edge Interrupt Selection 17 1 write-only P18 Edge Interrupt Selection 18 1 write-only P19 Edge Interrupt Selection 19 1 write-only P2 Edge Interrupt Selection 2 1 write-only P20 Edge Interrupt Selection 20 1 write-only P21 Edge Interrupt Selection 21 1 write-only P22 Edge Interrupt Selection 22 1 write-only P23 Edge Interrupt Selection 23 1 write-only P24 Edge Interrupt Selection 24 1 write-only P25 Edge Interrupt Selection 25 1 write-only P26 Edge Interrupt Selection 26 1 write-only P27 Edge Interrupt Selection 27 1 write-only P28 Edge Interrupt Selection 28 1 write-only P29 Edge Interrupt Selection 29 1 write-only P3 Edge Interrupt Selection 3 1 write-only P30 Edge Interrupt Selection 30 1 write-only P31 Edge Interrupt Selection 31 1 write-only P4 Edge Interrupt Selection 4 1 write-only P5 Edge Interrupt Selection 5 1 write-only P6 Edge Interrupt Selection 6 1 write-only P7 Edge Interrupt Selection 7 1 write-only P8 Edge Interrupt Selection 8 1 write-only P9 Edge Interrupt Selection 9 1 write-only FELLSR Falling Edge/Low-Level Select Register 0xD0 32 write-only n 0x0 0x0 P0 Falling Edge/Low-Level Interrupt Selection 0 1 write-only P1 Falling Edge/Low-Level Interrupt Selection 1 1 write-only P10 Falling Edge/Low-Level Interrupt Selection 10 1 write-only P11 Falling Edge/Low-Level Interrupt Selection 11 1 write-only P12 Falling Edge/Low-Level Interrupt Selection 12 1 write-only P13 Falling Edge/Low-Level Interrupt Selection 13 1 write-only P14 Falling Edge/Low-Level Interrupt Selection 14 1 write-only P15 Falling Edge/Low-Level Interrupt Selection 15 1 write-only P16 Falling Edge/Low-Level Interrupt Selection 16 1 write-only P17 Falling Edge/Low-Level Interrupt Selection 17 1 write-only P18 Falling Edge/Low-Level Interrupt Selection 18 1 write-only P19 Falling Edge/Low-Level Interrupt Selection 19 1 write-only P2 Falling Edge/Low-Level Interrupt Selection 2 1 write-only P20 Falling Edge/Low-Level Interrupt Selection 20 1 write-only P21 Falling Edge/Low-Level Interrupt Selection 21 1 write-only P22 Falling Edge/Low-Level Interrupt Selection 22 1 write-only P23 Falling Edge/Low-Level Interrupt Selection 23 1 write-only P24 Falling Edge/Low-Level Interrupt Selection 24 1 write-only P25 Falling Edge/Low-Level Interrupt Selection 25 1 write-only P26 Falling Edge/Low-Level Interrupt Selection 26 1 write-only P27 Falling Edge/Low-Level Interrupt Selection 27 1 write-only P28 Falling Edge/Low-Level Interrupt Selection 28 1 write-only P29 Falling Edge/Low-Level Interrupt Selection 29 1 write-only P3 Falling Edge/Low-Level Interrupt Selection 3 1 write-only P30 Falling Edge/Low-Level Interrupt Selection 30 1 write-only P31 Falling Edge/Low-Level Interrupt Selection 31 1 write-only P4 Falling Edge/Low-Level Interrupt Selection 4 1 write-only P5 Falling Edge/Low-Level Interrupt Selection 5 1 write-only P6 Falling Edge/Low-Level Interrupt Selection 6 1 write-only P7 Falling Edge/Low-Level Interrupt Selection 7 1 write-only P8 Falling Edge/Low-Level Interrupt Selection 8 1 write-only P9 Falling Edge/Low-Level Interrupt Selection 9 1 write-only FRLHSR Fall/Rise - Low/High Status Register 0xD8 32 read-only n 0x0 0x0 P0 Edge/Level Interrupt Source Selection 0 1 read-only P1 Edge/Level Interrupt Source Selection 1 1 read-only P10 Edge/Level Interrupt Source Selection 10 1 read-only P11 Edge/Level Interrupt Source Selection 11 1 read-only P12 Edge/Level Interrupt Source Selection 12 1 read-only P13 Edge/Level Interrupt Source Selection 13 1 read-only P14 Edge/Level Interrupt Source Selection 14 1 read-only P15 Edge/Level Interrupt Source Selection 15 1 read-only P16 Edge/Level Interrupt Source Selection 16 1 read-only P17 Edge/Level Interrupt Source Selection 17 1 read-only P18 Edge/Level Interrupt Source Selection 18 1 read-only P19 Edge/Level Interrupt Source Selection 19 1 read-only P2 Edge/Level Interrupt Source Selection 2 1 read-only P20 Edge/Level Interrupt Source Selection 20 1 read-only P21 Edge/Level Interrupt Source Selection 21 1 read-only P22 Edge/Level Interrupt Source Selection 22 1 read-only P23 Edge/Level Interrupt Source Selection 23 1 read-only P24 Edge/Level Interrupt Source Selection 24 1 read-only P25 Edge/Level Interrupt Source Selection 25 1 read-only P26 Edge/Level Interrupt Source Selection 26 1 read-only P27 Edge/Level Interrupt Source Selection 27 1 read-only P28 Edge/Level Interrupt Source Selection 28 1 read-only P29 Edge/Level Interrupt Source Selection 29 1 read-only P3 Edge/Level Interrupt Source Selection 3 1 read-only P30 Edge/Level Interrupt Source Selection 30 1 read-only P31 Edge/Level Interrupt Source Selection 31 1 read-only P4 Edge/Level Interrupt Source Selection 4 1 read-only P5 Edge/Level Interrupt Source Selection 5 1 read-only P6 Edge/Level Interrupt Source Selection 6 1 read-only P7 Edge/Level Interrupt Source Selection 7 1 read-only P8 Edge/Level Interrupt Source Selection 8 1 read-only P9 Edge/Level Interrupt Source Selection 9 1 read-only IDR Interrupt Disable Register 0x44 32 write-only n 0x0 0x0 P0 Input Change Interrupt Disable 0 1 write-only P1 Input Change Interrupt Disable 1 1 write-only P10 Input Change Interrupt Disable 10 1 write-only P11 Input Change Interrupt Disable 11 1 write-only P12 Input Change Interrupt Disable 12 1 write-only P13 Input Change Interrupt Disable 13 1 write-only P14 Input Change Interrupt Disable 14 1 write-only P15 Input Change Interrupt Disable 15 1 write-only P16 Input Change Interrupt Disable 16 1 write-only P17 Input Change Interrupt Disable 17 1 write-only P18 Input Change Interrupt Disable 18 1 write-only P19 Input Change Interrupt Disable 19 1 write-only P2 Input Change Interrupt Disable 2 1 write-only P20 Input Change Interrupt Disable 20 1 write-only P21 Input Change Interrupt Disable 21 1 write-only P22 Input Change Interrupt Disable 22 1 write-only P23 Input Change Interrupt Disable 23 1 write-only P24 Input Change Interrupt Disable 24 1 write-only P25 Input Change Interrupt Disable 25 1 write-only P26 Input Change Interrupt Disable 26 1 write-only P27 Input Change Interrupt Disable 27 1 write-only P28 Input Change Interrupt Disable 28 1 write-only P29 Input Change Interrupt Disable 29 1 write-only P3 Input Change Interrupt Disable 3 1 write-only P30 Input Change Interrupt Disable 30 1 write-only P31 Input Change Interrupt Disable 31 1 write-only P4 Input Change Interrupt Disable 4 1 write-only P5 Input Change Interrupt Disable 5 1 write-only P6 Input Change Interrupt Disable 6 1 write-only P7 Input Change Interrupt Disable 7 1 write-only P8 Input Change Interrupt Disable 8 1 write-only P9 Input Change Interrupt Disable 9 1 write-only IER Interrupt Enable Register 0x40 32 write-only n 0x0 0x0 P0 Input Change Interrupt Enable 0 1 write-only P1 Input Change Interrupt Enable 1 1 write-only P10 Input Change Interrupt Enable 10 1 write-only P11 Input Change Interrupt Enable 11 1 write-only P12 Input Change Interrupt Enable 12 1 write-only P13 Input Change Interrupt Enable 13 1 write-only P14 Input Change Interrupt Enable 14 1 write-only P15 Input Change Interrupt Enable 15 1 write-only P16 Input Change Interrupt Enable 16 1 write-only P17 Input Change Interrupt Enable 17 1 write-only P18 Input Change Interrupt Enable 18 1 write-only P19 Input Change Interrupt Enable 19 1 write-only P2 Input Change Interrupt Enable 2 1 write-only P20 Input Change Interrupt Enable 20 1 write-only P21 Input Change Interrupt Enable 21 1 write-only P22 Input Change Interrupt Enable 22 1 write-only P23 Input Change Interrupt Enable 23 1 write-only P24 Input Change Interrupt Enable 24 1 write-only P25 Input Change Interrupt Enable 25 1 write-only P26 Input Change Interrupt Enable 26 1 write-only P27 Input Change Interrupt Enable 27 1 write-only P28 Input Change Interrupt Enable 28 1 write-only P29 Input Change Interrupt Enable 29 1 write-only P3 Input Change Interrupt Enable 3 1 write-only P30 Input Change Interrupt Enable 30 1 write-only P31 Input Change Interrupt Enable 31 1 write-only P4 Input Change Interrupt Enable 4 1 write-only P5 Input Change Interrupt Enable 5 1 write-only P6 Input Change Interrupt Enable 6 1 write-only P7 Input Change Interrupt Enable 7 1 write-only P8 Input Change Interrupt Enable 8 1 write-only P9 Input Change Interrupt Enable 9 1 write-only IFDR Glitch Input Filter Disable Register 0x24 32 write-only n 0x0 0x0 P0 Input Filter Disable 0 1 write-only P1 Input Filter Disable 1 1 write-only P10 Input Filter Disable 10 1 write-only P11 Input Filter Disable 11 1 write-only P12 Input Filter Disable 12 1 write-only P13 Input Filter Disable 13 1 write-only P14 Input Filter Disable 14 1 write-only P15 Input Filter Disable 15 1 write-only P16 Input Filter Disable 16 1 write-only P17 Input Filter Disable 17 1 write-only P18 Input Filter Disable 18 1 write-only P19 Input Filter Disable 19 1 write-only P2 Input Filter Disable 2 1 write-only P20 Input Filter Disable 20 1 write-only P21 Input Filter Disable 21 1 write-only P22 Input Filter Disable 22 1 write-only P23 Input Filter Disable 23 1 write-only P24 Input Filter Disable 24 1 write-only P25 Input Filter Disable 25 1 write-only P26 Input Filter Disable 26 1 write-only P27 Input Filter Disable 27 1 write-only P28 Input Filter Disable 28 1 write-only P29 Input Filter Disable 29 1 write-only P3 Input Filter Disable 3 1 write-only P30 Input Filter Disable 30 1 write-only P31 Input Filter Disable 31 1 write-only P4 Input Filter Disable 4 1 write-only P5 Input Filter Disable 5 1 write-only P6 Input Filter Disable 6 1 write-only P7 Input Filter Disable 7 1 write-only P8 Input Filter Disable 8 1 write-only P9 Input Filter Disable 9 1 write-only IFER Glitch Input Filter Enable Register 0x20 32 write-only n 0x0 0x0 P0 Input Filter Enable 0 1 write-only P1 Input Filter Enable 1 1 write-only P10 Input Filter Enable 10 1 write-only P11 Input Filter Enable 11 1 write-only P12 Input Filter Enable 12 1 write-only P13 Input Filter Enable 13 1 write-only P14 Input Filter Enable 14 1 write-only P15 Input Filter Enable 15 1 write-only P16 Input Filter Enable 16 1 write-only P17 Input Filter Enable 17 1 write-only P18 Input Filter Enable 18 1 write-only P19 Input Filter Enable 19 1 write-only P2 Input Filter Enable 2 1 write-only P20 Input Filter Enable 20 1 write-only P21 Input Filter Enable 21 1 write-only P22 Input Filter Enable 22 1 write-only P23 Input Filter Enable 23 1 write-only P24 Input Filter Enable 24 1 write-only P25 Input Filter Enable 25 1 write-only P26 Input Filter Enable 26 1 write-only P27 Input Filter Enable 27 1 write-only P28 Input Filter Enable 28 1 write-only P29 Input Filter Enable 29 1 write-only P3 Input Filter Enable 3 1 write-only P30 Input Filter Enable 30 1 write-only P31 Input Filter Enable 31 1 write-only P4 Input Filter Enable 4 1 write-only P5 Input Filter Enable 5 1 write-only P6 Input Filter Enable 6 1 write-only P7 Input Filter Enable 7 1 write-only P8 Input Filter Enable 8 1 write-only P9 Input Filter Enable 9 1 write-only IFSCDR Input Filter Slow Clock Disable Register 0x80 32 write-only n 0x0 0x0 P0 Peripheral Clock Glitch Filtering Select 0 1 write-only P1 Peripheral Clock Glitch Filtering Select 1 1 write-only P10 Peripheral Clock Glitch Filtering Select 10 1 write-only P11 Peripheral Clock Glitch Filtering Select 11 1 write-only P12 Peripheral Clock Glitch Filtering Select 12 1 write-only P13 Peripheral Clock Glitch Filtering Select 13 1 write-only P14 Peripheral Clock Glitch Filtering Select 14 1 write-only P15 Peripheral Clock Glitch Filtering Select 15 1 write-only P16 Peripheral Clock Glitch Filtering Select 16 1 write-only P17 Peripheral Clock Glitch Filtering Select 17 1 write-only P18 Peripheral Clock Glitch Filtering Select 18 1 write-only P19 Peripheral Clock Glitch Filtering Select 19 1 write-only P2 Peripheral Clock Glitch Filtering Select 2 1 write-only P20 Peripheral Clock Glitch Filtering Select 20 1 write-only P21 Peripheral Clock Glitch Filtering Select 21 1 write-only P22 Peripheral Clock Glitch Filtering Select 22 1 write-only P23 Peripheral Clock Glitch Filtering Select 23 1 write-only P24 Peripheral Clock Glitch Filtering Select 24 1 write-only P25 Peripheral Clock Glitch Filtering Select 25 1 write-only P26 Peripheral Clock Glitch Filtering Select 26 1 write-only P27 Peripheral Clock Glitch Filtering Select 27 1 write-only P28 Peripheral Clock Glitch Filtering Select 28 1 write-only P29 Peripheral Clock Glitch Filtering Select 29 1 write-only P3 Peripheral Clock Glitch Filtering Select 3 1 write-only P30 Peripheral Clock Glitch Filtering Select 30 1 write-only P31 Peripheral Clock Glitch Filtering Select 31 1 write-only P4 Peripheral Clock Glitch Filtering Select 4 1 write-only P5 Peripheral Clock Glitch Filtering Select 5 1 write-only P6 Peripheral Clock Glitch Filtering Select 6 1 write-only P7 Peripheral Clock Glitch Filtering Select 7 1 write-only P8 Peripheral Clock Glitch Filtering Select 8 1 write-only P9 Peripheral Clock Glitch Filtering Select 9 1 write-only IFSCER Input Filter Slow Clock Enable Register 0x84 32 write-only n 0x0 0x0 P0 Slow Clock Debouncing Filtering Select 0 1 write-only P1 Slow Clock Debouncing Filtering Select 1 1 write-only P10 Slow Clock Debouncing Filtering Select 10 1 write-only P11 Slow Clock Debouncing Filtering Select 11 1 write-only P12 Slow Clock Debouncing Filtering Select 12 1 write-only P13 Slow Clock Debouncing Filtering Select 13 1 write-only P14 Slow Clock Debouncing Filtering Select 14 1 write-only P15 Slow Clock Debouncing Filtering Select 15 1 write-only P16 Slow Clock Debouncing Filtering Select 16 1 write-only P17 Slow Clock Debouncing Filtering Select 17 1 write-only P18 Slow Clock Debouncing Filtering Select 18 1 write-only P19 Slow Clock Debouncing Filtering Select 19 1 write-only P2 Slow Clock Debouncing Filtering Select 2 1 write-only P20 Slow Clock Debouncing Filtering Select 20 1 write-only P21 Slow Clock Debouncing Filtering Select 21 1 write-only P22 Slow Clock Debouncing Filtering Select 22 1 write-only P23 Slow Clock Debouncing Filtering Select 23 1 write-only P24 Slow Clock Debouncing Filtering Select 24 1 write-only P25 Slow Clock Debouncing Filtering Select 25 1 write-only P26 Slow Clock Debouncing Filtering Select 26 1 write-only P27 Slow Clock Debouncing Filtering Select 27 1 write-only P28 Slow Clock Debouncing Filtering Select 28 1 write-only P29 Slow Clock Debouncing Filtering Select 29 1 write-only P3 Slow Clock Debouncing Filtering Select 3 1 write-only P30 Slow Clock Debouncing Filtering Select 30 1 write-only P31 Slow Clock Debouncing Filtering Select 31 1 write-only P4 Slow Clock Debouncing Filtering Select 4 1 write-only P5 Slow Clock Debouncing Filtering Select 5 1 write-only P6 Slow Clock Debouncing Filtering Select 6 1 write-only P7 Slow Clock Debouncing Filtering Select 7 1 write-only P8 Slow Clock Debouncing Filtering Select 8 1 write-only P9 Slow Clock Debouncing Filtering Select 9 1 write-only IFSCSR Input Filter Slow Clock Status Register 0x88 32 read-only n 0x0 0x0 P0 Glitch or Debouncing Filter Selection Status 0 1 read-only P1 Glitch or Debouncing Filter Selection Status 1 1 read-only P10 Glitch or Debouncing Filter Selection Status 10 1 read-only P11 Glitch or Debouncing Filter Selection Status 11 1 read-only P12 Glitch or Debouncing Filter Selection Status 12 1 read-only P13 Glitch or Debouncing Filter Selection Status 13 1 read-only P14 Glitch or Debouncing Filter Selection Status 14 1 read-only P15 Glitch or Debouncing Filter Selection Status 15 1 read-only P16 Glitch or Debouncing Filter Selection Status 16 1 read-only P17 Glitch or Debouncing Filter Selection Status 17 1 read-only P18 Glitch or Debouncing Filter Selection Status 18 1 read-only P19 Glitch or Debouncing Filter Selection Status 19 1 read-only P2 Glitch or Debouncing Filter Selection Status 2 1 read-only P20 Glitch or Debouncing Filter Selection Status 20 1 read-only P21 Glitch or Debouncing Filter Selection Status 21 1 read-only P22 Glitch or Debouncing Filter Selection Status 22 1 read-only P23 Glitch or Debouncing Filter Selection Status 23 1 read-only P24 Glitch or Debouncing Filter Selection Status 24 1 read-only P25 Glitch or Debouncing Filter Selection Status 25 1 read-only P26 Glitch or Debouncing Filter Selection Status 26 1 read-only P27 Glitch or Debouncing Filter Selection Status 27 1 read-only P28 Glitch or Debouncing Filter Selection Status 28 1 read-only P29 Glitch or Debouncing Filter Selection Status 29 1 read-only P3 Glitch or Debouncing Filter Selection Status 3 1 read-only P30 Glitch or Debouncing Filter Selection Status 30 1 read-only P31 Glitch or Debouncing Filter Selection Status 31 1 read-only P4 Glitch or Debouncing Filter Selection Status 4 1 read-only P5 Glitch or Debouncing Filter Selection Status 5 1 read-only P6 Glitch or Debouncing Filter Selection Status 6 1 read-only P7 Glitch or Debouncing Filter Selection Status 7 1 read-only P8 Glitch or Debouncing Filter Selection Status 8 1 read-only P9 Glitch or Debouncing Filter Selection Status 9 1 read-only IFSR Glitch Input Filter Status Register 0x28 32 read-only n 0x0 0x0 P0 Input Filter Status 0 1 read-only P1 Input Filter Status 1 1 read-only P10 Input Filter Status 10 1 read-only P11 Input Filter Status 11 1 read-only P12 Input Filter Status 12 1 read-only P13 Input Filter Status 13 1 read-only P14 Input Filter Status 14 1 read-only P15 Input Filter Status 15 1 read-only P16 Input Filter Status 16 1 read-only P17 Input Filter Status 17 1 read-only P18 Input Filter Status 18 1 read-only P19 Input Filter Status 19 1 read-only P2 Input Filter Status 2 1 read-only P20 Input Filter Status 20 1 read-only P21 Input Filter Status 21 1 read-only P22 Input Filter Status 22 1 read-only P23 Input Filter Status 23 1 read-only P24 Input Filter Status 24 1 read-only P25 Input Filter Status 25 1 read-only P26 Input Filter Status 26 1 read-only P27 Input Filter Status 27 1 read-only P28 Input Filter Status 28 1 read-only P29 Input Filter Status 29 1 read-only P3 Input Filter Status 3 1 read-only P30 Input Filter Status 30 1 read-only P31 Input Filter Status 31 1 read-only P4 Input Filter Status 4 1 read-only P5 Input Filter Status 5 1 read-only P6 Input Filter Status 6 1 read-only P7 Input Filter Status 7 1 read-only P8 Input Filter Status 8 1 read-only P9 Input Filter Status 9 1 read-only IMR Interrupt Mask Register 0x48 32 read-only n 0x0 0x0 P0 Input Change Interrupt Mask 0 1 read-only P1 Input Change Interrupt Mask 1 1 read-only P10 Input Change Interrupt Mask 10 1 read-only P11 Input Change Interrupt Mask 11 1 read-only P12 Input Change Interrupt Mask 12 1 read-only P13 Input Change Interrupt Mask 13 1 read-only P14 Input Change Interrupt Mask 14 1 read-only P15 Input Change Interrupt Mask 15 1 read-only P16 Input Change Interrupt Mask 16 1 read-only P17 Input Change Interrupt Mask 17 1 read-only P18 Input Change Interrupt Mask 18 1 read-only P19 Input Change Interrupt Mask 19 1 read-only P2 Input Change Interrupt Mask 2 1 read-only P20 Input Change Interrupt Mask 20 1 read-only P21 Input Change Interrupt Mask 21 1 read-only P22 Input Change Interrupt Mask 22 1 read-only P23 Input Change Interrupt Mask 23 1 read-only P24 Input Change Interrupt Mask 24 1 read-only P25 Input Change Interrupt Mask 25 1 read-only P26 Input Change Interrupt Mask 26 1 read-only P27 Input Change Interrupt Mask 27 1 read-only P28 Input Change Interrupt Mask 28 1 read-only P29 Input Change Interrupt Mask 29 1 read-only P3 Input Change Interrupt Mask 3 1 read-only P30 Input Change Interrupt Mask 30 1 read-only P31 Input Change Interrupt Mask 31 1 read-only P4 Input Change Interrupt Mask 4 1 read-only P5 Input Change Interrupt Mask 5 1 read-only P6 Input Change Interrupt Mask 6 1 read-only P7 Input Change Interrupt Mask 7 1 read-only P8 Input Change Interrupt Mask 8 1 read-only P9 Input Change Interrupt Mask 9 1 read-only ISLR PIO Interrupt Security Level Register 0xC 32 read-write n 0x0 0x0 P0 PIO Interrupt Security Level 0 1 read-write P1 PIO Interrupt Security Level 1 1 read-write P10 PIO Interrupt Security Level 10 1 read-write P11 PIO Interrupt Security Level 11 1 read-write P12 PIO Interrupt Security Level 12 1 read-write P13 PIO Interrupt Security Level 13 1 read-write P14 PIO Interrupt Security Level 14 1 read-write P15 PIO Interrupt Security Level 15 1 read-write P16 PIO Interrupt Security Level 16 1 read-write P17 PIO Interrupt Security Level 17 1 read-write P18 PIO Interrupt Security Level 18 1 read-write P19 PIO Interrupt Security Level 19 1 read-write P2 PIO Interrupt Security Level 2 1 read-write P20 PIO Interrupt Security Level 20 1 read-write P21 PIO Interrupt Security Level 21 1 read-write P22 PIO Interrupt Security Level 22 1 read-write P23 PIO Interrupt Security Level 23 1 read-write P24 PIO Interrupt Security Level 24 1 read-write P25 PIO Interrupt Security Level 25 1 read-write P26 PIO Interrupt Security Level 26 1 read-write P27 PIO Interrupt Security Level 27 1 read-write P28 PIO Interrupt Security Level 28 1 read-write P29 PIO Interrupt Security Level 29 1 read-write P3 PIO Interrupt Security Level 3 1 read-write P30 PIO Interrupt Security Level 30 1 read-write P31 PIO Interrupt Security Level 31 1 read-write P4 PIO Interrupt Security Level 4 1 read-write P5 PIO Interrupt Security Level 5 1 read-write P6 PIO Interrupt Security Level 6 1 read-write P7 PIO Interrupt Security Level 7 1 read-write P8 PIO Interrupt Security Level 8 1 read-write P9 PIO Interrupt Security Level 9 1 read-write ISR Interrupt Status Register 0x4C 32 read-only n 0x0 0x0 P0 Input Change Interrupt Status 0 1 read-only P1 Input Change Interrupt Status 1 1 read-only P10 Input Change Interrupt Status 10 1 read-only P11 Input Change Interrupt Status 11 1 read-only P12 Input Change Interrupt Status 12 1 read-only P13 Input Change Interrupt Status 13 1 read-only P14 Input Change Interrupt Status 14 1 read-only P15 Input Change Interrupt Status 15 1 read-only P16 Input Change Interrupt Status 16 1 read-only P17 Input Change Interrupt Status 17 1 read-only P18 Input Change Interrupt Status 18 1 read-only P19 Input Change Interrupt Status 19 1 read-only P2 Input Change Interrupt Status 2 1 read-only P20 Input Change Interrupt Status 20 1 read-only P21 Input Change Interrupt Status 21 1 read-only P22 Input Change Interrupt Status 22 1 read-only P23 Input Change Interrupt Status 23 1 read-only P24 Input Change Interrupt Status 24 1 read-only P25 Input Change Interrupt Status 25 1 read-only P26 Input Change Interrupt Status 26 1 read-only P27 Input Change Interrupt Status 27 1 read-only P28 Input Change Interrupt Status 28 1 read-only P29 Input Change Interrupt Status 29 1 read-only P3 Input Change Interrupt Status 3 1 read-only P30 Input Change Interrupt Status 30 1 read-only P31 Input Change Interrupt Status 31 1 read-only P4 Input Change Interrupt Status 4 1 read-only P5 Input Change Interrupt Status 5 1 read-only P6 Input Change Interrupt Status 6 1 read-only P7 Input Change Interrupt Status 7 1 read-only P8 Input Change Interrupt Status 8 1 read-only P9 Input Change Interrupt Status 9 1 read-only LSR Level Select Register 0xC4 32 write-only n 0x0 0x0 P0 Level Interrupt Selection 0 1 write-only P1 Level Interrupt Selection 1 1 write-only P10 Level Interrupt Selection 10 1 write-only P11 Level Interrupt Selection 11 1 write-only P12 Level Interrupt Selection 12 1 write-only P13 Level Interrupt Selection 13 1 write-only P14 Level Interrupt Selection 14 1 write-only P15 Level Interrupt Selection 15 1 write-only P16 Level Interrupt Selection 16 1 write-only P17 Level Interrupt Selection 17 1 write-only P18 Level Interrupt Selection 18 1 write-only P19 Level Interrupt Selection 19 1 write-only P2 Level Interrupt Selection 2 1 write-only P20 Level Interrupt Selection 20 1 write-only P21 Level Interrupt Selection 21 1 write-only P22 Level Interrupt Selection 22 1 write-only P23 Level Interrupt Selection 23 1 write-only P24 Level Interrupt Selection 24 1 write-only P25 Level Interrupt Selection 25 1 write-only P26 Level Interrupt Selection 26 1 write-only P27 Level Interrupt Selection 27 1 write-only P28 Level Interrupt Selection 28 1 write-only P29 Level Interrupt Selection 29 1 write-only P3 Level Interrupt Selection 3 1 write-only P30 Level Interrupt Selection 30 1 write-only P31 Level Interrupt Selection 31 1 write-only P4 Level Interrupt Selection 4 1 write-only P5 Level Interrupt Selection 5 1 write-only P6 Level Interrupt Selection 6 1 write-only P7 Level Interrupt Selection 7 1 write-only P8 Level Interrupt Selection 8 1 write-only P9 Level Interrupt Selection 9 1 write-only MDDR Multi-driver Disable Register 0x54 32 write-only n 0x0 0x0 P0 Multi-drive Disable 0 1 write-only P1 Multi-drive Disable 1 1 write-only P10 Multi-drive Disable 10 1 write-only P11 Multi-drive Disable 11 1 write-only P12 Multi-drive Disable 12 1 write-only P13 Multi-drive Disable 13 1 write-only P14 Multi-drive Disable 14 1 write-only P15 Multi-drive Disable 15 1 write-only P16 Multi-drive Disable 16 1 write-only P17 Multi-drive Disable 17 1 write-only P18 Multi-drive Disable 18 1 write-only P19 Multi-drive Disable 19 1 write-only P2 Multi-drive Disable 2 1 write-only P20 Multi-drive Disable 20 1 write-only P21 Multi-drive Disable 21 1 write-only P22 Multi-drive Disable 22 1 write-only P23 Multi-drive Disable 23 1 write-only P24 Multi-drive Disable 24 1 write-only P25 Multi-drive Disable 25 1 write-only P26 Multi-drive Disable 26 1 write-only P27 Multi-drive Disable 27 1 write-only P28 Multi-drive Disable 28 1 write-only P29 Multi-drive Disable 29 1 write-only P3 Multi-drive Disable 3 1 write-only P30 Multi-drive Disable 30 1 write-only P31 Multi-drive Disable 31 1 write-only P4 Multi-drive Disable 4 1 write-only P5 Multi-drive Disable 5 1 write-only P6 Multi-drive Disable 6 1 write-only P7 Multi-drive Disable 7 1 write-only P8 Multi-drive Disable 8 1 write-only P9 Multi-drive Disable 9 1 write-only MDER Multi-driver Enable Register 0x50 32 write-only n 0x0 0x0 P0 Multi-drive Enable 0 1 write-only P1 Multi-drive Enable 1 1 write-only P10 Multi-drive Enable 10 1 write-only P11 Multi-drive Enable 11 1 write-only P12 Multi-drive Enable 12 1 write-only P13 Multi-drive Enable 13 1 write-only P14 Multi-drive Enable 14 1 write-only P15 Multi-drive Enable 15 1 write-only P16 Multi-drive Enable 16 1 write-only P17 Multi-drive Enable 17 1 write-only P18 Multi-drive Enable 18 1 write-only P19 Multi-drive Enable 19 1 write-only P2 Multi-drive Enable 2 1 write-only P20 Multi-drive Enable 20 1 write-only P21 Multi-drive Enable 21 1 write-only P22 Multi-drive Enable 22 1 write-only P23 Multi-drive Enable 23 1 write-only P24 Multi-drive Enable 24 1 write-only P25 Multi-drive Enable 25 1 write-only P26 Multi-drive Enable 26 1 write-only P27 Multi-drive Enable 27 1 write-only P28 Multi-drive Enable 28 1 write-only P29 Multi-drive Enable 29 1 write-only P3 Multi-drive Enable 3 1 write-only P30 Multi-drive Enable 30 1 write-only P31 Multi-drive Enable 31 1 write-only P4 Multi-drive Enable 4 1 write-only P5 Multi-drive Enable 5 1 write-only P6 Multi-drive Enable 6 1 write-only P7 Multi-drive Enable 7 1 write-only P8 Multi-drive Enable 8 1 write-only P9 Multi-drive Enable 9 1 write-only MDSR Multi-driver Status Register 0x58 32 read-only n 0x0 0x0 P0 Multi-drive Status 0 1 read-only P1 Multi-drive Status 1 1 read-only P10 Multi-drive Status 10 1 read-only P11 Multi-drive Status 11 1 read-only P12 Multi-drive Status 12 1 read-only P13 Multi-drive Status 13 1 read-only P14 Multi-drive Status 14 1 read-only P15 Multi-drive Status 15 1 read-only P16 Multi-drive Status 16 1 read-only P17 Multi-drive Status 17 1 read-only P18 Multi-drive Status 18 1 read-only P19 Multi-drive Status 19 1 read-only P2 Multi-drive Status 2 1 read-only P20 Multi-drive Status 20 1 read-only P21 Multi-drive Status 21 1 read-only P22 Multi-drive Status 22 1 read-only P23 Multi-drive Status 23 1 read-only P24 Multi-drive Status 24 1 read-only P25 Multi-drive Status 25 1 read-only P26 Multi-drive Status 26 1 read-only P27 Multi-drive Status 27 1 read-only P28 Multi-drive Status 28 1 read-only P29 Multi-drive Status 29 1 read-only P3 Multi-drive Status 3 1 read-only P30 Multi-drive Status 30 1 read-only P31 Multi-drive Status 31 1 read-only P4 Multi-drive Status 4 1 read-only P5 Multi-drive Status 5 1 read-only P6 Multi-drive Status 6 1 read-only P7 Multi-drive Status 7 1 read-only P8 Multi-drive Status 8 1 read-only P9 Multi-drive Status 9 1 read-only ODR Output Disable Register 0x14 32 write-only n 0x0 0x0 P0 Output Disable 0 1 write-only P1 Output Disable 1 1 write-only P10 Output Disable 10 1 write-only P11 Output Disable 11 1 write-only P12 Output Disable 12 1 write-only P13 Output Disable 13 1 write-only P14 Output Disable 14 1 write-only P15 Output Disable 15 1 write-only P16 Output Disable 16 1 write-only P17 Output Disable 17 1 write-only P18 Output Disable 18 1 write-only P19 Output Disable 19 1 write-only P2 Output Disable 2 1 write-only P20 Output Disable 20 1 write-only P21 Output Disable 21 1 write-only P22 Output Disable 22 1 write-only P23 Output Disable 23 1 write-only P24 Output Disable 24 1 write-only P25 Output Disable 25 1 write-only P26 Output Disable 26 1 write-only P27 Output Disable 27 1 write-only P28 Output Disable 28 1 write-only P29 Output Disable 29 1 write-only P3 Output Disable 3 1 write-only P30 Output Disable 30 1 write-only P31 Output Disable 31 1 write-only P4 Output Disable 4 1 write-only P5 Output Disable 5 1 write-only P6 Output Disable 6 1 write-only P7 Output Disable 7 1 write-only P8 Output Disable 8 1 write-only P9 Output Disable 9 1 write-only ODSR Output Data Status Register 0x38 32 read-write n 0x0 0x0 P0 Output Data Status 0 1 read-write P1 Output Data Status 1 1 read-write P10 Output Data Status 10 1 read-write P11 Output Data Status 11 1 read-write P12 Output Data Status 12 1 read-write P13 Output Data Status 13 1 read-write P14 Output Data Status 14 1 read-write P15 Output Data Status 15 1 read-write P16 Output Data Status 16 1 read-write P17 Output Data Status 17 1 read-write P18 Output Data Status 18 1 read-write P19 Output Data Status 19 1 read-write P2 Output Data Status 2 1 read-write P20 Output Data Status 20 1 read-write P21 Output Data Status 21 1 read-write P22 Output Data Status 22 1 read-write P23 Output Data Status 23 1 read-write P24 Output Data Status 24 1 read-write P25 Output Data Status 25 1 read-write P26 Output Data Status 26 1 read-write P27 Output Data Status 27 1 read-write P28 Output Data Status 28 1 read-write P29 Output Data Status 29 1 read-write P3 Output Data Status 3 1 read-write P30 Output Data Status 30 1 read-write P31 Output Data Status 31 1 read-write P4 Output Data Status 4 1 read-write P5 Output Data Status 5 1 read-write P6 Output Data Status 6 1 read-write P7 Output Data Status 7 1 read-write P8 Output Data Status 8 1 read-write P9 Output Data Status 9 1 read-write OER Output Enable Register 0x10 32 write-only n 0x0 0x0 P0 Output Enable 0 1 write-only P1 Output Enable 1 1 write-only P10 Output Enable 10 1 write-only P11 Output Enable 11 1 write-only P12 Output Enable 12 1 write-only P13 Output Enable 13 1 write-only P14 Output Enable 14 1 write-only P15 Output Enable 15 1 write-only P16 Output Enable 16 1 write-only P17 Output Enable 17 1 write-only P18 Output Enable 18 1 write-only P19 Output Enable 19 1 write-only P2 Output Enable 2 1 write-only P20 Output Enable 20 1 write-only P21 Output Enable 21 1 write-only P22 Output Enable 22 1 write-only P23 Output Enable 23 1 write-only P24 Output Enable 24 1 write-only P25 Output Enable 25 1 write-only P26 Output Enable 26 1 write-only P27 Output Enable 27 1 write-only P28 Output Enable 28 1 write-only P29 Output Enable 29 1 write-only P3 Output Enable 3 1 write-only P30 Output Enable 30 1 write-only P31 Output Enable 31 1 write-only P4 Output Enable 4 1 write-only P5 Output Enable 5 1 write-only P6 Output Enable 6 1 write-only P7 Output Enable 7 1 write-only P8 Output Enable 8 1 write-only P9 Output Enable 9 1 write-only OSR Output Status Register 0x18 32 read-only n 0x0 0x0 P0 Output Status 0 1 read-only P1 Output Status 1 1 read-only P10 Output Status 10 1 read-only P11 Output Status 11 1 read-only P12 Output Status 12 1 read-only P13 Output Status 13 1 read-only P14 Output Status 14 1 read-only P15 Output Status 15 1 read-only P16 Output Status 16 1 read-only P17 Output Status 17 1 read-only P18 Output Status 18 1 read-only P19 Output Status 19 1 read-only P2 Output Status 2 1 read-only P20 Output Status 20 1 read-only P21 Output Status 21 1 read-only P22 Output Status 22 1 read-only P23 Output Status 23 1 read-only P24 Output Status 24 1 read-only P25 Output Status 25 1 read-only P26 Output Status 26 1 read-only P27 Output Status 27 1 read-only P28 Output Status 28 1 read-only P29 Output Status 29 1 read-only P3 Output Status 3 1 read-only P30 Output Status 30 1 read-only P31 Output Status 31 1 read-only P4 Output Status 4 1 read-only P5 Output Status 5 1 read-only P6 Output Status 6 1 read-only P7 Output Status 7 1 read-only P8 Output Status 8 1 read-only P9 Output Status 9 1 read-only OWDR Output Write Disable 0xA4 32 write-only n 0x0 0x0 P0 Output Write Disable 0 1 write-only P1 Output Write Disable 1 1 write-only P10 Output Write Disable 10 1 write-only P11 Output Write Disable 11 1 write-only P12 Output Write Disable 12 1 write-only P13 Output Write Disable 13 1 write-only P14 Output Write Disable 14 1 write-only P15 Output Write Disable 15 1 write-only P16 Output Write Disable 16 1 write-only P17 Output Write Disable 17 1 write-only P18 Output Write Disable 18 1 write-only P19 Output Write Disable 19 1 write-only P2 Output Write Disable 2 1 write-only P20 Output Write Disable 20 1 write-only P21 Output Write Disable 21 1 write-only P22 Output Write Disable 22 1 write-only P23 Output Write Disable 23 1 write-only P24 Output Write Disable 24 1 write-only P25 Output Write Disable 25 1 write-only P26 Output Write Disable 26 1 write-only P27 Output Write Disable 27 1 write-only P28 Output Write Disable 28 1 write-only P29 Output Write Disable 29 1 write-only P3 Output Write Disable 3 1 write-only P30 Output Write Disable 30 1 write-only P31 Output Write Disable 31 1 write-only P4 Output Write Disable 4 1 write-only P5 Output Write Disable 5 1 write-only P6 Output Write Disable 6 1 write-only P7 Output Write Disable 7 1 write-only P8 Output Write Disable 8 1 write-only P9 Output Write Disable 9 1 write-only OWER Output Write Enable 0xA0 32 write-only n 0x0 0x0 P0 Output Write Enable 0 1 write-only P1 Output Write Enable 1 1 write-only P10 Output Write Enable 10 1 write-only P11 Output Write Enable 11 1 write-only P12 Output Write Enable 12 1 write-only P13 Output Write Enable 13 1 write-only P14 Output Write Enable 14 1 write-only P15 Output Write Enable 15 1 write-only P16 Output Write Enable 16 1 write-only P17 Output Write Enable 17 1 write-only P18 Output Write Enable 18 1 write-only P19 Output Write Enable 19 1 write-only P2 Output Write Enable 2 1 write-only P20 Output Write Enable 20 1 write-only P21 Output Write Enable 21 1 write-only P22 Output Write Enable 22 1 write-only P23 Output Write Enable 23 1 write-only P24 Output Write Enable 24 1 write-only P25 Output Write Enable 25 1 write-only P26 Output Write Enable 26 1 write-only P27 Output Write Enable 27 1 write-only P28 Output Write Enable 28 1 write-only P29 Output Write Enable 29 1 write-only P3 Output Write Enable 3 1 write-only P30 Output Write Enable 30 1 write-only P31 Output Write Enable 31 1 write-only P4 Output Write Enable 4 1 write-only P5 Output Write Enable 5 1 write-only P6 Output Write Enable 6 1 write-only P7 Output Write Enable 7 1 write-only P8 Output Write Enable 8 1 write-only P9 Output Write Enable 9 1 write-only OWSR Output Write Status Register 0xA8 32 read-only n 0x0 0x0 P0 Output Write Status 0 1 read-only P1 Output Write Status 1 1 read-only P10 Output Write Status 10 1 read-only P11 Output Write Status 11 1 read-only P12 Output Write Status 12 1 read-only P13 Output Write Status 13 1 read-only P14 Output Write Status 14 1 read-only P15 Output Write Status 15 1 read-only P16 Output Write Status 16 1 read-only P17 Output Write Status 17 1 read-only P18 Output Write Status 18 1 read-only P19 Output Write Status 19 1 read-only P2 Output Write Status 2 1 read-only P20 Output Write Status 20 1 read-only P21 Output Write Status 21 1 read-only P22 Output Write Status 22 1 read-only P23 Output Write Status 23 1 read-only P24 Output Write Status 24 1 read-only P25 Output Write Status 25 1 read-only P26 Output Write Status 26 1 read-only P27 Output Write Status 27 1 read-only P28 Output Write Status 28 1 read-only P29 Output Write Status 29 1 read-only P3 Output Write Status 3 1 read-only P30 Output Write Status 30 1 read-only P31 Output Write Status 31 1 read-only P4 Output Write Status 4 1 read-only P5 Output Write Status 5 1 read-only P6 Output Write Status 6 1 read-only P7 Output Write Status 7 1 read-only P8 Output Write Status 8 1 read-only P9 Output Write Status 9 1 read-only PDR PIO Disable Register 0x4 32 write-only n 0x0 0x0 P0 PIO Disable 0 1 write-only P1 PIO Disable 1 1 write-only P10 PIO Disable 10 1 write-only P11 PIO Disable 11 1 write-only P12 PIO Disable 12 1 write-only P13 PIO Disable 13 1 write-only P14 PIO Disable 14 1 write-only P15 PIO Disable 15 1 write-only P16 PIO Disable 16 1 write-only P17 PIO Disable 17 1 write-only P18 PIO Disable 18 1 write-only P19 PIO Disable 19 1 write-only P2 PIO Disable 2 1 write-only P20 PIO Disable 20 1 write-only P21 PIO Disable 21 1 write-only P22 PIO Disable 22 1 write-only P23 PIO Disable 23 1 write-only P24 PIO Disable 24 1 write-only P25 PIO Disable 25 1 write-only P26 PIO Disable 26 1 write-only P27 PIO Disable 27 1 write-only P28 PIO Disable 28 1 write-only P29 PIO Disable 29 1 write-only P3 PIO Disable 3 1 write-only P30 PIO Disable 30 1 write-only P31 PIO Disable 31 1 write-only P4 PIO Disable 4 1 write-only P5 PIO Disable 5 1 write-only P6 PIO Disable 6 1 write-only P7 PIO Disable 7 1 write-only P8 PIO Disable 8 1 write-only P9 PIO Disable 9 1 write-only PDSR Pin Data Status Register 0x3C 32 read-only n 0x0 0x0 P0 Output Data Status 0 1 read-only P1 Output Data Status 1 1 read-only P10 Output Data Status 10 1 read-only P11 Output Data Status 11 1 read-only P12 Output Data Status 12 1 read-only P13 Output Data Status 13 1 read-only P14 Output Data Status 14 1 read-only P15 Output Data Status 15 1 read-only P16 Output Data Status 16 1 read-only P17 Output Data Status 17 1 read-only P18 Output Data Status 18 1 read-only P19 Output Data Status 19 1 read-only P2 Output Data Status 2 1 read-only P20 Output Data Status 20 1 read-only P21 Output Data Status 21 1 read-only P22 Output Data Status 22 1 read-only P23 Output Data Status 23 1 read-only P24 Output Data Status 24 1 read-only P25 Output Data Status 25 1 read-only P26 Output Data Status 26 1 read-only P27 Output Data Status 27 1 read-only P28 Output Data Status 28 1 read-only P29 Output Data Status 29 1 read-only P3 Output Data Status 3 1 read-only P30 Output Data Status 30 1 read-only P31 Output Data Status 31 1 read-only P4 Output Data Status 4 1 read-only P5 Output Data Status 5 1 read-only P6 Output Data Status 6 1 read-only P7 Output Data Status 7 1 read-only P8 Output Data Status 8 1 read-only P9 Output Data Status 9 1 read-only PER PIO Enable Register 0x0 32 write-only n 0x0 0x0 P0 PIO Enable 0 1 write-only P1 PIO Enable 1 1 write-only P10 PIO Enable 10 1 write-only P11 PIO Enable 11 1 write-only P12 PIO Enable 12 1 write-only P13 PIO Enable 13 1 write-only P14 PIO Enable 14 1 write-only P15 PIO Enable 15 1 write-only P16 PIO Enable 16 1 write-only P17 PIO Enable 17 1 write-only P18 PIO Enable 18 1 write-only P19 PIO Enable 19 1 write-only P2 PIO Enable 2 1 write-only P20 PIO Enable 20 1 write-only P21 PIO Enable 21 1 write-only P22 PIO Enable 22 1 write-only P23 PIO Enable 23 1 write-only P24 PIO Enable 24 1 write-only P25 PIO Enable 25 1 write-only P26 PIO Enable 26 1 write-only P27 PIO Enable 27 1 write-only P28 PIO Enable 28 1 write-only P29 PIO Enable 29 1 write-only P3 PIO Enable 3 1 write-only P30 PIO Enable 30 1 write-only P31 PIO Enable 31 1 write-only P4 PIO Enable 4 1 write-only P5 PIO Enable 5 1 write-only P6 PIO Enable 6 1 write-only P7 PIO Enable 7 1 write-only P8 PIO Enable 8 1 write-only P9 PIO Enable 9 1 write-only PPDDR Pad Pull-Down Disable Register 0x90 32 write-only n 0x0 0x0 P0 Pull-Down Disable 0 1 write-only P1 Pull-Down Disable 1 1 write-only P10 Pull-Down Disable 10 1 write-only P11 Pull-Down Disable 11 1 write-only P12 Pull-Down Disable 12 1 write-only P13 Pull-Down Disable 13 1 write-only P14 Pull-Down Disable 14 1 write-only P15 Pull-Down Disable 15 1 write-only P16 Pull-Down Disable 16 1 write-only P17 Pull-Down Disable 17 1 write-only P18 Pull-Down Disable 18 1 write-only P19 Pull-Down Disable 19 1 write-only P2 Pull-Down Disable 2 1 write-only P20 Pull-Down Disable 20 1 write-only P21 Pull-Down Disable 21 1 write-only P22 Pull-Down Disable 22 1 write-only P23 Pull-Down Disable 23 1 write-only P24 Pull-Down Disable 24 1 write-only P25 Pull-Down Disable 25 1 write-only P26 Pull-Down Disable 26 1 write-only P27 Pull-Down Disable 27 1 write-only P28 Pull-Down Disable 28 1 write-only P29 Pull-Down Disable 29 1 write-only P3 Pull-Down Disable 3 1 write-only P30 Pull-Down Disable 30 1 write-only P31 Pull-Down Disable 31 1 write-only P4 Pull-Down Disable 4 1 write-only P5 Pull-Down Disable 5 1 write-only P6 Pull-Down Disable 6 1 write-only P7 Pull-Down Disable 7 1 write-only P8 Pull-Down Disable 8 1 write-only P9 Pull-Down Disable 9 1 write-only PPDER Pad Pull-Down Enable Register 0x94 32 write-only n 0x0 0x0 P0 Pull-Down Enable 0 1 write-only P1 Pull-Down Enable 1 1 write-only P10 Pull-Down Enable 10 1 write-only P11 Pull-Down Enable 11 1 write-only P12 Pull-Down Enable 12 1 write-only P13 Pull-Down Enable 13 1 write-only P14 Pull-Down Enable 14 1 write-only P15 Pull-Down Enable 15 1 write-only P16 Pull-Down Enable 16 1 write-only P17 Pull-Down Enable 17 1 write-only P18 Pull-Down Enable 18 1 write-only P19 Pull-Down Enable 19 1 write-only P2 Pull-Down Enable 2 1 write-only P20 Pull-Down Enable 20 1 write-only P21 Pull-Down Enable 21 1 write-only P22 Pull-Down Enable 22 1 write-only P23 Pull-Down Enable 23 1 write-only P24 Pull-Down Enable 24 1 write-only P25 Pull-Down Enable 25 1 write-only P26 Pull-Down Enable 26 1 write-only P27 Pull-Down Enable 27 1 write-only P28 Pull-Down Enable 28 1 write-only P29 Pull-Down Enable 29 1 write-only P3 Pull-Down Enable 3 1 write-only P30 Pull-Down Enable 30 1 write-only P31 Pull-Down Enable 31 1 write-only P4 Pull-Down Enable 4 1 write-only P5 Pull-Down Enable 5 1 write-only P6 Pull-Down Enable 6 1 write-only P7 Pull-Down Enable 7 1 write-only P8 Pull-Down Enable 8 1 write-only P9 Pull-Down Enable 9 1 write-only PPDSR Pad Pull-Down Status Register 0x98 32 read-only n 0x0 0x0 P0 Pull-Down Status 0 1 read-only P1 Pull-Down Status 1 1 read-only P10 Pull-Down Status 10 1 read-only P11 Pull-Down Status 11 1 read-only P12 Pull-Down Status 12 1 read-only P13 Pull-Down Status 13 1 read-only P14 Pull-Down Status 14 1 read-only P15 Pull-Down Status 15 1 read-only P16 Pull-Down Status 16 1 read-only P17 Pull-Down Status 17 1 read-only P18 Pull-Down Status 18 1 read-only P19 Pull-Down Status 19 1 read-only P2 Pull-Down Status 2 1 read-only P20 Pull-Down Status 20 1 read-only P21 Pull-Down Status 21 1 read-only P22 Pull-Down Status 22 1 read-only P23 Pull-Down Status 23 1 read-only P24 Pull-Down Status 24 1 read-only P25 Pull-Down Status 25 1 read-only P26 Pull-Down Status 26 1 read-only P27 Pull-Down Status 27 1 read-only P28 Pull-Down Status 28 1 read-only P29 Pull-Down Status 29 1 read-only P3 Pull-Down Status 3 1 read-only P30 Pull-Down Status 30 1 read-only P31 Pull-Down Status 31 1 read-only P4 Pull-Down Status 4 1 read-only P5 Pull-Down Status 5 1 read-only P6 Pull-Down Status 6 1 read-only P7 Pull-Down Status 7 1 read-only P8 Pull-Down Status 8 1 read-only P9 Pull-Down Status 9 1 read-only PSR PIO Status Register 0x8 32 read-only n 0x0 0x0 P0 PIO Status 0 1 read-only P1 PIO Status 1 1 read-only P10 PIO Status 10 1 read-only P11 PIO Status 11 1 read-only P12 PIO Status 12 1 read-only P13 PIO Status 13 1 read-only P14 PIO Status 14 1 read-only P15 PIO Status 15 1 read-only P16 PIO Status 16 1 read-only P17 PIO Status 17 1 read-only P18 PIO Status 18 1 read-only P19 PIO Status 19 1 read-only P2 PIO Status 2 1 read-only P20 PIO Status 20 1 read-only P21 PIO Status 21 1 read-only P22 PIO Status 22 1 read-only P23 PIO Status 23 1 read-only P24 PIO Status 24 1 read-only P25 PIO Status 25 1 read-only P26 PIO Status 26 1 read-only P27 PIO Status 27 1 read-only P28 PIO Status 28 1 read-only P29 PIO Status 29 1 read-only P3 PIO Status 3 1 read-only P30 PIO Status 30 1 read-only P31 PIO Status 31 1 read-only P4 PIO Status 4 1 read-only P5 PIO Status 5 1 read-only P6 PIO Status 6 1 read-only P7 PIO Status 7 1 read-only P8 PIO Status 8 1 read-only P9 PIO Status 9 1 read-only PUDR Pull-Up Disable Register 0x60 32 write-only n 0x0 0x0 P0 Pull-Up Disable 0 1 write-only P1 Pull-Up Disable 1 1 write-only P10 Pull-Up Disable 10 1 write-only P11 Pull-Up Disable 11 1 write-only P12 Pull-Up Disable 12 1 write-only P13 Pull-Up Disable 13 1 write-only P14 Pull-Up Disable 14 1 write-only P15 Pull-Up Disable 15 1 write-only P16 Pull-Up Disable 16 1 write-only P17 Pull-Up Disable 17 1 write-only P18 Pull-Up Disable 18 1 write-only P19 Pull-Up Disable 19 1 write-only P2 Pull-Up Disable 2 1 write-only P20 Pull-Up Disable 20 1 write-only P21 Pull-Up Disable 21 1 write-only P22 Pull-Up Disable 22 1 write-only P23 Pull-Up Disable 23 1 write-only P24 Pull-Up Disable 24 1 write-only P25 Pull-Up Disable 25 1 write-only P26 Pull-Up Disable 26 1 write-only P27 Pull-Up Disable 27 1 write-only P28 Pull-Up Disable 28 1 write-only P29 Pull-Up Disable 29 1 write-only P3 Pull-Up Disable 3 1 write-only P30 Pull-Up Disable 30 1 write-only P31 Pull-Up Disable 31 1 write-only P4 Pull-Up Disable 4 1 write-only P5 Pull-Up Disable 5 1 write-only P6 Pull-Up Disable 6 1 write-only P7 Pull-Up Disable 7 1 write-only P8 Pull-Up Disable 8 1 write-only P9 Pull-Up Disable 9 1 write-only PUER Pull-Up Enable Register 0x64 32 write-only n 0x0 0x0 P0 Pull-Up Enable 0 1 write-only P1 Pull-Up Enable 1 1 write-only P10 Pull-Up Enable 10 1 write-only P11 Pull-Up Enable 11 1 write-only P12 Pull-Up Enable 12 1 write-only P13 Pull-Up Enable 13 1 write-only P14 Pull-Up Enable 14 1 write-only P15 Pull-Up Enable 15 1 write-only P16 Pull-Up Enable 16 1 write-only P17 Pull-Up Enable 17 1 write-only P18 Pull-Up Enable 18 1 write-only P19 Pull-Up Enable 19 1 write-only P2 Pull-Up Enable 2 1 write-only P20 Pull-Up Enable 20 1 write-only P21 Pull-Up Enable 21 1 write-only P22 Pull-Up Enable 22 1 write-only P23 Pull-Up Enable 23 1 write-only P24 Pull-Up Enable 24 1 write-only P25 Pull-Up Enable 25 1 write-only P26 Pull-Up Enable 26 1 write-only P27 Pull-Up Enable 27 1 write-only P28 Pull-Up Enable 28 1 write-only P29 Pull-Up Enable 29 1 write-only P3 Pull-Up Enable 3 1 write-only P30 Pull-Up Enable 30 1 write-only P31 Pull-Up Enable 31 1 write-only P4 Pull-Up Enable 4 1 write-only P5 Pull-Up Enable 5 1 write-only P6 Pull-Up Enable 6 1 write-only P7 Pull-Up Enable 7 1 write-only P8 Pull-Up Enable 8 1 write-only P9 Pull-Up Enable 9 1 write-only PUSR Pad Pull-Up Status Register 0x68 32 read-only n 0x0 0x0 P0 Pull-Up Status 0 1 read-only P1 Pull-Up Status 1 1 read-only P10 Pull-Up Status 10 1 read-only P11 Pull-Up Status 11 1 read-only P12 Pull-Up Status 12 1 read-only P13 Pull-Up Status 13 1 read-only P14 Pull-Up Status 14 1 read-only P15 Pull-Up Status 15 1 read-only P16 Pull-Up Status 16 1 read-only P17 Pull-Up Status 17 1 read-only P18 Pull-Up Status 18 1 read-only P19 Pull-Up Status 19 1 read-only P2 Pull-Up Status 2 1 read-only P20 Pull-Up Status 20 1 read-only P21 Pull-Up Status 21 1 read-only P22 Pull-Up Status 22 1 read-only P23 Pull-Up Status 23 1 read-only P24 Pull-Up Status 24 1 read-only P25 Pull-Up Status 25 1 read-only P26 Pull-Up Status 26 1 read-only P27 Pull-Up Status 27 1 read-only P28 Pull-Up Status 28 1 read-only P29 Pull-Up Status 29 1 read-only P3 Pull-Up Status 3 1 read-only P30 Pull-Up Status 30 1 read-only P31 Pull-Up Status 31 1 read-only P4 Pull-Up Status 4 1 read-only P5 Pull-Up Status 5 1 read-only P6 Pull-Up Status 6 1 read-only P7 Pull-Up Status 7 1 read-only P8 Pull-Up Status 8 1 read-only P9 Pull-Up Status 9 1 read-only REHLSR Rising Edge/High-Level Select Register 0xD4 32 write-only n 0x0 0x0 P0 Rising Edge/High-Level Interrupt Selection 0 1 write-only P1 Rising Edge/High-Level Interrupt Selection 1 1 write-only P10 Rising Edge/High-Level Interrupt Selection 10 1 write-only P11 Rising Edge/High-Level Interrupt Selection 11 1 write-only P12 Rising Edge/High-Level Interrupt Selection 12 1 write-only P13 Rising Edge/High-Level Interrupt Selection 13 1 write-only P14 Rising Edge/High-Level Interrupt Selection 14 1 write-only P15 Rising Edge/High-Level Interrupt Selection 15 1 write-only P16 Rising Edge/High-Level Interrupt Selection 16 1 write-only P17 Rising Edge/High-Level Interrupt Selection 17 1 write-only P18 Rising Edge/High-Level Interrupt Selection 18 1 write-only P19 Rising Edge/High-Level Interrupt Selection 19 1 write-only P2 Rising Edge/High-Level Interrupt Selection 2 1 write-only P20 Rising Edge/High-Level Interrupt Selection 20 1 write-only P21 Rising Edge/High-Level Interrupt Selection 21 1 write-only P22 Rising Edge/High-Level Interrupt Selection 22 1 write-only P23 Rising Edge/High-Level Interrupt Selection 23 1 write-only P24 Rising Edge/High-Level Interrupt Selection 24 1 write-only P25 Rising Edge/High-Level Interrupt Selection 25 1 write-only P26 Rising Edge/High-Level Interrupt Selection 26 1 write-only P27 Rising Edge/High-Level Interrupt Selection 27 1 write-only P28 Rising Edge/High-Level Interrupt Selection 28 1 write-only P29 Rising Edge/High-Level Interrupt Selection 29 1 write-only P3 Rising Edge/High-Level Interrupt Selection 3 1 write-only P30 Rising Edge/High-Level Interrupt Selection 30 1 write-only P31 Rising Edge/High-Level Interrupt Selection 31 1 write-only P4 Rising Edge/High-Level Interrupt Selection 4 1 write-only P5 Rising Edge/High-Level Interrupt Selection 5 1 write-only P6 Rising Edge/High-Level Interrupt Selection 6 1 write-only P7 Rising Edge/High-Level Interrupt Selection 7 1 write-only P8 Rising Edge/High-Level Interrupt Selection 8 1 write-only P9 Rising Edge/High-Level Interrupt Selection 9 1 write-only SCDR Slow Clock Divider Debouncing Register 0x8C 32 read-write n 0x0 0x0 DIV Slow Clock Divider Selection for Debouncing 0 14 read-write SCHMITT Schmitt Trigger Register 0x100 32 read-write n 0x0 0x0 SCHMITT0 Schmitt Trigger Control 0 1 read-write SCHMITT1 Schmitt Trigger Control 1 1 read-write SCHMITT10 Schmitt Trigger Control 10 1 read-write SCHMITT11 Schmitt Trigger Control 11 1 read-write SCHMITT12 Schmitt Trigger Control 12 1 read-write SCHMITT13 Schmitt Trigger Control 13 1 read-write SCHMITT14 Schmitt Trigger Control 14 1 read-write SCHMITT15 Schmitt Trigger Control 15 1 read-write SCHMITT16 Schmitt Trigger Control 16 1 read-write SCHMITT17 Schmitt Trigger Control 17 1 read-write SCHMITT18 Schmitt Trigger Control 18 1 read-write SCHMITT19 Schmitt Trigger Control 19 1 read-write SCHMITT2 Schmitt Trigger Control 2 1 read-write SCHMITT20 Schmitt Trigger Control 20 1 read-write SCHMITT21 Schmitt Trigger Control 21 1 read-write SCHMITT22 Schmitt Trigger Control 22 1 read-write SCHMITT23 Schmitt Trigger Control 23 1 read-write SCHMITT24 Schmitt Trigger Control 24 1 read-write SCHMITT25 Schmitt Trigger Control 25 1 read-write SCHMITT26 Schmitt Trigger Control 26 1 read-write SCHMITT27 Schmitt Trigger Control 27 1 read-write SCHMITT28 Schmitt Trigger Control 28 1 read-write SCHMITT29 Schmitt Trigger Control 29 1 read-write SCHMITT3 Schmitt Trigger Control 3 1 read-write SCHMITT30 Schmitt Trigger Control 30 1 read-write SCHMITT31 Schmitt Trigger Control 31 1 read-write SCHMITT4 Schmitt Trigger Control 4 1 read-write SCHMITT5 Schmitt Trigger Control 5 1 read-write SCHMITT6 Schmitt Trigger Control 6 1 read-write SCHMITT7 Schmitt Trigger Control 7 1 read-write SCHMITT8 Schmitt Trigger Control 8 1 read-write SCHMITT9 Schmitt Trigger Control 9 1 read-write SODR Set Output Data Register 0x30 32 write-only n 0x0 0x0 P0 Set Output Data 0 1 write-only P1 Set Output Data 1 1 write-only P10 Set Output Data 10 1 write-only P11 Set Output Data 11 1 write-only P12 Set Output Data 12 1 write-only P13 Set Output Data 13 1 write-only P14 Set Output Data 14 1 write-only P15 Set Output Data 15 1 write-only P16 Set Output Data 16 1 write-only P17 Set Output Data 17 1 write-only P18 Set Output Data 18 1 write-only P19 Set Output Data 19 1 write-only P2 Set Output Data 2 1 write-only P20 Set Output Data 20 1 write-only P21 Set Output Data 21 1 write-only P22 Set Output Data 22 1 write-only P23 Set Output Data 23 1 write-only P24 Set Output Data 24 1 write-only P25 Set Output Data 25 1 write-only P26 Set Output Data 26 1 write-only P27 Set Output Data 27 1 write-only P28 Set Output Data 28 1 write-only P29 Set Output Data 29 1 write-only P3 Set Output Data 3 1 write-only P30 Set Output Data 30 1 write-only P31 Set Output Data 31 1 write-only P4 Set Output Data 4 1 write-only P5 Set Output Data 5 1 write-only P6 Set Output Data 6 1 write-only P7 Set Output Data 7 1 write-only P8 Set Output Data 8 1 write-only P9 Set Output Data 9 1 write-only WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 read-write WPKEY Write Protection Key 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 0x50494F WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 read-only WPVSRC Write Protection Violation Source 8 16 read-only PIOD Parallel Input/Output Controller D PIO 0x0 0x0 0x200 registers n PIOD 5 ABCDSR0 Peripheral ABCD Select Register 0x70 32 read-write n P0 Peripheral Select 0 1 read-write P1 Peripheral Select 1 1 read-write P10 Peripheral Select 10 1 read-write P11 Peripheral Select 11 1 read-write P12 Peripheral Select 12 1 read-write P13 Peripheral Select 13 1 read-write P14 Peripheral Select 14 1 read-write P15 Peripheral Select 15 1 read-write P16 Peripheral Select 16 1 read-write P17 Peripheral Select 17 1 read-write P18 Peripheral Select 18 1 read-write P19 Peripheral Select 19 1 read-write P2 Peripheral Select 2 1 read-write P20 Peripheral Select 20 1 read-write P21 Peripheral Select 21 1 read-write P22 Peripheral Select 22 1 read-write P23 Peripheral Select 23 1 read-write P24 Peripheral Select 24 1 read-write P25 Peripheral Select 25 1 read-write P26 Peripheral Select 26 1 read-write P27 Peripheral Select 27 1 read-write P28 Peripheral Select 28 1 read-write P29 Peripheral Select 29 1 read-write P3 Peripheral Select 3 1 read-write P30 Peripheral Select 30 1 read-write P31 Peripheral Select 31 1 read-write P4 Peripheral Select 4 1 read-write P5 Peripheral Select 5 1 read-write P6 Peripheral Select 6 1 read-write P7 Peripheral Select 7 1 read-write P8 Peripheral Select 8 1 read-write P9 Peripheral Select 9 1 read-write ABCDSR1 Peripheral ABCD Select Register 0x74 32 read-write n P0 Peripheral Select 0 1 read-write P1 Peripheral Select 1 1 read-write P10 Peripheral Select 10 1 read-write P11 Peripheral Select 11 1 read-write P12 Peripheral Select 12 1 read-write P13 Peripheral Select 13 1 read-write P14 Peripheral Select 14 1 read-write P15 Peripheral Select 15 1 read-write P16 Peripheral Select 16 1 read-write P17 Peripheral Select 17 1 read-write P18 Peripheral Select 18 1 read-write P19 Peripheral Select 19 1 read-write P2 Peripheral Select 2 1 read-write P20 Peripheral Select 20 1 read-write P21 Peripheral Select 21 1 read-write P22 Peripheral Select 22 1 read-write P23 Peripheral Select 23 1 read-write P24 Peripheral Select 24 1 read-write P25 Peripheral Select 25 1 read-write P26 Peripheral Select 26 1 read-write P27 Peripheral Select 27 1 read-write P28 Peripheral Select 28 1 read-write P29 Peripheral Select 29 1 read-write P3 Peripheral Select 3 1 read-write P30 Peripheral Select 30 1 read-write P31 Peripheral Select 31 1 read-write P4 Peripheral Select 4 1 read-write P5 Peripheral Select 5 1 read-write P6 Peripheral Select 6 1 read-write P7 Peripheral Select 7 1 read-write P8 Peripheral Select 8 1 read-write P9 Peripheral Select 9 1 read-write ABCDSR[0] Peripheral ABCD Select Register 0xE0 32 read-write n 0x0 0x0 P0 Peripheral Select 0 1 read-write P1 Peripheral Select 1 1 read-write P10 Peripheral Select 10 1 read-write P11 Peripheral Select 11 1 read-write P12 Peripheral Select 12 1 read-write P13 Peripheral Select 13 1 read-write P14 Peripheral Select 14 1 read-write P15 Peripheral Select 15 1 read-write P16 Peripheral Select 16 1 read-write P17 Peripheral Select 17 1 read-write P18 Peripheral Select 18 1 read-write P19 Peripheral Select 19 1 read-write P2 Peripheral Select 2 1 read-write P20 Peripheral Select 20 1 read-write P21 Peripheral Select 21 1 read-write P22 Peripheral Select 22 1 read-write P23 Peripheral Select 23 1 read-write P24 Peripheral Select 24 1 read-write P25 Peripheral Select 25 1 read-write P26 Peripheral Select 26 1 read-write P27 Peripheral Select 27 1 read-write P28 Peripheral Select 28 1 read-write P29 Peripheral Select 29 1 read-write P3 Peripheral Select 3 1 read-write P30 Peripheral Select 30 1 read-write P31 Peripheral Select 31 1 read-write P4 Peripheral Select 4 1 read-write P5 Peripheral Select 5 1 read-write P6 Peripheral Select 6 1 read-write P7 Peripheral Select 7 1 read-write P8 Peripheral Select 8 1 read-write P9 Peripheral Select 9 1 read-write ABCDSR[1] Peripheral ABCD Select Register 0x154 32 read-write n 0x0 0x0 P0 Peripheral Select 0 1 read-write P1 Peripheral Select 1 1 read-write P10 Peripheral Select 10 1 read-write P11 Peripheral Select 11 1 read-write P12 Peripheral Select 12 1 read-write P13 Peripheral Select 13 1 read-write P14 Peripheral Select 14 1 read-write P15 Peripheral Select 15 1 read-write P16 Peripheral Select 16 1 read-write P17 Peripheral Select 17 1 read-write P18 Peripheral Select 18 1 read-write P19 Peripheral Select 19 1 read-write P2 Peripheral Select 2 1 read-write P20 Peripheral Select 20 1 read-write P21 Peripheral Select 21 1 read-write P22 Peripheral Select 22 1 read-write P23 Peripheral Select 23 1 read-write P24 Peripheral Select 24 1 read-write P25 Peripheral Select 25 1 read-write P26 Peripheral Select 26 1 read-write P27 Peripheral Select 27 1 read-write P28 Peripheral Select 28 1 read-write P29 Peripheral Select 29 1 read-write P3 Peripheral Select 3 1 read-write P30 Peripheral Select 30 1 read-write P31 Peripheral Select 31 1 read-write P4 Peripheral Select 4 1 read-write P5 Peripheral Select 5 1 read-write P6 Peripheral Select 6 1 read-write P7 Peripheral Select 7 1 read-write P8 Peripheral Select 8 1 read-write P9 Peripheral Select 9 1 read-write AIMDR Additional Interrupt Modes Disable Register 0xB4 32 write-only n 0x0 0x0 P0 Additional Interrupt Modes Disable 0 1 write-only P1 Additional Interrupt Modes Disable 1 1 write-only P10 Additional Interrupt Modes Disable 10 1 write-only P11 Additional Interrupt Modes Disable 11 1 write-only P12 Additional Interrupt Modes Disable 12 1 write-only P13 Additional Interrupt Modes Disable 13 1 write-only P14 Additional Interrupt Modes Disable 14 1 write-only P15 Additional Interrupt Modes Disable 15 1 write-only P16 Additional Interrupt Modes Disable 16 1 write-only P17 Additional Interrupt Modes Disable 17 1 write-only P18 Additional Interrupt Modes Disable 18 1 write-only P19 Additional Interrupt Modes Disable 19 1 write-only P2 Additional Interrupt Modes Disable 2 1 write-only P20 Additional Interrupt Modes Disable 20 1 write-only P21 Additional Interrupt Modes Disable 21 1 write-only P22 Additional Interrupt Modes Disable 22 1 write-only P23 Additional Interrupt Modes Disable 23 1 write-only P24 Additional Interrupt Modes Disable 24 1 write-only P25 Additional Interrupt Modes Disable 25 1 write-only P26 Additional Interrupt Modes Disable 26 1 write-only P27 Additional Interrupt Modes Disable 27 1 write-only P28 Additional Interrupt Modes Disable 28 1 write-only P29 Additional Interrupt Modes Disable 29 1 write-only P3 Additional Interrupt Modes Disable 3 1 write-only P30 Additional Interrupt Modes Disable 30 1 write-only P31 Additional Interrupt Modes Disable 31 1 write-only P4 Additional Interrupt Modes Disable 4 1 write-only P5 Additional Interrupt Modes Disable 5 1 write-only P6 Additional Interrupt Modes Disable 6 1 write-only P7 Additional Interrupt Modes Disable 7 1 write-only P8 Additional Interrupt Modes Disable 8 1 write-only P9 Additional Interrupt Modes Disable 9 1 write-only AIMER Additional Interrupt Modes Enable Register 0xB0 32 write-only n 0x0 0x0 P0 Additional Interrupt Modes Enable 0 1 write-only P1 Additional Interrupt Modes Enable 1 1 write-only P10 Additional Interrupt Modes Enable 10 1 write-only P11 Additional Interrupt Modes Enable 11 1 write-only P12 Additional Interrupt Modes Enable 12 1 write-only P13 Additional Interrupt Modes Enable 13 1 write-only P14 Additional Interrupt Modes Enable 14 1 write-only P15 Additional Interrupt Modes Enable 15 1 write-only P16 Additional Interrupt Modes Enable 16 1 write-only P17 Additional Interrupt Modes Enable 17 1 write-only P18 Additional Interrupt Modes Enable 18 1 write-only P19 Additional Interrupt Modes Enable 19 1 write-only P2 Additional Interrupt Modes Enable 2 1 write-only P20 Additional Interrupt Modes Enable 20 1 write-only P21 Additional Interrupt Modes Enable 21 1 write-only P22 Additional Interrupt Modes Enable 22 1 write-only P23 Additional Interrupt Modes Enable 23 1 write-only P24 Additional Interrupt Modes Enable 24 1 write-only P25 Additional Interrupt Modes Enable 25 1 write-only P26 Additional Interrupt Modes Enable 26 1 write-only P27 Additional Interrupt Modes Enable 27 1 write-only P28 Additional Interrupt Modes Enable 28 1 write-only P29 Additional Interrupt Modes Enable 29 1 write-only P3 Additional Interrupt Modes Enable 3 1 write-only P30 Additional Interrupt Modes Enable 30 1 write-only P31 Additional Interrupt Modes Enable 31 1 write-only P4 Additional Interrupt Modes Enable 4 1 write-only P5 Additional Interrupt Modes Enable 5 1 write-only P6 Additional Interrupt Modes Enable 6 1 write-only P7 Additional Interrupt Modes Enable 7 1 write-only P8 Additional Interrupt Modes Enable 8 1 write-only P9 Additional Interrupt Modes Enable 9 1 write-only AIMMR Additional Interrupt Modes Mask Register 0xB8 32 read-only n 0x0 0x0 P0 IO Line Index 0 1 read-only P1 IO Line Index 1 1 read-only P10 IO Line Index 10 1 read-only P11 IO Line Index 11 1 read-only P12 IO Line Index 12 1 read-only P13 IO Line Index 13 1 read-only P14 IO Line Index 14 1 read-only P15 IO Line Index 15 1 read-only P16 IO Line Index 16 1 read-only P17 IO Line Index 17 1 read-only P18 IO Line Index 18 1 read-only P19 IO Line Index 19 1 read-only P2 IO Line Index 2 1 read-only P20 IO Line Index 20 1 read-only P21 IO Line Index 21 1 read-only P22 IO Line Index 22 1 read-only P23 IO Line Index 23 1 read-only P24 IO Line Index 24 1 read-only P25 IO Line Index 25 1 read-only P26 IO Line Index 26 1 read-only P27 IO Line Index 27 1 read-only P28 IO Line Index 28 1 read-only P29 IO Line Index 29 1 read-only P3 IO Line Index 3 1 read-only P30 IO Line Index 30 1 read-only P31 IO Line Index 31 1 read-only P4 IO Line Index 4 1 read-only P5 IO Line Index 5 1 read-only P6 IO Line Index 6 1 read-only P7 IO Line Index 7 1 read-only P8 IO Line Index 8 1 read-only P9 IO Line Index 9 1 read-only CODR Clear Output Data Register 0x34 32 write-only n 0x0 0x0 P0 Clear Output Data 0 1 write-only P1 Clear Output Data 1 1 write-only P10 Clear Output Data 10 1 write-only P11 Clear Output Data 11 1 write-only P12 Clear Output Data 12 1 write-only P13 Clear Output Data 13 1 write-only P14 Clear Output Data 14 1 write-only P15 Clear Output Data 15 1 write-only P16 Clear Output Data 16 1 write-only P17 Clear Output Data 17 1 write-only P18 Clear Output Data 18 1 write-only P19 Clear Output Data 19 1 write-only P2 Clear Output Data 2 1 write-only P20 Clear Output Data 20 1 write-only P21 Clear Output Data 21 1 write-only P22 Clear Output Data 22 1 write-only P23 Clear Output Data 23 1 write-only P24 Clear Output Data 24 1 write-only P25 Clear Output Data 25 1 write-only P26 Clear Output Data 26 1 write-only P27 Clear Output Data 27 1 write-only P28 Clear Output Data 28 1 write-only P29 Clear Output Data 29 1 write-only P3 Clear Output Data 3 1 write-only P30 Clear Output Data 30 1 write-only P31 Clear Output Data 31 1 write-only P4 Clear Output Data 4 1 write-only P5 Clear Output Data 5 1 write-only P6 Clear Output Data 6 1 write-only P7 Clear Output Data 7 1 write-only P8 Clear Output Data 8 1 write-only P9 Clear Output Data 9 1 write-only DRIVER1 I/O Drive Register 1 0x118 32 read-write n 0x0 0x0 LINE0 Drive of PIO Line 0 0 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE1 Drive of PIO Line 1 2 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE10 Drive of PIO Line 10 20 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE11 Drive of PIO Line 11 22 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE12 Drive of PIO Line 12 24 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE13 Drive of PIO Line 13 26 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE14 Drive of PIO Line 14 28 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE15 Drive of PIO Line 15 30 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE2 Drive of PIO Line 2 4 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE3 Drive of PIO Line 3 6 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE4 Drive of PIO Line 4 8 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE5 Drive of PIO Line 5 10 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE6 Drive of PIO Line 6 12 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE7 Drive of PIO Line 7 14 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE8 Drive of PIO Line 8 16 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE9 Drive of PIO Line 9 18 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 DRIVER2 I/O Drive Register 2 0x11C 32 read-write n 0x0 0x0 LINE16 Drive of PIO line 16 0 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE17 Drive of PIO line 17 2 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE18 Drive of PIO line 18 4 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE19 Drive of PIO line 19 6 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE20 Drive of PIO line 20 8 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE21 Drive of PIO line 21 10 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE22 Drive of PIO line 22 12 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE23 Drive of PIO line 23 14 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE24 Drive of PIO line 24 16 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE25 Drive of PIO line 25 18 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE26 Drive of PIO line 26 20 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE27 Drive of PIO line 27 22 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE28 Drive of PIO line 28 24 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE29 Drive of PIO line 29 26 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE30 Drive of PIO line 30 28 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE31 Drive of PIO line 31 30 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 ELSR Edge/Level Status Register 0xC8 32 read-only n 0x0 0x0 P0 Edge/Level Interrupt Source Selection 0 1 read-only P1 Edge/Level Interrupt Source Selection 1 1 read-only P10 Edge/Level Interrupt Source Selection 10 1 read-only P11 Edge/Level Interrupt Source Selection 11 1 read-only P12 Edge/Level Interrupt Source Selection 12 1 read-only P13 Edge/Level Interrupt Source Selection 13 1 read-only P14 Edge/Level Interrupt Source Selection 14 1 read-only P15 Edge/Level Interrupt Source Selection 15 1 read-only P16 Edge/Level Interrupt Source Selection 16 1 read-only P17 Edge/Level Interrupt Source Selection 17 1 read-only P18 Edge/Level Interrupt Source Selection 18 1 read-only P19 Edge/Level Interrupt Source Selection 19 1 read-only P2 Edge/Level Interrupt Source Selection 2 1 read-only P20 Edge/Level Interrupt Source Selection 20 1 read-only P21 Edge/Level Interrupt Source Selection 21 1 read-only P22 Edge/Level Interrupt Source Selection 22 1 read-only P23 Edge/Level Interrupt Source Selection 23 1 read-only P24 Edge/Level Interrupt Source Selection 24 1 read-only P25 Edge/Level Interrupt Source Selection 25 1 read-only P26 Edge/Level Interrupt Source Selection 26 1 read-only P27 Edge/Level Interrupt Source Selection 27 1 read-only P28 Edge/Level Interrupt Source Selection 28 1 read-only P29 Edge/Level Interrupt Source Selection 29 1 read-only P3 Edge/Level Interrupt Source Selection 3 1 read-only P30 Edge/Level Interrupt Source Selection 30 1 read-only P31 Edge/Level Interrupt Source Selection 31 1 read-only P4 Edge/Level Interrupt Source Selection 4 1 read-only P5 Edge/Level Interrupt Source Selection 5 1 read-only P6 Edge/Level Interrupt Source Selection 6 1 read-only P7 Edge/Level Interrupt Source Selection 7 1 read-only P8 Edge/Level Interrupt Source Selection 8 1 read-only P9 Edge/Level Interrupt Source Selection 9 1 read-only ESR Edge Select Register 0xC0 32 write-only n 0x0 0x0 P0 Edge Interrupt Selection 0 1 write-only P1 Edge Interrupt Selection 1 1 write-only P10 Edge Interrupt Selection 10 1 write-only P11 Edge Interrupt Selection 11 1 write-only P12 Edge Interrupt Selection 12 1 write-only P13 Edge Interrupt Selection 13 1 write-only P14 Edge Interrupt Selection 14 1 write-only P15 Edge Interrupt Selection 15 1 write-only P16 Edge Interrupt Selection 16 1 write-only P17 Edge Interrupt Selection 17 1 write-only P18 Edge Interrupt Selection 18 1 write-only P19 Edge Interrupt Selection 19 1 write-only P2 Edge Interrupt Selection 2 1 write-only P20 Edge Interrupt Selection 20 1 write-only P21 Edge Interrupt Selection 21 1 write-only P22 Edge Interrupt Selection 22 1 write-only P23 Edge Interrupt Selection 23 1 write-only P24 Edge Interrupt Selection 24 1 write-only P25 Edge Interrupt Selection 25 1 write-only P26 Edge Interrupt Selection 26 1 write-only P27 Edge Interrupt Selection 27 1 write-only P28 Edge Interrupt Selection 28 1 write-only P29 Edge Interrupt Selection 29 1 write-only P3 Edge Interrupt Selection 3 1 write-only P30 Edge Interrupt Selection 30 1 write-only P31 Edge Interrupt Selection 31 1 write-only P4 Edge Interrupt Selection 4 1 write-only P5 Edge Interrupt Selection 5 1 write-only P6 Edge Interrupt Selection 6 1 write-only P7 Edge Interrupt Selection 7 1 write-only P8 Edge Interrupt Selection 8 1 write-only P9 Edge Interrupt Selection 9 1 write-only FELLSR Falling Edge/Low-Level Select Register 0xD0 32 write-only n 0x0 0x0 P0 Falling Edge/Low-Level Interrupt Selection 0 1 write-only P1 Falling Edge/Low-Level Interrupt Selection 1 1 write-only P10 Falling Edge/Low-Level Interrupt Selection 10 1 write-only P11 Falling Edge/Low-Level Interrupt Selection 11 1 write-only P12 Falling Edge/Low-Level Interrupt Selection 12 1 write-only P13 Falling Edge/Low-Level Interrupt Selection 13 1 write-only P14 Falling Edge/Low-Level Interrupt Selection 14 1 write-only P15 Falling Edge/Low-Level Interrupt Selection 15 1 write-only P16 Falling Edge/Low-Level Interrupt Selection 16 1 write-only P17 Falling Edge/Low-Level Interrupt Selection 17 1 write-only P18 Falling Edge/Low-Level Interrupt Selection 18 1 write-only P19 Falling Edge/Low-Level Interrupt Selection 19 1 write-only P2 Falling Edge/Low-Level Interrupt Selection 2 1 write-only P20 Falling Edge/Low-Level Interrupt Selection 20 1 write-only P21 Falling Edge/Low-Level Interrupt Selection 21 1 write-only P22 Falling Edge/Low-Level Interrupt Selection 22 1 write-only P23 Falling Edge/Low-Level Interrupt Selection 23 1 write-only P24 Falling Edge/Low-Level Interrupt Selection 24 1 write-only P25 Falling Edge/Low-Level Interrupt Selection 25 1 write-only P26 Falling Edge/Low-Level Interrupt Selection 26 1 write-only P27 Falling Edge/Low-Level Interrupt Selection 27 1 write-only P28 Falling Edge/Low-Level Interrupt Selection 28 1 write-only P29 Falling Edge/Low-Level Interrupt Selection 29 1 write-only P3 Falling Edge/Low-Level Interrupt Selection 3 1 write-only P30 Falling Edge/Low-Level Interrupt Selection 30 1 write-only P31 Falling Edge/Low-Level Interrupt Selection 31 1 write-only P4 Falling Edge/Low-Level Interrupt Selection 4 1 write-only P5 Falling Edge/Low-Level Interrupt Selection 5 1 write-only P6 Falling Edge/Low-Level Interrupt Selection 6 1 write-only P7 Falling Edge/Low-Level Interrupt Selection 7 1 write-only P8 Falling Edge/Low-Level Interrupt Selection 8 1 write-only P9 Falling Edge/Low-Level Interrupt Selection 9 1 write-only FRLHSR Fall/Rise - Low/High Status Register 0xD8 32 read-only n 0x0 0x0 P0 Edge/Level Interrupt Source Selection 0 1 read-only P1 Edge/Level Interrupt Source Selection 1 1 read-only P10 Edge/Level Interrupt Source Selection 10 1 read-only P11 Edge/Level Interrupt Source Selection 11 1 read-only P12 Edge/Level Interrupt Source Selection 12 1 read-only P13 Edge/Level Interrupt Source Selection 13 1 read-only P14 Edge/Level Interrupt Source Selection 14 1 read-only P15 Edge/Level Interrupt Source Selection 15 1 read-only P16 Edge/Level Interrupt Source Selection 16 1 read-only P17 Edge/Level Interrupt Source Selection 17 1 read-only P18 Edge/Level Interrupt Source Selection 18 1 read-only P19 Edge/Level Interrupt Source Selection 19 1 read-only P2 Edge/Level Interrupt Source Selection 2 1 read-only P20 Edge/Level Interrupt Source Selection 20 1 read-only P21 Edge/Level Interrupt Source Selection 21 1 read-only P22 Edge/Level Interrupt Source Selection 22 1 read-only P23 Edge/Level Interrupt Source Selection 23 1 read-only P24 Edge/Level Interrupt Source Selection 24 1 read-only P25 Edge/Level Interrupt Source Selection 25 1 read-only P26 Edge/Level Interrupt Source Selection 26 1 read-only P27 Edge/Level Interrupt Source Selection 27 1 read-only P28 Edge/Level Interrupt Source Selection 28 1 read-only P29 Edge/Level Interrupt Source Selection 29 1 read-only P3 Edge/Level Interrupt Source Selection 3 1 read-only P30 Edge/Level Interrupt Source Selection 30 1 read-only P31 Edge/Level Interrupt Source Selection 31 1 read-only P4 Edge/Level Interrupt Source Selection 4 1 read-only P5 Edge/Level Interrupt Source Selection 5 1 read-only P6 Edge/Level Interrupt Source Selection 6 1 read-only P7 Edge/Level Interrupt Source Selection 7 1 read-only P8 Edge/Level Interrupt Source Selection 8 1 read-only P9 Edge/Level Interrupt Source Selection 9 1 read-only IDR Interrupt Disable Register 0x44 32 write-only n 0x0 0x0 P0 Input Change Interrupt Disable 0 1 write-only P1 Input Change Interrupt Disable 1 1 write-only P10 Input Change Interrupt Disable 10 1 write-only P11 Input Change Interrupt Disable 11 1 write-only P12 Input Change Interrupt Disable 12 1 write-only P13 Input Change Interrupt Disable 13 1 write-only P14 Input Change Interrupt Disable 14 1 write-only P15 Input Change Interrupt Disable 15 1 write-only P16 Input Change Interrupt Disable 16 1 write-only P17 Input Change Interrupt Disable 17 1 write-only P18 Input Change Interrupt Disable 18 1 write-only P19 Input Change Interrupt Disable 19 1 write-only P2 Input Change Interrupt Disable 2 1 write-only P20 Input Change Interrupt Disable 20 1 write-only P21 Input Change Interrupt Disable 21 1 write-only P22 Input Change Interrupt Disable 22 1 write-only P23 Input Change Interrupt Disable 23 1 write-only P24 Input Change Interrupt Disable 24 1 write-only P25 Input Change Interrupt Disable 25 1 write-only P26 Input Change Interrupt Disable 26 1 write-only P27 Input Change Interrupt Disable 27 1 write-only P28 Input Change Interrupt Disable 28 1 write-only P29 Input Change Interrupt Disable 29 1 write-only P3 Input Change Interrupt Disable 3 1 write-only P30 Input Change Interrupt Disable 30 1 write-only P31 Input Change Interrupt Disable 31 1 write-only P4 Input Change Interrupt Disable 4 1 write-only P5 Input Change Interrupt Disable 5 1 write-only P6 Input Change Interrupt Disable 6 1 write-only P7 Input Change Interrupt Disable 7 1 write-only P8 Input Change Interrupt Disable 8 1 write-only P9 Input Change Interrupt Disable 9 1 write-only IER Interrupt Enable Register 0x40 32 write-only n 0x0 0x0 P0 Input Change Interrupt Enable 0 1 write-only P1 Input Change Interrupt Enable 1 1 write-only P10 Input Change Interrupt Enable 10 1 write-only P11 Input Change Interrupt Enable 11 1 write-only P12 Input Change Interrupt Enable 12 1 write-only P13 Input Change Interrupt Enable 13 1 write-only P14 Input Change Interrupt Enable 14 1 write-only P15 Input Change Interrupt Enable 15 1 write-only P16 Input Change Interrupt Enable 16 1 write-only P17 Input Change Interrupt Enable 17 1 write-only P18 Input Change Interrupt Enable 18 1 write-only P19 Input Change Interrupt Enable 19 1 write-only P2 Input Change Interrupt Enable 2 1 write-only P20 Input Change Interrupt Enable 20 1 write-only P21 Input Change Interrupt Enable 21 1 write-only P22 Input Change Interrupt Enable 22 1 write-only P23 Input Change Interrupt Enable 23 1 write-only P24 Input Change Interrupt Enable 24 1 write-only P25 Input Change Interrupt Enable 25 1 write-only P26 Input Change Interrupt Enable 26 1 write-only P27 Input Change Interrupt Enable 27 1 write-only P28 Input Change Interrupt Enable 28 1 write-only P29 Input Change Interrupt Enable 29 1 write-only P3 Input Change Interrupt Enable 3 1 write-only P30 Input Change Interrupt Enable 30 1 write-only P31 Input Change Interrupt Enable 31 1 write-only P4 Input Change Interrupt Enable 4 1 write-only P5 Input Change Interrupt Enable 5 1 write-only P6 Input Change Interrupt Enable 6 1 write-only P7 Input Change Interrupt Enable 7 1 write-only P8 Input Change Interrupt Enable 8 1 write-only P9 Input Change Interrupt Enable 9 1 write-only IFDR Glitch Input Filter Disable Register 0x24 32 write-only n 0x0 0x0 P0 Input Filter Disable 0 1 write-only P1 Input Filter Disable 1 1 write-only P10 Input Filter Disable 10 1 write-only P11 Input Filter Disable 11 1 write-only P12 Input Filter Disable 12 1 write-only P13 Input Filter Disable 13 1 write-only P14 Input Filter Disable 14 1 write-only P15 Input Filter Disable 15 1 write-only P16 Input Filter Disable 16 1 write-only P17 Input Filter Disable 17 1 write-only P18 Input Filter Disable 18 1 write-only P19 Input Filter Disable 19 1 write-only P2 Input Filter Disable 2 1 write-only P20 Input Filter Disable 20 1 write-only P21 Input Filter Disable 21 1 write-only P22 Input Filter Disable 22 1 write-only P23 Input Filter Disable 23 1 write-only P24 Input Filter Disable 24 1 write-only P25 Input Filter Disable 25 1 write-only P26 Input Filter Disable 26 1 write-only P27 Input Filter Disable 27 1 write-only P28 Input Filter Disable 28 1 write-only P29 Input Filter Disable 29 1 write-only P3 Input Filter Disable 3 1 write-only P30 Input Filter Disable 30 1 write-only P31 Input Filter Disable 31 1 write-only P4 Input Filter Disable 4 1 write-only P5 Input Filter Disable 5 1 write-only P6 Input Filter Disable 6 1 write-only P7 Input Filter Disable 7 1 write-only P8 Input Filter Disable 8 1 write-only P9 Input Filter Disable 9 1 write-only IFER Glitch Input Filter Enable Register 0x20 32 write-only n 0x0 0x0 P0 Input Filter Enable 0 1 write-only P1 Input Filter Enable 1 1 write-only P10 Input Filter Enable 10 1 write-only P11 Input Filter Enable 11 1 write-only P12 Input Filter Enable 12 1 write-only P13 Input Filter Enable 13 1 write-only P14 Input Filter Enable 14 1 write-only P15 Input Filter Enable 15 1 write-only P16 Input Filter Enable 16 1 write-only P17 Input Filter Enable 17 1 write-only P18 Input Filter Enable 18 1 write-only P19 Input Filter Enable 19 1 write-only P2 Input Filter Enable 2 1 write-only P20 Input Filter Enable 20 1 write-only P21 Input Filter Enable 21 1 write-only P22 Input Filter Enable 22 1 write-only P23 Input Filter Enable 23 1 write-only P24 Input Filter Enable 24 1 write-only P25 Input Filter Enable 25 1 write-only P26 Input Filter Enable 26 1 write-only P27 Input Filter Enable 27 1 write-only P28 Input Filter Enable 28 1 write-only P29 Input Filter Enable 29 1 write-only P3 Input Filter Enable 3 1 write-only P30 Input Filter Enable 30 1 write-only P31 Input Filter Enable 31 1 write-only P4 Input Filter Enable 4 1 write-only P5 Input Filter Enable 5 1 write-only P6 Input Filter Enable 6 1 write-only P7 Input Filter Enable 7 1 write-only P8 Input Filter Enable 8 1 write-only P9 Input Filter Enable 9 1 write-only IFSCDR Input Filter Slow Clock Disable Register 0x80 32 write-only n 0x0 0x0 P0 Peripheral Clock Glitch Filtering Select 0 1 write-only P1 Peripheral Clock Glitch Filtering Select 1 1 write-only P10 Peripheral Clock Glitch Filtering Select 10 1 write-only P11 Peripheral Clock Glitch Filtering Select 11 1 write-only P12 Peripheral Clock Glitch Filtering Select 12 1 write-only P13 Peripheral Clock Glitch Filtering Select 13 1 write-only P14 Peripheral Clock Glitch Filtering Select 14 1 write-only P15 Peripheral Clock Glitch Filtering Select 15 1 write-only P16 Peripheral Clock Glitch Filtering Select 16 1 write-only P17 Peripheral Clock Glitch Filtering Select 17 1 write-only P18 Peripheral Clock Glitch Filtering Select 18 1 write-only P19 Peripheral Clock Glitch Filtering Select 19 1 write-only P2 Peripheral Clock Glitch Filtering Select 2 1 write-only P20 Peripheral Clock Glitch Filtering Select 20 1 write-only P21 Peripheral Clock Glitch Filtering Select 21 1 write-only P22 Peripheral Clock Glitch Filtering Select 22 1 write-only P23 Peripheral Clock Glitch Filtering Select 23 1 write-only P24 Peripheral Clock Glitch Filtering Select 24 1 write-only P25 Peripheral Clock Glitch Filtering Select 25 1 write-only P26 Peripheral Clock Glitch Filtering Select 26 1 write-only P27 Peripheral Clock Glitch Filtering Select 27 1 write-only P28 Peripheral Clock Glitch Filtering Select 28 1 write-only P29 Peripheral Clock Glitch Filtering Select 29 1 write-only P3 Peripheral Clock Glitch Filtering Select 3 1 write-only P30 Peripheral Clock Glitch Filtering Select 30 1 write-only P31 Peripheral Clock Glitch Filtering Select 31 1 write-only P4 Peripheral Clock Glitch Filtering Select 4 1 write-only P5 Peripheral Clock Glitch Filtering Select 5 1 write-only P6 Peripheral Clock Glitch Filtering Select 6 1 write-only P7 Peripheral Clock Glitch Filtering Select 7 1 write-only P8 Peripheral Clock Glitch Filtering Select 8 1 write-only P9 Peripheral Clock Glitch Filtering Select 9 1 write-only IFSCER Input Filter Slow Clock Enable Register 0x84 32 write-only n 0x0 0x0 P0 Slow Clock Debouncing Filtering Select 0 1 write-only P1 Slow Clock Debouncing Filtering Select 1 1 write-only P10 Slow Clock Debouncing Filtering Select 10 1 write-only P11 Slow Clock Debouncing Filtering Select 11 1 write-only P12 Slow Clock Debouncing Filtering Select 12 1 write-only P13 Slow Clock Debouncing Filtering Select 13 1 write-only P14 Slow Clock Debouncing Filtering Select 14 1 write-only P15 Slow Clock Debouncing Filtering Select 15 1 write-only P16 Slow Clock Debouncing Filtering Select 16 1 write-only P17 Slow Clock Debouncing Filtering Select 17 1 write-only P18 Slow Clock Debouncing Filtering Select 18 1 write-only P19 Slow Clock Debouncing Filtering Select 19 1 write-only P2 Slow Clock Debouncing Filtering Select 2 1 write-only P20 Slow Clock Debouncing Filtering Select 20 1 write-only P21 Slow Clock Debouncing Filtering Select 21 1 write-only P22 Slow Clock Debouncing Filtering Select 22 1 write-only P23 Slow Clock Debouncing Filtering Select 23 1 write-only P24 Slow Clock Debouncing Filtering Select 24 1 write-only P25 Slow Clock Debouncing Filtering Select 25 1 write-only P26 Slow Clock Debouncing Filtering Select 26 1 write-only P27 Slow Clock Debouncing Filtering Select 27 1 write-only P28 Slow Clock Debouncing Filtering Select 28 1 write-only P29 Slow Clock Debouncing Filtering Select 29 1 write-only P3 Slow Clock Debouncing Filtering Select 3 1 write-only P30 Slow Clock Debouncing Filtering Select 30 1 write-only P31 Slow Clock Debouncing Filtering Select 31 1 write-only P4 Slow Clock Debouncing Filtering Select 4 1 write-only P5 Slow Clock Debouncing Filtering Select 5 1 write-only P6 Slow Clock Debouncing Filtering Select 6 1 write-only P7 Slow Clock Debouncing Filtering Select 7 1 write-only P8 Slow Clock Debouncing Filtering Select 8 1 write-only P9 Slow Clock Debouncing Filtering Select 9 1 write-only IFSCSR Input Filter Slow Clock Status Register 0x88 32 read-only n 0x0 0x0 P0 Glitch or Debouncing Filter Selection Status 0 1 read-only P1 Glitch or Debouncing Filter Selection Status 1 1 read-only P10 Glitch or Debouncing Filter Selection Status 10 1 read-only P11 Glitch or Debouncing Filter Selection Status 11 1 read-only P12 Glitch or Debouncing Filter Selection Status 12 1 read-only P13 Glitch or Debouncing Filter Selection Status 13 1 read-only P14 Glitch or Debouncing Filter Selection Status 14 1 read-only P15 Glitch or Debouncing Filter Selection Status 15 1 read-only P16 Glitch or Debouncing Filter Selection Status 16 1 read-only P17 Glitch or Debouncing Filter Selection Status 17 1 read-only P18 Glitch or Debouncing Filter Selection Status 18 1 read-only P19 Glitch or Debouncing Filter Selection Status 19 1 read-only P2 Glitch or Debouncing Filter Selection Status 2 1 read-only P20 Glitch or Debouncing Filter Selection Status 20 1 read-only P21 Glitch or Debouncing Filter Selection Status 21 1 read-only P22 Glitch or Debouncing Filter Selection Status 22 1 read-only P23 Glitch or Debouncing Filter Selection Status 23 1 read-only P24 Glitch or Debouncing Filter Selection Status 24 1 read-only P25 Glitch or Debouncing Filter Selection Status 25 1 read-only P26 Glitch or Debouncing Filter Selection Status 26 1 read-only P27 Glitch or Debouncing Filter Selection Status 27 1 read-only P28 Glitch or Debouncing Filter Selection Status 28 1 read-only P29 Glitch or Debouncing Filter Selection Status 29 1 read-only P3 Glitch or Debouncing Filter Selection Status 3 1 read-only P30 Glitch or Debouncing Filter Selection Status 30 1 read-only P31 Glitch or Debouncing Filter Selection Status 31 1 read-only P4 Glitch or Debouncing Filter Selection Status 4 1 read-only P5 Glitch or Debouncing Filter Selection Status 5 1 read-only P6 Glitch or Debouncing Filter Selection Status 6 1 read-only P7 Glitch or Debouncing Filter Selection Status 7 1 read-only P8 Glitch or Debouncing Filter Selection Status 8 1 read-only P9 Glitch or Debouncing Filter Selection Status 9 1 read-only IFSR Glitch Input Filter Status Register 0x28 32 read-only n 0x0 0x0 P0 Input Filter Status 0 1 read-only P1 Input Filter Status 1 1 read-only P10 Input Filter Status 10 1 read-only P11 Input Filter Status 11 1 read-only P12 Input Filter Status 12 1 read-only P13 Input Filter Status 13 1 read-only P14 Input Filter Status 14 1 read-only P15 Input Filter Status 15 1 read-only P16 Input Filter Status 16 1 read-only P17 Input Filter Status 17 1 read-only P18 Input Filter Status 18 1 read-only P19 Input Filter Status 19 1 read-only P2 Input Filter Status 2 1 read-only P20 Input Filter Status 20 1 read-only P21 Input Filter Status 21 1 read-only P22 Input Filter Status 22 1 read-only P23 Input Filter Status 23 1 read-only P24 Input Filter Status 24 1 read-only P25 Input Filter Status 25 1 read-only P26 Input Filter Status 26 1 read-only P27 Input Filter Status 27 1 read-only P28 Input Filter Status 28 1 read-only P29 Input Filter Status 29 1 read-only P3 Input Filter Status 3 1 read-only P30 Input Filter Status 30 1 read-only P31 Input Filter Status 31 1 read-only P4 Input Filter Status 4 1 read-only P5 Input Filter Status 5 1 read-only P6 Input Filter Status 6 1 read-only P7 Input Filter Status 7 1 read-only P8 Input Filter Status 8 1 read-only P9 Input Filter Status 9 1 read-only IMR Interrupt Mask Register 0x48 32 read-only n 0x0 0x0 P0 Input Change Interrupt Mask 0 1 read-only P1 Input Change Interrupt Mask 1 1 read-only P10 Input Change Interrupt Mask 10 1 read-only P11 Input Change Interrupt Mask 11 1 read-only P12 Input Change Interrupt Mask 12 1 read-only P13 Input Change Interrupt Mask 13 1 read-only P14 Input Change Interrupt Mask 14 1 read-only P15 Input Change Interrupt Mask 15 1 read-only P16 Input Change Interrupt Mask 16 1 read-only P17 Input Change Interrupt Mask 17 1 read-only P18 Input Change Interrupt Mask 18 1 read-only P19 Input Change Interrupt Mask 19 1 read-only P2 Input Change Interrupt Mask 2 1 read-only P20 Input Change Interrupt Mask 20 1 read-only P21 Input Change Interrupt Mask 21 1 read-only P22 Input Change Interrupt Mask 22 1 read-only P23 Input Change Interrupt Mask 23 1 read-only P24 Input Change Interrupt Mask 24 1 read-only P25 Input Change Interrupt Mask 25 1 read-only P26 Input Change Interrupt Mask 26 1 read-only P27 Input Change Interrupt Mask 27 1 read-only P28 Input Change Interrupt Mask 28 1 read-only P29 Input Change Interrupt Mask 29 1 read-only P3 Input Change Interrupt Mask 3 1 read-only P30 Input Change Interrupt Mask 30 1 read-only P31 Input Change Interrupt Mask 31 1 read-only P4 Input Change Interrupt Mask 4 1 read-only P5 Input Change Interrupt Mask 5 1 read-only P6 Input Change Interrupt Mask 6 1 read-only P7 Input Change Interrupt Mask 7 1 read-only P8 Input Change Interrupt Mask 8 1 read-only P9 Input Change Interrupt Mask 9 1 read-only ISLR PIO Interrupt Security Level Register 0xC 32 read-write n 0x0 0x0 P0 PIO Interrupt Security Level 0 1 read-write P1 PIO Interrupt Security Level 1 1 read-write P10 PIO Interrupt Security Level 10 1 read-write P11 PIO Interrupt Security Level 11 1 read-write P12 PIO Interrupt Security Level 12 1 read-write P13 PIO Interrupt Security Level 13 1 read-write P14 PIO Interrupt Security Level 14 1 read-write P15 PIO Interrupt Security Level 15 1 read-write P16 PIO Interrupt Security Level 16 1 read-write P17 PIO Interrupt Security Level 17 1 read-write P18 PIO Interrupt Security Level 18 1 read-write P19 PIO Interrupt Security Level 19 1 read-write P2 PIO Interrupt Security Level 2 1 read-write P20 PIO Interrupt Security Level 20 1 read-write P21 PIO Interrupt Security Level 21 1 read-write P22 PIO Interrupt Security Level 22 1 read-write P23 PIO Interrupt Security Level 23 1 read-write P24 PIO Interrupt Security Level 24 1 read-write P25 PIO Interrupt Security Level 25 1 read-write P26 PIO Interrupt Security Level 26 1 read-write P27 PIO Interrupt Security Level 27 1 read-write P28 PIO Interrupt Security Level 28 1 read-write P29 PIO Interrupt Security Level 29 1 read-write P3 PIO Interrupt Security Level 3 1 read-write P30 PIO Interrupt Security Level 30 1 read-write P31 PIO Interrupt Security Level 31 1 read-write P4 PIO Interrupt Security Level 4 1 read-write P5 PIO Interrupt Security Level 5 1 read-write P6 PIO Interrupt Security Level 6 1 read-write P7 PIO Interrupt Security Level 7 1 read-write P8 PIO Interrupt Security Level 8 1 read-write P9 PIO Interrupt Security Level 9 1 read-write ISR Interrupt Status Register 0x4C 32 read-only n 0x0 0x0 P0 Input Change Interrupt Status 0 1 read-only P1 Input Change Interrupt Status 1 1 read-only P10 Input Change Interrupt Status 10 1 read-only P11 Input Change Interrupt Status 11 1 read-only P12 Input Change Interrupt Status 12 1 read-only P13 Input Change Interrupt Status 13 1 read-only P14 Input Change Interrupt Status 14 1 read-only P15 Input Change Interrupt Status 15 1 read-only P16 Input Change Interrupt Status 16 1 read-only P17 Input Change Interrupt Status 17 1 read-only P18 Input Change Interrupt Status 18 1 read-only P19 Input Change Interrupt Status 19 1 read-only P2 Input Change Interrupt Status 2 1 read-only P20 Input Change Interrupt Status 20 1 read-only P21 Input Change Interrupt Status 21 1 read-only P22 Input Change Interrupt Status 22 1 read-only P23 Input Change Interrupt Status 23 1 read-only P24 Input Change Interrupt Status 24 1 read-only P25 Input Change Interrupt Status 25 1 read-only P26 Input Change Interrupt Status 26 1 read-only P27 Input Change Interrupt Status 27 1 read-only P28 Input Change Interrupt Status 28 1 read-only P29 Input Change Interrupt Status 29 1 read-only P3 Input Change Interrupt Status 3 1 read-only P30 Input Change Interrupt Status 30 1 read-only P31 Input Change Interrupt Status 31 1 read-only P4 Input Change Interrupt Status 4 1 read-only P5 Input Change Interrupt Status 5 1 read-only P6 Input Change Interrupt Status 6 1 read-only P7 Input Change Interrupt Status 7 1 read-only P8 Input Change Interrupt Status 8 1 read-only P9 Input Change Interrupt Status 9 1 read-only LSR Level Select Register 0xC4 32 write-only n 0x0 0x0 P0 Level Interrupt Selection 0 1 write-only P1 Level Interrupt Selection 1 1 write-only P10 Level Interrupt Selection 10 1 write-only P11 Level Interrupt Selection 11 1 write-only P12 Level Interrupt Selection 12 1 write-only P13 Level Interrupt Selection 13 1 write-only P14 Level Interrupt Selection 14 1 write-only P15 Level Interrupt Selection 15 1 write-only P16 Level Interrupt Selection 16 1 write-only P17 Level Interrupt Selection 17 1 write-only P18 Level Interrupt Selection 18 1 write-only P19 Level Interrupt Selection 19 1 write-only P2 Level Interrupt Selection 2 1 write-only P20 Level Interrupt Selection 20 1 write-only P21 Level Interrupt Selection 21 1 write-only P22 Level Interrupt Selection 22 1 write-only P23 Level Interrupt Selection 23 1 write-only P24 Level Interrupt Selection 24 1 write-only P25 Level Interrupt Selection 25 1 write-only P26 Level Interrupt Selection 26 1 write-only P27 Level Interrupt Selection 27 1 write-only P28 Level Interrupt Selection 28 1 write-only P29 Level Interrupt Selection 29 1 write-only P3 Level Interrupt Selection 3 1 write-only P30 Level Interrupt Selection 30 1 write-only P31 Level Interrupt Selection 31 1 write-only P4 Level Interrupt Selection 4 1 write-only P5 Level Interrupt Selection 5 1 write-only P6 Level Interrupt Selection 6 1 write-only P7 Level Interrupt Selection 7 1 write-only P8 Level Interrupt Selection 8 1 write-only P9 Level Interrupt Selection 9 1 write-only MDDR Multi-driver Disable Register 0x54 32 write-only n 0x0 0x0 P0 Multi-drive Disable 0 1 write-only P1 Multi-drive Disable 1 1 write-only P10 Multi-drive Disable 10 1 write-only P11 Multi-drive Disable 11 1 write-only P12 Multi-drive Disable 12 1 write-only P13 Multi-drive Disable 13 1 write-only P14 Multi-drive Disable 14 1 write-only P15 Multi-drive Disable 15 1 write-only P16 Multi-drive Disable 16 1 write-only P17 Multi-drive Disable 17 1 write-only P18 Multi-drive Disable 18 1 write-only P19 Multi-drive Disable 19 1 write-only P2 Multi-drive Disable 2 1 write-only P20 Multi-drive Disable 20 1 write-only P21 Multi-drive Disable 21 1 write-only P22 Multi-drive Disable 22 1 write-only P23 Multi-drive Disable 23 1 write-only P24 Multi-drive Disable 24 1 write-only P25 Multi-drive Disable 25 1 write-only P26 Multi-drive Disable 26 1 write-only P27 Multi-drive Disable 27 1 write-only P28 Multi-drive Disable 28 1 write-only P29 Multi-drive Disable 29 1 write-only P3 Multi-drive Disable 3 1 write-only P30 Multi-drive Disable 30 1 write-only P31 Multi-drive Disable 31 1 write-only P4 Multi-drive Disable 4 1 write-only P5 Multi-drive Disable 5 1 write-only P6 Multi-drive Disable 6 1 write-only P7 Multi-drive Disable 7 1 write-only P8 Multi-drive Disable 8 1 write-only P9 Multi-drive Disable 9 1 write-only MDER Multi-driver Enable Register 0x50 32 write-only n 0x0 0x0 P0 Multi-drive Enable 0 1 write-only P1 Multi-drive Enable 1 1 write-only P10 Multi-drive Enable 10 1 write-only P11 Multi-drive Enable 11 1 write-only P12 Multi-drive Enable 12 1 write-only P13 Multi-drive Enable 13 1 write-only P14 Multi-drive Enable 14 1 write-only P15 Multi-drive Enable 15 1 write-only P16 Multi-drive Enable 16 1 write-only P17 Multi-drive Enable 17 1 write-only P18 Multi-drive Enable 18 1 write-only P19 Multi-drive Enable 19 1 write-only P2 Multi-drive Enable 2 1 write-only P20 Multi-drive Enable 20 1 write-only P21 Multi-drive Enable 21 1 write-only P22 Multi-drive Enable 22 1 write-only P23 Multi-drive Enable 23 1 write-only P24 Multi-drive Enable 24 1 write-only P25 Multi-drive Enable 25 1 write-only P26 Multi-drive Enable 26 1 write-only P27 Multi-drive Enable 27 1 write-only P28 Multi-drive Enable 28 1 write-only P29 Multi-drive Enable 29 1 write-only P3 Multi-drive Enable 3 1 write-only P30 Multi-drive Enable 30 1 write-only P31 Multi-drive Enable 31 1 write-only P4 Multi-drive Enable 4 1 write-only P5 Multi-drive Enable 5 1 write-only P6 Multi-drive Enable 6 1 write-only P7 Multi-drive Enable 7 1 write-only P8 Multi-drive Enable 8 1 write-only P9 Multi-drive Enable 9 1 write-only MDSR Multi-driver Status Register 0x58 32 read-only n 0x0 0x0 P0 Multi-drive Status 0 1 read-only P1 Multi-drive Status 1 1 read-only P10 Multi-drive Status 10 1 read-only P11 Multi-drive Status 11 1 read-only P12 Multi-drive Status 12 1 read-only P13 Multi-drive Status 13 1 read-only P14 Multi-drive Status 14 1 read-only P15 Multi-drive Status 15 1 read-only P16 Multi-drive Status 16 1 read-only P17 Multi-drive Status 17 1 read-only P18 Multi-drive Status 18 1 read-only P19 Multi-drive Status 19 1 read-only P2 Multi-drive Status 2 1 read-only P20 Multi-drive Status 20 1 read-only P21 Multi-drive Status 21 1 read-only P22 Multi-drive Status 22 1 read-only P23 Multi-drive Status 23 1 read-only P24 Multi-drive Status 24 1 read-only P25 Multi-drive Status 25 1 read-only P26 Multi-drive Status 26 1 read-only P27 Multi-drive Status 27 1 read-only P28 Multi-drive Status 28 1 read-only P29 Multi-drive Status 29 1 read-only P3 Multi-drive Status 3 1 read-only P30 Multi-drive Status 30 1 read-only P31 Multi-drive Status 31 1 read-only P4 Multi-drive Status 4 1 read-only P5 Multi-drive Status 5 1 read-only P6 Multi-drive Status 6 1 read-only P7 Multi-drive Status 7 1 read-only P8 Multi-drive Status 8 1 read-only P9 Multi-drive Status 9 1 read-only ODR Output Disable Register 0x14 32 write-only n 0x0 0x0 P0 Output Disable 0 1 write-only P1 Output Disable 1 1 write-only P10 Output Disable 10 1 write-only P11 Output Disable 11 1 write-only P12 Output Disable 12 1 write-only P13 Output Disable 13 1 write-only P14 Output Disable 14 1 write-only P15 Output Disable 15 1 write-only P16 Output Disable 16 1 write-only P17 Output Disable 17 1 write-only P18 Output Disable 18 1 write-only P19 Output Disable 19 1 write-only P2 Output Disable 2 1 write-only P20 Output Disable 20 1 write-only P21 Output Disable 21 1 write-only P22 Output Disable 22 1 write-only P23 Output Disable 23 1 write-only P24 Output Disable 24 1 write-only P25 Output Disable 25 1 write-only P26 Output Disable 26 1 write-only P27 Output Disable 27 1 write-only P28 Output Disable 28 1 write-only P29 Output Disable 29 1 write-only P3 Output Disable 3 1 write-only P30 Output Disable 30 1 write-only P31 Output Disable 31 1 write-only P4 Output Disable 4 1 write-only P5 Output Disable 5 1 write-only P6 Output Disable 6 1 write-only P7 Output Disable 7 1 write-only P8 Output Disable 8 1 write-only P9 Output Disable 9 1 write-only ODSR Output Data Status Register 0x38 32 read-write n 0x0 0x0 P0 Output Data Status 0 1 read-write P1 Output Data Status 1 1 read-write P10 Output Data Status 10 1 read-write P11 Output Data Status 11 1 read-write P12 Output Data Status 12 1 read-write P13 Output Data Status 13 1 read-write P14 Output Data Status 14 1 read-write P15 Output Data Status 15 1 read-write P16 Output Data Status 16 1 read-write P17 Output Data Status 17 1 read-write P18 Output Data Status 18 1 read-write P19 Output Data Status 19 1 read-write P2 Output Data Status 2 1 read-write P20 Output Data Status 20 1 read-write P21 Output Data Status 21 1 read-write P22 Output Data Status 22 1 read-write P23 Output Data Status 23 1 read-write P24 Output Data Status 24 1 read-write P25 Output Data Status 25 1 read-write P26 Output Data Status 26 1 read-write P27 Output Data Status 27 1 read-write P28 Output Data Status 28 1 read-write P29 Output Data Status 29 1 read-write P3 Output Data Status 3 1 read-write P30 Output Data Status 30 1 read-write P31 Output Data Status 31 1 read-write P4 Output Data Status 4 1 read-write P5 Output Data Status 5 1 read-write P6 Output Data Status 6 1 read-write P7 Output Data Status 7 1 read-write P8 Output Data Status 8 1 read-write P9 Output Data Status 9 1 read-write OER Output Enable Register 0x10 32 write-only n 0x0 0x0 P0 Output Enable 0 1 write-only P1 Output Enable 1 1 write-only P10 Output Enable 10 1 write-only P11 Output Enable 11 1 write-only P12 Output Enable 12 1 write-only P13 Output Enable 13 1 write-only P14 Output Enable 14 1 write-only P15 Output Enable 15 1 write-only P16 Output Enable 16 1 write-only P17 Output Enable 17 1 write-only P18 Output Enable 18 1 write-only P19 Output Enable 19 1 write-only P2 Output Enable 2 1 write-only P20 Output Enable 20 1 write-only P21 Output Enable 21 1 write-only P22 Output Enable 22 1 write-only P23 Output Enable 23 1 write-only P24 Output Enable 24 1 write-only P25 Output Enable 25 1 write-only P26 Output Enable 26 1 write-only P27 Output Enable 27 1 write-only P28 Output Enable 28 1 write-only P29 Output Enable 29 1 write-only P3 Output Enable 3 1 write-only P30 Output Enable 30 1 write-only P31 Output Enable 31 1 write-only P4 Output Enable 4 1 write-only P5 Output Enable 5 1 write-only P6 Output Enable 6 1 write-only P7 Output Enable 7 1 write-only P8 Output Enable 8 1 write-only P9 Output Enable 9 1 write-only OSR Output Status Register 0x18 32 read-only n 0x0 0x0 P0 Output Status 0 1 read-only P1 Output Status 1 1 read-only P10 Output Status 10 1 read-only P11 Output Status 11 1 read-only P12 Output Status 12 1 read-only P13 Output Status 13 1 read-only P14 Output Status 14 1 read-only P15 Output Status 15 1 read-only P16 Output Status 16 1 read-only P17 Output Status 17 1 read-only P18 Output Status 18 1 read-only P19 Output Status 19 1 read-only P2 Output Status 2 1 read-only P20 Output Status 20 1 read-only P21 Output Status 21 1 read-only P22 Output Status 22 1 read-only P23 Output Status 23 1 read-only P24 Output Status 24 1 read-only P25 Output Status 25 1 read-only P26 Output Status 26 1 read-only P27 Output Status 27 1 read-only P28 Output Status 28 1 read-only P29 Output Status 29 1 read-only P3 Output Status 3 1 read-only P30 Output Status 30 1 read-only P31 Output Status 31 1 read-only P4 Output Status 4 1 read-only P5 Output Status 5 1 read-only P6 Output Status 6 1 read-only P7 Output Status 7 1 read-only P8 Output Status 8 1 read-only P9 Output Status 9 1 read-only OWDR Output Write Disable 0xA4 32 write-only n 0x0 0x0 P0 Output Write Disable 0 1 write-only P1 Output Write Disable 1 1 write-only P10 Output Write Disable 10 1 write-only P11 Output Write Disable 11 1 write-only P12 Output Write Disable 12 1 write-only P13 Output Write Disable 13 1 write-only P14 Output Write Disable 14 1 write-only P15 Output Write Disable 15 1 write-only P16 Output Write Disable 16 1 write-only P17 Output Write Disable 17 1 write-only P18 Output Write Disable 18 1 write-only P19 Output Write Disable 19 1 write-only P2 Output Write Disable 2 1 write-only P20 Output Write Disable 20 1 write-only P21 Output Write Disable 21 1 write-only P22 Output Write Disable 22 1 write-only P23 Output Write Disable 23 1 write-only P24 Output Write Disable 24 1 write-only P25 Output Write Disable 25 1 write-only P26 Output Write Disable 26 1 write-only P27 Output Write Disable 27 1 write-only P28 Output Write Disable 28 1 write-only P29 Output Write Disable 29 1 write-only P3 Output Write Disable 3 1 write-only P30 Output Write Disable 30 1 write-only P31 Output Write Disable 31 1 write-only P4 Output Write Disable 4 1 write-only P5 Output Write Disable 5 1 write-only P6 Output Write Disable 6 1 write-only P7 Output Write Disable 7 1 write-only P8 Output Write Disable 8 1 write-only P9 Output Write Disable 9 1 write-only OWER Output Write Enable 0xA0 32 write-only n 0x0 0x0 P0 Output Write Enable 0 1 write-only P1 Output Write Enable 1 1 write-only P10 Output Write Enable 10 1 write-only P11 Output Write Enable 11 1 write-only P12 Output Write Enable 12 1 write-only P13 Output Write Enable 13 1 write-only P14 Output Write Enable 14 1 write-only P15 Output Write Enable 15 1 write-only P16 Output Write Enable 16 1 write-only P17 Output Write Enable 17 1 write-only P18 Output Write Enable 18 1 write-only P19 Output Write Enable 19 1 write-only P2 Output Write Enable 2 1 write-only P20 Output Write Enable 20 1 write-only P21 Output Write Enable 21 1 write-only P22 Output Write Enable 22 1 write-only P23 Output Write Enable 23 1 write-only P24 Output Write Enable 24 1 write-only P25 Output Write Enable 25 1 write-only P26 Output Write Enable 26 1 write-only P27 Output Write Enable 27 1 write-only P28 Output Write Enable 28 1 write-only P29 Output Write Enable 29 1 write-only P3 Output Write Enable 3 1 write-only P30 Output Write Enable 30 1 write-only P31 Output Write Enable 31 1 write-only P4 Output Write Enable 4 1 write-only P5 Output Write Enable 5 1 write-only P6 Output Write Enable 6 1 write-only P7 Output Write Enable 7 1 write-only P8 Output Write Enable 8 1 write-only P9 Output Write Enable 9 1 write-only OWSR Output Write Status Register 0xA8 32 read-only n 0x0 0x0 P0 Output Write Status 0 1 read-only P1 Output Write Status 1 1 read-only P10 Output Write Status 10 1 read-only P11 Output Write Status 11 1 read-only P12 Output Write Status 12 1 read-only P13 Output Write Status 13 1 read-only P14 Output Write Status 14 1 read-only P15 Output Write Status 15 1 read-only P16 Output Write Status 16 1 read-only P17 Output Write Status 17 1 read-only P18 Output Write Status 18 1 read-only P19 Output Write Status 19 1 read-only P2 Output Write Status 2 1 read-only P20 Output Write Status 20 1 read-only P21 Output Write Status 21 1 read-only P22 Output Write Status 22 1 read-only P23 Output Write Status 23 1 read-only P24 Output Write Status 24 1 read-only P25 Output Write Status 25 1 read-only P26 Output Write Status 26 1 read-only P27 Output Write Status 27 1 read-only P28 Output Write Status 28 1 read-only P29 Output Write Status 29 1 read-only P3 Output Write Status 3 1 read-only P30 Output Write Status 30 1 read-only P31 Output Write Status 31 1 read-only P4 Output Write Status 4 1 read-only P5 Output Write Status 5 1 read-only P6 Output Write Status 6 1 read-only P7 Output Write Status 7 1 read-only P8 Output Write Status 8 1 read-only P9 Output Write Status 9 1 read-only PDR PIO Disable Register 0x4 32 write-only n 0x0 0x0 P0 PIO Disable 0 1 write-only P1 PIO Disable 1 1 write-only P10 PIO Disable 10 1 write-only P11 PIO Disable 11 1 write-only P12 PIO Disable 12 1 write-only P13 PIO Disable 13 1 write-only P14 PIO Disable 14 1 write-only P15 PIO Disable 15 1 write-only P16 PIO Disable 16 1 write-only P17 PIO Disable 17 1 write-only P18 PIO Disable 18 1 write-only P19 PIO Disable 19 1 write-only P2 PIO Disable 2 1 write-only P20 PIO Disable 20 1 write-only P21 PIO Disable 21 1 write-only P22 PIO Disable 22 1 write-only P23 PIO Disable 23 1 write-only P24 PIO Disable 24 1 write-only P25 PIO Disable 25 1 write-only P26 PIO Disable 26 1 write-only P27 PIO Disable 27 1 write-only P28 PIO Disable 28 1 write-only P29 PIO Disable 29 1 write-only P3 PIO Disable 3 1 write-only P30 PIO Disable 30 1 write-only P31 PIO Disable 31 1 write-only P4 PIO Disable 4 1 write-only P5 PIO Disable 5 1 write-only P6 PIO Disable 6 1 write-only P7 PIO Disable 7 1 write-only P8 PIO Disable 8 1 write-only P9 PIO Disable 9 1 write-only PDSR Pin Data Status Register 0x3C 32 read-only n 0x0 0x0 P0 Output Data Status 0 1 read-only P1 Output Data Status 1 1 read-only P10 Output Data Status 10 1 read-only P11 Output Data Status 11 1 read-only P12 Output Data Status 12 1 read-only P13 Output Data Status 13 1 read-only P14 Output Data Status 14 1 read-only P15 Output Data Status 15 1 read-only P16 Output Data Status 16 1 read-only P17 Output Data Status 17 1 read-only P18 Output Data Status 18 1 read-only P19 Output Data Status 19 1 read-only P2 Output Data Status 2 1 read-only P20 Output Data Status 20 1 read-only P21 Output Data Status 21 1 read-only P22 Output Data Status 22 1 read-only P23 Output Data Status 23 1 read-only P24 Output Data Status 24 1 read-only P25 Output Data Status 25 1 read-only P26 Output Data Status 26 1 read-only P27 Output Data Status 27 1 read-only P28 Output Data Status 28 1 read-only P29 Output Data Status 29 1 read-only P3 Output Data Status 3 1 read-only P30 Output Data Status 30 1 read-only P31 Output Data Status 31 1 read-only P4 Output Data Status 4 1 read-only P5 Output Data Status 5 1 read-only P6 Output Data Status 6 1 read-only P7 Output Data Status 7 1 read-only P8 Output Data Status 8 1 read-only P9 Output Data Status 9 1 read-only PER PIO Enable Register 0x0 32 write-only n 0x0 0x0 P0 PIO Enable 0 1 write-only P1 PIO Enable 1 1 write-only P10 PIO Enable 10 1 write-only P11 PIO Enable 11 1 write-only P12 PIO Enable 12 1 write-only P13 PIO Enable 13 1 write-only P14 PIO Enable 14 1 write-only P15 PIO Enable 15 1 write-only P16 PIO Enable 16 1 write-only P17 PIO Enable 17 1 write-only P18 PIO Enable 18 1 write-only P19 PIO Enable 19 1 write-only P2 PIO Enable 2 1 write-only P20 PIO Enable 20 1 write-only P21 PIO Enable 21 1 write-only P22 PIO Enable 22 1 write-only P23 PIO Enable 23 1 write-only P24 PIO Enable 24 1 write-only P25 PIO Enable 25 1 write-only P26 PIO Enable 26 1 write-only P27 PIO Enable 27 1 write-only P28 PIO Enable 28 1 write-only P29 PIO Enable 29 1 write-only P3 PIO Enable 3 1 write-only P30 PIO Enable 30 1 write-only P31 PIO Enable 31 1 write-only P4 PIO Enable 4 1 write-only P5 PIO Enable 5 1 write-only P6 PIO Enable 6 1 write-only P7 PIO Enable 7 1 write-only P8 PIO Enable 8 1 write-only P9 PIO Enable 9 1 write-only PPDDR Pad Pull-Down Disable Register 0x90 32 write-only n 0x0 0x0 P0 Pull-Down Disable 0 1 write-only P1 Pull-Down Disable 1 1 write-only P10 Pull-Down Disable 10 1 write-only P11 Pull-Down Disable 11 1 write-only P12 Pull-Down Disable 12 1 write-only P13 Pull-Down Disable 13 1 write-only P14 Pull-Down Disable 14 1 write-only P15 Pull-Down Disable 15 1 write-only P16 Pull-Down Disable 16 1 write-only P17 Pull-Down Disable 17 1 write-only P18 Pull-Down Disable 18 1 write-only P19 Pull-Down Disable 19 1 write-only P2 Pull-Down Disable 2 1 write-only P20 Pull-Down Disable 20 1 write-only P21 Pull-Down Disable 21 1 write-only P22 Pull-Down Disable 22 1 write-only P23 Pull-Down Disable 23 1 write-only P24 Pull-Down Disable 24 1 write-only P25 Pull-Down Disable 25 1 write-only P26 Pull-Down Disable 26 1 write-only P27 Pull-Down Disable 27 1 write-only P28 Pull-Down Disable 28 1 write-only P29 Pull-Down Disable 29 1 write-only P3 Pull-Down Disable 3 1 write-only P30 Pull-Down Disable 30 1 write-only P31 Pull-Down Disable 31 1 write-only P4 Pull-Down Disable 4 1 write-only P5 Pull-Down Disable 5 1 write-only P6 Pull-Down Disable 6 1 write-only P7 Pull-Down Disable 7 1 write-only P8 Pull-Down Disable 8 1 write-only P9 Pull-Down Disable 9 1 write-only PPDER Pad Pull-Down Enable Register 0x94 32 write-only n 0x0 0x0 P0 Pull-Down Enable 0 1 write-only P1 Pull-Down Enable 1 1 write-only P10 Pull-Down Enable 10 1 write-only P11 Pull-Down Enable 11 1 write-only P12 Pull-Down Enable 12 1 write-only P13 Pull-Down Enable 13 1 write-only P14 Pull-Down Enable 14 1 write-only P15 Pull-Down Enable 15 1 write-only P16 Pull-Down Enable 16 1 write-only P17 Pull-Down Enable 17 1 write-only P18 Pull-Down Enable 18 1 write-only P19 Pull-Down Enable 19 1 write-only P2 Pull-Down Enable 2 1 write-only P20 Pull-Down Enable 20 1 write-only P21 Pull-Down Enable 21 1 write-only P22 Pull-Down Enable 22 1 write-only P23 Pull-Down Enable 23 1 write-only P24 Pull-Down Enable 24 1 write-only P25 Pull-Down Enable 25 1 write-only P26 Pull-Down Enable 26 1 write-only P27 Pull-Down Enable 27 1 write-only P28 Pull-Down Enable 28 1 write-only P29 Pull-Down Enable 29 1 write-only P3 Pull-Down Enable 3 1 write-only P30 Pull-Down Enable 30 1 write-only P31 Pull-Down Enable 31 1 write-only P4 Pull-Down Enable 4 1 write-only P5 Pull-Down Enable 5 1 write-only P6 Pull-Down Enable 6 1 write-only P7 Pull-Down Enable 7 1 write-only P8 Pull-Down Enable 8 1 write-only P9 Pull-Down Enable 9 1 write-only PPDSR Pad Pull-Down Status Register 0x98 32 read-only n 0x0 0x0 P0 Pull-Down Status 0 1 read-only P1 Pull-Down Status 1 1 read-only P10 Pull-Down Status 10 1 read-only P11 Pull-Down Status 11 1 read-only P12 Pull-Down Status 12 1 read-only P13 Pull-Down Status 13 1 read-only P14 Pull-Down Status 14 1 read-only P15 Pull-Down Status 15 1 read-only P16 Pull-Down Status 16 1 read-only P17 Pull-Down Status 17 1 read-only P18 Pull-Down Status 18 1 read-only P19 Pull-Down Status 19 1 read-only P2 Pull-Down Status 2 1 read-only P20 Pull-Down Status 20 1 read-only P21 Pull-Down Status 21 1 read-only P22 Pull-Down Status 22 1 read-only P23 Pull-Down Status 23 1 read-only P24 Pull-Down Status 24 1 read-only P25 Pull-Down Status 25 1 read-only P26 Pull-Down Status 26 1 read-only P27 Pull-Down Status 27 1 read-only P28 Pull-Down Status 28 1 read-only P29 Pull-Down Status 29 1 read-only P3 Pull-Down Status 3 1 read-only P30 Pull-Down Status 30 1 read-only P31 Pull-Down Status 31 1 read-only P4 Pull-Down Status 4 1 read-only P5 Pull-Down Status 5 1 read-only P6 Pull-Down Status 6 1 read-only P7 Pull-Down Status 7 1 read-only P8 Pull-Down Status 8 1 read-only P9 Pull-Down Status 9 1 read-only PSR PIO Status Register 0x8 32 read-only n 0x0 0x0 P0 PIO Status 0 1 read-only P1 PIO Status 1 1 read-only P10 PIO Status 10 1 read-only P11 PIO Status 11 1 read-only P12 PIO Status 12 1 read-only P13 PIO Status 13 1 read-only P14 PIO Status 14 1 read-only P15 PIO Status 15 1 read-only P16 PIO Status 16 1 read-only P17 PIO Status 17 1 read-only P18 PIO Status 18 1 read-only P19 PIO Status 19 1 read-only P2 PIO Status 2 1 read-only P20 PIO Status 20 1 read-only P21 PIO Status 21 1 read-only P22 PIO Status 22 1 read-only P23 PIO Status 23 1 read-only P24 PIO Status 24 1 read-only P25 PIO Status 25 1 read-only P26 PIO Status 26 1 read-only P27 PIO Status 27 1 read-only P28 PIO Status 28 1 read-only P29 PIO Status 29 1 read-only P3 PIO Status 3 1 read-only P30 PIO Status 30 1 read-only P31 PIO Status 31 1 read-only P4 PIO Status 4 1 read-only P5 PIO Status 5 1 read-only P6 PIO Status 6 1 read-only P7 PIO Status 7 1 read-only P8 PIO Status 8 1 read-only P9 PIO Status 9 1 read-only PUDR Pull-Up Disable Register 0x60 32 write-only n 0x0 0x0 P0 Pull-Up Disable 0 1 write-only P1 Pull-Up Disable 1 1 write-only P10 Pull-Up Disable 10 1 write-only P11 Pull-Up Disable 11 1 write-only P12 Pull-Up Disable 12 1 write-only P13 Pull-Up Disable 13 1 write-only P14 Pull-Up Disable 14 1 write-only P15 Pull-Up Disable 15 1 write-only P16 Pull-Up Disable 16 1 write-only P17 Pull-Up Disable 17 1 write-only P18 Pull-Up Disable 18 1 write-only P19 Pull-Up Disable 19 1 write-only P2 Pull-Up Disable 2 1 write-only P20 Pull-Up Disable 20 1 write-only P21 Pull-Up Disable 21 1 write-only P22 Pull-Up Disable 22 1 write-only P23 Pull-Up Disable 23 1 write-only P24 Pull-Up Disable 24 1 write-only P25 Pull-Up Disable 25 1 write-only P26 Pull-Up Disable 26 1 write-only P27 Pull-Up Disable 27 1 write-only P28 Pull-Up Disable 28 1 write-only P29 Pull-Up Disable 29 1 write-only P3 Pull-Up Disable 3 1 write-only P30 Pull-Up Disable 30 1 write-only P31 Pull-Up Disable 31 1 write-only P4 Pull-Up Disable 4 1 write-only P5 Pull-Up Disable 5 1 write-only P6 Pull-Up Disable 6 1 write-only P7 Pull-Up Disable 7 1 write-only P8 Pull-Up Disable 8 1 write-only P9 Pull-Up Disable 9 1 write-only PUER Pull-Up Enable Register 0x64 32 write-only n 0x0 0x0 P0 Pull-Up Enable 0 1 write-only P1 Pull-Up Enable 1 1 write-only P10 Pull-Up Enable 10 1 write-only P11 Pull-Up Enable 11 1 write-only P12 Pull-Up Enable 12 1 write-only P13 Pull-Up Enable 13 1 write-only P14 Pull-Up Enable 14 1 write-only P15 Pull-Up Enable 15 1 write-only P16 Pull-Up Enable 16 1 write-only P17 Pull-Up Enable 17 1 write-only P18 Pull-Up Enable 18 1 write-only P19 Pull-Up Enable 19 1 write-only P2 Pull-Up Enable 2 1 write-only P20 Pull-Up Enable 20 1 write-only P21 Pull-Up Enable 21 1 write-only P22 Pull-Up Enable 22 1 write-only P23 Pull-Up Enable 23 1 write-only P24 Pull-Up Enable 24 1 write-only P25 Pull-Up Enable 25 1 write-only P26 Pull-Up Enable 26 1 write-only P27 Pull-Up Enable 27 1 write-only P28 Pull-Up Enable 28 1 write-only P29 Pull-Up Enable 29 1 write-only P3 Pull-Up Enable 3 1 write-only P30 Pull-Up Enable 30 1 write-only P31 Pull-Up Enable 31 1 write-only P4 Pull-Up Enable 4 1 write-only P5 Pull-Up Enable 5 1 write-only P6 Pull-Up Enable 6 1 write-only P7 Pull-Up Enable 7 1 write-only P8 Pull-Up Enable 8 1 write-only P9 Pull-Up Enable 9 1 write-only PUSR Pad Pull-Up Status Register 0x68 32 read-only n 0x0 0x0 P0 Pull-Up Status 0 1 read-only P1 Pull-Up Status 1 1 read-only P10 Pull-Up Status 10 1 read-only P11 Pull-Up Status 11 1 read-only P12 Pull-Up Status 12 1 read-only P13 Pull-Up Status 13 1 read-only P14 Pull-Up Status 14 1 read-only P15 Pull-Up Status 15 1 read-only P16 Pull-Up Status 16 1 read-only P17 Pull-Up Status 17 1 read-only P18 Pull-Up Status 18 1 read-only P19 Pull-Up Status 19 1 read-only P2 Pull-Up Status 2 1 read-only P20 Pull-Up Status 20 1 read-only P21 Pull-Up Status 21 1 read-only P22 Pull-Up Status 22 1 read-only P23 Pull-Up Status 23 1 read-only P24 Pull-Up Status 24 1 read-only P25 Pull-Up Status 25 1 read-only P26 Pull-Up Status 26 1 read-only P27 Pull-Up Status 27 1 read-only P28 Pull-Up Status 28 1 read-only P29 Pull-Up Status 29 1 read-only P3 Pull-Up Status 3 1 read-only P30 Pull-Up Status 30 1 read-only P31 Pull-Up Status 31 1 read-only P4 Pull-Up Status 4 1 read-only P5 Pull-Up Status 5 1 read-only P6 Pull-Up Status 6 1 read-only P7 Pull-Up Status 7 1 read-only P8 Pull-Up Status 8 1 read-only P9 Pull-Up Status 9 1 read-only REHLSR Rising Edge/High-Level Select Register 0xD4 32 write-only n 0x0 0x0 P0 Rising Edge/High-Level Interrupt Selection 0 1 write-only P1 Rising Edge/High-Level Interrupt Selection 1 1 write-only P10 Rising Edge/High-Level Interrupt Selection 10 1 write-only P11 Rising Edge/High-Level Interrupt Selection 11 1 write-only P12 Rising Edge/High-Level Interrupt Selection 12 1 write-only P13 Rising Edge/High-Level Interrupt Selection 13 1 write-only P14 Rising Edge/High-Level Interrupt Selection 14 1 write-only P15 Rising Edge/High-Level Interrupt Selection 15 1 write-only P16 Rising Edge/High-Level Interrupt Selection 16 1 write-only P17 Rising Edge/High-Level Interrupt Selection 17 1 write-only P18 Rising Edge/High-Level Interrupt Selection 18 1 write-only P19 Rising Edge/High-Level Interrupt Selection 19 1 write-only P2 Rising Edge/High-Level Interrupt Selection 2 1 write-only P20 Rising Edge/High-Level Interrupt Selection 20 1 write-only P21 Rising Edge/High-Level Interrupt Selection 21 1 write-only P22 Rising Edge/High-Level Interrupt Selection 22 1 write-only P23 Rising Edge/High-Level Interrupt Selection 23 1 write-only P24 Rising Edge/High-Level Interrupt Selection 24 1 write-only P25 Rising Edge/High-Level Interrupt Selection 25 1 write-only P26 Rising Edge/High-Level Interrupt Selection 26 1 write-only P27 Rising Edge/High-Level Interrupt Selection 27 1 write-only P28 Rising Edge/High-Level Interrupt Selection 28 1 write-only P29 Rising Edge/High-Level Interrupt Selection 29 1 write-only P3 Rising Edge/High-Level Interrupt Selection 3 1 write-only P30 Rising Edge/High-Level Interrupt Selection 30 1 write-only P31 Rising Edge/High-Level Interrupt Selection 31 1 write-only P4 Rising Edge/High-Level Interrupt Selection 4 1 write-only P5 Rising Edge/High-Level Interrupt Selection 5 1 write-only P6 Rising Edge/High-Level Interrupt Selection 6 1 write-only P7 Rising Edge/High-Level Interrupt Selection 7 1 write-only P8 Rising Edge/High-Level Interrupt Selection 8 1 write-only P9 Rising Edge/High-Level Interrupt Selection 9 1 write-only SCDR Slow Clock Divider Debouncing Register 0x8C 32 read-write n 0x0 0x0 DIV Slow Clock Divider Selection for Debouncing 0 14 read-write SCHMITT Schmitt Trigger Register 0x100 32 read-write n 0x0 0x0 SCHMITT0 Schmitt Trigger Control 0 1 read-write SCHMITT1 Schmitt Trigger Control 1 1 read-write SCHMITT10 Schmitt Trigger Control 10 1 read-write SCHMITT11 Schmitt Trigger Control 11 1 read-write SCHMITT12 Schmitt Trigger Control 12 1 read-write SCHMITT13 Schmitt Trigger Control 13 1 read-write SCHMITT14 Schmitt Trigger Control 14 1 read-write SCHMITT15 Schmitt Trigger Control 15 1 read-write SCHMITT16 Schmitt Trigger Control 16 1 read-write SCHMITT17 Schmitt Trigger Control 17 1 read-write SCHMITT18 Schmitt Trigger Control 18 1 read-write SCHMITT19 Schmitt Trigger Control 19 1 read-write SCHMITT2 Schmitt Trigger Control 2 1 read-write SCHMITT20 Schmitt Trigger Control 20 1 read-write SCHMITT21 Schmitt Trigger Control 21 1 read-write SCHMITT22 Schmitt Trigger Control 22 1 read-write SCHMITT23 Schmitt Trigger Control 23 1 read-write SCHMITT24 Schmitt Trigger Control 24 1 read-write SCHMITT25 Schmitt Trigger Control 25 1 read-write SCHMITT26 Schmitt Trigger Control 26 1 read-write SCHMITT27 Schmitt Trigger Control 27 1 read-write SCHMITT28 Schmitt Trigger Control 28 1 read-write SCHMITT29 Schmitt Trigger Control 29 1 read-write SCHMITT3 Schmitt Trigger Control 3 1 read-write SCHMITT30 Schmitt Trigger Control 30 1 read-write SCHMITT31 Schmitt Trigger Control 31 1 read-write SCHMITT4 Schmitt Trigger Control 4 1 read-write SCHMITT5 Schmitt Trigger Control 5 1 read-write SCHMITT6 Schmitt Trigger Control 6 1 read-write SCHMITT7 Schmitt Trigger Control 7 1 read-write SCHMITT8 Schmitt Trigger Control 8 1 read-write SCHMITT9 Schmitt Trigger Control 9 1 read-write SODR Set Output Data Register 0x30 32 write-only n 0x0 0x0 P0 Set Output Data 0 1 write-only P1 Set Output Data 1 1 write-only P10 Set Output Data 10 1 write-only P11 Set Output Data 11 1 write-only P12 Set Output Data 12 1 write-only P13 Set Output Data 13 1 write-only P14 Set Output Data 14 1 write-only P15 Set Output Data 15 1 write-only P16 Set Output Data 16 1 write-only P17 Set Output Data 17 1 write-only P18 Set Output Data 18 1 write-only P19 Set Output Data 19 1 write-only P2 Set Output Data 2 1 write-only P20 Set Output Data 20 1 write-only P21 Set Output Data 21 1 write-only P22 Set Output Data 22 1 write-only P23 Set Output Data 23 1 write-only P24 Set Output Data 24 1 write-only P25 Set Output Data 25 1 write-only P26 Set Output Data 26 1 write-only P27 Set Output Data 27 1 write-only P28 Set Output Data 28 1 write-only P29 Set Output Data 29 1 write-only P3 Set Output Data 3 1 write-only P30 Set Output Data 30 1 write-only P31 Set Output Data 31 1 write-only P4 Set Output Data 4 1 write-only P5 Set Output Data 5 1 write-only P6 Set Output Data 6 1 write-only P7 Set Output Data 7 1 write-only P8 Set Output Data 8 1 write-only P9 Set Output Data 9 1 write-only WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 read-write WPKEY Write Protection Key 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 0x50494F WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 read-only WPVSRC Write Protection Violation Source 8 16 read-only PIOE Parallel Input/Output Controller E PIO 0x0 0x0 0x1000 registers n PIOE 26 ABCDSR0 Peripheral ABCD Select Register 0x70 32 read-write n P0 Peripheral Select 0 1 read-write P1 Peripheral Select 1 1 read-write P10 Peripheral Select 10 1 read-write P11 Peripheral Select 11 1 read-write P12 Peripheral Select 12 1 read-write P13 Peripheral Select 13 1 read-write P14 Peripheral Select 14 1 read-write P15 Peripheral Select 15 1 read-write P16 Peripheral Select 16 1 read-write P17 Peripheral Select 17 1 read-write P18 Peripheral Select 18 1 read-write P19 Peripheral Select 19 1 read-write P2 Peripheral Select 2 1 read-write P20 Peripheral Select 20 1 read-write P21 Peripheral Select 21 1 read-write P22 Peripheral Select 22 1 read-write P23 Peripheral Select 23 1 read-write P24 Peripheral Select 24 1 read-write P25 Peripheral Select 25 1 read-write P26 Peripheral Select 26 1 read-write P27 Peripheral Select 27 1 read-write P28 Peripheral Select 28 1 read-write P29 Peripheral Select 29 1 read-write P3 Peripheral Select 3 1 read-write P30 Peripheral Select 30 1 read-write P31 Peripheral Select 31 1 read-write P4 Peripheral Select 4 1 read-write P5 Peripheral Select 5 1 read-write P6 Peripheral Select 6 1 read-write P7 Peripheral Select 7 1 read-write P8 Peripheral Select 8 1 read-write P9 Peripheral Select 9 1 read-write ABCDSR1 Peripheral ABCD Select Register 0x74 32 read-write n P0 Peripheral Select 0 1 read-write P1 Peripheral Select 1 1 read-write P10 Peripheral Select 10 1 read-write P11 Peripheral Select 11 1 read-write P12 Peripheral Select 12 1 read-write P13 Peripheral Select 13 1 read-write P14 Peripheral Select 14 1 read-write P15 Peripheral Select 15 1 read-write P16 Peripheral Select 16 1 read-write P17 Peripheral Select 17 1 read-write P18 Peripheral Select 18 1 read-write P19 Peripheral Select 19 1 read-write P2 Peripheral Select 2 1 read-write P20 Peripheral Select 20 1 read-write P21 Peripheral Select 21 1 read-write P22 Peripheral Select 22 1 read-write P23 Peripheral Select 23 1 read-write P24 Peripheral Select 24 1 read-write P25 Peripheral Select 25 1 read-write P26 Peripheral Select 26 1 read-write P27 Peripheral Select 27 1 read-write P28 Peripheral Select 28 1 read-write P29 Peripheral Select 29 1 read-write P3 Peripheral Select 3 1 read-write P30 Peripheral Select 30 1 read-write P31 Peripheral Select 31 1 read-write P4 Peripheral Select 4 1 read-write P5 Peripheral Select 5 1 read-write P6 Peripheral Select 6 1 read-write P7 Peripheral Select 7 1 read-write P8 Peripheral Select 8 1 read-write P9 Peripheral Select 9 1 read-write ABCDSR[0] Peripheral ABCD Select Register 0xE0 32 read-write n 0x0 0x0 P0 Peripheral Select 0 1 read-write P1 Peripheral Select 1 1 read-write P10 Peripheral Select 10 1 read-write P11 Peripheral Select 11 1 read-write P12 Peripheral Select 12 1 read-write P13 Peripheral Select 13 1 read-write P14 Peripheral Select 14 1 read-write P15 Peripheral Select 15 1 read-write P16 Peripheral Select 16 1 read-write P17 Peripheral Select 17 1 read-write P18 Peripheral Select 18 1 read-write P19 Peripheral Select 19 1 read-write P2 Peripheral Select 2 1 read-write P20 Peripheral Select 20 1 read-write P21 Peripheral Select 21 1 read-write P22 Peripheral Select 22 1 read-write P23 Peripheral Select 23 1 read-write P24 Peripheral Select 24 1 read-write P25 Peripheral Select 25 1 read-write P26 Peripheral Select 26 1 read-write P27 Peripheral Select 27 1 read-write P28 Peripheral Select 28 1 read-write P29 Peripheral Select 29 1 read-write P3 Peripheral Select 3 1 read-write P30 Peripheral Select 30 1 read-write P31 Peripheral Select 31 1 read-write P4 Peripheral Select 4 1 read-write P5 Peripheral Select 5 1 read-write P6 Peripheral Select 6 1 read-write P7 Peripheral Select 7 1 read-write P8 Peripheral Select 8 1 read-write P9 Peripheral Select 9 1 read-write ABCDSR[1] Peripheral ABCD Select Register 0x154 32 read-write n 0x0 0x0 P0 Peripheral Select 0 1 read-write P1 Peripheral Select 1 1 read-write P10 Peripheral Select 10 1 read-write P11 Peripheral Select 11 1 read-write P12 Peripheral Select 12 1 read-write P13 Peripheral Select 13 1 read-write P14 Peripheral Select 14 1 read-write P15 Peripheral Select 15 1 read-write P16 Peripheral Select 16 1 read-write P17 Peripheral Select 17 1 read-write P18 Peripheral Select 18 1 read-write P19 Peripheral Select 19 1 read-write P2 Peripheral Select 2 1 read-write P20 Peripheral Select 20 1 read-write P21 Peripheral Select 21 1 read-write P22 Peripheral Select 22 1 read-write P23 Peripheral Select 23 1 read-write P24 Peripheral Select 24 1 read-write P25 Peripheral Select 25 1 read-write P26 Peripheral Select 26 1 read-write P27 Peripheral Select 27 1 read-write P28 Peripheral Select 28 1 read-write P29 Peripheral Select 29 1 read-write P3 Peripheral Select 3 1 read-write P30 Peripheral Select 30 1 read-write P31 Peripheral Select 31 1 read-write P4 Peripheral Select 4 1 read-write P5 Peripheral Select 5 1 read-write P6 Peripheral Select 6 1 read-write P7 Peripheral Select 7 1 read-write P8 Peripheral Select 8 1 read-write P9 Peripheral Select 9 1 read-write AIMDR Additional Interrupt Modes Disable Register 0xB4 32 write-only n 0x0 0x0 P0 Additional Interrupt Modes Disable 0 1 write-only P1 Additional Interrupt Modes Disable 1 1 write-only P10 Additional Interrupt Modes Disable 10 1 write-only P11 Additional Interrupt Modes Disable 11 1 write-only P12 Additional Interrupt Modes Disable 12 1 write-only P13 Additional Interrupt Modes Disable 13 1 write-only P14 Additional Interrupt Modes Disable 14 1 write-only P15 Additional Interrupt Modes Disable 15 1 write-only P16 Additional Interrupt Modes Disable 16 1 write-only P17 Additional Interrupt Modes Disable 17 1 write-only P18 Additional Interrupt Modes Disable 18 1 write-only P19 Additional Interrupt Modes Disable 19 1 write-only P2 Additional Interrupt Modes Disable 2 1 write-only P20 Additional Interrupt Modes Disable 20 1 write-only P21 Additional Interrupt Modes Disable 21 1 write-only P22 Additional Interrupt Modes Disable 22 1 write-only P23 Additional Interrupt Modes Disable 23 1 write-only P24 Additional Interrupt Modes Disable 24 1 write-only P25 Additional Interrupt Modes Disable 25 1 write-only P26 Additional Interrupt Modes Disable 26 1 write-only P27 Additional Interrupt Modes Disable 27 1 write-only P28 Additional Interrupt Modes Disable 28 1 write-only P29 Additional Interrupt Modes Disable 29 1 write-only P3 Additional Interrupt Modes Disable 3 1 write-only P30 Additional Interrupt Modes Disable 30 1 write-only P31 Additional Interrupt Modes Disable 31 1 write-only P4 Additional Interrupt Modes Disable 4 1 write-only P5 Additional Interrupt Modes Disable 5 1 write-only P6 Additional Interrupt Modes Disable 6 1 write-only P7 Additional Interrupt Modes Disable 7 1 write-only P8 Additional Interrupt Modes Disable 8 1 write-only P9 Additional Interrupt Modes Disable 9 1 write-only AIMER Additional Interrupt Modes Enable Register 0xB0 32 write-only n 0x0 0x0 P0 Additional Interrupt Modes Enable 0 1 write-only P1 Additional Interrupt Modes Enable 1 1 write-only P10 Additional Interrupt Modes Enable 10 1 write-only P11 Additional Interrupt Modes Enable 11 1 write-only P12 Additional Interrupt Modes Enable 12 1 write-only P13 Additional Interrupt Modes Enable 13 1 write-only P14 Additional Interrupt Modes Enable 14 1 write-only P15 Additional Interrupt Modes Enable 15 1 write-only P16 Additional Interrupt Modes Enable 16 1 write-only P17 Additional Interrupt Modes Enable 17 1 write-only P18 Additional Interrupt Modes Enable 18 1 write-only P19 Additional Interrupt Modes Enable 19 1 write-only P2 Additional Interrupt Modes Enable 2 1 write-only P20 Additional Interrupt Modes Enable 20 1 write-only P21 Additional Interrupt Modes Enable 21 1 write-only P22 Additional Interrupt Modes Enable 22 1 write-only P23 Additional Interrupt Modes Enable 23 1 write-only P24 Additional Interrupt Modes Enable 24 1 write-only P25 Additional Interrupt Modes Enable 25 1 write-only P26 Additional Interrupt Modes Enable 26 1 write-only P27 Additional Interrupt Modes Enable 27 1 write-only P28 Additional Interrupt Modes Enable 28 1 write-only P29 Additional Interrupt Modes Enable 29 1 write-only P3 Additional Interrupt Modes Enable 3 1 write-only P30 Additional Interrupt Modes Enable 30 1 write-only P31 Additional Interrupt Modes Enable 31 1 write-only P4 Additional Interrupt Modes Enable 4 1 write-only P5 Additional Interrupt Modes Enable 5 1 write-only P6 Additional Interrupt Modes Enable 6 1 write-only P7 Additional Interrupt Modes Enable 7 1 write-only P8 Additional Interrupt Modes Enable 8 1 write-only P9 Additional Interrupt Modes Enable 9 1 write-only AIMMR Additional Interrupt Modes Mask Register 0xB8 32 read-only n 0x0 0x0 P0 IO Line Index 0 1 read-only P1 IO Line Index 1 1 read-only P10 IO Line Index 10 1 read-only P11 IO Line Index 11 1 read-only P12 IO Line Index 12 1 read-only P13 IO Line Index 13 1 read-only P14 IO Line Index 14 1 read-only P15 IO Line Index 15 1 read-only P16 IO Line Index 16 1 read-only P17 IO Line Index 17 1 read-only P18 IO Line Index 18 1 read-only P19 IO Line Index 19 1 read-only P2 IO Line Index 2 1 read-only P20 IO Line Index 20 1 read-only P21 IO Line Index 21 1 read-only P22 IO Line Index 22 1 read-only P23 IO Line Index 23 1 read-only P24 IO Line Index 24 1 read-only P25 IO Line Index 25 1 read-only P26 IO Line Index 26 1 read-only P27 IO Line Index 27 1 read-only P28 IO Line Index 28 1 read-only P29 IO Line Index 29 1 read-only P3 IO Line Index 3 1 read-only P30 IO Line Index 30 1 read-only P31 IO Line Index 31 1 read-only P4 IO Line Index 4 1 read-only P5 IO Line Index 5 1 read-only P6 IO Line Index 6 1 read-only P7 IO Line Index 7 1 read-only P8 IO Line Index 8 1 read-only P9 IO Line Index 9 1 read-only CODR Clear Output Data Register 0x34 32 write-only n 0x0 0x0 P0 Clear Output Data 0 1 write-only P1 Clear Output Data 1 1 write-only P10 Clear Output Data 10 1 write-only P11 Clear Output Data 11 1 write-only P12 Clear Output Data 12 1 write-only P13 Clear Output Data 13 1 write-only P14 Clear Output Data 14 1 write-only P15 Clear Output Data 15 1 write-only P16 Clear Output Data 16 1 write-only P17 Clear Output Data 17 1 write-only P18 Clear Output Data 18 1 write-only P19 Clear Output Data 19 1 write-only P2 Clear Output Data 2 1 write-only P20 Clear Output Data 20 1 write-only P21 Clear Output Data 21 1 write-only P22 Clear Output Data 22 1 write-only P23 Clear Output Data 23 1 write-only P24 Clear Output Data 24 1 write-only P25 Clear Output Data 25 1 write-only P26 Clear Output Data 26 1 write-only P27 Clear Output Data 27 1 write-only P28 Clear Output Data 28 1 write-only P29 Clear Output Data 29 1 write-only P3 Clear Output Data 3 1 write-only P30 Clear Output Data 30 1 write-only P31 Clear Output Data 31 1 write-only P4 Clear Output Data 4 1 write-only P5 Clear Output Data 5 1 write-only P6 Clear Output Data 6 1 write-only P7 Clear Output Data 7 1 write-only P8 Clear Output Data 8 1 write-only P9 Clear Output Data 9 1 write-only DRIVER1 I/O Drive Register 1 0x118 32 read-write n 0x0 0x0 LINE0 Drive of PIO Line 0 0 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE1 Drive of PIO Line 1 2 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE10 Drive of PIO Line 10 20 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE11 Drive of PIO Line 11 22 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE12 Drive of PIO Line 12 24 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE13 Drive of PIO Line 13 26 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE14 Drive of PIO Line 14 28 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE15 Drive of PIO Line 15 30 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE2 Drive of PIO Line 2 4 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE3 Drive of PIO Line 3 6 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE4 Drive of PIO Line 4 8 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE5 Drive of PIO Line 5 10 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE6 Drive of PIO Line 6 12 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE7 Drive of PIO Line 7 14 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE8 Drive of PIO Line 8 16 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE9 Drive of PIO Line 9 18 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 DRIVER2 I/O Drive Register 2 0x11C 32 read-write n 0x0 0x0 LINE16 Drive of PIO line 16 0 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE17 Drive of PIO line 17 2 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE18 Drive of PIO line 18 4 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE19 Drive of PIO line 19 6 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE20 Drive of PIO line 20 8 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE21 Drive of PIO line 21 10 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE22 Drive of PIO line 22 12 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE23 Drive of PIO line 23 14 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE24 Drive of PIO line 24 16 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE25 Drive of PIO line 25 18 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE26 Drive of PIO line 26 20 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE27 Drive of PIO line 27 22 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE28 Drive of PIO line 28 24 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE29 Drive of PIO line 29 26 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE30 Drive of PIO line 30 28 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 LINE31 Drive of PIO line 31 30 2 read-write LO_DRIVE Low drive 0x0 ME_DRIVE Medium drive 0x2 HI_DRIVE High drive 0x3 ELSR Edge/Level Status Register 0xC8 32 read-only n 0x0 0x0 P0 Edge/Level Interrupt Source Selection 0 1 read-only P1 Edge/Level Interrupt Source Selection 1 1 read-only P10 Edge/Level Interrupt Source Selection 10 1 read-only P11 Edge/Level Interrupt Source Selection 11 1 read-only P12 Edge/Level Interrupt Source Selection 12 1 read-only P13 Edge/Level Interrupt Source Selection 13 1 read-only P14 Edge/Level Interrupt Source Selection 14 1 read-only P15 Edge/Level Interrupt Source Selection 15 1 read-only P16 Edge/Level Interrupt Source Selection 16 1 read-only P17 Edge/Level Interrupt Source Selection 17 1 read-only P18 Edge/Level Interrupt Source Selection 18 1 read-only P19 Edge/Level Interrupt Source Selection 19 1 read-only P2 Edge/Level Interrupt Source Selection 2 1 read-only P20 Edge/Level Interrupt Source Selection 20 1 read-only P21 Edge/Level Interrupt Source Selection 21 1 read-only P22 Edge/Level Interrupt Source Selection 22 1 read-only P23 Edge/Level Interrupt Source Selection 23 1 read-only P24 Edge/Level Interrupt Source Selection 24 1 read-only P25 Edge/Level Interrupt Source Selection 25 1 read-only P26 Edge/Level Interrupt Source Selection 26 1 read-only P27 Edge/Level Interrupt Source Selection 27 1 read-only P28 Edge/Level Interrupt Source Selection 28 1 read-only P29 Edge/Level Interrupt Source Selection 29 1 read-only P3 Edge/Level Interrupt Source Selection 3 1 read-only P30 Edge/Level Interrupt Source Selection 30 1 read-only P31 Edge/Level Interrupt Source Selection 31 1 read-only P4 Edge/Level Interrupt Source Selection 4 1 read-only P5 Edge/Level Interrupt Source Selection 5 1 read-only P6 Edge/Level Interrupt Source Selection 6 1 read-only P7 Edge/Level Interrupt Source Selection 7 1 read-only P8 Edge/Level Interrupt Source Selection 8 1 read-only P9 Edge/Level Interrupt Source Selection 9 1 read-only ESR Edge Select Register 0xC0 32 write-only n 0x0 0x0 P0 Edge Interrupt Selection 0 1 write-only P1 Edge Interrupt Selection 1 1 write-only P10 Edge Interrupt Selection 10 1 write-only P11 Edge Interrupt Selection 11 1 write-only P12 Edge Interrupt Selection 12 1 write-only P13 Edge Interrupt Selection 13 1 write-only P14 Edge Interrupt Selection 14 1 write-only P15 Edge Interrupt Selection 15 1 write-only P16 Edge Interrupt Selection 16 1 write-only P17 Edge Interrupt Selection 17 1 write-only P18 Edge Interrupt Selection 18 1 write-only P19 Edge Interrupt Selection 19 1 write-only P2 Edge Interrupt Selection 2 1 write-only P20 Edge Interrupt Selection 20 1 write-only P21 Edge Interrupt Selection 21 1 write-only P22 Edge Interrupt Selection 22 1 write-only P23 Edge Interrupt Selection 23 1 write-only P24 Edge Interrupt Selection 24 1 write-only P25 Edge Interrupt Selection 25 1 write-only P26 Edge Interrupt Selection 26 1 write-only P27 Edge Interrupt Selection 27 1 write-only P28 Edge Interrupt Selection 28 1 write-only P29 Edge Interrupt Selection 29 1 write-only P3 Edge Interrupt Selection 3 1 write-only P30 Edge Interrupt Selection 30 1 write-only P31 Edge Interrupt Selection 31 1 write-only P4 Edge Interrupt Selection 4 1 write-only P5 Edge Interrupt Selection 5 1 write-only P6 Edge Interrupt Selection 6 1 write-only P7 Edge Interrupt Selection 7 1 write-only P8 Edge Interrupt Selection 8 1 write-only P9 Edge Interrupt Selection 9 1 write-only FELLSR Falling Edge/Low-Level Select Register 0xD0 32 write-only n 0x0 0x0 P0 Falling Edge/Low-Level Interrupt Selection 0 1 write-only P1 Falling Edge/Low-Level Interrupt Selection 1 1 write-only P10 Falling Edge/Low-Level Interrupt Selection 10 1 write-only P11 Falling Edge/Low-Level Interrupt Selection 11 1 write-only P12 Falling Edge/Low-Level Interrupt Selection 12 1 write-only P13 Falling Edge/Low-Level Interrupt Selection 13 1 write-only P14 Falling Edge/Low-Level Interrupt Selection 14 1 write-only P15 Falling Edge/Low-Level Interrupt Selection 15 1 write-only P16 Falling Edge/Low-Level Interrupt Selection 16 1 write-only P17 Falling Edge/Low-Level Interrupt Selection 17 1 write-only P18 Falling Edge/Low-Level Interrupt Selection 18 1 write-only P19 Falling Edge/Low-Level Interrupt Selection 19 1 write-only P2 Falling Edge/Low-Level Interrupt Selection 2 1 write-only P20 Falling Edge/Low-Level Interrupt Selection 20 1 write-only P21 Falling Edge/Low-Level Interrupt Selection 21 1 write-only P22 Falling Edge/Low-Level Interrupt Selection 22 1 write-only P23 Falling Edge/Low-Level Interrupt Selection 23 1 write-only P24 Falling Edge/Low-Level Interrupt Selection 24 1 write-only P25 Falling Edge/Low-Level Interrupt Selection 25 1 write-only P26 Falling Edge/Low-Level Interrupt Selection 26 1 write-only P27 Falling Edge/Low-Level Interrupt Selection 27 1 write-only P28 Falling Edge/Low-Level Interrupt Selection 28 1 write-only P29 Falling Edge/Low-Level Interrupt Selection 29 1 write-only P3 Falling Edge/Low-Level Interrupt Selection 3 1 write-only P30 Falling Edge/Low-Level Interrupt Selection 30 1 write-only P31 Falling Edge/Low-Level Interrupt Selection 31 1 write-only P4 Falling Edge/Low-Level Interrupt Selection 4 1 write-only P5 Falling Edge/Low-Level Interrupt Selection 5 1 write-only P6 Falling Edge/Low-Level Interrupt Selection 6 1 write-only P7 Falling Edge/Low-Level Interrupt Selection 7 1 write-only P8 Falling Edge/Low-Level Interrupt Selection 8 1 write-only P9 Falling Edge/Low-Level Interrupt Selection 9 1 write-only FRLHSR Fall/Rise - Low/High Status Register 0xD8 32 read-only n 0x0 0x0 P0 Edge/Level Interrupt Source Selection 0 1 read-only P1 Edge/Level Interrupt Source Selection 1 1 read-only P10 Edge/Level Interrupt Source Selection 10 1 read-only P11 Edge/Level Interrupt Source Selection 11 1 read-only P12 Edge/Level Interrupt Source Selection 12 1 read-only P13 Edge/Level Interrupt Source Selection 13 1 read-only P14 Edge/Level Interrupt Source Selection 14 1 read-only P15 Edge/Level Interrupt Source Selection 15 1 read-only P16 Edge/Level Interrupt Source Selection 16 1 read-only P17 Edge/Level Interrupt Source Selection 17 1 read-only P18 Edge/Level Interrupt Source Selection 18 1 read-only P19 Edge/Level Interrupt Source Selection 19 1 read-only P2 Edge/Level Interrupt Source Selection 2 1 read-only P20 Edge/Level Interrupt Source Selection 20 1 read-only P21 Edge/Level Interrupt Source Selection 21 1 read-only P22 Edge/Level Interrupt Source Selection 22 1 read-only P23 Edge/Level Interrupt Source Selection 23 1 read-only P24 Edge/Level Interrupt Source Selection 24 1 read-only P25 Edge/Level Interrupt Source Selection 25 1 read-only P26 Edge/Level Interrupt Source Selection 26 1 read-only P27 Edge/Level Interrupt Source Selection 27 1 read-only P28 Edge/Level Interrupt Source Selection 28 1 read-only P29 Edge/Level Interrupt Source Selection 29 1 read-only P3 Edge/Level Interrupt Source Selection 3 1 read-only P30 Edge/Level Interrupt Source Selection 30 1 read-only P31 Edge/Level Interrupt Source Selection 31 1 read-only P4 Edge/Level Interrupt Source Selection 4 1 read-only P5 Edge/Level Interrupt Source Selection 5 1 read-only P6 Edge/Level Interrupt Source Selection 6 1 read-only P7 Edge/Level Interrupt Source Selection 7 1 read-only P8 Edge/Level Interrupt Source Selection 8 1 read-only P9 Edge/Level Interrupt Source Selection 9 1 read-only IDR Interrupt Disable Register 0x44 32 write-only n 0x0 0x0 P0 Input Change Interrupt Disable 0 1 write-only P1 Input Change Interrupt Disable 1 1 write-only P10 Input Change Interrupt Disable 10 1 write-only P11 Input Change Interrupt Disable 11 1 write-only P12 Input Change Interrupt Disable 12 1 write-only P13 Input Change Interrupt Disable 13 1 write-only P14 Input Change Interrupt Disable 14 1 write-only P15 Input Change Interrupt Disable 15 1 write-only P16 Input Change Interrupt Disable 16 1 write-only P17 Input Change Interrupt Disable 17 1 write-only P18 Input Change Interrupt Disable 18 1 write-only P19 Input Change Interrupt Disable 19 1 write-only P2 Input Change Interrupt Disable 2 1 write-only P20 Input Change Interrupt Disable 20 1 write-only P21 Input Change Interrupt Disable 21 1 write-only P22 Input Change Interrupt Disable 22 1 write-only P23 Input Change Interrupt Disable 23 1 write-only P24 Input Change Interrupt Disable 24 1 write-only P25 Input Change Interrupt Disable 25 1 write-only P26 Input Change Interrupt Disable 26 1 write-only P27 Input Change Interrupt Disable 27 1 write-only P28 Input Change Interrupt Disable 28 1 write-only P29 Input Change Interrupt Disable 29 1 write-only P3 Input Change Interrupt Disable 3 1 write-only P30 Input Change Interrupt Disable 30 1 write-only P31 Input Change Interrupt Disable 31 1 write-only P4 Input Change Interrupt Disable 4 1 write-only P5 Input Change Interrupt Disable 5 1 write-only P6 Input Change Interrupt Disable 6 1 write-only P7 Input Change Interrupt Disable 7 1 write-only P8 Input Change Interrupt Disable 8 1 write-only P9 Input Change Interrupt Disable 9 1 write-only IER Interrupt Enable Register 0x40 32 write-only n 0x0 0x0 P0 Input Change Interrupt Enable 0 1 write-only P1 Input Change Interrupt Enable 1 1 write-only P10 Input Change Interrupt Enable 10 1 write-only P11 Input Change Interrupt Enable 11 1 write-only P12 Input Change Interrupt Enable 12 1 write-only P13 Input Change Interrupt Enable 13 1 write-only P14 Input Change Interrupt Enable 14 1 write-only P15 Input Change Interrupt Enable 15 1 write-only P16 Input Change Interrupt Enable 16 1 write-only P17 Input Change Interrupt Enable 17 1 write-only P18 Input Change Interrupt Enable 18 1 write-only P19 Input Change Interrupt Enable 19 1 write-only P2 Input Change Interrupt Enable 2 1 write-only P20 Input Change Interrupt Enable 20 1 write-only P21 Input Change Interrupt Enable 21 1 write-only P22 Input Change Interrupt Enable 22 1 write-only P23 Input Change Interrupt Enable 23 1 write-only P24 Input Change Interrupt Enable 24 1 write-only P25 Input Change Interrupt Enable 25 1 write-only P26 Input Change Interrupt Enable 26 1 write-only P27 Input Change Interrupt Enable 27 1 write-only P28 Input Change Interrupt Enable 28 1 write-only P29 Input Change Interrupt Enable 29 1 write-only P3 Input Change Interrupt Enable 3 1 write-only P30 Input Change Interrupt Enable 30 1 write-only P31 Input Change Interrupt Enable 31 1 write-only P4 Input Change Interrupt Enable 4 1 write-only P5 Input Change Interrupt Enable 5 1 write-only P6 Input Change Interrupt Enable 6 1 write-only P7 Input Change Interrupt Enable 7 1 write-only P8 Input Change Interrupt Enable 8 1 write-only P9 Input Change Interrupt Enable 9 1 write-only IFDR Glitch Input Filter Disable Register 0x24 32 write-only n 0x0 0x0 P0 Input Filter Disable 0 1 write-only P1 Input Filter Disable 1 1 write-only P10 Input Filter Disable 10 1 write-only P11 Input Filter Disable 11 1 write-only P12 Input Filter Disable 12 1 write-only P13 Input Filter Disable 13 1 write-only P14 Input Filter Disable 14 1 write-only P15 Input Filter Disable 15 1 write-only P16 Input Filter Disable 16 1 write-only P17 Input Filter Disable 17 1 write-only P18 Input Filter Disable 18 1 write-only P19 Input Filter Disable 19 1 write-only P2 Input Filter Disable 2 1 write-only P20 Input Filter Disable 20 1 write-only P21 Input Filter Disable 21 1 write-only P22 Input Filter Disable 22 1 write-only P23 Input Filter Disable 23 1 write-only P24 Input Filter Disable 24 1 write-only P25 Input Filter Disable 25 1 write-only P26 Input Filter Disable 26 1 write-only P27 Input Filter Disable 27 1 write-only P28 Input Filter Disable 28 1 write-only P29 Input Filter Disable 29 1 write-only P3 Input Filter Disable 3 1 write-only P30 Input Filter Disable 30 1 write-only P31 Input Filter Disable 31 1 write-only P4 Input Filter Disable 4 1 write-only P5 Input Filter Disable 5 1 write-only P6 Input Filter Disable 6 1 write-only P7 Input Filter Disable 7 1 write-only P8 Input Filter Disable 8 1 write-only P9 Input Filter Disable 9 1 write-only IFER Glitch Input Filter Enable Register 0x20 32 write-only n 0x0 0x0 P0 Input Filter Enable 0 1 write-only P1 Input Filter Enable 1 1 write-only P10 Input Filter Enable 10 1 write-only P11 Input Filter Enable 11 1 write-only P12 Input Filter Enable 12 1 write-only P13 Input Filter Enable 13 1 write-only P14 Input Filter Enable 14 1 write-only P15 Input Filter Enable 15 1 write-only P16 Input Filter Enable 16 1 write-only P17 Input Filter Enable 17 1 write-only P18 Input Filter Enable 18 1 write-only P19 Input Filter Enable 19 1 write-only P2 Input Filter Enable 2 1 write-only P20 Input Filter Enable 20 1 write-only P21 Input Filter Enable 21 1 write-only P22 Input Filter Enable 22 1 write-only P23 Input Filter Enable 23 1 write-only P24 Input Filter Enable 24 1 write-only P25 Input Filter Enable 25 1 write-only P26 Input Filter Enable 26 1 write-only P27 Input Filter Enable 27 1 write-only P28 Input Filter Enable 28 1 write-only P29 Input Filter Enable 29 1 write-only P3 Input Filter Enable 3 1 write-only P30 Input Filter Enable 30 1 write-only P31 Input Filter Enable 31 1 write-only P4 Input Filter Enable 4 1 write-only P5 Input Filter Enable 5 1 write-only P6 Input Filter Enable 6 1 write-only P7 Input Filter Enable 7 1 write-only P8 Input Filter Enable 8 1 write-only P9 Input Filter Enable 9 1 write-only IFSCDR Input Filter Slow Clock Disable Register 0x80 32 write-only n 0x0 0x0 P0 Peripheral Clock Glitch Filtering Select 0 1 write-only P1 Peripheral Clock Glitch Filtering Select 1 1 write-only P10 Peripheral Clock Glitch Filtering Select 10 1 write-only P11 Peripheral Clock Glitch Filtering Select 11 1 write-only P12 Peripheral Clock Glitch Filtering Select 12 1 write-only P13 Peripheral Clock Glitch Filtering Select 13 1 write-only P14 Peripheral Clock Glitch Filtering Select 14 1 write-only P15 Peripheral Clock Glitch Filtering Select 15 1 write-only P16 Peripheral Clock Glitch Filtering Select 16 1 write-only P17 Peripheral Clock Glitch Filtering Select 17 1 write-only P18 Peripheral Clock Glitch Filtering Select 18 1 write-only P19 Peripheral Clock Glitch Filtering Select 19 1 write-only P2 Peripheral Clock Glitch Filtering Select 2 1 write-only P20 Peripheral Clock Glitch Filtering Select 20 1 write-only P21 Peripheral Clock Glitch Filtering Select 21 1 write-only P22 Peripheral Clock Glitch Filtering Select 22 1 write-only P23 Peripheral Clock Glitch Filtering Select 23 1 write-only P24 Peripheral Clock Glitch Filtering Select 24 1 write-only P25 Peripheral Clock Glitch Filtering Select 25 1 write-only P26 Peripheral Clock Glitch Filtering Select 26 1 write-only P27 Peripheral Clock Glitch Filtering Select 27 1 write-only P28 Peripheral Clock Glitch Filtering Select 28 1 write-only P29 Peripheral Clock Glitch Filtering Select 29 1 write-only P3 Peripheral Clock Glitch Filtering Select 3 1 write-only P30 Peripheral Clock Glitch Filtering Select 30 1 write-only P31 Peripheral Clock Glitch Filtering Select 31 1 write-only P4 Peripheral Clock Glitch Filtering Select 4 1 write-only P5 Peripheral Clock Glitch Filtering Select 5 1 write-only P6 Peripheral Clock Glitch Filtering Select 6 1 write-only P7 Peripheral Clock Glitch Filtering Select 7 1 write-only P8 Peripheral Clock Glitch Filtering Select 8 1 write-only P9 Peripheral Clock Glitch Filtering Select 9 1 write-only IFSCER Input Filter Slow Clock Enable Register 0x84 32 write-only n 0x0 0x0 P0 Slow Clock Debouncing Filtering Select 0 1 write-only P1 Slow Clock Debouncing Filtering Select 1 1 write-only P10 Slow Clock Debouncing Filtering Select 10 1 write-only P11 Slow Clock Debouncing Filtering Select 11 1 write-only P12 Slow Clock Debouncing Filtering Select 12 1 write-only P13 Slow Clock Debouncing Filtering Select 13 1 write-only P14 Slow Clock Debouncing Filtering Select 14 1 write-only P15 Slow Clock Debouncing Filtering Select 15 1 write-only P16 Slow Clock Debouncing Filtering Select 16 1 write-only P17 Slow Clock Debouncing Filtering Select 17 1 write-only P18 Slow Clock Debouncing Filtering Select 18 1 write-only P19 Slow Clock Debouncing Filtering Select 19 1 write-only P2 Slow Clock Debouncing Filtering Select 2 1 write-only P20 Slow Clock Debouncing Filtering Select 20 1 write-only P21 Slow Clock Debouncing Filtering Select 21 1 write-only P22 Slow Clock Debouncing Filtering Select 22 1 write-only P23 Slow Clock Debouncing Filtering Select 23 1 write-only P24 Slow Clock Debouncing Filtering Select 24 1 write-only P25 Slow Clock Debouncing Filtering Select 25 1 write-only P26 Slow Clock Debouncing Filtering Select 26 1 write-only P27 Slow Clock Debouncing Filtering Select 27 1 write-only P28 Slow Clock Debouncing Filtering Select 28 1 write-only P29 Slow Clock Debouncing Filtering Select 29 1 write-only P3 Slow Clock Debouncing Filtering Select 3 1 write-only P30 Slow Clock Debouncing Filtering Select 30 1 write-only P31 Slow Clock Debouncing Filtering Select 31 1 write-only P4 Slow Clock Debouncing Filtering Select 4 1 write-only P5 Slow Clock Debouncing Filtering Select 5 1 write-only P6 Slow Clock Debouncing Filtering Select 6 1 write-only P7 Slow Clock Debouncing Filtering Select 7 1 write-only P8 Slow Clock Debouncing Filtering Select 8 1 write-only P9 Slow Clock Debouncing Filtering Select 9 1 write-only IFSCSR Input Filter Slow Clock Status Register 0x88 32 read-only n 0x0 0x0 P0 Glitch or Debouncing Filter Selection Status 0 1 read-only P1 Glitch or Debouncing Filter Selection Status 1 1 read-only P10 Glitch or Debouncing Filter Selection Status 10 1 read-only P11 Glitch or Debouncing Filter Selection Status 11 1 read-only P12 Glitch or Debouncing Filter Selection Status 12 1 read-only P13 Glitch or Debouncing Filter Selection Status 13 1 read-only P14 Glitch or Debouncing Filter Selection Status 14 1 read-only P15 Glitch or Debouncing Filter Selection Status 15 1 read-only P16 Glitch or Debouncing Filter Selection Status 16 1 read-only P17 Glitch or Debouncing Filter Selection Status 17 1 read-only P18 Glitch or Debouncing Filter Selection Status 18 1 read-only P19 Glitch or Debouncing Filter Selection Status 19 1 read-only P2 Glitch or Debouncing Filter Selection Status 2 1 read-only P20 Glitch or Debouncing Filter Selection Status 20 1 read-only P21 Glitch or Debouncing Filter Selection Status 21 1 read-only P22 Glitch or Debouncing Filter Selection Status 22 1 read-only P23 Glitch or Debouncing Filter Selection Status 23 1 read-only P24 Glitch or Debouncing Filter Selection Status 24 1 read-only P25 Glitch or Debouncing Filter Selection Status 25 1 read-only P26 Glitch or Debouncing Filter Selection Status 26 1 read-only P27 Glitch or Debouncing Filter Selection Status 27 1 read-only P28 Glitch or Debouncing Filter Selection Status 28 1 read-only P29 Glitch or Debouncing Filter Selection Status 29 1 read-only P3 Glitch or Debouncing Filter Selection Status 3 1 read-only P30 Glitch or Debouncing Filter Selection Status 30 1 read-only P31 Glitch or Debouncing Filter Selection Status 31 1 read-only P4 Glitch or Debouncing Filter Selection Status 4 1 read-only P5 Glitch or Debouncing Filter Selection Status 5 1 read-only P6 Glitch or Debouncing Filter Selection Status 6 1 read-only P7 Glitch or Debouncing Filter Selection Status 7 1 read-only P8 Glitch or Debouncing Filter Selection Status 8 1 read-only P9 Glitch or Debouncing Filter Selection Status 9 1 read-only IFSR Glitch Input Filter Status Register 0x28 32 read-only n 0x0 0x0 P0 Input Filter Status 0 1 read-only P1 Input Filter Status 1 1 read-only P10 Input Filter Status 10 1 read-only P11 Input Filter Status 11 1 read-only P12 Input Filter Status 12 1 read-only P13 Input Filter Status 13 1 read-only P14 Input Filter Status 14 1 read-only P15 Input Filter Status 15 1 read-only P16 Input Filter Status 16 1 read-only P17 Input Filter Status 17 1 read-only P18 Input Filter Status 18 1 read-only P19 Input Filter Status 19 1 read-only P2 Input Filter Status 2 1 read-only P20 Input Filter Status 20 1 read-only P21 Input Filter Status 21 1 read-only P22 Input Filter Status 22 1 read-only P23 Input Filter Status 23 1 read-only P24 Input Filter Status 24 1 read-only P25 Input Filter Status 25 1 read-only P26 Input Filter Status 26 1 read-only P27 Input Filter Status 27 1 read-only P28 Input Filter Status 28 1 read-only P29 Input Filter Status 29 1 read-only P3 Input Filter Status 3 1 read-only P30 Input Filter Status 30 1 read-only P31 Input Filter Status 31 1 read-only P4 Input Filter Status 4 1 read-only P5 Input Filter Status 5 1 read-only P6 Input Filter Status 6 1 read-only P7 Input Filter Status 7 1 read-only P8 Input Filter Status 8 1 read-only P9 Input Filter Status 9 1 read-only IMR Interrupt Mask Register 0x48 32 read-only n 0x0 0x0 P0 Input Change Interrupt Mask 0 1 read-only P1 Input Change Interrupt Mask 1 1 read-only P10 Input Change Interrupt Mask 10 1 read-only P11 Input Change Interrupt Mask 11 1 read-only P12 Input Change Interrupt Mask 12 1 read-only P13 Input Change Interrupt Mask 13 1 read-only P14 Input Change Interrupt Mask 14 1 read-only P15 Input Change Interrupt Mask 15 1 read-only P16 Input Change Interrupt Mask 16 1 read-only P17 Input Change Interrupt Mask 17 1 read-only P18 Input Change Interrupt Mask 18 1 read-only P19 Input Change Interrupt Mask 19 1 read-only P2 Input Change Interrupt Mask 2 1 read-only P20 Input Change Interrupt Mask 20 1 read-only P21 Input Change Interrupt Mask 21 1 read-only P22 Input Change Interrupt Mask 22 1 read-only P23 Input Change Interrupt Mask 23 1 read-only P24 Input Change Interrupt Mask 24 1 read-only P25 Input Change Interrupt Mask 25 1 read-only P26 Input Change Interrupt Mask 26 1 read-only P27 Input Change Interrupt Mask 27 1 read-only P28 Input Change Interrupt Mask 28 1 read-only P29 Input Change Interrupt Mask 29 1 read-only P3 Input Change Interrupt Mask 3 1 read-only P30 Input Change Interrupt Mask 30 1 read-only P31 Input Change Interrupt Mask 31 1 read-only P4 Input Change Interrupt Mask 4 1 read-only P5 Input Change Interrupt Mask 5 1 read-only P6 Input Change Interrupt Mask 6 1 read-only P7 Input Change Interrupt Mask 7 1 read-only P8 Input Change Interrupt Mask 8 1 read-only P9 Input Change Interrupt Mask 9 1 read-only ISLR PIO Interrupt Security Level Register 0xC 32 read-write n 0x0 0x0 P0 PIO Interrupt Security Level 0 1 read-write P1 PIO Interrupt Security Level 1 1 read-write P10 PIO Interrupt Security Level 10 1 read-write P11 PIO Interrupt Security Level 11 1 read-write P12 PIO Interrupt Security Level 12 1 read-write P13 PIO Interrupt Security Level 13 1 read-write P14 PIO Interrupt Security Level 14 1 read-write P15 PIO Interrupt Security Level 15 1 read-write P16 PIO Interrupt Security Level 16 1 read-write P17 PIO Interrupt Security Level 17 1 read-write P18 PIO Interrupt Security Level 18 1 read-write P19 PIO Interrupt Security Level 19 1 read-write P2 PIO Interrupt Security Level 2 1 read-write P20 PIO Interrupt Security Level 20 1 read-write P21 PIO Interrupt Security Level 21 1 read-write P22 PIO Interrupt Security Level 22 1 read-write P23 PIO Interrupt Security Level 23 1 read-write P24 PIO Interrupt Security Level 24 1 read-write P25 PIO Interrupt Security Level 25 1 read-write P26 PIO Interrupt Security Level 26 1 read-write P27 PIO Interrupt Security Level 27 1 read-write P28 PIO Interrupt Security Level 28 1 read-write P29 PIO Interrupt Security Level 29 1 read-write P3 PIO Interrupt Security Level 3 1 read-write P30 PIO Interrupt Security Level 30 1 read-write P31 PIO Interrupt Security Level 31 1 read-write P4 PIO Interrupt Security Level 4 1 read-write P5 PIO Interrupt Security Level 5 1 read-write P6 PIO Interrupt Security Level 6 1 read-write P7 PIO Interrupt Security Level 7 1 read-write P8 PIO Interrupt Security Level 8 1 read-write P9 PIO Interrupt Security Level 9 1 read-write ISR Interrupt Status Register 0x4C 32 read-only n 0x0 0x0 P0 Input Change Interrupt Status 0 1 read-only P1 Input Change Interrupt Status 1 1 read-only P10 Input Change Interrupt Status 10 1 read-only P11 Input Change Interrupt Status 11 1 read-only P12 Input Change Interrupt Status 12 1 read-only P13 Input Change Interrupt Status 13 1 read-only P14 Input Change Interrupt Status 14 1 read-only P15 Input Change Interrupt Status 15 1 read-only P16 Input Change Interrupt Status 16 1 read-only P17 Input Change Interrupt Status 17 1 read-only P18 Input Change Interrupt Status 18 1 read-only P19 Input Change Interrupt Status 19 1 read-only P2 Input Change Interrupt Status 2 1 read-only P20 Input Change Interrupt Status 20 1 read-only P21 Input Change Interrupt Status 21 1 read-only P22 Input Change Interrupt Status 22 1 read-only P23 Input Change Interrupt Status 23 1 read-only P24 Input Change Interrupt Status 24 1 read-only P25 Input Change Interrupt Status 25 1 read-only P26 Input Change Interrupt Status 26 1 read-only P27 Input Change Interrupt Status 27 1 read-only P28 Input Change Interrupt Status 28 1 read-only P29 Input Change Interrupt Status 29 1 read-only P3 Input Change Interrupt Status 3 1 read-only P30 Input Change Interrupt Status 30 1 read-only P31 Input Change Interrupt Status 31 1 read-only P4 Input Change Interrupt Status 4 1 read-only P5 Input Change Interrupt Status 5 1 read-only P6 Input Change Interrupt Status 6 1 read-only P7 Input Change Interrupt Status 7 1 read-only P8 Input Change Interrupt Status 8 1 read-only P9 Input Change Interrupt Status 9 1 read-only LSR Level Select Register 0xC4 32 write-only n 0x0 0x0 P0 Level Interrupt Selection 0 1 write-only P1 Level Interrupt Selection 1 1 write-only P10 Level Interrupt Selection 10 1 write-only P11 Level Interrupt Selection 11 1 write-only P12 Level Interrupt Selection 12 1 write-only P13 Level Interrupt Selection 13 1 write-only P14 Level Interrupt Selection 14 1 write-only P15 Level Interrupt Selection 15 1 write-only P16 Level Interrupt Selection 16 1 write-only P17 Level Interrupt Selection 17 1 write-only P18 Level Interrupt Selection 18 1 write-only P19 Level Interrupt Selection 19 1 write-only P2 Level Interrupt Selection 2 1 write-only P20 Level Interrupt Selection 20 1 write-only P21 Level Interrupt Selection 21 1 write-only P22 Level Interrupt Selection 22 1 write-only P23 Level Interrupt Selection 23 1 write-only P24 Level Interrupt Selection 24 1 write-only P25 Level Interrupt Selection 25 1 write-only P26 Level Interrupt Selection 26 1 write-only P27 Level Interrupt Selection 27 1 write-only P28 Level Interrupt Selection 28 1 write-only P29 Level Interrupt Selection 29 1 write-only P3 Level Interrupt Selection 3 1 write-only P30 Level Interrupt Selection 30 1 write-only P31 Level Interrupt Selection 31 1 write-only P4 Level Interrupt Selection 4 1 write-only P5 Level Interrupt Selection 5 1 write-only P6 Level Interrupt Selection 6 1 write-only P7 Level Interrupt Selection 7 1 write-only P8 Level Interrupt Selection 8 1 write-only P9 Level Interrupt Selection 9 1 write-only MDDR Multi-driver Disable Register 0x54 32 write-only n 0x0 0x0 P0 Multi-drive Disable 0 1 write-only P1 Multi-drive Disable 1 1 write-only P10 Multi-drive Disable 10 1 write-only P11 Multi-drive Disable 11 1 write-only P12 Multi-drive Disable 12 1 write-only P13 Multi-drive Disable 13 1 write-only P14 Multi-drive Disable 14 1 write-only P15 Multi-drive Disable 15 1 write-only P16 Multi-drive Disable 16 1 write-only P17 Multi-drive Disable 17 1 write-only P18 Multi-drive Disable 18 1 write-only P19 Multi-drive Disable 19 1 write-only P2 Multi-drive Disable 2 1 write-only P20 Multi-drive Disable 20 1 write-only P21 Multi-drive Disable 21 1 write-only P22 Multi-drive Disable 22 1 write-only P23 Multi-drive Disable 23 1 write-only P24 Multi-drive Disable 24 1 write-only P25 Multi-drive Disable 25 1 write-only P26 Multi-drive Disable 26 1 write-only P27 Multi-drive Disable 27 1 write-only P28 Multi-drive Disable 28 1 write-only P29 Multi-drive Disable 29 1 write-only P3 Multi-drive Disable 3 1 write-only P30 Multi-drive Disable 30 1 write-only P31 Multi-drive Disable 31 1 write-only P4 Multi-drive Disable 4 1 write-only P5 Multi-drive Disable 5 1 write-only P6 Multi-drive Disable 6 1 write-only P7 Multi-drive Disable 7 1 write-only P8 Multi-drive Disable 8 1 write-only P9 Multi-drive Disable 9 1 write-only MDER Multi-driver Enable Register 0x50 32 write-only n 0x0 0x0 P0 Multi-drive Enable 0 1 write-only P1 Multi-drive Enable 1 1 write-only P10 Multi-drive Enable 10 1 write-only P11 Multi-drive Enable 11 1 write-only P12 Multi-drive Enable 12 1 write-only P13 Multi-drive Enable 13 1 write-only P14 Multi-drive Enable 14 1 write-only P15 Multi-drive Enable 15 1 write-only P16 Multi-drive Enable 16 1 write-only P17 Multi-drive Enable 17 1 write-only P18 Multi-drive Enable 18 1 write-only P19 Multi-drive Enable 19 1 write-only P2 Multi-drive Enable 2 1 write-only P20 Multi-drive Enable 20 1 write-only P21 Multi-drive Enable 21 1 write-only P22 Multi-drive Enable 22 1 write-only P23 Multi-drive Enable 23 1 write-only P24 Multi-drive Enable 24 1 write-only P25 Multi-drive Enable 25 1 write-only P26 Multi-drive Enable 26 1 write-only P27 Multi-drive Enable 27 1 write-only P28 Multi-drive Enable 28 1 write-only P29 Multi-drive Enable 29 1 write-only P3 Multi-drive Enable 3 1 write-only P30 Multi-drive Enable 30 1 write-only P31 Multi-drive Enable 31 1 write-only P4 Multi-drive Enable 4 1 write-only P5 Multi-drive Enable 5 1 write-only P6 Multi-drive Enable 6 1 write-only P7 Multi-drive Enable 7 1 write-only P8 Multi-drive Enable 8 1 write-only P9 Multi-drive Enable 9 1 write-only MDSR Multi-driver Status Register 0x58 32 read-only n 0x0 0x0 P0 Multi-drive Status 0 1 read-only P1 Multi-drive Status 1 1 read-only P10 Multi-drive Status 10 1 read-only P11 Multi-drive Status 11 1 read-only P12 Multi-drive Status 12 1 read-only P13 Multi-drive Status 13 1 read-only P14 Multi-drive Status 14 1 read-only P15 Multi-drive Status 15 1 read-only P16 Multi-drive Status 16 1 read-only P17 Multi-drive Status 17 1 read-only P18 Multi-drive Status 18 1 read-only P19 Multi-drive Status 19 1 read-only P2 Multi-drive Status 2 1 read-only P20 Multi-drive Status 20 1 read-only P21 Multi-drive Status 21 1 read-only P22 Multi-drive Status 22 1 read-only P23 Multi-drive Status 23 1 read-only P24 Multi-drive Status 24 1 read-only P25 Multi-drive Status 25 1 read-only P26 Multi-drive Status 26 1 read-only P27 Multi-drive Status 27 1 read-only P28 Multi-drive Status 28 1 read-only P29 Multi-drive Status 29 1 read-only P3 Multi-drive Status 3 1 read-only P30 Multi-drive Status 30 1 read-only P31 Multi-drive Status 31 1 read-only P4 Multi-drive Status 4 1 read-only P5 Multi-drive Status 5 1 read-only P6 Multi-drive Status 6 1 read-only P7 Multi-drive Status 7 1 read-only P8 Multi-drive Status 8 1 read-only P9 Multi-drive Status 9 1 read-only ODR Output Disable Register 0x14 32 write-only n 0x0 0x0 P0 Output Disable 0 1 write-only P1 Output Disable 1 1 write-only P10 Output Disable 10 1 write-only P11 Output Disable 11 1 write-only P12 Output Disable 12 1 write-only P13 Output Disable 13 1 write-only P14 Output Disable 14 1 write-only P15 Output Disable 15 1 write-only P16 Output Disable 16 1 write-only P17 Output Disable 17 1 write-only P18 Output Disable 18 1 write-only P19 Output Disable 19 1 write-only P2 Output Disable 2 1 write-only P20 Output Disable 20 1 write-only P21 Output Disable 21 1 write-only P22 Output Disable 22 1 write-only P23 Output Disable 23 1 write-only P24 Output Disable 24 1 write-only P25 Output Disable 25 1 write-only P26 Output Disable 26 1 write-only P27 Output Disable 27 1 write-only P28 Output Disable 28 1 write-only P29 Output Disable 29 1 write-only P3 Output Disable 3 1 write-only P30 Output Disable 30 1 write-only P31 Output Disable 31 1 write-only P4 Output Disable 4 1 write-only P5 Output Disable 5 1 write-only P6 Output Disable 6 1 write-only P7 Output Disable 7 1 write-only P8 Output Disable 8 1 write-only P9 Output Disable 9 1 write-only ODSR Output Data Status Register 0x38 32 read-write n 0x0 0x0 P0 Output Data Status 0 1 read-write P1 Output Data Status 1 1 read-write P10 Output Data Status 10 1 read-write P11 Output Data Status 11 1 read-write P12 Output Data Status 12 1 read-write P13 Output Data Status 13 1 read-write P14 Output Data Status 14 1 read-write P15 Output Data Status 15 1 read-write P16 Output Data Status 16 1 read-write P17 Output Data Status 17 1 read-write P18 Output Data Status 18 1 read-write P19 Output Data Status 19 1 read-write P2 Output Data Status 2 1 read-write P20 Output Data Status 20 1 read-write P21 Output Data Status 21 1 read-write P22 Output Data Status 22 1 read-write P23 Output Data Status 23 1 read-write P24 Output Data Status 24 1 read-write P25 Output Data Status 25 1 read-write P26 Output Data Status 26 1 read-write P27 Output Data Status 27 1 read-write P28 Output Data Status 28 1 read-write P29 Output Data Status 29 1 read-write P3 Output Data Status 3 1 read-write P30 Output Data Status 30 1 read-write P31 Output Data Status 31 1 read-write P4 Output Data Status 4 1 read-write P5 Output Data Status 5 1 read-write P6 Output Data Status 6 1 read-write P7 Output Data Status 7 1 read-write P8 Output Data Status 8 1 read-write P9 Output Data Status 9 1 read-write OER Output Enable Register 0x10 32 write-only n 0x0 0x0 P0 Output Enable 0 1 write-only P1 Output Enable 1 1 write-only P10 Output Enable 10 1 write-only P11 Output Enable 11 1 write-only P12 Output Enable 12 1 write-only P13 Output Enable 13 1 write-only P14 Output Enable 14 1 write-only P15 Output Enable 15 1 write-only P16 Output Enable 16 1 write-only P17 Output Enable 17 1 write-only P18 Output Enable 18 1 write-only P19 Output Enable 19 1 write-only P2 Output Enable 2 1 write-only P20 Output Enable 20 1 write-only P21 Output Enable 21 1 write-only P22 Output Enable 22 1 write-only P23 Output Enable 23 1 write-only P24 Output Enable 24 1 write-only P25 Output Enable 25 1 write-only P26 Output Enable 26 1 write-only P27 Output Enable 27 1 write-only P28 Output Enable 28 1 write-only P29 Output Enable 29 1 write-only P3 Output Enable 3 1 write-only P30 Output Enable 30 1 write-only P31 Output Enable 31 1 write-only P4 Output Enable 4 1 write-only P5 Output Enable 5 1 write-only P6 Output Enable 6 1 write-only P7 Output Enable 7 1 write-only P8 Output Enable 8 1 write-only P9 Output Enable 9 1 write-only OSR Output Status Register 0x18 32 read-only n 0x0 0x0 P0 Output Status 0 1 read-only P1 Output Status 1 1 read-only P10 Output Status 10 1 read-only P11 Output Status 11 1 read-only P12 Output Status 12 1 read-only P13 Output Status 13 1 read-only P14 Output Status 14 1 read-only P15 Output Status 15 1 read-only P16 Output Status 16 1 read-only P17 Output Status 17 1 read-only P18 Output Status 18 1 read-only P19 Output Status 19 1 read-only P2 Output Status 2 1 read-only P20 Output Status 20 1 read-only P21 Output Status 21 1 read-only P22 Output Status 22 1 read-only P23 Output Status 23 1 read-only P24 Output Status 24 1 read-only P25 Output Status 25 1 read-only P26 Output Status 26 1 read-only P27 Output Status 27 1 read-only P28 Output Status 28 1 read-only P29 Output Status 29 1 read-only P3 Output Status 3 1 read-only P30 Output Status 30 1 read-only P31 Output Status 31 1 read-only P4 Output Status 4 1 read-only P5 Output Status 5 1 read-only P6 Output Status 6 1 read-only P7 Output Status 7 1 read-only P8 Output Status 8 1 read-only P9 Output Status 9 1 read-only OWDR Output Write Disable 0xA4 32 write-only n 0x0 0x0 P0 Output Write Disable 0 1 write-only P1 Output Write Disable 1 1 write-only P10 Output Write Disable 10 1 write-only P11 Output Write Disable 11 1 write-only P12 Output Write Disable 12 1 write-only P13 Output Write Disable 13 1 write-only P14 Output Write Disable 14 1 write-only P15 Output Write Disable 15 1 write-only P16 Output Write Disable 16 1 write-only P17 Output Write Disable 17 1 write-only P18 Output Write Disable 18 1 write-only P19 Output Write Disable 19 1 write-only P2 Output Write Disable 2 1 write-only P20 Output Write Disable 20 1 write-only P21 Output Write Disable 21 1 write-only P22 Output Write Disable 22 1 write-only P23 Output Write Disable 23 1 write-only P24 Output Write Disable 24 1 write-only P25 Output Write Disable 25 1 write-only P26 Output Write Disable 26 1 write-only P27 Output Write Disable 27 1 write-only P28 Output Write Disable 28 1 write-only P29 Output Write Disable 29 1 write-only P3 Output Write Disable 3 1 write-only P30 Output Write Disable 30 1 write-only P31 Output Write Disable 31 1 write-only P4 Output Write Disable 4 1 write-only P5 Output Write Disable 5 1 write-only P6 Output Write Disable 6 1 write-only P7 Output Write Disable 7 1 write-only P8 Output Write Disable 8 1 write-only P9 Output Write Disable 9 1 write-only OWER Output Write Enable 0xA0 32 write-only n 0x0 0x0 P0 Output Write Enable 0 1 write-only P1 Output Write Enable 1 1 write-only P10 Output Write Enable 10 1 write-only P11 Output Write Enable 11 1 write-only P12 Output Write Enable 12 1 write-only P13 Output Write Enable 13 1 write-only P14 Output Write Enable 14 1 write-only P15 Output Write Enable 15 1 write-only P16 Output Write Enable 16 1 write-only P17 Output Write Enable 17 1 write-only P18 Output Write Enable 18 1 write-only P19 Output Write Enable 19 1 write-only P2 Output Write Enable 2 1 write-only P20 Output Write Enable 20 1 write-only P21 Output Write Enable 21 1 write-only P22 Output Write Enable 22 1 write-only P23 Output Write Enable 23 1 write-only P24 Output Write Enable 24 1 write-only P25 Output Write Enable 25 1 write-only P26 Output Write Enable 26 1 write-only P27 Output Write Enable 27 1 write-only P28 Output Write Enable 28 1 write-only P29 Output Write Enable 29 1 write-only P3 Output Write Enable 3 1 write-only P30 Output Write Enable 30 1 write-only P31 Output Write Enable 31 1 write-only P4 Output Write Enable 4 1 write-only P5 Output Write Enable 5 1 write-only P6 Output Write Enable 6 1 write-only P7 Output Write Enable 7 1 write-only P8 Output Write Enable 8 1 write-only P9 Output Write Enable 9 1 write-only OWSR Output Write Status Register 0xA8 32 read-only n 0x0 0x0 P0 Output Write Status 0 1 read-only P1 Output Write Status 1 1 read-only P10 Output Write Status 10 1 read-only P11 Output Write Status 11 1 read-only P12 Output Write Status 12 1 read-only P13 Output Write Status 13 1 read-only P14 Output Write Status 14 1 read-only P15 Output Write Status 15 1 read-only P16 Output Write Status 16 1 read-only P17 Output Write Status 17 1 read-only P18 Output Write Status 18 1 read-only P19 Output Write Status 19 1 read-only P2 Output Write Status 2 1 read-only P20 Output Write Status 20 1 read-only P21 Output Write Status 21 1 read-only P22 Output Write Status 22 1 read-only P23 Output Write Status 23 1 read-only P24 Output Write Status 24 1 read-only P25 Output Write Status 25 1 read-only P26 Output Write Status 26 1 read-only P27 Output Write Status 27 1 read-only P28 Output Write Status 28 1 read-only P29 Output Write Status 29 1 read-only P3 Output Write Status 3 1 read-only P30 Output Write Status 30 1 read-only P31 Output Write Status 31 1 read-only P4 Output Write Status 4 1 read-only P5 Output Write Status 5 1 read-only P6 Output Write Status 6 1 read-only P7 Output Write Status 7 1 read-only P8 Output Write Status 8 1 read-only P9 Output Write Status 9 1 read-only PDR PIO Disable Register 0x4 32 write-only n 0x0 0x0 P0 PIO Disable 0 1 write-only P1 PIO Disable 1 1 write-only P10 PIO Disable 10 1 write-only P11 PIO Disable 11 1 write-only P12 PIO Disable 12 1 write-only P13 PIO Disable 13 1 write-only P14 PIO Disable 14 1 write-only P15 PIO Disable 15 1 write-only P16 PIO Disable 16 1 write-only P17 PIO Disable 17 1 write-only P18 PIO Disable 18 1 write-only P19 PIO Disable 19 1 write-only P2 PIO Disable 2 1 write-only P20 PIO Disable 20 1 write-only P21 PIO Disable 21 1 write-only P22 PIO Disable 22 1 write-only P23 PIO Disable 23 1 write-only P24 PIO Disable 24 1 write-only P25 PIO Disable 25 1 write-only P26 PIO Disable 26 1 write-only P27 PIO Disable 27 1 write-only P28 PIO Disable 28 1 write-only P29 PIO Disable 29 1 write-only P3 PIO Disable 3 1 write-only P30 PIO Disable 30 1 write-only P31 PIO Disable 31 1 write-only P4 PIO Disable 4 1 write-only P5 PIO Disable 5 1 write-only P6 PIO Disable 6 1 write-only P7 PIO Disable 7 1 write-only P8 PIO Disable 8 1 write-only P9 PIO Disable 9 1 write-only PDSR Pin Data Status Register 0x3C 32 read-only n 0x0 0x0 P0 Output Data Status 0 1 read-only P1 Output Data Status 1 1 read-only P10 Output Data Status 10 1 read-only P11 Output Data Status 11 1 read-only P12 Output Data Status 12 1 read-only P13 Output Data Status 13 1 read-only P14 Output Data Status 14 1 read-only P15 Output Data Status 15 1 read-only P16 Output Data Status 16 1 read-only P17 Output Data Status 17 1 read-only P18 Output Data Status 18 1 read-only P19 Output Data Status 19 1 read-only P2 Output Data Status 2 1 read-only P20 Output Data Status 20 1 read-only P21 Output Data Status 21 1 read-only P22 Output Data Status 22 1 read-only P23 Output Data Status 23 1 read-only P24 Output Data Status 24 1 read-only P25 Output Data Status 25 1 read-only P26 Output Data Status 26 1 read-only P27 Output Data Status 27 1 read-only P28 Output Data Status 28 1 read-only P29 Output Data Status 29 1 read-only P3 Output Data Status 3 1 read-only P30 Output Data Status 30 1 read-only P31 Output Data Status 31 1 read-only P4 Output Data Status 4 1 read-only P5 Output Data Status 5 1 read-only P6 Output Data Status 6 1 read-only P7 Output Data Status 7 1 read-only P8 Output Data Status 8 1 read-only P9 Output Data Status 9 1 read-only PER PIO Enable Register 0x0 32 write-only n 0x0 0x0 P0 PIO Enable 0 1 write-only P1 PIO Enable 1 1 write-only P10 PIO Enable 10 1 write-only P11 PIO Enable 11 1 write-only P12 PIO Enable 12 1 write-only P13 PIO Enable 13 1 write-only P14 PIO Enable 14 1 write-only P15 PIO Enable 15 1 write-only P16 PIO Enable 16 1 write-only P17 PIO Enable 17 1 write-only P18 PIO Enable 18 1 write-only P19 PIO Enable 19 1 write-only P2 PIO Enable 2 1 write-only P20 PIO Enable 20 1 write-only P21 PIO Enable 21 1 write-only P22 PIO Enable 22 1 write-only P23 PIO Enable 23 1 write-only P24 PIO Enable 24 1 write-only P25 PIO Enable 25 1 write-only P26 PIO Enable 26 1 write-only P27 PIO Enable 27 1 write-only P28 PIO Enable 28 1 write-only P29 PIO Enable 29 1 write-only P3 PIO Enable 3 1 write-only P30 PIO Enable 30 1 write-only P31 PIO Enable 31 1 write-only P4 PIO Enable 4 1 write-only P5 PIO Enable 5 1 write-only P6 PIO Enable 6 1 write-only P7 PIO Enable 7 1 write-only P8 PIO Enable 8 1 write-only P9 PIO Enable 9 1 write-only PPDDR Pad Pull-Down Disable Register 0x90 32 write-only n 0x0 0x0 P0 Pull-Down Disable 0 1 write-only P1 Pull-Down Disable 1 1 write-only P10 Pull-Down Disable 10 1 write-only P11 Pull-Down Disable 11 1 write-only P12 Pull-Down Disable 12 1 write-only P13 Pull-Down Disable 13 1 write-only P14 Pull-Down Disable 14 1 write-only P15 Pull-Down Disable 15 1 write-only P16 Pull-Down Disable 16 1 write-only P17 Pull-Down Disable 17 1 write-only P18 Pull-Down Disable 18 1 write-only P19 Pull-Down Disable 19 1 write-only P2 Pull-Down Disable 2 1 write-only P20 Pull-Down Disable 20 1 write-only P21 Pull-Down Disable 21 1 write-only P22 Pull-Down Disable 22 1 write-only P23 Pull-Down Disable 23 1 write-only P24 Pull-Down Disable 24 1 write-only P25 Pull-Down Disable 25 1 write-only P26 Pull-Down Disable 26 1 write-only P27 Pull-Down Disable 27 1 write-only P28 Pull-Down Disable 28 1 write-only P29 Pull-Down Disable 29 1 write-only P3 Pull-Down Disable 3 1 write-only P30 Pull-Down Disable 30 1 write-only P31 Pull-Down Disable 31 1 write-only P4 Pull-Down Disable 4 1 write-only P5 Pull-Down Disable 5 1 write-only P6 Pull-Down Disable 6 1 write-only P7 Pull-Down Disable 7 1 write-only P8 Pull-Down Disable 8 1 write-only P9 Pull-Down Disable 9 1 write-only PPDER Pad Pull-Down Enable Register 0x94 32 write-only n 0x0 0x0 P0 Pull-Down Enable 0 1 write-only P1 Pull-Down Enable 1 1 write-only P10 Pull-Down Enable 10 1 write-only P11 Pull-Down Enable 11 1 write-only P12 Pull-Down Enable 12 1 write-only P13 Pull-Down Enable 13 1 write-only P14 Pull-Down Enable 14 1 write-only P15 Pull-Down Enable 15 1 write-only P16 Pull-Down Enable 16 1 write-only P17 Pull-Down Enable 17 1 write-only P18 Pull-Down Enable 18 1 write-only P19 Pull-Down Enable 19 1 write-only P2 Pull-Down Enable 2 1 write-only P20 Pull-Down Enable 20 1 write-only P21 Pull-Down Enable 21 1 write-only P22 Pull-Down Enable 22 1 write-only P23 Pull-Down Enable 23 1 write-only P24 Pull-Down Enable 24 1 write-only P25 Pull-Down Enable 25 1 write-only P26 Pull-Down Enable 26 1 write-only P27 Pull-Down Enable 27 1 write-only P28 Pull-Down Enable 28 1 write-only P29 Pull-Down Enable 29 1 write-only P3 Pull-Down Enable 3 1 write-only P30 Pull-Down Enable 30 1 write-only P31 Pull-Down Enable 31 1 write-only P4 Pull-Down Enable 4 1 write-only P5 Pull-Down Enable 5 1 write-only P6 Pull-Down Enable 6 1 write-only P7 Pull-Down Enable 7 1 write-only P8 Pull-Down Enable 8 1 write-only P9 Pull-Down Enable 9 1 write-only PPDSR Pad Pull-Down Status Register 0x98 32 read-only n 0x0 0x0 P0 Pull-Down Status 0 1 read-only P1 Pull-Down Status 1 1 read-only P10 Pull-Down Status 10 1 read-only P11 Pull-Down Status 11 1 read-only P12 Pull-Down Status 12 1 read-only P13 Pull-Down Status 13 1 read-only P14 Pull-Down Status 14 1 read-only P15 Pull-Down Status 15 1 read-only P16 Pull-Down Status 16 1 read-only P17 Pull-Down Status 17 1 read-only P18 Pull-Down Status 18 1 read-only P19 Pull-Down Status 19 1 read-only P2 Pull-Down Status 2 1 read-only P20 Pull-Down Status 20 1 read-only P21 Pull-Down Status 21 1 read-only P22 Pull-Down Status 22 1 read-only P23 Pull-Down Status 23 1 read-only P24 Pull-Down Status 24 1 read-only P25 Pull-Down Status 25 1 read-only P26 Pull-Down Status 26 1 read-only P27 Pull-Down Status 27 1 read-only P28 Pull-Down Status 28 1 read-only P29 Pull-Down Status 29 1 read-only P3 Pull-Down Status 3 1 read-only P30 Pull-Down Status 30 1 read-only P31 Pull-Down Status 31 1 read-only P4 Pull-Down Status 4 1 read-only P5 Pull-Down Status 5 1 read-only P6 Pull-Down Status 6 1 read-only P7 Pull-Down Status 7 1 read-only P8 Pull-Down Status 8 1 read-only P9 Pull-Down Status 9 1 read-only PSR PIO Status Register 0x8 32 read-only n 0x0 0x0 P0 PIO Status 0 1 read-only P1 PIO Status 1 1 read-only P10 PIO Status 10 1 read-only P11 PIO Status 11 1 read-only P12 PIO Status 12 1 read-only P13 PIO Status 13 1 read-only P14 PIO Status 14 1 read-only P15 PIO Status 15 1 read-only P16 PIO Status 16 1 read-only P17 PIO Status 17 1 read-only P18 PIO Status 18 1 read-only P19 PIO Status 19 1 read-only P2 PIO Status 2 1 read-only P20 PIO Status 20 1 read-only P21 PIO Status 21 1 read-only P22 PIO Status 22 1 read-only P23 PIO Status 23 1 read-only P24 PIO Status 24 1 read-only P25 PIO Status 25 1 read-only P26 PIO Status 26 1 read-only P27 PIO Status 27 1 read-only P28 PIO Status 28 1 read-only P29 PIO Status 29 1 read-only P3 PIO Status 3 1 read-only P30 PIO Status 30 1 read-only P31 PIO Status 31 1 read-only P4 PIO Status 4 1 read-only P5 PIO Status 5 1 read-only P6 PIO Status 6 1 read-only P7 PIO Status 7 1 read-only P8 PIO Status 8 1 read-only P9 PIO Status 9 1 read-only PUDR Pull-Up Disable Register 0x60 32 write-only n 0x0 0x0 P0 Pull-Up Disable 0 1 write-only P1 Pull-Up Disable 1 1 write-only P10 Pull-Up Disable 10 1 write-only P11 Pull-Up Disable 11 1 write-only P12 Pull-Up Disable 12 1 write-only P13 Pull-Up Disable 13 1 write-only P14 Pull-Up Disable 14 1 write-only P15 Pull-Up Disable 15 1 write-only P16 Pull-Up Disable 16 1 write-only P17 Pull-Up Disable 17 1 write-only P18 Pull-Up Disable 18 1 write-only P19 Pull-Up Disable 19 1 write-only P2 Pull-Up Disable 2 1 write-only P20 Pull-Up Disable 20 1 write-only P21 Pull-Up Disable 21 1 write-only P22 Pull-Up Disable 22 1 write-only P23 Pull-Up Disable 23 1 write-only P24 Pull-Up Disable 24 1 write-only P25 Pull-Up Disable 25 1 write-only P26 Pull-Up Disable 26 1 write-only P27 Pull-Up Disable 27 1 write-only P28 Pull-Up Disable 28 1 write-only P29 Pull-Up Disable 29 1 write-only P3 Pull-Up Disable 3 1 write-only P30 Pull-Up Disable 30 1 write-only P31 Pull-Up Disable 31 1 write-only P4 Pull-Up Disable 4 1 write-only P5 Pull-Up Disable 5 1 write-only P6 Pull-Up Disable 6 1 write-only P7 Pull-Up Disable 7 1 write-only P8 Pull-Up Disable 8 1 write-only P9 Pull-Up Disable 9 1 write-only PUER Pull-Up Enable Register 0x64 32 write-only n 0x0 0x0 P0 Pull-Up Enable 0 1 write-only P1 Pull-Up Enable 1 1 write-only P10 Pull-Up Enable 10 1 write-only P11 Pull-Up Enable 11 1 write-only P12 Pull-Up Enable 12 1 write-only P13 Pull-Up Enable 13 1 write-only P14 Pull-Up Enable 14 1 write-only P15 Pull-Up Enable 15 1 write-only P16 Pull-Up Enable 16 1 write-only P17 Pull-Up Enable 17 1 write-only P18 Pull-Up Enable 18 1 write-only P19 Pull-Up Enable 19 1 write-only P2 Pull-Up Enable 2 1 write-only P20 Pull-Up Enable 20 1 write-only P21 Pull-Up Enable 21 1 write-only P22 Pull-Up Enable 22 1 write-only P23 Pull-Up Enable 23 1 write-only P24 Pull-Up Enable 24 1 write-only P25 Pull-Up Enable 25 1 write-only P26 Pull-Up Enable 26 1 write-only P27 Pull-Up Enable 27 1 write-only P28 Pull-Up Enable 28 1 write-only P29 Pull-Up Enable 29 1 write-only P3 Pull-Up Enable 3 1 write-only P30 Pull-Up Enable 30 1 write-only P31 Pull-Up Enable 31 1 write-only P4 Pull-Up Enable 4 1 write-only P5 Pull-Up Enable 5 1 write-only P6 Pull-Up Enable 6 1 write-only P7 Pull-Up Enable 7 1 write-only P8 Pull-Up Enable 8 1 write-only P9 Pull-Up Enable 9 1 write-only PUSR Pad Pull-Up Status Register 0x68 32 read-only n 0x0 0x0 P0 Pull-Up Status 0 1 read-only P1 Pull-Up Status 1 1 read-only P10 Pull-Up Status 10 1 read-only P11 Pull-Up Status 11 1 read-only P12 Pull-Up Status 12 1 read-only P13 Pull-Up Status 13 1 read-only P14 Pull-Up Status 14 1 read-only P15 Pull-Up Status 15 1 read-only P16 Pull-Up Status 16 1 read-only P17 Pull-Up Status 17 1 read-only P18 Pull-Up Status 18 1 read-only P19 Pull-Up Status 19 1 read-only P2 Pull-Up Status 2 1 read-only P20 Pull-Up Status 20 1 read-only P21 Pull-Up Status 21 1 read-only P22 Pull-Up Status 22 1 read-only P23 Pull-Up Status 23 1 read-only P24 Pull-Up Status 24 1 read-only P25 Pull-Up Status 25 1 read-only P26 Pull-Up Status 26 1 read-only P27 Pull-Up Status 27 1 read-only P28 Pull-Up Status 28 1 read-only P29 Pull-Up Status 29 1 read-only P3 Pull-Up Status 3 1 read-only P30 Pull-Up Status 30 1 read-only P31 Pull-Up Status 31 1 read-only P4 Pull-Up Status 4 1 read-only P5 Pull-Up Status 5 1 read-only P6 Pull-Up Status 6 1 read-only P7 Pull-Up Status 7 1 read-only P8 Pull-Up Status 8 1 read-only P9 Pull-Up Status 9 1 read-only REHLSR Rising Edge/High-Level Select Register 0xD4 32 write-only n 0x0 0x0 P0 Rising Edge/High-Level Interrupt Selection 0 1 write-only P1 Rising Edge/High-Level Interrupt Selection 1 1 write-only P10 Rising Edge/High-Level Interrupt Selection 10 1 write-only P11 Rising Edge/High-Level Interrupt Selection 11 1 write-only P12 Rising Edge/High-Level Interrupt Selection 12 1 write-only P13 Rising Edge/High-Level Interrupt Selection 13 1 write-only P14 Rising Edge/High-Level Interrupt Selection 14 1 write-only P15 Rising Edge/High-Level Interrupt Selection 15 1 write-only P16 Rising Edge/High-Level Interrupt Selection 16 1 write-only P17 Rising Edge/High-Level Interrupt Selection 17 1 write-only P18 Rising Edge/High-Level Interrupt Selection 18 1 write-only P19 Rising Edge/High-Level Interrupt Selection 19 1 write-only P2 Rising Edge/High-Level Interrupt Selection 2 1 write-only P20 Rising Edge/High-Level Interrupt Selection 20 1 write-only P21 Rising Edge/High-Level Interrupt Selection 21 1 write-only P22 Rising Edge/High-Level Interrupt Selection 22 1 write-only P23 Rising Edge/High-Level Interrupt Selection 23 1 write-only P24 Rising Edge/High-Level Interrupt Selection 24 1 write-only P25 Rising Edge/High-Level Interrupt Selection 25 1 write-only P26 Rising Edge/High-Level Interrupt Selection 26 1 write-only P27 Rising Edge/High-Level Interrupt Selection 27 1 write-only P28 Rising Edge/High-Level Interrupt Selection 28 1 write-only P29 Rising Edge/High-Level Interrupt Selection 29 1 write-only P3 Rising Edge/High-Level Interrupt Selection 3 1 write-only P30 Rising Edge/High-Level Interrupt Selection 30 1 write-only P31 Rising Edge/High-Level Interrupt Selection 31 1 write-only P4 Rising Edge/High-Level Interrupt Selection 4 1 write-only P5 Rising Edge/High-Level Interrupt Selection 5 1 write-only P6 Rising Edge/High-Level Interrupt Selection 6 1 write-only P7 Rising Edge/High-Level Interrupt Selection 7 1 write-only P8 Rising Edge/High-Level Interrupt Selection 8 1 write-only P9 Rising Edge/High-Level Interrupt Selection 9 1 write-only SCDR Slow Clock Divider Debouncing Register 0x8C 32 read-write n 0x0 0x0 DIV Slow Clock Divider Selection for Debouncing 0 14 read-write SCHMITT Schmitt Trigger Register 0x100 32 read-write n 0x0 0x0 SCHMITT0 Schmitt Trigger Control 0 1 read-write SCHMITT1 Schmitt Trigger Control 1 1 read-write SCHMITT10 Schmitt Trigger Control 10 1 read-write SCHMITT11 Schmitt Trigger Control 11 1 read-write SCHMITT12 Schmitt Trigger Control 12 1 read-write SCHMITT13 Schmitt Trigger Control 13 1 read-write SCHMITT14 Schmitt Trigger Control 14 1 read-write SCHMITT15 Schmitt Trigger Control 15 1 read-write SCHMITT16 Schmitt Trigger Control 16 1 read-write SCHMITT17 Schmitt Trigger Control 17 1 read-write SCHMITT18 Schmitt Trigger Control 18 1 read-write SCHMITT19 Schmitt Trigger Control 19 1 read-write SCHMITT2 Schmitt Trigger Control 2 1 read-write SCHMITT20 Schmitt Trigger Control 20 1 read-write SCHMITT21 Schmitt Trigger Control 21 1 read-write SCHMITT22 Schmitt Trigger Control 22 1 read-write SCHMITT23 Schmitt Trigger Control 23 1 read-write SCHMITT24 Schmitt Trigger Control 24 1 read-write SCHMITT25 Schmitt Trigger Control 25 1 read-write SCHMITT26 Schmitt Trigger Control 26 1 read-write SCHMITT27 Schmitt Trigger Control 27 1 read-write SCHMITT28 Schmitt Trigger Control 28 1 read-write SCHMITT29 Schmitt Trigger Control 29 1 read-write SCHMITT3 Schmitt Trigger Control 3 1 read-write SCHMITT30 Schmitt Trigger Control 30 1 read-write SCHMITT31 Schmitt Trigger Control 31 1 read-write SCHMITT4 Schmitt Trigger Control 4 1 read-write SCHMITT5 Schmitt Trigger Control 5 1 read-write SCHMITT6 Schmitt Trigger Control 6 1 read-write SCHMITT7 Schmitt Trigger Control 7 1 read-write SCHMITT8 Schmitt Trigger Control 8 1 read-write SCHMITT9 Schmitt Trigger Control 9 1 read-write SODR Set Output Data Register 0x30 32 write-only n 0x0 0x0 P0 Set Output Data 0 1 write-only P1 Set Output Data 1 1 write-only P10 Set Output Data 10 1 write-only P11 Set Output Data 11 1 write-only P12 Set Output Data 12 1 write-only P13 Set Output Data 13 1 write-only P14 Set Output Data 14 1 write-only P15 Set Output Data 15 1 write-only P16 Set Output Data 16 1 write-only P17 Set Output Data 17 1 write-only P18 Set Output Data 18 1 write-only P19 Set Output Data 19 1 write-only P2 Set Output Data 2 1 write-only P20 Set Output Data 20 1 write-only P21 Set Output Data 21 1 write-only P22 Set Output Data 22 1 write-only P23 Set Output Data 23 1 write-only P24 Set Output Data 24 1 write-only P25 Set Output Data 25 1 write-only P26 Set Output Data 26 1 write-only P27 Set Output Data 27 1 write-only P28 Set Output Data 28 1 write-only P29 Set Output Data 29 1 write-only P3 Set Output Data 3 1 write-only P30 Set Output Data 30 1 write-only P31 Set Output Data 31 1 write-only P4 Set Output Data 4 1 write-only P5 Set Output Data 5 1 write-only P6 Set Output Data 6 1 write-only P7 Set Output Data 7 1 write-only P8 Set Output Data 8 1 write-only P9 Set Output Data 9 1 write-only WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 read-write WPKEY Write Protection Key 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 0x50494F WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 read-only WPVSRC Write Protection Violation Source 8 16 read-only PIT Periodic Interval Timer SYSC 0x0 0x0 0x200 registers n MR Mode Register 0x0 32 read-write n 0x0 0x0 PITEN Period Interval Timer Enabled 24 1 read-write PITIEN Periodic Interval Timer Interrupt Enable 25 1 read-write PIV Periodic Interval Value 0 20 read-write PIIR Periodic Interval Image Register 0xC 32 read-only n 0x0 0x0 CPIV Current Periodic Interval Value 0 20 read-only PICNT Periodic Interval Counter 20 12 read-only PIVR Periodic Interval Value Register 0x8 32 read-only n 0x0 0x0 CPIV Current Periodic Interval Value 0 20 read-only PICNT Periodic Interval Counter 20 12 read-only SR Status Register 0x4 32 read-only n 0x0 0x0 PITS Periodic Interval Timer Status 0 1 read-only PMC Power Management Controller PMC 0x0 0x0 0x50 registers n PMC 1 CKGR_MCFR Main Clock Frequency Register 0x24 32 read-write n 0x0 0x0 MAINF Main Clock Frequency 0 16 read-write MAINFRDY Main Clock Frequency Measure Ready 16 1 read-write RCMEAS RC Oscillator Frequency Measure (write-only) 20 1 read-write CKGR_MOR Main Oscillator Register 0x20 32 read-write n 0x0 0x0 CFDEN Clock Failure Detector Enable 25 1 read-write KEY Password 16 8 read-write PASSWD Writing any other value in this field aborts the write operation. 0x37 MOSCSEL Main Clock Oscillator Selection 24 1 read-write MOSCXTBY 12 MHz Crystal Oscillator Bypass 1 1 read-write MOSCXTEN 12 MHz Crystal Oscillator Enable 0 1 read-write MOSCXTST 12 MHz Crystal Oscillator Startup Time 8 8 read-write XT32KFME 32.768 kHz Crystal Oscillator Frequency Monitoring Enable 26 1 read-write CKGR_PLLAR PLLA Register 0x28 32 read-write n 0x0 0x0 DIVA Divider A 0 1 read-write MULA PLLA Multiplier 18 7 read-write ONE Must Be Set to 1 29 1 read-write OUTA PLLA Clock Frequency Range 14 4 read-write PLLACOUNT PLLA Counter 8 6 read-write CKGR_UCKR UTMI Clock Register 0x1C 32 read-write n 0x0 0x0 BIASCOUNT UTMI BIAS Startup Time 28 4 read-write BIASEN UTMI BIAS Enable 24 1 read-write UPLLCOUNT UTMI PLL Startup Time 20 4 read-write UPLLEN UTMI PLL Enable 16 1 read-write FOCR Fault Output Clear Register 0x78 32 write-only n 0x0 0x0 FOCLR Fault Output Clear 0 1 write-only IDR Interrupt Disable Register 0x64 32 write-only n 0x0 0x0 CFDEV Clock Failure Detector Event Interrupt Disable 18 1 write-only LOCKA PLLA Lock Interrupt Disable 1 1 write-only LOCKU UTMI PLL Lock Interrupt Enable 6 1 write-only MCKRDY Master Clock Ready Interrupt Disable 3 1 write-only MOSCSELS Main Oscillator Clock Source Selection Status Interrupt Disable 16 1 write-only MOSCXTS 12 MHz Crystal Oscillator Status Interrupt Disable 0 1 write-only PCKRDY0 Programmable Clock Ready 0 Interrupt Disable 8 1 write-only PCKRDY1 Programmable Clock Ready 1 Interrupt Disable 9 1 write-only PCKRDY2 Programmable Clock Ready 2 Interrupt Disable 10 1 write-only XT32KERR 32.768 kHz Crystal Oscillator Error Interrupt Disable 21 1 write-only IER Interrupt Enable Register 0x60 32 write-only n 0x0 0x0 CFDEV Clock Failure Detector Event Interrupt Enable 18 1 write-only LOCKA PLLA Lock Interrupt Enable 1 1 write-only LOCKU UTMI PLL Lock Interrupt Enable 6 1 write-only MCKRDY Master Clock Ready Interrupt Enable 3 1 write-only MOSCSELS Main Clock Source Oscillator Selection Status Interrupt Enable 16 1 write-only MOSCXTS 12 MHz Crystal Oscillator Status Interrupt Enable 0 1 write-only PCKRDY0 Programmable Clock Ready 0 Interrupt Enable 8 1 write-only PCKRDY1 Programmable Clock Ready 1 Interrupt Enable 9 1 write-only PCKRDY2 Programmable Clock Ready 2 Interrupt Enable 10 1 write-only XT32KERR 32.768 kHz Crystal Oscillator Error Interrupt Enable 21 1 write-only IMR Interrupt Mask Register 0x6C 32 read-only n 0x0 0x0 CFDEV Clock Failure Detector Event Interrupt Mask 18 1 read-only LOCKA PLLA Lock Interrupt Mask 1 1 read-only MCKRDY Master Clock Ready Interrupt Mask 3 1 read-only MOSCSELS Main Oscillator Clock Source Selection Status Interrupt Mask 16 1 read-only MOSCXTS 12 MHz Crystal Oscillator Status Interrupt Mask 0 1 read-only PCKRDY0 Programmable Clock Ready 0 Interrupt Mask 8 1 read-only PCKRDY1 Programmable Clock Ready 1 Interrupt Mask 9 1 read-only PCKRDY2 Programmable Clock Ready 2 Interrupt Mask 10 1 read-only XT32KERR 32.768 kHz Crystal Oscillator Error Interrupt Mask 21 1 read-only MCKR Master Clock Register 0x30 32 read-write n 0x0 0x0 CSS Master/Processor Clock Source Selection 0 2 read-write SLOW_CLK Slow clock is selected 0x0 MAIN_CLK Main clock is selected 0x1 PLLA_CLK PLLACK is selected 0x2 UPLL_CLK UPLL Clock is selected 0x3 H32MXDIV AHB 32-bit Matrix Divisor 24 1 read-write H32MXDIV1 The AHB 32-bit Matrix frequency is equal to the AHB 64-bit Matrix frequency. It is possible only if the AHB 64-bit Matrix frequency does not exceed 100 MHz. 0 H32MXDIV2 The AHB 32-bit Matrix frequency is equal to the AHB 64-bit Matrix frequency divided by 2. 1 MDIV Master Clock Division 8 2 read-write EQ_PCK Master Clock is Prescaler Output Clock divided by 1.Warning: DDRCK is not available. 0x0 PCK_DIV2 Master Clock is Prescaler Output Clock divided by 2. DDRCK is equal to MCK. 0x1 PCK_DIV4 Master Clock is Prescaler Output Clock divided by 4. DDRCK is equal to MCK. 0x2 PCK_DIV3 Master Clock is Prescaler Output Clock divided by 3. DDRCK is equal to MCK. 0x3 PLLADIV2 PLLA Divisor by 2 12 1 read-write PRES Master/Processor Clock Prescaler 4 3 read-write CLOCK Selected clock 0x0 CLOCK_DIV2 Selected clock divided by 2 0x1 CLOCK_DIV4 Selected clock divided by 4 0x2 CLOCK_DIV8 Selected clock divided by 8 0x3 CLOCK_DIV16 Selected clock divided by 16 0x4 CLOCK_DIV32 Selected clock divided by 32 0x5 CLOCK_DIV64 Selected clock divided by 64 0x6 PCDR0 Peripheral Clock Disable Register 0 0x14 32 write-only n 0x0 0x0 PID10 Peripheral Clock 10 Disable 10 1 write-only PID11 Peripheral Clock 11 Disable 11 1 write-only PID12 Peripheral Clock 12 Disable 12 1 write-only PID13 Peripheral Clock 13 Disable 13 1 write-only PID14 Peripheral Clock 14 Disable 14 1 write-only PID15 Peripheral Clock 15 Disable 15 1 write-only PID16 Peripheral Clock 16 Disable 16 1 write-only PID17 Peripheral Clock 17 Disable 17 1 write-only PID18 Peripheral Clock 18 Disable 18 1 write-only PID19 Peripheral Clock 19 Disable 19 1 write-only PID2 Peripheral Clock 2 Disable 2 1 write-only PID20 Peripheral Clock 20 Disable 20 1 write-only PID21 Peripheral Clock 21 Disable 21 1 write-only PID22 Peripheral Clock 22 Disable 22 1 write-only PID23 Peripheral Clock 23 Disable 23 1 write-only PID24 Peripheral Clock 24 Disable 24 1 write-only PID25 Peripheral Clock 25 Disable 25 1 write-only PID26 Peripheral Clock 26 Disable 26 1 write-only PID27 Peripheral Clock 27 Disable 27 1 write-only PID28 Peripheral Clock 28 Disable 28 1 write-only PID29 Peripheral Clock 29 Disable 29 1 write-only PID3 Peripheral Clock 3 Disable 3 1 write-only PID30 Peripheral Clock 30 Disable 30 1 write-only PID31 Peripheral Clock 31 Disable 31 1 write-only PID4 Peripheral Clock 4 Disable 4 1 write-only PID5 Peripheral Clock 5 Disable 5 1 write-only PID6 Peripheral Clock 6 Disable 6 1 write-only PID7 Peripheral Clock 7 Disable 7 1 write-only PID8 Peripheral Clock 8 Disable 8 1 write-only PID9 Peripheral Clock 9 Disable 9 1 write-only PCDR1 Peripheral Clock Disable Register 1 0x104 32 write-only n 0x0 0x0 PID32 Peripheral Clock 32 Disable 0 1 write-only PID33 Peripheral Clock 33 Disable 1 1 write-only PID34 Peripheral Clock 34 Disable 2 1 write-only PID35 Peripheral Clock 35 Disable 3 1 write-only PID36 Peripheral Clock 36 Disable 4 1 write-only PID37 Peripheral Clock 37 Disable 5 1 write-only PID38 Peripheral Clock 38 Disable 6 1 write-only PID39 Peripheral Clock 39 Disable 7 1 write-only PID40 Peripheral Clock 40 Disable 8 1 write-only PID41 Peripheral Clock 41 Disable 9 1 write-only PID42 Peripheral Clock 42 Disable 10 1 write-only PID43 Peripheral Clock 43 Disable 11 1 write-only PID44 Peripheral Clock 44 Disable 12 1 write-only PID45 Peripheral Clock 45 Disable 13 1 write-only PID46 Peripheral Clock 46 Disable 14 1 write-only PID47 Peripheral Clock 47 Disable 15 1 write-only PID48 Peripheral Clock 48 Disable 16 1 write-only PID49 Peripheral Clock 49 Disable 17 1 write-only PID50 Peripheral Clock 50 Disable 18 1 write-only PID51 Peripheral Clock 51 Disable 19 1 write-only PID52 Peripheral Clock 52 Disable 20 1 write-only PID53 Peripheral Clock 53 Disable 21 1 write-only PID54 Peripheral Clock 54 Disable 22 1 write-only PID55 Peripheral Clock 55 Disable 23 1 write-only PID56 Peripheral Clock 56 Disable 24 1 write-only PID57 Peripheral Clock 57 Disable 25 1 write-only PID58 Peripheral Clock 58 Disable 26 1 write-only PID59 Peripheral Clock 59 Disable 27 1 write-only PID60 Peripheral Clock 60 Disable 28 1 write-only PID61 Peripheral Clock 61 Disable 29 1 write-only PID62 Peripheral Clock 62 Disable 30 1 write-only PID63 Peripheral Clock 63 Disable 31 1 write-only PCER0 Peripheral Clock Enable Register 0 0x10 32 write-only n 0x0 0x0 PID10 Peripheral Clock 10 Enable 10 1 write-only PID11 Peripheral Clock 11 Enable 11 1 write-only PID12 Peripheral Clock 12 Enable 12 1 write-only PID13 Peripheral Clock 13 Enable 13 1 write-only PID14 Peripheral Clock 14 Enable 14 1 write-only PID15 Peripheral Clock 15 Enable 15 1 write-only PID16 Peripheral Clock 16 Enable 16 1 write-only PID17 Peripheral Clock 17 Enable 17 1 write-only PID18 Peripheral Clock 18 Enable 18 1 write-only PID19 Peripheral Clock 19 Enable 19 1 write-only PID2 Peripheral Clock 2 Enable 2 1 write-only PID20 Peripheral Clock 20 Enable 20 1 write-only PID21 Peripheral Clock 21 Enable 21 1 write-only PID22 Peripheral Clock 22 Enable 22 1 write-only PID23 Peripheral Clock 23 Enable 23 1 write-only PID24 Peripheral Clock 24 Enable 24 1 write-only PID25 Peripheral Clock 25 Enable 25 1 write-only PID26 Peripheral Clock 26 Enable 26 1 write-only PID27 Peripheral Clock 27 Enable 27 1 write-only PID28 Peripheral Clock 28 Enable 28 1 write-only PID29 Peripheral Clock 29 Enable 29 1 write-only PID3 Peripheral Clock 3 Enable 3 1 write-only PID30 Peripheral Clock 30 Enable 30 1 write-only PID31 Peripheral Clock 31 Enable 31 1 write-only PID4 Peripheral Clock 4 Enable 4 1 write-only PID5 Peripheral Clock 5 Enable 5 1 write-only PID6 Peripheral Clock 6 Enable 6 1 write-only PID7 Peripheral Clock 7 Enable 7 1 write-only PID8 Peripheral Clock 8 Enable 8 1 write-only PID9 Peripheral Clock 9 Enable 9 1 write-only PCER1 Peripheral Clock Enable Register 1 0x100 32 write-only n 0x0 0x0 PID32 Peripheral Clock 32 Enable 0 1 write-only PID33 Peripheral Clock 33 Enable 1 1 write-only PID34 Peripheral Clock 34 Enable 2 1 write-only PID35 Peripheral Clock 35 Enable 3 1 write-only PID36 Peripheral Clock 36 Enable 4 1 write-only PID37 Peripheral Clock 37 Enable 5 1 write-only PID38 Peripheral Clock 38 Enable 6 1 write-only PID39 Peripheral Clock 39 Enable 7 1 write-only PID40 Peripheral Clock 40 Enable 8 1 write-only PID41 Peripheral Clock 41 Enable 9 1 write-only PID42 Peripheral Clock 42 Enable 10 1 write-only PID43 Peripheral Clock 43 Enable 11 1 write-only PID44 Peripheral Clock 44 Enable 12 1 write-only PID45 Peripheral Clock 45 Enable 13 1 write-only PID46 Peripheral Clock 46 Enable 14 1 write-only PID47 Peripheral Clock 47 Enable 15 1 write-only PID48 Peripheral Clock 48 Enable 16 1 write-only PID49 Peripheral Clock 49 Enable 17 1 write-only PID50 Peripheral Clock 50 Enable 18 1 write-only PID51 Peripheral Clock 51 Enable 19 1 write-only PID52 Peripheral Clock 52 Enable 20 1 write-only PID53 Peripheral Clock 53 Enable 21 1 write-only PID54 Peripheral Clock 54 Enable 22 1 write-only PID55 Peripheral Clock 55 Enable 23 1 write-only PID56 Peripheral Clock 56 Enable 24 1 write-only PID57 Peripheral Clock 57 Enable 25 1 write-only PID58 Peripheral Clock 58 Enable 26 1 write-only PID59 Peripheral Clock 59 Enable 27 1 write-only PID60 Peripheral Clock 60 Enable 28 1 write-only PID61 Peripheral Clock 61 Enable 29 1 write-only PID62 Peripheral Clock 62 Enable 30 1 write-only PID63 Peripheral Clock 63 Enable 31 1 write-only PCK0 Programmable Clock 0 Register 0x40 32 read-write n CSS Master Clock Source Selection 0 3 read-write SLOW_CLK Slow clock is selected 0x0 MAIN_CLK Main clock is selected 0x1 PLLA_CLK PLLACK is selected 0x2 UPLL_CLK UPLL Clock is selected 0x3 MCK_CLK Master Clock is selected 0x4 PRES Programmable Clock Prescaler 4 3 read-write CLOCK Selected clock 0x0 CLOCK_DIV2 Selected clock divided by 2 0x1 CLOCK_DIV4 Selected clock divided by 4 0x2 CLOCK_DIV8 Selected clock divided by 8 0x3 CLOCK_DIV16 Selected clock divided by 16 0x4 CLOCK_DIV32 Selected clock divided by 32 0x5 CLOCK_DIV64 Selected clock divided by 64 0x6 PCK1 Programmable Clock 0 Register 0x44 32 read-write n CSS Master Clock Source Selection 0 3 read-write SLOW_CLK Slow clock is selected 0x0 MAIN_CLK Main clock is selected 0x1 PLLA_CLK PLLACK is selected 0x2 UPLL_CLK UPLL Clock is selected 0x3 MCK_CLK Master Clock is selected 0x4 PRES Programmable Clock Prescaler 4 3 read-write CLOCK Selected clock 0x0 CLOCK_DIV2 Selected clock divided by 2 0x1 CLOCK_DIV4 Selected clock divided by 4 0x2 CLOCK_DIV8 Selected clock divided by 8 0x3 CLOCK_DIV16 Selected clock divided by 16 0x4 CLOCK_DIV32 Selected clock divided by 32 0x5 CLOCK_DIV64 Selected clock divided by 64 0x6 PCK2 Programmable Clock 0 Register 0x48 32 read-write n CSS Master Clock Source Selection 0 3 read-write SLOW_CLK Slow clock is selected 0x0 MAIN_CLK Main clock is selected 0x1 PLLA_CLK PLLACK is selected 0x2 UPLL_CLK UPLL Clock is selected 0x3 MCK_CLK Master Clock is selected 0x4 PRES Programmable Clock Prescaler 4 3 read-write CLOCK Selected clock 0x0 CLOCK_DIV2 Selected clock divided by 2 0x1 CLOCK_DIV4 Selected clock divided by 4 0x2 CLOCK_DIV8 Selected clock divided by 8 0x3 CLOCK_DIV16 Selected clock divided by 16 0x4 CLOCK_DIV32 Selected clock divided by 32 0x5 CLOCK_DIV64 Selected clock divided by 64 0x6 PCK[0] Programmable Clock 0 Register 0x80 32 read-write n 0x0 0x0 CSS Master Clock Source Selection 0 3 read-write SLOW_CLK Slow clock is selected 0x0 MAIN_CLK Main clock is selected 0x1 PLLA_CLK PLLACK is selected 0x2 UPLL_CLK UPLL Clock is selected 0x3 MCK_CLK Master Clock is selected 0x4 PRES Programmable Clock Prescaler 4 3 read-write CLOCK Selected clock 0x0 CLOCK_DIV2 Selected clock divided by 2 0x1 CLOCK_DIV4 Selected clock divided by 4 0x2 CLOCK_DIV8 Selected clock divided by 8 0x3 CLOCK_DIV16 Selected clock divided by 16 0x4 CLOCK_DIV32 Selected clock divided by 32 0x5 CLOCK_DIV64 Selected clock divided by 64 0x6 PCK[1] Programmable Clock 0 Register 0xC4 32 read-write n 0x0 0x0 CSS Master Clock Source Selection 0 3 read-write SLOW_CLK Slow clock is selected 0x0 MAIN_CLK Main clock is selected 0x1 PLLA_CLK PLLACK is selected 0x2 UPLL_CLK UPLL Clock is selected 0x3 MCK_CLK Master Clock is selected 0x4 PRES Programmable Clock Prescaler 4 3 read-write CLOCK Selected clock 0x0 CLOCK_DIV2 Selected clock divided by 2 0x1 CLOCK_DIV4 Selected clock divided by 4 0x2 CLOCK_DIV8 Selected clock divided by 8 0x3 CLOCK_DIV16 Selected clock divided by 16 0x4 CLOCK_DIV32 Selected clock divided by 32 0x5 CLOCK_DIV64 Selected clock divided by 64 0x6 PCK[2] Programmable Clock 0 Register 0x10C 32 read-write n 0x0 0x0 CSS Master Clock Source Selection 0 3 read-write SLOW_CLK Slow clock is selected 0x0 MAIN_CLK Main clock is selected 0x1 PLLA_CLK PLLACK is selected 0x2 UPLL_CLK UPLL Clock is selected 0x3 MCK_CLK Master Clock is selected 0x4 PRES Programmable Clock Prescaler 4 3 read-write CLOCK Selected clock 0x0 CLOCK_DIV2 Selected clock divided by 2 0x1 CLOCK_DIV4 Selected clock divided by 4 0x2 CLOCK_DIV8 Selected clock divided by 8 0x3 CLOCK_DIV16 Selected clock divided by 16 0x4 CLOCK_DIV32 Selected clock divided by 32 0x5 CLOCK_DIV64 Selected clock divided by 64 0x6 PCR Peripheral Control Register 0x10C 32 read-write n 0x0 0x0 CMD Command 12 1 read-write EN Enable 28 1 read-write PID Peripheral ID 0 7 read-write PCSR0 Peripheral Clock Status Register 0 0x18 32 read-only n 0x0 0x0 PID10 Peripheral Clock 10 Status 10 1 read-only PID11 Peripheral Clock 11 Status 11 1 read-only PID12 Peripheral Clock 12 Status 12 1 read-only PID13 Peripheral Clock 13 Status 13 1 read-only PID14 Peripheral Clock 14 Status 14 1 read-only PID15 Peripheral Clock 15 Status 15 1 read-only PID16 Peripheral Clock 16 Status 16 1 read-only PID17 Peripheral Clock 17 Status 17 1 read-only PID18 Peripheral Clock 18 Status 18 1 read-only PID19 Peripheral Clock 19 Status 19 1 read-only PID2 Peripheral Clock 2 Status 2 1 read-only PID20 Peripheral Clock 20 Status 20 1 read-only PID21 Peripheral Clock 21 Status 21 1 read-only PID22 Peripheral Clock 22 Status 22 1 read-only PID23 Peripheral Clock 23 Status 23 1 read-only PID24 Peripheral Clock 24 Status 24 1 read-only PID25 Peripheral Clock 25 Status 25 1 read-only PID26 Peripheral Clock 26 Status 26 1 read-only PID27 Peripheral Clock 27 Status 27 1 read-only PID28 Peripheral Clock 28 Status 28 1 read-only PID29 Peripheral Clock 29 Status 29 1 read-only PID3 Peripheral Clock 3 Status 3 1 read-only PID30 Peripheral Clock 30 Status 30 1 read-only PID31 Peripheral Clock 31 Status 31 1 read-only PID4 Peripheral Clock 4 Status 4 1 read-only PID5 Peripheral Clock 5 Status 5 1 read-only PID6 Peripheral Clock 6 Status 6 1 read-only PID7 Peripheral Clock 7 Status 7 1 read-only PID8 Peripheral Clock 8 Status 8 1 read-only PID9 Peripheral Clock 9 Status 9 1 read-only PCSR1 Peripheral Clock Status Register 1 0x108 32 read-only n 0x0 0x0 PID32 Peripheral Clock 32 Status 0 1 read-only PID33 Peripheral Clock 33 Status 1 1 read-only PID34 Peripheral Clock 34 Status 2 1 read-only PID35 Peripheral Clock 35 Status 3 1 read-only PID36 Peripheral Clock 36 Status 4 1 read-only PID37 Peripheral Clock 37 Status 5 1 read-only PID38 Peripheral Clock 38 Status 6 1 read-only PID39 Peripheral Clock 39 Status 7 1 read-only PID40 Peripheral Clock 40 Status 8 1 read-only PID41 Peripheral Clock 41 Status 9 1 read-only PID42 Peripheral Clock 42 Status 10 1 read-only PID43 Peripheral Clock 43 Status 11 1 read-only PID44 Peripheral Clock 44 Status 12 1 read-only PID45 Peripheral Clock 45 Status 13 1 read-only PID46 Peripheral Clock 46 Status 14 1 read-only PID47 Peripheral Clock 47 Status 15 1 read-only PID48 Peripheral Clock 48 Status 16 1 read-only PID49 Peripheral Clock 49 Status 17 1 read-only PID50 Peripheral Clock 50 Status 18 1 read-only PID51 Peripheral Clock 51 Status 19 1 read-only PID52 Peripheral Clock 52 Status 20 1 read-only PID53 Peripheral Clock 53 Status 21 1 read-only PID54 Peripheral Clock 54 Status 22 1 read-only PID55 Peripheral Clock 55 Status 23 1 read-only PID56 Peripheral Clock 56 Status 24 1 read-only PID57 Peripheral Clock 57 Status 25 1 read-only PID58 Peripheral Clock 58 Status 26 1 read-only PID59 Peripheral Clock 59 Status 27 1 read-only PID60 Peripheral Clock 60 Status 28 1 read-only PID61 Peripheral Clock 61 Status 29 1 read-only PID62 Peripheral Clock 62 Status 30 1 read-only PID63 Peripheral Clock 63 Status 31 1 read-only PLLICPR PLL Charge Pump Current Register 0x80 32 read-write n 0x0 0x0 ICP_PLLA Must Be Written to Zero 0 2 read-write ICP_PLLU Charge Pump Current PLL UTMI 16 2 read-write IPLL_PLLA Engineering Configuration PLLA 8 3 read-write IVCO_PLLU Voltage Control Output Current PLL UTMI 24 2 read-write SCDR System Clock Disable Register 0x4 32 write-only n 0x0 0x0 DDRCK DDR Clock Disable 2 1 write-only LCDCK MCK2x Clock Disable 3 1 write-only PCK Processor Clock Disable 0 1 write-only PCK0 Programmable Clock 0 Output Disable 8 1 write-only PCK1 Programmable Clock 1 Output Disable 9 1 write-only PCK2 Programmable Clock 2 Output Disable 10 1 write-only SMDCK SMD Clock Disable 4 1 write-only UDP USB Device Clock Enable 7 1 write-only UHP USB Host OHCI Clock Disable 6 1 write-only SCER System Clock Enable Register 0x0 32 write-only n 0x0 0x0 DDRCK DDR Clock Enable 2 1 write-only LCDCK MCK2x Clock Enable 3 1 write-only PCK0 Programmable Clock 0 Output Enable 8 1 write-only PCK1 Programmable Clock 1 Output Enable 9 1 write-only PCK2 Programmable Clock 2 Output Enable 10 1 write-only SMDCK SMD Clock Enable 4 1 write-only UDP USB Device Clock Enable 7 1 write-only UHP USB Host OHCI Clocks Enable 6 1 write-only SCSR System Clock Status Register 0x8 32 read-only n 0x0 0x0 DDRCK DDR Clock Status 2 1 read-only LCDCK MCK2x Clock Status 3 1 read-only PCK Processor Clock Status 0 1 read-only PCK0 Programmable Clock 0 Output Status 8 1 read-only PCK1 Programmable Clock 1 Output Status 9 1 read-only PCK2 Programmable Clock 2 Output Status 10 1 read-only SMDCK SMD Clock Status 4 1 read-only UDP USB Device Port Clock Status 7 1 read-only UHP USB Host Port Clock Status 6 1 read-only SMD Soft Modem Clock Register 0x3C 32 read-write n 0x0 0x0 SMDDIV Divider for SMD Clock 8 5 read-write SMDS SMD Input Clock Selection 0 1 read-write SR Status Register 0x68 32 read-only n 0x0 0x0 CFDEV Clock Failure Detector Event 18 1 read-only CFDS Clock Failure Detector Status 19 1 read-only FOS Clock Failure Detector Fault Output Status 20 1 read-only LOCKA PLLA Lock Status 1 1 read-only LOCKU UPLL Clock Status 6 1 read-only MCKRDY Master Clock Status 3 1 read-only MOSCSELS Main Oscillator Selection Status 16 1 read-only MOSCXTS 12 MHz Crystal Oscillator Status 0 1 read-only OSCSELS Slow Clock Oscillator Selection 7 1 read-only PCKRDY0 Programmable Clock Ready Status 8 1 read-only PCKRDY1 Programmable Clock Ready Status 9 1 read-only PCKRDY2 Programmable Clock Ready Status 10 1 read-only XT32KERR 32.768 kHz Crystal Oscillator Error 21 1 read-only USB USB Clock Register 0x38 32 read-write n 0x0 0x0 USBDIV Divider for USB OHCI Clock 8 4 read-write USBS USB OHCI Input Clock Selection 0 1 read-write WPMR Write ProtectIon Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 read-write WPKEY Write Protection Key 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 0x504D43 WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 read-only WPVSRC Write Protection Violation Source 8 16 read-only PWM Pulse Width Modulation Controller PWM 0x0 0x0 0x50 registers n PWM 43 CCNT0 PWM Channel Counter Register (ch_num = 0) 0x214 32 read-only n 0x0 0x0 CNT Channel Counter Register 0 24 read-only CCNT1 PWM Channel Counter Register (ch_num = 1) 0x234 32 read-only n 0x0 0x0 CNT Channel Counter Register 0 24 read-only CCNT2 PWM Channel Counter Register (ch_num = 2) 0x254 32 read-only n 0x0 0x0 CNT Channel Counter Register 0 24 read-only CCNT3 PWM Channel Counter Register (ch_num = 3) 0x274 32 read-only n 0x0 0x0 CNT Channel Counter Register 0 24 read-only CDTY0 PWM Channel Duty Cycle Register (ch_num = 0) 0x204 32 read-write n 0x0 0x0 CDTY Channel Duty-Cycle 0 24 read-write CDTY1 PWM Channel Duty Cycle Register (ch_num = 1) 0x224 32 read-write n 0x0 0x0 CDTY Channel Duty-Cycle 0 24 read-write CDTY2 PWM Channel Duty Cycle Register (ch_num = 2) 0x244 32 read-write n 0x0 0x0 CDTY Channel Duty-Cycle 0 24 read-write CDTY3 PWM Channel Duty Cycle Register (ch_num = 3) 0x264 32 read-write n 0x0 0x0 CDTY Channel Duty-Cycle 0 24 read-write CDTYUPD0 PWM Channel Duty Cycle Update Register (ch_num = 0) 0x208 32 write-only n 0x0 0x0 CDTYUPD Channel Duty-Cycle Update 0 24 write-only CDTYUPD1 PWM Channel Duty Cycle Update Register (ch_num = 1) 0x228 32 write-only n 0x0 0x0 CDTYUPD Channel Duty-Cycle Update 0 24 write-only CDTYUPD2 PWM Channel Duty Cycle Update Register (ch_num = 2) 0x248 32 write-only n 0x0 0x0 CDTYUPD Channel Duty-Cycle Update 0 24 write-only CDTYUPD3 PWM Channel Duty Cycle Update Register (ch_num = 3) 0x268 32 write-only n 0x0 0x0 CDTYUPD Channel Duty-Cycle Update 0 24 write-only CLK PWM Clock Register 0x0 32 read-write n 0x0 0x0 DIVA CLKA Divide Factor 0 8 read-write CLKA_POFF CLKA clock is turned off 0 PREA CLKA clock is clock selected by PREA 1 DIVB CLKB Divide Factor 16 8 read-write CLKB_POFF CLKB clock is turned off 0 PREB CLKB clock is clock selected by PREB 1 PREA CLKA Source Clock Selection 8 4 read-write CLK Peripheral clock 0x0 CLK_DIV2 Peripheral clock/2 0x1 CLK_DIV4 Peripheral clock/4 0x2 CLK_DIV8 Peripheral clock/8 0x3 CLK_DIV16 Peripheral clock/16 0x4 CLK_DIV32 Peripheral clock/32 0x5 CLK_DIV64 Peripheral clock/64 0x6 CLK_DIV128 Peripheral clock/128 0x7 CLK_DIV256 Peripheral clock/256 0x8 CLK_DIV512 Peripheral clock/512 0x9 CLK_DIV1024 Peripheral clock/1024 0xA PREB CLKB Source Clock Selection 24 4 read-write CLK Peripheral clock 0x0 CLK_DIV2 Peripheral clock/2 0x1 CLK_DIV4 Peripheral clock/4 0x2 CLK_DIV8 Peripheral clock/8 0x3 CLK_DIV16 Peripheral clock/16 0x4 CLK_DIV32 Peripheral clock/32 0x5 CLK_DIV64 Peripheral clock/64 0x6 CLK_DIV128 Peripheral clock/128 0x7 CLK_DIV256 Peripheral clock/256 0x8 CLK_DIV512 Peripheral clock/512 0x9 CLK_DIV1024 Peripheral clock/1024 0xA CMPM0 PWM Comparison 0 Mode Register 0x138 32 read-write n 0x0 0x0 CEN Comparison x Enable 0 1 read-write CPR Comparison x Period 8 4 read-write CPRCNT Comparison x Period Counter 12 4 read-write CTR Comparison x Trigger 4 4 read-write CUPR Comparison x Update Period 16 4 read-write CUPRCNT Comparison x Update Period Counter 20 4 read-write CMPM1 PWM Comparison 1 Mode Register 0x148 32 read-write n 0x0 0x0 CEN Comparison x Enable 0 1 read-write CPR Comparison x Period 8 4 read-write CPRCNT Comparison x Period Counter 12 4 read-write CTR Comparison x Trigger 4 4 read-write CUPR Comparison x Update Period 16 4 read-write CUPRCNT Comparison x Update Period Counter 20 4 read-write CMPM2 PWM Comparison 2 Mode Register 0x158 32 read-write n 0x0 0x0 CEN Comparison x Enable 0 1 read-write CPR Comparison x Period 8 4 read-write CPRCNT Comparison x Period Counter 12 4 read-write CTR Comparison x Trigger 4 4 read-write CUPR Comparison x Update Period 16 4 read-write CUPRCNT Comparison x Update Period Counter 20 4 read-write CMPM3 PWM Comparison 3 Mode Register 0x168 32 read-write n 0x0 0x0 CEN Comparison x Enable 0 1 read-write CPR Comparison x Period 8 4 read-write CPRCNT Comparison x Period Counter 12 4 read-write CTR Comparison x Trigger 4 4 read-write CUPR Comparison x Update Period 16 4 read-write CUPRCNT Comparison x Update Period Counter 20 4 read-write CMPM4 PWM Comparison 4 Mode Register 0x178 32 read-write n 0x0 0x0 CEN Comparison x Enable 0 1 read-write CPR Comparison x Period 8 4 read-write CPRCNT Comparison x Period Counter 12 4 read-write CTR Comparison x Trigger 4 4 read-write CUPR Comparison x Update Period 16 4 read-write CUPRCNT Comparison x Update Period Counter 20 4 read-write CMPM5 PWM Comparison 5 Mode Register 0x188 32 read-write n 0x0 0x0 CEN Comparison x Enable 0 1 read-write CPR Comparison x Period 8 4 read-write CPRCNT Comparison x Period Counter 12 4 read-write CTR Comparison x Trigger 4 4 read-write CUPR Comparison x Update Period 16 4 read-write CUPRCNT Comparison x Update Period Counter 20 4 read-write CMPM6 PWM Comparison 6 Mode Register 0x198 32 read-write n 0x0 0x0 CEN Comparison x Enable 0 1 read-write CPR Comparison x Period 8 4 read-write CPRCNT Comparison x Period Counter 12 4 read-write CTR Comparison x Trigger 4 4 read-write CUPR Comparison x Update Period 16 4 read-write CUPRCNT Comparison x Update Period Counter 20 4 read-write CMPM7 PWM Comparison 7 Mode Register 0x1A8 32 read-write n 0x0 0x0 CEN Comparison x Enable 0 1 read-write CPR Comparison x Period 8 4 read-write CPRCNT Comparison x Period Counter 12 4 read-write CTR Comparison x Trigger 4 4 read-write CUPR Comparison x Update Period 16 4 read-write CUPRCNT Comparison x Update Period Counter 20 4 read-write CMPMUPD0 PWM Comparison 0 Mode Update Register 0x13C 32 write-only n 0x0 0x0 CENUPD Comparison x Enable Update 0 1 write-only CPRUPD Comparison x Period Update 8 4 write-only CTRUPD Comparison x Trigger Update 4 4 write-only CUPRUPD Comparison x Update Period Update 16 4 write-only CMPMUPD1 PWM Comparison 1 Mode Update Register 0x14C 32 write-only n 0x0 0x0 CENUPD Comparison x Enable Update 0 1 write-only CPRUPD Comparison x Period Update 8 4 write-only CTRUPD Comparison x Trigger Update 4 4 write-only CUPRUPD Comparison x Update Period Update 16 4 write-only CMPMUPD2 PWM Comparison 2 Mode Update Register 0x15C 32 write-only n 0x0 0x0 CENUPD Comparison x Enable Update 0 1 write-only CPRUPD Comparison x Period Update 8 4 write-only CTRUPD Comparison x Trigger Update 4 4 write-only CUPRUPD Comparison x Update Period Update 16 4 write-only CMPMUPD3 PWM Comparison 3 Mode Update Register 0x16C 32 write-only n 0x0 0x0 CENUPD Comparison x Enable Update 0 1 write-only CPRUPD Comparison x Period Update 8 4 write-only CTRUPD Comparison x Trigger Update 4 4 write-only CUPRUPD Comparison x Update Period Update 16 4 write-only CMPMUPD4 PWM Comparison 4 Mode Update Register 0x17C 32 write-only n 0x0 0x0 CENUPD Comparison x Enable Update 0 1 write-only CPRUPD Comparison x Period Update 8 4 write-only CTRUPD Comparison x Trigger Update 4 4 write-only CUPRUPD Comparison x Update Period Update 16 4 write-only CMPMUPD5 PWM Comparison 5 Mode Update Register 0x18C 32 write-only n 0x0 0x0 CENUPD Comparison x Enable Update 0 1 write-only CPRUPD Comparison x Period Update 8 4 write-only CTRUPD Comparison x Trigger Update 4 4 write-only CUPRUPD Comparison x Update Period Update 16 4 write-only CMPMUPD6 PWM Comparison 6 Mode Update Register 0x19C 32 write-only n 0x0 0x0 CENUPD Comparison x Enable Update 0 1 write-only CPRUPD Comparison x Period Update 8 4 write-only CTRUPD Comparison x Trigger Update 4 4 write-only CUPRUPD Comparison x Update Period Update 16 4 write-only CMPMUPD7 PWM Comparison 7 Mode Update Register 0x1AC 32 write-only n 0x0 0x0 CENUPD Comparison x Enable Update 0 1 write-only CPRUPD Comparison x Period Update 8 4 write-only CTRUPD Comparison x Trigger Update 4 4 write-only CUPRUPD Comparison x Update Period Update 16 4 write-only CMPV0 PWM Comparison 0 Value Register 0x130 32 read-write n 0x0 0x0 CV Comparison x Value 0 24 read-write CVM Comparison x Value Mode 24 1 read-write CMPV1 PWM Comparison 1 Value Register 0x140 32 read-write n 0x0 0x0 CV Comparison x Value 0 24 read-write CVM Comparison x Value Mode 24 1 read-write CMPV2 PWM Comparison 2 Value Register 0x150 32 read-write n 0x0 0x0 CV Comparison x Value 0 24 read-write CVM Comparison x Value Mode 24 1 read-write CMPV3 PWM Comparison 3 Value Register 0x160 32 read-write n 0x0 0x0 CV Comparison x Value 0 24 read-write CVM Comparison x Value Mode 24 1 read-write CMPV4 PWM Comparison 4 Value Register 0x170 32 read-write n 0x0 0x0 CV Comparison x Value 0 24 read-write CVM Comparison x Value Mode 24 1 read-write CMPV5 PWM Comparison 5 Value Register 0x180 32 read-write n 0x0 0x0 CV Comparison x Value 0 24 read-write CVM Comparison x Value Mode 24 1 read-write CMPV6 PWM Comparison 6 Value Register 0x190 32 read-write n 0x0 0x0 CV Comparison x Value 0 24 read-write CVM Comparison x Value Mode 24 1 read-write CMPV7 PWM Comparison 7 Value Register 0x1A0 32 read-write n 0x0 0x0 CV Comparison x Value 0 24 read-write CVM Comparison x Value Mode 24 1 read-write CMPVUPD0 PWM Comparison 0 Value Update Register 0x134 32 write-only n 0x0 0x0 CVMUPD Comparison x Value Mode Update 24 1 write-only CVUPD Comparison x Value Update 0 24 write-only CMPVUPD1 PWM Comparison 1 Value Update Register 0x144 32 write-only n 0x0 0x0 CVMUPD Comparison x Value Mode Update 24 1 write-only CVUPD Comparison x Value Update 0 24 write-only CMPVUPD2 PWM Comparison 2 Value Update Register 0x154 32 write-only n 0x0 0x0 CVMUPD Comparison x Value Mode Update 24 1 write-only CVUPD Comparison x Value Update 0 24 write-only CMPVUPD3 PWM Comparison 3 Value Update Register 0x164 32 write-only n 0x0 0x0 CVMUPD Comparison x Value Mode Update 24 1 write-only CVUPD Comparison x Value Update 0 24 write-only CMPVUPD4 PWM Comparison 4 Value Update Register 0x174 32 write-only n 0x0 0x0 CVMUPD Comparison x Value Mode Update 24 1 write-only CVUPD Comparison x Value Update 0 24 write-only CMPVUPD5 PWM Comparison 5 Value Update Register 0x184 32 write-only n 0x0 0x0 CVMUPD Comparison x Value Mode Update 24 1 write-only CVUPD Comparison x Value Update 0 24 write-only CMPVUPD6 PWM Comparison 6 Value Update Register 0x194 32 write-only n 0x0 0x0 CVMUPD Comparison x Value Mode Update 24 1 write-only CVUPD Comparison x Value Update 0 24 write-only CMPVUPD7 PWM Comparison 7 Value Update Register 0x1A4 32 write-only n 0x0 0x0 CVMUPD Comparison x Value Mode Update 24 1 write-only CVUPD Comparison x Value Update 0 24 write-only CMR0 PWM Channel Mode Register (ch_num = 0) 0x200 32 read-write n 0x0 0x0 CALG Channel Alignment 8 1 read-write CES Counter Event Selection 10 1 read-write CPOL Channel Polarity 9 1 read-write CPRE Channel Prescaler 0 4 read-write MCK Peripheral clock 0x0 MCK_DIV_2 Peripheral clock/2 0x1 MCK_DIV_4 Peripheral clock/4 0x2 MCK_DIV_8 Peripheral clock/8 0x3 MCK_DIV_16 Peripheral clock/16 0x4 MCK_DIV_32 Peripheral clock/32 0x5 MCK_DIV_64 Peripheral clock/64 0x6 MCK_DIV_128 Peripheral clock/128 0x7 MCK_DIV_256 Peripheral clock/256 0x8 MCK_DIV_512 Peripheral clock/512 0x9 MCK_DIV_1024 Peripheral clock/1024 0xA CLKA Clock A 0xB CLKB Clock B 0xC DTE Dead-Time Generator Enable 16 1 read-write DTHI Dead-Time PWMHx Output Inverted 17 1 read-write DTLI Dead-Time PWMLx Output Inverted 18 1 read-write UPDS Update Selection 11 1 read-write CMR1 PWM Channel Mode Register (ch_num = 1) 0x220 32 read-write n 0x0 0x0 CALG Channel Alignment 8 1 read-write CES Counter Event Selection 10 1 read-write CPOL Channel Polarity 9 1 read-write CPRE Channel Prescaler 0 4 read-write MCK Peripheral clock 0x0 MCK_DIV_2 Peripheral clock/2 0x1 MCK_DIV_4 Peripheral clock/4 0x2 MCK_DIV_8 Peripheral clock/8 0x3 MCK_DIV_16 Peripheral clock/16 0x4 MCK_DIV_32 Peripheral clock/32 0x5 MCK_DIV_64 Peripheral clock/64 0x6 MCK_DIV_128 Peripheral clock/128 0x7 MCK_DIV_256 Peripheral clock/256 0x8 MCK_DIV_512 Peripheral clock/512 0x9 MCK_DIV_1024 Peripheral clock/1024 0xA CLKA Clock A 0xB CLKB Clock B 0xC DTE Dead-Time Generator Enable 16 1 read-write DTHI Dead-Time PWMHx Output Inverted 17 1 read-write DTLI Dead-Time PWMLx Output Inverted 18 1 read-write UPDS Update Selection 11 1 read-write CMR2 PWM Channel Mode Register (ch_num = 2) 0x240 32 read-write n 0x0 0x0 CALG Channel Alignment 8 1 read-write CES Counter Event Selection 10 1 read-write CPOL Channel Polarity 9 1 read-write CPRE Channel Prescaler 0 4 read-write MCK Peripheral clock 0x0 MCK_DIV_2 Peripheral clock/2 0x1 MCK_DIV_4 Peripheral clock/4 0x2 MCK_DIV_8 Peripheral clock/8 0x3 MCK_DIV_16 Peripheral clock/16 0x4 MCK_DIV_32 Peripheral clock/32 0x5 MCK_DIV_64 Peripheral clock/64 0x6 MCK_DIV_128 Peripheral clock/128 0x7 MCK_DIV_256 Peripheral clock/256 0x8 MCK_DIV_512 Peripheral clock/512 0x9 MCK_DIV_1024 Peripheral clock/1024 0xA CLKA Clock A 0xB CLKB Clock B 0xC DTE Dead-Time Generator Enable 16 1 read-write DTHI Dead-Time PWMHx Output Inverted 17 1 read-write DTLI Dead-Time PWMLx Output Inverted 18 1 read-write UPDS Update Selection 11 1 read-write CMR3 PWM Channel Mode Register (ch_num = 3) 0x260 32 read-write n 0x0 0x0 CALG Channel Alignment 8 1 read-write CES Counter Event Selection 10 1 read-write CPOL Channel Polarity 9 1 read-write CPRE Channel Prescaler 0 4 read-write MCK Peripheral clock 0x0 MCK_DIV_2 Peripheral clock/2 0x1 MCK_DIV_4 Peripheral clock/4 0x2 MCK_DIV_8 Peripheral clock/8 0x3 MCK_DIV_16 Peripheral clock/16 0x4 MCK_DIV_32 Peripheral clock/32 0x5 MCK_DIV_64 Peripheral clock/64 0x6 MCK_DIV_128 Peripheral clock/128 0x7 MCK_DIV_256 Peripheral clock/256 0x8 MCK_DIV_512 Peripheral clock/512 0x9 MCK_DIV_1024 Peripheral clock/1024 0xA CLKA Clock A 0xB CLKB Clock B 0xC DTE Dead-Time Generator Enable 16 1 read-write DTHI Dead-Time PWMHx Output Inverted 17 1 read-write DTLI Dead-Time PWMLx Output Inverted 18 1 read-write UPDS Update Selection 11 1 read-write CMUPD0 PWM Channel Mode Update Register (ch_num = 0) 0x400 32 write-only n 0x0 0x0 CPOLINVUP Channel Polarity Inversion Update 13 1 write-only CPOLUP Channel Polarity Update 9 1 write-only CMUPD1 PWM Channel Mode Update Register (ch_num = 1) 0x420 32 write-only n 0x0 0x0 CPOLINVUP Channel Polarity Inversion Update 13 1 write-only CPOLUP Channel Polarity Update 9 1 write-only CMUPD2 PWM Channel Mode Update Register (ch_num = 2) 0x440 32 write-only n 0x0 0x0 CPOLINVUP Channel Polarity Inversion Update 13 1 write-only CPOLUP Channel Polarity Update 9 1 write-only CMUPD3 PWM Channel Mode Update Register (ch_num = 3) 0x460 32 write-only n 0x0 0x0 CPOLINVUP Channel Polarity Inversion Update 13 1 write-only CPOLUP Channel Polarity Update 9 1 write-only CPRD0 PWM Channel Period Register (ch_num = 0) 0x20C 32 read-write n 0x0 0x0 CPRD Channel Period 0 24 read-write CPRD1 PWM Channel Period Register (ch_num = 1) 0x22C 32 read-write n 0x0 0x0 CPRD Channel Period 0 24 read-write CPRD2 PWM Channel Period Register (ch_num = 2) 0x24C 32 read-write n 0x0 0x0 CPRD Channel Period 0 24 read-write CPRD3 PWM Channel Period Register (ch_num = 3) 0x26C 32 read-write n 0x0 0x0 CPRD Channel Period 0 24 read-write CPRDUPD0 PWM Channel Period Update Register (ch_num = 0) 0x210 32 write-only n 0x0 0x0 CPRDUPD Channel Period Update 0 24 write-only CPRDUPD1 PWM Channel Period Update Register (ch_num = 1) 0x230 32 write-only n 0x0 0x0 CPRDUPD Channel Period Update 0 24 write-only CPRDUPD2 PWM Channel Period Update Register (ch_num = 2) 0x250 32 write-only n 0x0 0x0 CPRDUPD Channel Period Update 0 24 write-only CPRDUPD3 PWM Channel Period Update Register (ch_num = 3) 0x270 32 write-only n 0x0 0x0 CPRDUPD Channel Period Update 0 24 write-only DIS PWM Disable Register 0x8 32 write-only n 0x0 0x0 CHID0 Channel ID 0 1 write-only CHID1 Channel ID 1 1 write-only CHID2 Channel ID 2 1 write-only CHID3 Channel ID 3 1 write-only DT0 PWM Channel Dead Time Register (ch_num = 0) 0x218 32 read-write n 0x0 0x0 DTH Dead-Time Value for PWMHx Output 0 16 read-write DTL Dead-Time Value for PWMLx Output 16 16 read-write DT1 PWM Channel Dead Time Register (ch_num = 1) 0x238 32 read-write n 0x0 0x0 DTH Dead-Time Value for PWMHx Output 0 16 read-write DTL Dead-Time Value for PWMLx Output 16 16 read-write DT2 PWM Channel Dead Time Register (ch_num = 2) 0x258 32 read-write n 0x0 0x0 DTH Dead-Time Value for PWMHx Output 0 16 read-write DTL Dead-Time Value for PWMLx Output 16 16 read-write DT3 PWM Channel Dead Time Register (ch_num = 3) 0x278 32 read-write n 0x0 0x0 DTH Dead-Time Value for PWMHx Output 0 16 read-write DTL Dead-Time Value for PWMLx Output 16 16 read-write DTUPD0 PWM Channel Dead Time Update Register (ch_num = 0) 0x21C 32 write-only n 0x0 0x0 DTHUPD Dead-Time Value Update for PWMHx Output 0 16 write-only DTLUPD Dead-Time Value Update for PWMLx Output 16 16 write-only DTUPD1 PWM Channel Dead Time Update Register (ch_num = 1) 0x23C 32 write-only n 0x0 0x0 DTHUPD Dead-Time Value Update for PWMHx Output 0 16 write-only DTLUPD Dead-Time Value Update for PWMLx Output 16 16 write-only DTUPD2 PWM Channel Dead Time Update Register (ch_num = 2) 0x25C 32 write-only n 0x0 0x0 DTHUPD Dead-Time Value Update for PWMHx Output 0 16 write-only DTLUPD Dead-Time Value Update for PWMLx Output 16 16 write-only DTUPD3 PWM Channel Dead Time Update Register (ch_num = 3) 0x27C 32 write-only n 0x0 0x0 DTHUPD Dead-Time Value Update for PWMHx Output 0 16 write-only DTLUPD Dead-Time Value Update for PWMLx Output 16 16 write-only ELMR0 PWM Event Line 0 Mode Register 0x7C 32 read-write n CSEL0 Comparison 0 Selection 0 1 read-write CSEL1 Comparison 1 Selection 1 1 read-write CSEL2 Comparison 2 Selection 2 1 read-write CSEL3 Comparison 3 Selection 3 1 read-write CSEL4 Comparison 4 Selection 4 1 read-write CSEL5 Comparison 5 Selection 5 1 read-write CSEL6 Comparison 6 Selection 6 1 read-write CSEL7 Comparison 7 Selection 7 1 read-write ELMR1 PWM Event Line 0 Mode Register 0x80 32 read-write n CSEL0 Comparison 0 Selection 0 1 read-write CSEL1 Comparison 1 Selection 1 1 read-write CSEL2 Comparison 2 Selection 2 1 read-write CSEL3 Comparison 3 Selection 3 1 read-write CSEL4 Comparison 4 Selection 4 1 read-write CSEL5 Comparison 5 Selection 5 1 read-write CSEL6 Comparison 6 Selection 6 1 read-write CSEL7 Comparison 7 Selection 7 1 read-write ELMR[0] PWM Event Line 0 Mode Register 0xF8 32 read-write n 0x0 0x0 CSEL0 Comparison 0 Selection 0 1 read-write CSEL1 Comparison 1 Selection 1 1 read-write CSEL2 Comparison 2 Selection 2 1 read-write CSEL3 Comparison 3 Selection 3 1 read-write CSEL4 Comparison 4 Selection 4 1 read-write CSEL5 Comparison 5 Selection 5 1 read-write CSEL6 Comparison 6 Selection 6 1 read-write CSEL7 Comparison 7 Selection 7 1 read-write ELMR[1] PWM Event Line 0 Mode Register 0x178 32 read-write n 0x0 0x0 CSEL0 Comparison 0 Selection 0 1 read-write CSEL1 Comparison 1 Selection 1 1 read-write CSEL2 Comparison 2 Selection 2 1 read-write CSEL3 Comparison 3 Selection 3 1 read-write CSEL4 Comparison 4 Selection 4 1 read-write CSEL5 Comparison 5 Selection 5 1 read-write CSEL6 Comparison 6 Selection 6 1 read-write CSEL7 Comparison 7 Selection 7 1 read-write ENA PWM Enable Register 0x4 32 write-only n 0x0 0x0 CHID0 Channel ID 0 1 write-only CHID1 Channel ID 1 1 write-only CHID2 Channel ID 2 1 write-only CHID3 Channel ID 3 1 write-only FCR PWM Fault Clear Register 0x64 32 write-only n 0x0 0x0 FCLR Fault Clear 0 8 write-only FMR PWM Fault Mode Register 0x5C 32 read-write n 0x0 0x0 FFIL Fault Filtering 16 8 read-write FMOD Fault Activation Mode 8 8 read-write FPOL Fault Polarity 0 8 read-write FPE PWM Fault Protection Enable Register 0x6C 32 read-write n 0x0 0x0 FPE0 Fault Protection Enable for channel 0 0 8 read-write FPE1 Fault Protection Enable for channel 1 8 8 read-write FPE2 Fault Protection Enable for channel 2 16 8 read-write FPE3 Fault Protection Enable for channel 3 24 8 read-write FPV1 PWM Fault Protection Value Register 1 0x68 32 read-write n 0x0 0x0 FPVH0 Fault Protection Value for PWMH output on channel 0 0 1 read-write FPVH1 Fault Protection Value for PWMH output on channel 1 1 1 read-write FPVH2 Fault Protection Value for PWMH output on channel 2 2 1 read-write FPVH3 Fault Protection Value for PWMH output on channel 3 3 1 read-write FPVL0 Fault Protection Value for PWML output on channel 0 16 1 read-write FPVL1 Fault Protection Value for PWML output on channel 1 17 1 read-write FPVL2 Fault Protection Value for PWML output on channel 2 18 1 read-write FPVL3 Fault Protection Value for PWML output on channel 3 19 1 read-write FPV2 PWM Fault Protection Value 2 Register 0xC0 32 read-write n 0x0 0x0 FPZH0 Fault Protection to Hi-Z for PWMH output on channel 0 0 1 read-write FPZH1 Fault Protection to Hi-Z for PWMH output on channel 1 1 1 read-write FPZH2 Fault Protection to Hi-Z for PWMH output on channel 2 2 1 read-write FPZH3 Fault Protection to Hi-Z for PWMH output on channel 3 3 1 read-write FPZL0 Fault Protection to Hi-Z for PWML output on channel 0 16 1 read-write FPZL1 Fault Protection to Hi-Z for PWML output on channel 1 17 1 read-write FPZL2 Fault Protection to Hi-Z for PWML output on channel 2 18 1 read-write FPZL3 Fault Protection to Hi-Z for PWML output on channel 3 19 1 read-write FSR PWM Fault Status Register 0x60 32 read-only n 0x0 0x0 FIV Fault Input Value 0 8 read-only FS Fault Status 8 8 read-only IDR1 PWM Interrupt Disable Register 1 0x14 32 write-only n 0x0 0x0 CHID0 Counter Event on Channel 0 Interrupt Disable 0 1 write-only CHID1 Counter Event on Channel 1 Interrupt Disable 1 1 write-only CHID2 Counter Event on Channel 2 Interrupt Disable 2 1 write-only CHID3 Counter Event on Channel 3 Interrupt Disable 3 1 write-only FCHID0 Fault Protection Trigger on Channel 0 Interrupt Disable 16 1 write-only FCHID1 Fault Protection Trigger on Channel 1 Interrupt Disable 17 1 write-only FCHID2 Fault Protection Trigger on Channel 2 Interrupt Disable 18 1 write-only FCHID3 Fault Protection Trigger on Channel 3 Interrupt Disable 19 1 write-only IDR2 PWM Interrupt Disable Register 2 0x38 32 write-only n 0x0 0x0 CMPM0 Comparison 0 Match Interrupt Disable 8 1 write-only CMPM1 Comparison 1 Match Interrupt Disable 9 1 write-only CMPM2 Comparison 2 Match Interrupt Disable 10 1 write-only CMPM3 Comparison 3 Match Interrupt Disable 11 1 write-only CMPM4 Comparison 4 Match Interrupt Disable 12 1 write-only CMPM5 Comparison 5 Match Interrupt Disable 13 1 write-only CMPM6 Comparison 6 Match Interrupt Disable 14 1 write-only CMPM7 Comparison 7 Match Interrupt Disable 15 1 write-only CMPU0 Comparison 0 Update Interrupt Disable 16 1 write-only CMPU1 Comparison 1 Update Interrupt Disable 17 1 write-only CMPU2 Comparison 2 Update Interrupt Disable 18 1 write-only CMPU3 Comparison 3 Update Interrupt Disable 19 1 write-only CMPU4 Comparison 4 Update Interrupt Disable 20 1 write-only CMPU5 Comparison 5 Update Interrupt Disable 21 1 write-only CMPU6 Comparison 6 Update Interrupt Disable 22 1 write-only CMPU7 Comparison 7 Update Interrupt Disable 23 1 write-only UNRE Synchronous Channels Update Underrun Error Interrupt Disable 3 1 write-only WRDY Write Ready for Synchronous Channels Update Interrupt Disable 0 1 write-only IER1 PWM Interrupt Enable Register 1 0x10 32 write-only n 0x0 0x0 CHID0 Counter Event on Channel 0 Interrupt Enable 0 1 write-only CHID1 Counter Event on Channel 1 Interrupt Enable 1 1 write-only CHID2 Counter Event on Channel 2 Interrupt Enable 2 1 write-only CHID3 Counter Event on Channel 3 Interrupt Enable 3 1 write-only FCHID0 Fault Protection Trigger on Channel 0 Interrupt Enable 16 1 write-only FCHID1 Fault Protection Trigger on Channel 1 Interrupt Enable 17 1 write-only FCHID2 Fault Protection Trigger on Channel 2 Interrupt Enable 18 1 write-only FCHID3 Fault Protection Trigger on Channel 3 Interrupt Enable 19 1 write-only IER2 PWM Interrupt Enable Register 2 0x34 32 write-only n 0x0 0x0 CMPM0 Comparison 0 Match Interrupt Enable 8 1 write-only CMPM1 Comparison 1 Match Interrupt Enable 9 1 write-only CMPM2 Comparison 2 Match Interrupt Enable 10 1 write-only CMPM3 Comparison 3 Match Interrupt Enable 11 1 write-only CMPM4 Comparison 4 Match Interrupt Enable 12 1 write-only CMPM5 Comparison 5 Match Interrupt Enable 13 1 write-only CMPM6 Comparison 6 Match Interrupt Enable 14 1 write-only CMPM7 Comparison 7 Match Interrupt Enable 15 1 write-only CMPU0 Comparison 0 Update Interrupt Enable 16 1 write-only CMPU1 Comparison 1 Update Interrupt Enable 17 1 write-only CMPU2 Comparison 2 Update Interrupt Enable 18 1 write-only CMPU3 Comparison 3 Update Interrupt Enable 19 1 write-only CMPU4 Comparison 4 Update Interrupt Enable 20 1 write-only CMPU5 Comparison 5 Update Interrupt Enable 21 1 write-only CMPU6 Comparison 6 Update Interrupt Enable 22 1 write-only CMPU7 Comparison 7 Update Interrupt Enable 23 1 write-only UNRE Synchronous Channels Update Underrun Error Interrupt Enable 3 1 write-only WRDY Write Ready for Synchronous Channels Update Interrupt Enable 0 1 write-only IMR1 PWM Interrupt Mask Register 1 0x18 32 read-only n 0x0 0x0 CHID0 Counter Event on Channel 0 Interrupt Mask 0 1 read-only CHID1 Counter Event on Channel 1 Interrupt Mask 1 1 read-only CHID2 Counter Event on Channel 2 Interrupt Mask 2 1 read-only CHID3 Counter Event on Channel 3 Interrupt Mask 3 1 read-only FCHID0 Fault Protection Trigger on Channel 0 Interrupt Mask 16 1 read-only FCHID1 Fault Protection Trigger on Channel 1 Interrupt Mask 17 1 read-only FCHID2 Fault Protection Trigger on Channel 2 Interrupt Mask 18 1 read-only FCHID3 Fault Protection Trigger on Channel 3 Interrupt Mask 19 1 read-only IMR2 PWM Interrupt Mask Register 2 0x3C 32 read-only n 0x0 0x0 CMPM0 Comparison 0 Match Interrupt Mask 8 1 read-only CMPM1 Comparison 1 Match Interrupt Mask 9 1 read-only CMPM2 Comparison 2 Match Interrupt Mask 10 1 read-only CMPM3 Comparison 3 Match Interrupt Mask 11 1 read-only CMPM4 Comparison 4 Match Interrupt Mask 12 1 read-only CMPM5 Comparison 5 Match Interrupt Mask 13 1 read-only CMPM6 Comparison 6 Match Interrupt Mask 14 1 read-only CMPM7 Comparison 7 Match Interrupt Mask 15 1 read-only CMPU0 Comparison 0 Update Interrupt Mask 16 1 read-only CMPU1 Comparison 1 Update Interrupt Mask 17 1 read-only CMPU2 Comparison 2 Update Interrupt Mask 18 1 read-only CMPU3 Comparison 3 Update Interrupt Mask 19 1 read-only CMPU4 Comparison 4 Update Interrupt Mask 20 1 read-only CMPU5 Comparison 5 Update Interrupt Mask 21 1 read-only CMPU6 Comparison 6 Update Interrupt Mask 22 1 read-only CMPU7 Comparison 7 Update Interrupt Mask 23 1 read-only UNRE Synchronous Channels Update Underrun Error Interrupt Mask 3 1 read-only WRDY Write Ready for Synchronous Channels Update Interrupt Mask 0 1 read-only ISR1 PWM Interrupt Status Register 1 0x1C 32 read-only n 0x0 0x0 CHID0 Counter Event on Channel 0 0 1 read-only CHID1 Counter Event on Channel 1 1 1 read-only CHID2 Counter Event on Channel 2 2 1 read-only CHID3 Counter Event on Channel 3 3 1 read-only FCHID0 Fault Protection Trigger on Channel 0 16 1 read-only FCHID1 Fault Protection Trigger on Channel 1 17 1 read-only FCHID2 Fault Protection Trigger on Channel 2 18 1 read-only FCHID3 Fault Protection Trigger on Channel 3 19 1 read-only ISR2 PWM Interrupt Status Register 2 0x40 32 read-only n 0x0 0x0 CMPM0 Comparison 0 Match 8 1 read-only CMPM1 Comparison 1 Match 9 1 read-only CMPM2 Comparison 2 Match 10 1 read-only CMPM3 Comparison 3 Match 11 1 read-only CMPM4 Comparison 4 Match 12 1 read-only CMPM5 Comparison 5 Match 13 1 read-only CMPM6 Comparison 6 Match 14 1 read-only CMPM7 Comparison 7 Match 15 1 read-only CMPU0 Comparison 0 Update 16 1 read-only CMPU1 Comparison 1 Update 17 1 read-only CMPU2 Comparison 2 Update 18 1 read-only CMPU3 Comparison 3 Update 19 1 read-only CMPU4 Comparison 4 Update 20 1 read-only CMPU5 Comparison 5 Update 21 1 read-only CMPU6 Comparison 6 Update 22 1 read-only CMPU7 Comparison 7 Update 23 1 read-only UNRE Synchronous Channels Update Underrun Error 3 1 read-only WRDY Write Ready for Synchronous Channels Update 0 1 read-only OOV PWM Output Override Value Register 0x44 32 read-write n 0x0 0x0 OOVH0 Output Override Value for PWMH output of the channel 0 0 1 read-write OOVH1 Output Override Value for PWMH output of the channel 1 1 1 read-write OOVH2 Output Override Value for PWMH output of the channel 2 2 1 read-write OOVH3 Output Override Value for PWMH output of the channel 3 3 1 read-write OOVL0 Output Override Value for PWML output of the channel 0 16 1 read-write OOVL1 Output Override Value for PWML output of the channel 1 17 1 read-write OOVL2 Output Override Value for PWML output of the channel 2 18 1 read-write OOVL3 Output Override Value for PWML output of the channel 3 19 1 read-write OS PWM Output Selection Register 0x48 32 read-write n 0x0 0x0 OSH0 Output Selection for PWMH output of the channel 0 0 1 read-write OSH1 Output Selection for PWMH output of the channel 1 1 1 read-write OSH2 Output Selection for PWMH output of the channel 2 2 1 read-write OSH3 Output Selection for PWMH output of the channel 3 3 1 read-write OSL0 Output Selection for PWML output of the channel 0 16 1 read-write OSL1 Output Selection for PWML output of the channel 1 17 1 read-write OSL2 Output Selection for PWML output of the channel 2 18 1 read-write OSL3 Output Selection for PWML output of the channel 3 19 1 read-write OSC PWM Output Selection Clear Register 0x50 32 write-only n 0x0 0x0 OSCH0 Output Selection Clear for PWMH output of the channel 0 0 1 write-only OSCH1 Output Selection Clear for PWMH output of the channel 1 1 1 write-only OSCH2 Output Selection Clear for PWMH output of the channel 2 2 1 write-only OSCH3 Output Selection Clear for PWMH output of the channel 3 3 1 write-only OSCL0 Output Selection Clear for PWML output of the channel 0 16 1 write-only OSCL1 Output Selection Clear for PWML output of the channel 1 17 1 write-only OSCL2 Output Selection Clear for PWML output of the channel 2 18 1 write-only OSCL3 Output Selection Clear for PWML output of the channel 3 19 1 write-only OSCUPD PWM Output Selection Clear Update Register 0x58 32 write-only n 0x0 0x0 OSCUPH0 Output Selection Clear for PWMH output of the channel 0 0 1 write-only OSCUPH1 Output Selection Clear for PWMH output of the channel 1 1 1 write-only OSCUPH2 Output Selection Clear for PWMH output of the channel 2 2 1 write-only OSCUPH3 Output Selection Clear for PWMH output of the channel 3 3 1 write-only OSCUPL0 Output Selection Clear for PWML output of the channel 0 16 1 write-only OSCUPL1 Output Selection Clear for PWML output of the channel 1 17 1 write-only OSCUPL2 Output Selection Clear for PWML output of the channel 2 18 1 write-only OSCUPL3 Output Selection Clear for PWML output of the channel 3 19 1 write-only OSS PWM Output Selection Set Register 0x4C 32 write-only n 0x0 0x0 OSSH0 Output Selection Set for PWMH output of the channel 0 0 1 write-only OSSH1 Output Selection Set for PWMH output of the channel 1 1 1 write-only OSSH2 Output Selection Set for PWMH output of the channel 2 2 1 write-only OSSH3 Output Selection Set for PWMH output of the channel 3 3 1 write-only OSSL0 Output Selection Set for PWML output of the channel 0 16 1 write-only OSSL1 Output Selection Set for PWML output of the channel 1 17 1 write-only OSSL2 Output Selection Set for PWML output of the channel 2 18 1 write-only OSSL3 Output Selection Set for PWML output of the channel 3 19 1 write-only OSSUPD PWM Output Selection Set Update Register 0x54 32 write-only n 0x0 0x0 OSSUPH0 Output Selection Set for PWMH output of the channel 0 0 1 write-only OSSUPH1 Output Selection Set for PWMH output of the channel 1 1 1 write-only OSSUPH2 Output Selection Set for PWMH output of the channel 2 2 1 write-only OSSUPH3 Output Selection Set for PWMH output of the channel 3 3 1 write-only OSSUPL0 Output Selection Set for PWML output of the channel 0 16 1 write-only OSSUPL1 Output Selection Set for PWML output of the channel 1 17 1 write-only OSSUPL2 Output Selection Set for PWML output of the channel 2 18 1 write-only OSSUPL3 Output Selection Set for PWML output of the channel 3 19 1 write-only SCM PWM Sync Channels Mode Register 0x20 32 read-write n 0x0 0x0 SYNC0 Synchronous Channel 0 0 1 read-write SYNC1 Synchronous Channel 1 1 1 read-write SYNC2 Synchronous Channel 2 2 1 read-write SYNC3 Synchronous Channel 3 3 1 read-write UPDM Synchronous Channels Update Mode 16 2 read-write MODE0 Manual write of double buffer registers and manual update of synchronous channels 0 MODE1 Manual write of double buffer registers and automatic update of synchronous channels 1 SCUC PWM Sync Channels Update Control Register 0x28 32 read-write n 0x0 0x0 UPDULOCK Synchronous Channels Update Unlock 0 1 read-write SCUP PWM Sync Channels Update Period Register 0x2C 32 read-write n 0x0 0x0 UPR Update Period 0 4 read-write UPRCNT Update Period Counter 4 4 read-write SCUPUPD PWM Sync Channels Update Period Update Register 0x30 32 write-only n 0x0 0x0 UPRUPD Update Period Update 0 4 write-only SMMR PWM Stepper Motor Mode Register 0xB0 32 read-write n 0x0 0x0 DOWN0 Down Count 16 1 read-write DOWN1 Down Count 17 1 read-write GCEN0 Gray Count Enable 0 1 read-write GCEN1 Gray Count Enable 1 1 read-write SR PWM Status Register 0xC 32 read-only n 0x0 0x0 CHID0 Channel ID 0 1 read-only CHID1 Channel ID 1 1 read-only CHID2 Channel ID 2 1 read-only CHID3 Channel ID 3 1 read-only SSPR PWM Spread Spectrum Register 0xA0 32 read-write n 0x0 0x0 SPRD Spread Spectrum Limit Value 0 24 read-write SPRDM Spread Spectrum Counter Mode 24 1 read-write SSPUP PWM Spread Spectrum Update Register 0xA4 32 write-only n 0x0 0x0 SPRDUP Spread Spectrum Limit Value Update 0 24 write-only WPCR PWM Write Protection Control Register 0xE4 32 write-only n 0x0 0x0 WPCMD Write Protection Command 0 2 write-only DISABLE_SW_PROT Disables the software write protection of the register groups of which the bit WPRGx is at '1'. 0x0 ENABLE_SW_PROT Enables the software write protection of the register groups of which the bit WPRGx is at '1'. 0x1 ENABLE_HW_PROT Enables the hardware write protection of the register groups of which the bit WPRGx is at '1'. Only a hardware reset of the PWM controller can disable the hardware write protection. Moreover, to meet security requirements, the PIO lines associated with the PWM can not be configured through the PIO interface. 0x2 WPKEY Write Protection Key 8 24 write-only PASSWD Writing any other value in this field aborts the write operation of the WPCMD field.Always reads as 0 0x50574D WPRG0 Write Protection Register Group 0 2 1 write-only WPRG1 Write Protection Register Group 1 3 1 write-only WPRG2 Write Protection Register Group 2 4 1 write-only WPRG3 Write Protection Register Group 3 5 1 write-only WPRG4 Write Protection Register Group 4 6 1 write-only WPRG5 Write Protection Register Group 5 7 1 write-only WPSR PWM Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPHWS0 Write Protect HW Status 8 1 read-only WPHWS1 Write Protect HW Status 9 1 read-only WPHWS2 Write Protect HW Status 10 1 read-only WPHWS3 Write Protect HW Status 11 1 read-only WPHWS4 Write Protect HW Status 12 1 read-only WPHWS5 Write Protect HW Status 13 1 read-only WPSWS0 Write Protect SW Status 0 1 read-only WPSWS1 Write Protect SW Status 1 1 read-only WPSWS2 Write Protect SW Status 2 1 read-only WPSWS3 Write Protect SW Status 3 1 read-only WPSWS4 Write Protect SW Status 4 1 read-only WPSWS5 Write Protect SW Status 5 1 read-only WPVS Write Protect Violation Status 7 1 read-only WPVSRC Write Protect Violation Source 16 16 read-only RSTC Reset Controller SYSC 0x0 0x0 0x200 registers n CR Control Register 0x0 32 write-only n 0x0 0x0 KEY Write Access Password 24 8 write-only PASSWD Writing any other value in this field aborts the write operation.Always reads as 0. 0xA5 PROCRST Processor Reset 0 1 write-only MR Mode Register 0x8 32 read-write n 0x0 0x0 KEY Write Access Password 24 8 read-write PASSWD Writing any other value in this field aborts the write operation.Always reads as 0. 0xA5 URSTEN User Reset Enable 0 1 read-write URSTIEN User Reset Interrupt Enable 4 1 read-write SR Status Register 0x4 32 read-only n 0x0 0x0 NRSTL NRST Pin Level 16 1 read-only RSTTYP Reset Type 8 3 read-only GENERAL_RST Both VDDCORE and VDDBU rising 0x0 WKUP_RST VDDCORE rising 0x1 WDT_RST Watchdog fault occurred 0x2 SOFT_RST Processor reset required by the software 0x3 USER_RST NRST pin detected low 0x4 SRCMP Software Reset Command in Progress 17 1 read-only URSTS User Reset Status 0 1 read-only RTC Real-time Clock SYSC 0x0 0x0 0x200 registers n CALALR Calendar Alarm Register 0x14 32 read-write n 0x0 0x0 DATE Date Alarm 24 6 read-write DATEEN Date Alarm Enable 31 1 read-write MONTH Month Alarm 16 5 read-write MTHEN Month Alarm Enable 23 1 read-write CALR Calendar Register 0xC 32 read-write n 0x0 0x0 CENT Current Century 0 7 read-write DATE Current Day in Current Month 24 6 read-write DAY Current Day in Current Week 21 3 read-write MONTH Current Month 16 5 read-write YEAR Current Year 8 8 read-write CR Control Register 0x0 32 read-write n 0x0 0x0 CALEVSEL Calendar Event Selection 16 2 read-write WEEK Week change (every Monday at time 00:00:00) 0x0 MONTH Month change (every 01 of each month at time 00:00:00) 0x1 YEAR Year change (every January 1 at time 00:00:00) 0x2 TIMEVSEL Time Event Selection 8 2 read-write MINUTE Minute change 0x0 HOUR Hour change 0x1 MIDNIGHT Every day at midnight 0x2 NOON Every day at noon 0x3 UPDCAL Update Request Calendar Register 1 1 read-write UPDTIM Update Request Time Register 0 1 read-write IDR Interrupt Disable Register 0x24 32 write-only n 0x0 0x0 ACKDIS Acknowledge Update Interrupt Disable 0 1 write-only ALRDIS Alarm Interrupt Disable 1 1 write-only CALDIS Calendar Event Interrupt Disable 4 1 write-only SECDIS Second Event Interrupt Disable 2 1 write-only TDERRDIS Time and/or Date Error Interrupt Disable 5 1 write-only TIMDIS Time Event Interrupt Disable 3 1 write-only IER Interrupt Enable Register 0x20 32 write-only n 0x0 0x0 ACKEN Acknowledge Update Interrupt Enable 0 1 write-only ALREN Alarm Interrupt Enable 1 1 write-only CALEN Calendar Event Interrupt Enable 4 1 write-only SECEN Second Event Interrupt Enable 2 1 write-only TDERREN Time and/or Date Error Interrupt Enable 5 1 write-only TIMEN Time Event Interrupt Enable 3 1 write-only IMR Interrupt Mask Register 0x28 32 read-only n 0x0 0x0 ACK Acknowledge Update Interrupt Mask 0 1 read-only ALR Alarm Interrupt Mask 1 1 read-only CAL Calendar Event Interrupt Mask 4 1 read-only SEC Second Event Interrupt Mask 2 1 read-only TDERR Time and/or Date Error Mask 5 1 read-only TIM Time Event Interrupt Mask 3 1 read-only MR Mode Register 0x4 32 read-write n 0x0 0x0 CORRECTION Slow Clock Correction 8 7 read-write HIGHPPM HIGH PPM Correction 15 1 read-write HRMOD 12-/24-hour Mode 0 1 read-write NEGPPM NEGative PPM Correction 4 1 read-write PERSIAN PERSIAN Calendar 1 1 read-write SCCR Status Clear Command Register 0x1C 32 write-only n 0x0 0x0 ACKCLR Acknowledge Clear 0 1 write-only ALRCLR Alarm Clear 1 1 write-only CALCLR Calendar Clear 4 1 write-only SECCLR Second Clear 2 1 write-only TDERRCLR Time and/or Date Free Running Error Clear 5 1 write-only TIMCLR Time Clear 3 1 write-only SR Status Register 0x18 32 read-only n 0x0 0x0 ACKUPD Acknowledge for Update 0 1 read-only FREERUN Time and calendar registers cannot be updated. 0 UPDATE Time and calendar registers can be updated. 1 ALARM Alarm Flag 1 1 read-only NO_ALARMEVENT No alarm matching condition occurred. 0 ALARMEVENT An alarm matching condition has occurred. 1 CALEV Calendar Event 4 1 read-only NO_CALEVENT No calendar event has occurred since the last clear. 0 CALEVENT At least one calendar event has occurred since the last clear. 1 SEC Second Event 2 1 read-only NO_SECEVENT No second event has occurred since the last clear. 0 SECEVENT At least one second event has occurred since the last clear. 1 TDERR Time and/or Date Free Running Error 5 1 read-only CORRECT The internal free running counters are carrying valid values since the last read of the Status Register (RTC_SR). 0 ERR_TIMEDATE The internal free running counters have been corrupted (invalid date or time, non-BCD values) since the last read and/or they are still invalid. 1 TIMEV Time Event 3 1 read-only NO_TIMEVENT No time event has occurred since the last clear. 0 TIMEVENT At least one time event has occurred since the last clear. 1 TIMALR Time Alarm Register 0x10 32 read-write n 0x0 0x0 AMPM AM/PM Indicator 22 1 read-write HOUR Hour Alarm 16 6 read-write HOUREN Hour Alarm Enable 23 1 read-write MIN Minute Alarm 8 7 read-write MINEN Minute Alarm Enable 15 1 read-write SEC Second Alarm 0 7 read-write SECEN Second Alarm Enable 7 1 read-write TIMR Time Register 0x8 32 read-write n 0x0 0x0 AMPM Ante Meridiem Post Meridiem Indicator 22 1 read-write HOUR Current Hour 16 6 read-write MIN Current Minute 8 7 read-write SEC Current Second 0 7 read-write TSDR0 TimeStamp Date Register 0 0xB4 32 read-only n 0x0 0x0 CENT Century of the Tamper 0 7 read-only DATE Date of the Tamper 24 6 read-only DAY Day of the Tamper 21 3 read-only MONTH Month of the Tamper 16 5 read-only YEAR Year of the Tamper 8 8 read-only TSDR1 TimeStamp Date Register 1 0xC0 32 read-only n 0x0 0x0 CENT Century of the Tamper 0 7 read-only DATE Date of the Tamper 24 6 read-only DAY Day of the Tamper 21 3 read-only MONTH Month of the Tamper 16 5 read-only YEAR Year of the Tamper 8 8 read-only TSSR0 TimeStamp Source Register 0 0xB8 32 read-only n 0x0 0x0 DET0 PIOBU Intrusion Detector 16 1 read-only DET1 PIOBU Intrusion Detector 17 1 read-only DET2 PIOBU Intrusion Detector 18 1 read-only DET3 PIOBU Intrusion Detector 19 1 read-only DET4 PIOBU Intrusion Detector 20 1 read-only DET5 PIOBU Intrusion Detector 21 1 read-only DET6 PIOBU Intrusion Detector 22 1 read-only DET7 PIOBU Intrusion Detector 23 1 read-only JTAG JTAG Pins Monitor 3 1 read-only TST Test Pin Monitor 2 1 read-only TSSR1 TimeStamp Source Register 1 0xC4 32 read-only n 0x0 0x0 DET0 PIOBU Intrusion Detector 16 1 read-only DET1 PIOBU Intrusion Detector 17 1 read-only DET2 PIOBU Intrusion Detector 18 1 read-only DET3 PIOBU Intrusion Detector 19 1 read-only DET4 PIOBU Intrusion Detector 20 1 read-only DET5 PIOBU Intrusion Detector 21 1 read-only DET6 PIOBU Intrusion Detector 22 1 read-only DET7 PIOBU Intrusion Detector 23 1 read-only JTAG JTAG Pins Monitor 3 1 read-only TST Test Pin Monitor 2 1 read-only TSTR0 TimeStamp Time Register 0 0xB0 32 read-only n 0x0 0x0 AMPM AM/PM Indicator of the Tamper 22 1 read-only BACKUP System Mode of the Tamper 31 1 read-only HOUR Hours of the Tamper 16 6 read-only MIN Minutes of the Tamper 8 7 read-only SEC Seconds of the Tamper 0 7 read-only TEVCNT Tamper Events Counter 24 4 read-only TSTR1 TimeStamp Time Register 1 0xBC 32 read-only n 0x0 0x0 AMPM AM/PM Indicator of the Tamper 22 1 read-only BACKUP System Mode of the Tamper 31 1 read-only HOUR Hours of the Tamper 16 6 read-only MIN Minutes of the Tamper 8 7 read-only SEC Seconds of the Tamper 0 7 read-only VER Valid Entry Register 0x2C 32 read-only n 0x0 0x0 NVCAL Non-valid Calendar 1 1 read-only NVCALALR Non-valid Calendar Alarm 3 1 read-only NVTIM Non-valid Time 0 1 read-only NVTIMALR Non-valid Time Alarm 2 1 read-only SAIC Advanced Interrupt Controller SAIC 0x0 0x0 0x200 registers n FIQ 0 SAIC 66 CISR Core Interrupt Status Register 0x34 32 read-only n 0x0 0x0 NFIQ NFIQ Status 0 1 read-only NIRQ NIRQ Status 1 1 read-only DCR Debug Control Register 0x6C 32 read-write n 0x0 0x0 GMSK General Interrupt Mask 1 1 read-write PROT Protection Mode 0 1 read-write EOICR End of Interrupt Command Register 0x38 32 write-only n 0x0 0x0 ENDIT Interrupt Processing Complete Command 0 1 write-only FVR FIQ Vector Register 0x14 32 read-only n 0x0 0x0 FIQV FIQ Vector Register 0 32 read-only ICCR Interrupt Clear Command Register 0x48 32 write-only n 0x0 0x0 INTCLR Interrupt Clear 0 1 write-only IDCR Interrupt Disable Command Register 0x44 32 write-only n 0x0 0x0 INTD Interrupt Disable 0 1 write-only IECR Interrupt Enable Command Register 0x40 32 write-only n 0x0 0x0 INTEN Interrupt Enable 0 1 write-only IMR Interrupt Mask Register 0x30 32 read-only n 0x0 0x0 INTM Interrupt Mask 0 1 read-only IPR0 Interrupt Pending Register 0 0x20 32 read-only n 0x0 0x0 FIQ Interrupt Pending 0 1 read-only PID10 Interrupt Pending 10 1 read-only PID11 Interrupt Pending 11 1 read-only PID12 Interrupt Pending 12 1 read-only PID13 Interrupt Pending 13 1 read-only PID14 Interrupt Pending 14 1 read-only PID15 Interrupt Pending 15 1 read-only PID16 Interrupt Pending 16 1 read-only PID17 Interrupt Pending 17 1 read-only PID18 Interrupt Pending 18 1 read-only PID19 Interrupt Pending 19 1 read-only PID2 Interrupt Pending 2 1 read-only PID20 Interrupt Pending 20 1 read-only PID21 Interrupt Pending 21 1 read-only PID22 Interrupt Pending 22 1 read-only PID23 Interrupt Pending 23 1 read-only PID24 Interrupt Pending 24 1 read-only PID25 Interrupt Pending 25 1 read-only PID26 Interrupt Pending 26 1 read-only PID27 Interrupt Pending 27 1 read-only PID28 Interrupt Pending 28 1 read-only PID29 Interrupt Pending 29 1 read-only PID3 Interrupt Pending 3 1 read-only PID30 Interrupt Pending 30 1 read-only PID31 Interrupt Pending 31 1 read-only PID4 Interrupt Pending 4 1 read-only PID5 Interrupt Pending 5 1 read-only PID6 Interrupt Pending 6 1 read-only PID7 Interrupt Pending 7 1 read-only PID8 Interrupt Pending 8 1 read-only PID9 Interrupt Pending 9 1 read-only SYS Interrupt Pending 1 1 read-only IPR1 Interrupt Pending Register 1 0x24 32 read-only n 0x0 0x0 PID32 Interrupt Pending 0 1 read-only PID33 Interrupt Pending 1 1 read-only PID34 Interrupt Pending 2 1 read-only PID35 Interrupt Pending 3 1 read-only PID36 Interrupt Pending 4 1 read-only PID37 Interrupt Pending 5 1 read-only PID38 Interrupt Pending 6 1 read-only PID39 Interrupt Pending 7 1 read-only PID40 Interrupt Pending 8 1 read-only PID41 Interrupt Pending 9 1 read-only PID42 Interrupt Pending 10 1 read-only PID43 Interrupt Pending 11 1 read-only PID44 Interrupt Pending 12 1 read-only PID45 Interrupt Pending 13 1 read-only PID46 Interrupt Pending 14 1 read-only PID47 Interrupt Pending 15 1 read-only PID48 Interrupt Pending 16 1 read-only PID49 Interrupt Pending 17 1 read-only PID50 Interrupt Pending 18 1 read-only PID51 Interrupt Pending 19 1 read-only PID52 Interrupt Pending 20 1 read-only PID53 Interrupt Pending 21 1 read-only PID54 Interrupt Pending 22 1 read-only PID55 Interrupt Pending 23 1 read-only PID56 Interrupt Pending 24 1 read-only PID57 Interrupt Pending 25 1 read-only PID58 Interrupt Pending 26 1 read-only PID59 Interrupt Pending 27 1 read-only PID60 Interrupt Pending 28 1 read-only PID61 Interrupt Pending 29 1 read-only PID62 Interrupt Pending 30 1 read-only PID63 Interrupt Pending 31 1 read-only IPR2 Interrupt Pending Register 2 0x28 32 read-only n 0x0 0x0 PID64 Interrupt Pending 0 1 read-only PID65 Interrupt Pending 1 1 read-only PID66 Interrupt Pending 2 1 read-only PID67 Interrupt Pending 3 1 read-only PID68 Interrupt Pending 4 1 read-only PID69 Interrupt Pending 5 1 read-only PID70 Interrupt Pending 6 1 read-only PID71 Interrupt Pending 7 1 read-only PID72 Interrupt Pending 8 1 read-only PID73 Interrupt Pending 9 1 read-only PID74 Interrupt Pending 10 1 read-only PID75 Interrupt Pending 11 1 read-only PID76 Interrupt Pending 12 1 read-only PID77 Interrupt Pending 13 1 read-only PID78 Interrupt Pending 14 1 read-only PID79 Interrupt Pending 15 1 read-only PID80 Interrupt Pending 16 1 read-only PID81 Interrupt Pending 17 1 read-only PID82 Interrupt Pending 18 1 read-only PID83 Interrupt Pending 19 1 read-only PID84 Interrupt Pending 20 1 read-only PID85 Interrupt Pending 21 1 read-only PID86 Interrupt Pending 22 1 read-only PID87 Interrupt Pending 23 1 read-only PID88 Interrupt Pending 24 1 read-only PID89 Interrupt Pending 25 1 read-only PID90 Interrupt Pending 26 1 read-only PID91 Interrupt Pending 27 1 read-only PID92 Interrupt Pending 28 1 read-only PID93 Interrupt Pending 29 1 read-only PID94 Interrupt Pending 30 1 read-only PID95 Interrupt Pending 31 1 read-only IPR3 Interrupt Pending Register 3 0x2C 32 read-only n 0x0 0x0 PID100 Interrupt Pending 4 1 read-only PID101 Interrupt Pending 5 1 read-only PID102 Interrupt Pending 6 1 read-only PID103 Interrupt Pending 7 1 read-only PID104 Interrupt Pending 8 1 read-only PID105 Interrupt Pending 9 1 read-only PID106 Interrupt Pending 10 1 read-only PID107 Interrupt Pending 11 1 read-only PID108 Interrupt Pending 12 1 read-only PID109 Interrupt Pending 13 1 read-only PID110 Interrupt Pending 14 1 read-only PID111 Interrupt Pending 15 1 read-only PID112 Interrupt Pending 16 1 read-only PID113 Interrupt Pending 17 1 read-only PID114 Interrupt Pending 18 1 read-only PID115 Interrupt Pending 19 1 read-only PID116 Interrupt Pending 20 1 read-only PID117 Interrupt Pending 21 1 read-only PID118 Interrupt Pending 22 1 read-only PID119 Interrupt Pending 23 1 read-only PID120 Interrupt Pending 24 1 read-only PID121 Interrupt Pending 25 1 read-only PID122 Interrupt Pending 26 1 read-only PID123 Interrupt Pending 27 1 read-only PID124 Interrupt Pending 28 1 read-only PID125 Interrupt Pending 29 1 read-only PID126 Interrupt Pending 30 1 read-only PID127 Interrupt Pending 31 1 read-only PID96 Interrupt Pending 0 1 read-only PID97 Interrupt Pending 1 1 read-only PID98 Interrupt Pending 2 1 read-only PID99 Interrupt Pending 3 1 read-only ISCR Interrupt Set Command Register 0x4C 32 write-only n 0x0 0x0 INTSET Interrupt Set 0 1 write-only ISR Interrupt Status Register 0x18 32 read-only n 0x0 0x0 IRQID Current Interrupt Identifier 0 7 read-only IVR Interrupt Vector Register 0x10 32 read-only n 0x0 0x0 IRQV Interrupt Vector Register 0 32 read-only SMR Source Mode Register 0x4 32 read-write n 0x0 0x0 PRIOR Priority Level 0 3 read-write SRCTYPE Interrupt Source Type 5 2 read-write INT_LEVEL_SENSITIVE High level Sensitive for internal sourceLow level Sensitive for external source 0x0 INT_EDGE_TRIGGERED Positive edge triggered for internal sourceNegative edge triggered for external source 0x1 EXT_HIGH_LEVEL High level Sensitive for internal sourceHigh level Sensitive for external source 0x2 EXT_POSITIVE_EDGE Positive edge triggered for internal sourcePositive edge triggered for external source 0x3 SPU Spurious Interrupt Vector Register 0x3C 32 read-write n 0x0 0x0 SIVR Spurious Interrupt Vector Register 0 32 read-write SSR Source Select Register 0x0 32 read-write n 0x0 0x0 INTSEL Interrupt Line Selection 0 7 read-write SVR Source Vector Register 0x8 32 read-write n 0x0 0x0 VECTOR Source Vector 0 32 read-write WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 read-write WPKEY Write Protection Key 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 0x414943 WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 read-only WPVSRC Write Protection Violation Source 8 16 read-only SCKC Slow Clock Controller SYSC 0x0 0x0 0x200 registers n CR Slow Clock Controller Configuration Register 0x0 32 read-write n 0x0 0x0 OSCSEL Slow Clock Selector 3 1 read-write RC Slow clock is the embedded 32 kHz (typical) RC oscillator. 0 XTAL Slow clock is the 32.768 kHz crystal oscillator. 1 SFC Secure Fuse Controller SFC 0x0 0x0 0x50 registers n SFC 57 DR0 SFC Data Register 0x20 32 read-write n DATA Fuse Data 0 32 read-write DR1 SFC Data Register 0x24 32 read-write n DATA Fuse Data 0 32 read-write DR10 SFC Data Register 0x48 32 read-write n DATA Fuse Data 0 32 read-write DR11 SFC Data Register 0x4C 32 read-write n DATA Fuse Data 0 32 read-write DR12 SFC Data Register 0x50 32 read-write n DATA Fuse Data 0 32 read-write DR13 SFC Data Register 0x54 32 read-write n DATA Fuse Data 0 32 read-write DR14 SFC Data Register 0x58 32 read-write n DATA Fuse Data 0 32 read-write DR15 SFC Data Register 0x5C 32 read-write n DATA Fuse Data 0 32 read-write DR2 SFC Data Register 0x28 32 read-write n DATA Fuse Data 0 32 read-write DR3 SFC Data Register 0x2C 32 read-write n DATA Fuse Data 0 32 read-write DR4 SFC Data Register 0x30 32 read-write n DATA Fuse Data 0 32 read-write DR5 SFC Data Register 0x34 32 read-write n DATA Fuse Data 0 32 read-write DR6 SFC Data Register 0x38 32 read-write n DATA Fuse Data 0 32 read-write DR7 SFC Data Register 0x3C 32 read-write n DATA Fuse Data 0 32 read-write DR8 SFC Data Register 0x40 32 read-write n DATA Fuse Data 0 32 read-write DR9 SFC Data Register 0x44 32 read-write n DATA Fuse Data 0 32 read-write DR[0] SFC Data Register 0x40 32 read-write n 0x0 0x0 DATA Fuse Data 0 32 read-write DR[10] SFC Data Register 0x25C 32 read-write n 0x0 0x0 DATA Fuse Data 0 32 read-write DR[11] SFC Data Register 0x2A8 32 read-write n 0x0 0x0 DATA Fuse Data 0 32 read-write DR[12] SFC Data Register 0x2F8 32 read-write n 0x0 0x0 DATA Fuse Data 0 32 read-write DR[13] SFC Data Register 0x34C 32 read-write n 0x0 0x0 DATA Fuse Data 0 32 read-write DR[14] SFC Data Register 0x3A4 32 read-write n 0x0 0x0 DATA Fuse Data 0 32 read-write DR[15] SFC Data Register 0x400 32 read-write n 0x0 0x0 DATA Fuse Data 0 32 read-write DR[1] SFC Data Register 0x64 32 read-write n 0x0 0x0 DATA Fuse Data 0 32 read-write DR[2] SFC Data Register 0x8C 32 read-write n 0x0 0x0 DATA Fuse Data 0 32 read-write DR[3] SFC Data Register 0xB8 32 read-write n 0x0 0x0 DATA Fuse Data 0 32 read-write DR[4] SFC Data Register 0xE8 32 read-write n 0x0 0x0 DATA Fuse Data 0 32 read-write DR[5] SFC Data Register 0x11C 32 read-write n 0x0 0x0 DATA Fuse Data 0 32 read-write DR[6] SFC Data Register 0x154 32 read-write n 0x0 0x0 DATA Fuse Data 0 32 read-write DR[7] SFC Data Register 0x190 32 read-write n 0x0 0x0 DATA Fuse Data 0 32 read-write DR[8] SFC Data Register 0x1D0 32 read-write n 0x0 0x0 DATA Fuse Data 0 32 read-write DR[9] SFC Data Register 0x214 32 read-write n 0x0 0x0 DATA Fuse Data 0 32 read-write IDR SFC Interrupt Disable Register 0x14 32 write-only n 0x0 0x0 ACE Atmel Check Error Interrupt Disable 17 1 write-only PGMC Programming Sequence Completed Interrupt Disable 0 1 write-only PGMF Programming Sequence Failed Interrupt Disable 1 1 write-only IER SFC Interrupt Enable Register 0x10 32 write-only n 0x0 0x0 ACE Atmel Check Error Interrupt Enable 17 1 write-only PGMC Programming Sequence Completed Interrupt Enable 0 1 write-only PGMF Programming Sequence Failed Interrupt Enable 1 1 write-only IMR SFC Interrupt Mask Register 0x18 32 read-only n 0x0 0x0 ACE Atmel Check Error Interrupt Mask 17 1 read-only PGMC Programming Sequence Completed Interrupt Mask 0 1 read-only PGMF Programming Sequence Failed Interrupt Mask 1 1 read-only KR SFC Key Register 0x0 32 write-only n 0x0 0x0 KEY Key Code 0 8 write-only MR SFC Mode Register 0x4 32 read-write n 0x0 0x0 MSK Mask Data Registers 0 1 read-write SR SFC Status Register 0x1C 32 read-only n 0x0 0x0 ACE Atmel Check Error (cleared on read) 17 1 read-only APLE Atmel Programming Lock Error (cleared on read) 16 1 read-only PGMC Programming Sequence Completed (cleared on read) 0 1 read-only PGMF Programming Sequence Failed (cleared on read) 1 1 read-only SFR Special Function Registers SFR 0x0 0x0 0x50 registers n SFR 64 AICREDIR AIC Interrupt Redirection Register 0x54 32 read-write n 0x0 0x0 AICREDIRKEY Unlock Key 1 31 read-write NSAIC Interrupt Redirection to Non-Secure AIC 0 1 read-write ANACFG Analog Configuration Register 0x44 32 read-write n 0x0 0x0 SM_DDR_EN DDR Supply Monitor Enable 0 1 read-write DDRCFG DDR Configuration Register 0x4 32 read-write n 0x0 0x0 FDQIEN Force DDR_DQ Input Buffer Always On 16 1 read-write FDQSIEN Force DDR_DQS Input Buffer Always On 17 1 read-write OHCIICR OHCI Interrupt Configuration Register 0x10 32 read-write n 0x0 0x0 APPSTART Reserved 5 1 read-write ARIE OHCI Asynchronous Resume Interrupt Enable 4 1 read-write RES0 USB PORTx RESET 0 1 read-write RES1 USB PORTx RESET 1 1 read-write RES2 USB PORTx RESET 2 1 read-write UDPPUDIS USB DEVICE PULL-UP DISABLE 23 1 read-write OHCIISR OHCI Interrupt Status Register 0x14 32 read-only n 0x0 0x0 RIS0 OHCI Resume Interrupt Status Port 0 0 1 read-only RIS1 OHCI Resume Interrupt Status Port 1 1 1 read-only RIS2 OHCI Resume Interrupt Status Port 2 2 1 read-only SECURE Security Configuration Register 0x28 32 read-write n 0x0 0x0 FUSE Disable Access to Fuse Controller 8 1 read-write ROM Disable Access to ROM Code 0 1 read-write SN0 Serial Number 0 Register 0x4C 32 read-only n 0x0 0x0 SN0 Serial Number 0 0 32 read-only SN1 Serial Number 1 Register 0x50 32 read-only n 0x0 0x0 SN1 Serial Number 1 0 32 read-only SHA Secure Hash Algorithm SHA 0x0 0x0 0x50 registers n SHA 15 CR Control Register 0x0 32 write-only n 0x0 0x0 FIRST First Block of a Message 4 1 write-only START Start Processing 0 1 write-only SWRST Software Reset 8 1 write-only WUIHV Write User Initial Hash Values 12 1 write-only IDATAR0 Input Data 0 Register 0x40 32 write-only n IDATA Input Data 0 32 write-only IDATAR1 Input Data 0 Register 0x44 32 write-only n IDATA Input Data 0 32 write-only IDATAR10 Input Data 0 Register 0x68 32 write-only n IDATA Input Data 0 32 write-only IDATAR11 Input Data 0 Register 0x6C 32 write-only n IDATA Input Data 0 32 write-only IDATAR12 Input Data 0 Register 0x70 32 write-only n IDATA Input Data 0 32 write-only IDATAR13 Input Data 0 Register 0x74 32 write-only n IDATA Input Data 0 32 write-only IDATAR14 Input Data 0 Register 0x78 32 write-only n IDATA Input Data 0 32 write-only IDATAR15 Input Data 0 Register 0x7C 32 write-only n IDATA Input Data 0 32 write-only IDATAR2 Input Data 0 Register 0x48 32 write-only n IDATA Input Data 0 32 write-only IDATAR3 Input Data 0 Register 0x4C 32 write-only n IDATA Input Data 0 32 write-only IDATAR4 Input Data 0 Register 0x50 32 write-only n IDATA Input Data 0 32 write-only IDATAR5 Input Data 0 Register 0x54 32 write-only n IDATA Input Data 0 32 write-only IDATAR6 Input Data 0 Register 0x58 32 write-only n IDATA Input Data 0 32 write-only IDATAR7 Input Data 0 Register 0x5C 32 write-only n IDATA Input Data 0 32 write-only IDATAR8 Input Data 0 Register 0x60 32 write-only n IDATA Input Data 0 32 write-only IDATAR9 Input Data 0 Register 0x64 32 write-only n IDATA Input Data 0 32 write-only IDATAR[0] Input Data 0 Register 0x80 32 write-only n 0x0 0x0 IDATA Input Data 0 32 write-only IDATAR[10] Input Data 0 Register 0x3DC 32 write-only n 0x0 0x0 IDATA Input Data 0 32 write-only IDATAR[11] Input Data 0 Register 0x448 32 write-only n 0x0 0x0 IDATA Input Data 0 32 write-only IDATAR[12] Input Data 0 Register 0x4B8 32 write-only n 0x0 0x0 IDATA Input Data 0 32 write-only IDATAR[13] Input Data 0 Register 0x52C 32 write-only n 0x0 0x0 IDATA Input Data 0 32 write-only IDATAR[14] Input Data 0 Register 0x5A4 32 write-only n 0x0 0x0 IDATA Input Data 0 32 write-only IDATAR[15] Input Data 0 Register 0x620 32 write-only n 0x0 0x0 IDATA Input Data 0 32 write-only IDATAR[1] Input Data 0 Register 0xC4 32 write-only n 0x0 0x0 IDATA Input Data 0 32 write-only IDATAR[2] Input Data 0 Register 0x10C 32 write-only n 0x0 0x0 IDATA Input Data 0 32 write-only IDATAR[3] Input Data 0 Register 0x158 32 write-only n 0x0 0x0 IDATA Input Data 0 32 write-only IDATAR[4] Input Data 0 Register 0x1A8 32 write-only n 0x0 0x0 IDATA Input Data 0 32 write-only IDATAR[5] Input Data 0 Register 0x1FC 32 write-only n 0x0 0x0 IDATA Input Data 0 32 write-only IDATAR[6] Input Data 0 Register 0x254 32 write-only n 0x0 0x0 IDATA Input Data 0 32 write-only IDATAR[7] Input Data 0 Register 0x2B0 32 write-only n 0x0 0x0 IDATA Input Data 0 32 write-only IDATAR[8] Input Data 0 Register 0x310 32 write-only n 0x0 0x0 IDATA Input Data 0 32 write-only IDATAR[9] Input Data 0 Register 0x374 32 write-only n 0x0 0x0 IDATA Input Data 0 32 write-only IDR Interrupt Disable Register 0x14 32 write-only n 0x0 0x0 DATRDY Data Ready Interrupt Disable 0 1 write-only URAD Unspecified Register Access Detection Interrupt Disable 8 1 write-only IER Interrupt Enable Register 0x10 32 write-only n 0x0 0x0 DATRDY Data Ready Interrupt Enable 0 1 write-only URAD Unspecified Register Access Detection Interrupt Enable 8 1 write-only IMR Interrupt Mask Register 0x18 32 read-only n 0x0 0x0 DATRDY Data Ready Interrupt Mask 0 1 read-only URAD Unspecified Register Access Detection Interrupt Mask 8 1 read-only IODATAR0 Input/Output Data 0 Register 0x80 32 read-write n IODATA Input/Output Data 0 32 read-write IODATAR1 Input/Output Data 0 Register 0x84 32 read-write n IODATA Input/Output Data 0 32 read-write IODATAR10 Input/Output Data 0 Register 0xA8 32 read-write n IODATA Input/Output Data 0 32 read-write IODATAR11 Input/Output Data 0 Register 0xAC 32 read-write n IODATA Input/Output Data 0 32 read-write IODATAR12 Input/Output Data 0 Register 0xB0 32 read-write n IODATA Input/Output Data 0 32 read-write IODATAR13 Input/Output Data 0 Register 0xB4 32 read-write n IODATA Input/Output Data 0 32 read-write IODATAR14 Input/Output Data 0 Register 0xB8 32 read-write n IODATA Input/Output Data 0 32 read-write IODATAR15 Input/Output Data 0 Register 0xBC 32 read-write n IODATA Input/Output Data 0 32 read-write IODATAR2 Input/Output Data 0 Register 0x88 32 read-write n IODATA Input/Output Data 0 32 read-write IODATAR3 Input/Output Data 0 Register 0x8C 32 read-write n IODATA Input/Output Data 0 32 read-write IODATAR4 Input/Output Data 0 Register 0x90 32 read-write n IODATA Input/Output Data 0 32 read-write IODATAR5 Input/Output Data 0 Register 0x94 32 read-write n IODATA Input/Output Data 0 32 read-write IODATAR6 Input/Output Data 0 Register 0x98 32 read-write n IODATA Input/Output Data 0 32 read-write IODATAR7 Input/Output Data 0 Register 0x9C 32 read-write n IODATA Input/Output Data 0 32 read-write IODATAR8 Input/Output Data 0 Register 0xA0 32 read-write n IODATA Input/Output Data 0 32 read-write IODATAR9 Input/Output Data 0 Register 0xA4 32 read-write n IODATA Input/Output Data 0 32 read-write IODATAR[0] Input/Output Data 0 Register 0x100 32 read-write n 0x0 0x0 IODATA Input/Output Data 0 32 read-write IODATAR[10] Input/Output Data 0 Register 0x6DC 32 read-write n 0x0 0x0 IODATA Input/Output Data 0 32 read-write IODATAR[11] Input/Output Data 0 Register 0x788 32 read-write n 0x0 0x0 IODATA Input/Output Data 0 32 read-write IODATAR[12] Input/Output Data 0 Register 0x838 32 read-write n 0x0 0x0 IODATA Input/Output Data 0 32 read-write IODATAR[13] Input/Output Data 0 Register 0x8EC 32 read-write n 0x0 0x0 IODATA Input/Output Data 0 32 read-write IODATAR[14] Input/Output Data 0 Register 0x9A4 32 read-write n 0x0 0x0 IODATA Input/Output Data 0 32 read-write IODATAR[15] Input/Output Data 0 Register 0xA60 32 read-write n 0x0 0x0 IODATA Input/Output Data 0 32 read-write IODATAR[1] Input/Output Data 0 Register 0x184 32 read-write n 0x0 0x0 IODATA Input/Output Data 0 32 read-write IODATAR[2] Input/Output Data 0 Register 0x20C 32 read-write n 0x0 0x0 IODATA Input/Output Data 0 32 read-write IODATAR[3] Input/Output Data 0 Register 0x298 32 read-write n 0x0 0x0 IODATA Input/Output Data 0 32 read-write IODATAR[4] Input/Output Data 0 Register 0x328 32 read-write n 0x0 0x0 IODATA Input/Output Data 0 32 read-write IODATAR[5] Input/Output Data 0 Register 0x3BC 32 read-write n 0x0 0x0 IODATA Input/Output Data 0 32 read-write IODATAR[6] Input/Output Data 0 Register 0x454 32 read-write n 0x0 0x0 IODATA Input/Output Data 0 32 read-write IODATAR[7] Input/Output Data 0 Register 0x4F0 32 read-write n 0x0 0x0 IODATA Input/Output Data 0 32 read-write IODATAR[8] Input/Output Data 0 Register 0x590 32 read-write n 0x0 0x0 IODATA Input/Output Data 0 32 read-write IODATAR[9] Input/Output Data 0 Register 0x634 32 read-write n 0x0 0x0 IODATA Input/Output Data 0 32 read-write ISR Interrupt Status Register 0x1C 32 read-only n 0x0 0x0 DATRDY Data Ready (cleared by writing a 1 to bit SWRST or START in SHA_CR, or by reading SHA_IODATARx) 0 1 read-only URAD Unspecified Register Access Detection Status (cleared by writing a 1 to SWRST bit in SHA_CR) 8 1 read-only URAT Unspecified Register Access Type (cleared by writing a 1 to SWRST bit in SHA_CR) 12 3 read-only MR Mode Register 0x4 32 read-write n 0x0 0x0 ALGO SHA Algorithm 8 4 read-write SHA1 SHA1 algorithm processed 0x0 SHA256 SHA256 algorithm processed 0x1 SHA384 SHA384 algorithm processed 0x2 SHA512 SHA512 algorithm processed 0x3 SHA224 SHA224 algorithm processed 0x4 DUALBUFF Dual Input Buffer 16 1 read-write INACTIVE SHA_IDATARx and SHA_IODATARx cannot be written during processing of previous block. 0 ACTIVE SHA_IDATARx and SHA_IODATARx can be written during processing of previous block when SMOD value = 2. It speeds up the overall runtime of large files. 1 PROCDLY Processing Delay 4 1 read-write SHORTEST SHA processing runtime is the shortest one 0 LONGEST SHA processing runtime is the longest one (reduces the SHA bandwidth requirement, reduces the system bus overload) 1 SMOD Start Mode 0 2 read-write MANUAL_START Manual Mode 0x0 AUTO_START Auto Mode 0x1 IDATAR0_START SHA_IDATAR0 access only Auto Mode 0x2 UIHV User Initial Hash Values 5 1 read-write SHDWC Shutdown Controller SYSC 0x0 0x0 0x200 registers n CR Shutdown Control Register 0x0 32 write-only n 0x0 0x0 KEY Password 24 8 write-only PASSWD Writing any other value in this field aborts the write operation. 0xA5 SHDW Shutdown Command 0 1 write-only MR Shutdown Mode Register 0x4 32 read-write n 0x0 0x0 CPTWK0 Debounce Counter on Wake-up 0 4 4 read-write CPTWK1 Debounce Counter on Wake-up 1 12 4 read-write RTCWKEN Real-time Clock Wake-up Enable 17 1 read-write WKMODE0 Wake-up Mode 0 0 2 read-write NO_DETECTION No detection is performed on the wake-up input 0x0 RISING_EDGE Low to high transition triggers the detection process 0x1 FALLING_EDGE High to low level transition triggers the detection process 0x2 ANY_EDGE Any edge on the wake-up input triggers the detection process 0x3 WKMODE1 Wake-up Mode 1 8 2 read-write NO_DETECTION No detection is performed on the wake-up input 0x0 RISING_EDGE Low to high transition triggers the detection process 0x1 FALLING_EDGE High to low level transition triggers the detection process 0x2 ANY_EDGE Any edge on the wake-up input triggers the detection process 0x3 SR Shutdown Status Register 0x8 32 read-only n 0x0 0x0 RTCWK Real-time Clock Wake-up 17 1 read-only WAKEUP0 Wake-up 0 Status 0 1 read-only WAKEUP1 Wake-up 1 Status 1 1 read-only SMD Software Modem Device SMD 0x0 0x0 0x100000 registers n SMD 61 DRIVE SMD Drive Register 0xC 32 read-write n 0x0 0x0 DC_PWRCLKPN Direct Control of PWRCLKP, PWRCLKN Pins Enable 1 1 read-write MIE MADCVS Interrupt Enable 0 1 read-write PWRCLKN_PCS2 PWRCLKN Pin Control Select 4 2 read-write PWRCLKP_PCS PWRCLKP Pin Control Select 6 2 read-write PWRCLKP_PV PWRCLKP Pin Value 3 1 read-write PWRCLKP_PV2 PWRCLKP Pin Value 2 1 read-write SPI0 Serial Peripheral Interface 0 SPI 0x0 0x0 0x50 registers n SPI0 37 CR Control Register 0x0 32 write-only n 0x0 0x0 LASTXFER Last Transfer 24 1 write-only REQCLR Request to Clear the Comparison Trigger 12 1 write-only SPIDIS SPI Disable 1 1 write-only SPIEN SPI Enable 0 1 write-only SWRST SPI Software Reset 7 1 write-only CSR0 Chip Select Register (CS_number = 0) 0x30 32 read-write n BITS Bits Per Transfer 4 4 read-write 8_BIT 8 bits for transfer 0x0 9_BIT 9 bits for transfer 0x1 10_BIT 10 bits for transfer 0x2 11_BIT 11 bits for transfer 0x3 12_BIT 12 bits for transfer 0x4 13_BIT 13 bits for transfer 0x5 14_BIT 14 bits for transfer 0x6 15_BIT 15 bits for transfer 0x7 16_BIT 16 bits for transfer 0x8 CPOL Clock Polarity 0 1 read-write CSAAT Chip Select Active After Transfer 3 1 read-write CSNAAT Chip Select Not Active After Transfer (Ignored if CSAAT = 1) 2 1 read-write DLYBCT Delay Between Consecutive Transfers 24 8 read-write DLYBS Delay Before SPCK 16 8 read-write NCPHA Clock Phase 1 1 read-write SCBR Serial Clock Bit Rate 8 8 read-write CSR1 Chip Select Register (CS_number = 0) 0x34 32 read-write n BITS Bits Per Transfer 4 4 read-write 8_BIT 8 bits for transfer 0x0 9_BIT 9 bits for transfer 0x1 10_BIT 10 bits for transfer 0x2 11_BIT 11 bits for transfer 0x3 12_BIT 12 bits for transfer 0x4 13_BIT 13 bits for transfer 0x5 14_BIT 14 bits for transfer 0x6 15_BIT 15 bits for transfer 0x7 16_BIT 16 bits for transfer 0x8 CPOL Clock Polarity 0 1 read-write CSAAT Chip Select Active After Transfer 3 1 read-write CSNAAT Chip Select Not Active After Transfer (Ignored if CSAAT = 1) 2 1 read-write DLYBCT Delay Between Consecutive Transfers 24 8 read-write DLYBS Delay Before SPCK 16 8 read-write NCPHA Clock Phase 1 1 read-write SCBR Serial Clock Bit Rate 8 8 read-write CSR2 Chip Select Register (CS_number = 0) 0x38 32 read-write n BITS Bits Per Transfer 4 4 read-write 8_BIT 8 bits for transfer 0x0 9_BIT 9 bits for transfer 0x1 10_BIT 10 bits for transfer 0x2 11_BIT 11 bits for transfer 0x3 12_BIT 12 bits for transfer 0x4 13_BIT 13 bits for transfer 0x5 14_BIT 14 bits for transfer 0x6 15_BIT 15 bits for transfer 0x7 16_BIT 16 bits for transfer 0x8 CPOL Clock Polarity 0 1 read-write CSAAT Chip Select Active After Transfer 3 1 read-write CSNAAT Chip Select Not Active After Transfer (Ignored if CSAAT = 1) 2 1 read-write DLYBCT Delay Between Consecutive Transfers 24 8 read-write DLYBS Delay Before SPCK 16 8 read-write NCPHA Clock Phase 1 1 read-write SCBR Serial Clock Bit Rate 8 8 read-write CSR3 Chip Select Register (CS_number = 0) 0x3C 32 read-write n BITS Bits Per Transfer 4 4 read-write 8_BIT 8 bits for transfer 0x0 9_BIT 9 bits for transfer 0x1 10_BIT 10 bits for transfer 0x2 11_BIT 11 bits for transfer 0x3 12_BIT 12 bits for transfer 0x4 13_BIT 13 bits for transfer 0x5 14_BIT 14 bits for transfer 0x6 15_BIT 15 bits for transfer 0x7 16_BIT 16 bits for transfer 0x8 CPOL Clock Polarity 0 1 read-write CSAAT Chip Select Active After Transfer 3 1 read-write CSNAAT Chip Select Not Active After Transfer (Ignored if CSAAT = 1) 2 1 read-write DLYBCT Delay Between Consecutive Transfers 24 8 read-write DLYBS Delay Before SPCK 16 8 read-write NCPHA Clock Phase 1 1 read-write SCBR Serial Clock Bit Rate 8 8 read-write CSR[0] Chip Select Register (CS_number = 0) 0x60 32 read-write n 0x0 0x0 BITS Bits Per Transfer 4 4 read-write 8_BIT 8 bits for transfer 0x0 9_BIT 9 bits for transfer 0x1 10_BIT 10 bits for transfer 0x2 11_BIT 11 bits for transfer 0x3 12_BIT 12 bits for transfer 0x4 13_BIT 13 bits for transfer 0x5 14_BIT 14 bits for transfer 0x6 15_BIT 15 bits for transfer 0x7 16_BIT 16 bits for transfer 0x8 CPOL Clock Polarity 0 1 read-write CSAAT Chip Select Active After Transfer 3 1 read-write CSNAAT Chip Select Not Active After Transfer (Ignored if CSAAT = 1) 2 1 read-write DLYBCT Delay Between Consecutive Transfers 24 8 read-write DLYBS Delay Before SPCK 16 8 read-write NCPHA Clock Phase 1 1 read-write SCBR Serial Clock Bit Rate 8 8 read-write CSR[1] Chip Select Register (CS_number = 0) 0x94 32 read-write n 0x0 0x0 BITS Bits Per Transfer 4 4 read-write 8_BIT 8 bits for transfer 0x0 9_BIT 9 bits for transfer 0x1 10_BIT 10 bits for transfer 0x2 11_BIT 11 bits for transfer 0x3 12_BIT 12 bits for transfer 0x4 13_BIT 13 bits for transfer 0x5 14_BIT 14 bits for transfer 0x6 15_BIT 15 bits for transfer 0x7 16_BIT 16 bits for transfer 0x8 CPOL Clock Polarity 0 1 read-write CSAAT Chip Select Active After Transfer 3 1 read-write CSNAAT Chip Select Not Active After Transfer (Ignored if CSAAT = 1) 2 1 read-write DLYBCT Delay Between Consecutive Transfers 24 8 read-write DLYBS Delay Before SPCK 16 8 read-write NCPHA Clock Phase 1 1 read-write SCBR Serial Clock Bit Rate 8 8 read-write CSR[2] Chip Select Register (CS_number = 0) 0xCC 32 read-write n 0x0 0x0 BITS Bits Per Transfer 4 4 read-write 8_BIT 8 bits for transfer 0x0 9_BIT 9 bits for transfer 0x1 10_BIT 10 bits for transfer 0x2 11_BIT 11 bits for transfer 0x3 12_BIT 12 bits for transfer 0x4 13_BIT 13 bits for transfer 0x5 14_BIT 14 bits for transfer 0x6 15_BIT 15 bits for transfer 0x7 16_BIT 16 bits for transfer 0x8 CPOL Clock Polarity 0 1 read-write CSAAT Chip Select Active After Transfer 3 1 read-write CSNAAT Chip Select Not Active After Transfer (Ignored if CSAAT = 1) 2 1 read-write DLYBCT Delay Between Consecutive Transfers 24 8 read-write DLYBS Delay Before SPCK 16 8 read-write NCPHA Clock Phase 1 1 read-write SCBR Serial Clock Bit Rate 8 8 read-write CSR[3] Chip Select Register (CS_number = 0) 0x108 32 read-write n 0x0 0x0 BITS Bits Per Transfer 4 4 read-write 8_BIT 8 bits for transfer 0x0 9_BIT 9 bits for transfer 0x1 10_BIT 10 bits for transfer 0x2 11_BIT 11 bits for transfer 0x3 12_BIT 12 bits for transfer 0x4 13_BIT 13 bits for transfer 0x5 14_BIT 14 bits for transfer 0x6 15_BIT 15 bits for transfer 0x7 16_BIT 16 bits for transfer 0x8 CPOL Clock Polarity 0 1 read-write CSAAT Chip Select Active After Transfer 3 1 read-write CSNAAT Chip Select Not Active After Transfer (Ignored if CSAAT = 1) 2 1 read-write DLYBCT Delay Between Consecutive Transfers 24 8 read-write DLYBS Delay Before SPCK 16 8 read-write NCPHA Clock Phase 1 1 read-write SCBR Serial Clock Bit Rate 8 8 read-write IDR Interrupt Disable Register 0x18 32 write-only n 0x0 0x0 MODF Mode Fault Error Interrupt Disable 2 1 write-only NSSR NSS Rising Interrupt Disable 8 1 write-only OVRES Overrun Error Interrupt Disable 3 1 write-only RDRF Receive Data Register Full Interrupt Disable 0 1 write-only TDRE SPI Transmit Data Register Empty Interrupt Disable 1 1 write-only TXEMPTY Transmission Registers Empty Disable 9 1 write-only UNDES Underrun Error Interrupt Disable 10 1 write-only IER Interrupt Enable Register 0x14 32 write-only n 0x0 0x0 MODF Mode Fault Error Interrupt Enable 2 1 write-only NSSR NSS Rising Interrupt Enable 8 1 write-only OVRES Overrun Error Interrupt Enable 3 1 write-only RDRF Receive Data Register Full Interrupt Enable 0 1 write-only TDRE SPI Transmit Data Register Empty Interrupt Enable 1 1 write-only TXEMPTY Transmission Registers Empty Enable 9 1 write-only UNDES Underrun Error Interrupt Enable 10 1 write-only IMR Interrupt Mask Register 0x1C 32 read-only n 0x0 0x0 MODF Mode Fault Error Interrupt Mask 2 1 read-only NSSR NSS Rising Interrupt Mask 8 1 read-only OVRES Overrun Error Interrupt Mask 3 1 read-only RDRF Receive Data Register Full Interrupt Mask 0 1 read-only TDRE SPI Transmit Data Register Empty Interrupt Mask 1 1 read-only TXEMPTY Transmission Registers Empty Mask 9 1 read-only UNDES Underrun Error Interrupt Mask 10 1 read-only MR Mode Register 0x4 32 read-write n 0x0 0x0 DLYBCS Delay Between Chip Selects 24 8 read-write LLB Local Loopback Enable 7 1 read-write MODFDIS Mode Fault Detection 4 1 read-write MSTR Master/Slave Mode 0 1 read-write PCS Peripheral Chip Select 16 4 read-write PCSDEC Chip Select Decode 2 1 read-write PS Peripheral Select 1 1 read-write WDRBT Wait Data Read Before Transfer 5 1 read-write RDR Receive Data Register 0x8 32 read-only n 0x0 0x0 PCS Peripheral Chip Select 16 4 read-only RD Receive Data 0 16 read-only SR Status Register 0x10 32 read-only n 0x0 0x0 MODF Mode Fault Error (cleared on read) 2 1 read-only NSSR NSS Rising (cleared on read) 8 1 read-only OVRES Overrun Error Status (cleared on read) 3 1 read-only RDRF Receive Data Register Full (cleared by reading SPI_RDR) 0 1 read-only SPIENS SPI Enable Status 16 1 read-only TDRE Transmit Data Register Empty (cleared by writing SPI_TDR) 1 1 read-only TXEMPTY Transmission Registers Empty (cleared by writing SPI_TDR) 9 1 read-only UNDES Underrun Error Status (Slave mode only) (cleared on read) 10 1 read-only TDR Transmit Data Register 0xC 32 write-only n 0x0 0x0 LASTXFER Last Transfer 24 1 write-only PCS Peripheral Chip Select 16 4 write-only TD Transmit Data 0 16 write-only WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 read-write WPKEY Write Protection Key 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 0x535049 WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 read-only WPVSRC Write Protection Violation Source 8 8 read-only SPI1 Serial Peripheral Interface 1 SPI 0x0 0x0 0x50 registers n SPI1 38 CR Control Register 0x0 32 write-only n 0x0 0x0 LASTXFER Last Transfer 24 1 write-only REQCLR Request to Clear the Comparison Trigger 12 1 write-only SPIDIS SPI Disable 1 1 write-only SPIEN SPI Enable 0 1 write-only SWRST SPI Software Reset 7 1 write-only CSR0 Chip Select Register (CS_number = 0) 0x30 32 read-write n BITS Bits Per Transfer 4 4 read-write 8_BIT 8 bits for transfer 0x0 9_BIT 9 bits for transfer 0x1 10_BIT 10 bits for transfer 0x2 11_BIT 11 bits for transfer 0x3 12_BIT 12 bits for transfer 0x4 13_BIT 13 bits for transfer 0x5 14_BIT 14 bits for transfer 0x6 15_BIT 15 bits for transfer 0x7 16_BIT 16 bits for transfer 0x8 CPOL Clock Polarity 0 1 read-write CSAAT Chip Select Active After Transfer 3 1 read-write CSNAAT Chip Select Not Active After Transfer (Ignored if CSAAT = 1) 2 1 read-write DLYBCT Delay Between Consecutive Transfers 24 8 read-write DLYBS Delay Before SPCK 16 8 read-write NCPHA Clock Phase 1 1 read-write SCBR Serial Clock Bit Rate 8 8 read-write CSR1 Chip Select Register (CS_number = 0) 0x34 32 read-write n BITS Bits Per Transfer 4 4 read-write 8_BIT 8 bits for transfer 0x0 9_BIT 9 bits for transfer 0x1 10_BIT 10 bits for transfer 0x2 11_BIT 11 bits for transfer 0x3 12_BIT 12 bits for transfer 0x4 13_BIT 13 bits for transfer 0x5 14_BIT 14 bits for transfer 0x6 15_BIT 15 bits for transfer 0x7 16_BIT 16 bits for transfer 0x8 CPOL Clock Polarity 0 1 read-write CSAAT Chip Select Active After Transfer 3 1 read-write CSNAAT Chip Select Not Active After Transfer (Ignored if CSAAT = 1) 2 1 read-write DLYBCT Delay Between Consecutive Transfers 24 8 read-write DLYBS Delay Before SPCK 16 8 read-write NCPHA Clock Phase 1 1 read-write SCBR Serial Clock Bit Rate 8 8 read-write CSR2 Chip Select Register (CS_number = 0) 0x38 32 read-write n BITS Bits Per Transfer 4 4 read-write 8_BIT 8 bits for transfer 0x0 9_BIT 9 bits for transfer 0x1 10_BIT 10 bits for transfer 0x2 11_BIT 11 bits for transfer 0x3 12_BIT 12 bits for transfer 0x4 13_BIT 13 bits for transfer 0x5 14_BIT 14 bits for transfer 0x6 15_BIT 15 bits for transfer 0x7 16_BIT 16 bits for transfer 0x8 CPOL Clock Polarity 0 1 read-write CSAAT Chip Select Active After Transfer 3 1 read-write CSNAAT Chip Select Not Active After Transfer (Ignored if CSAAT = 1) 2 1 read-write DLYBCT Delay Between Consecutive Transfers 24 8 read-write DLYBS Delay Before SPCK 16 8 read-write NCPHA Clock Phase 1 1 read-write SCBR Serial Clock Bit Rate 8 8 read-write CSR3 Chip Select Register (CS_number = 0) 0x3C 32 read-write n BITS Bits Per Transfer 4 4 read-write 8_BIT 8 bits for transfer 0x0 9_BIT 9 bits for transfer 0x1 10_BIT 10 bits for transfer 0x2 11_BIT 11 bits for transfer 0x3 12_BIT 12 bits for transfer 0x4 13_BIT 13 bits for transfer 0x5 14_BIT 14 bits for transfer 0x6 15_BIT 15 bits for transfer 0x7 16_BIT 16 bits for transfer 0x8 CPOL Clock Polarity 0 1 read-write CSAAT Chip Select Active After Transfer 3 1 read-write CSNAAT Chip Select Not Active After Transfer (Ignored if CSAAT = 1) 2 1 read-write DLYBCT Delay Between Consecutive Transfers 24 8 read-write DLYBS Delay Before SPCK 16 8 read-write NCPHA Clock Phase 1 1 read-write SCBR Serial Clock Bit Rate 8 8 read-write CSR[0] Chip Select Register (CS_number = 0) 0x60 32 read-write n 0x0 0x0 BITS Bits Per Transfer 4 4 read-write 8_BIT 8 bits for transfer 0x0 9_BIT 9 bits for transfer 0x1 10_BIT 10 bits for transfer 0x2 11_BIT 11 bits for transfer 0x3 12_BIT 12 bits for transfer 0x4 13_BIT 13 bits for transfer 0x5 14_BIT 14 bits for transfer 0x6 15_BIT 15 bits for transfer 0x7 16_BIT 16 bits for transfer 0x8 CPOL Clock Polarity 0 1 read-write CSAAT Chip Select Active After Transfer 3 1 read-write CSNAAT Chip Select Not Active After Transfer (Ignored if CSAAT = 1) 2 1 read-write DLYBCT Delay Between Consecutive Transfers 24 8 read-write DLYBS Delay Before SPCK 16 8 read-write NCPHA Clock Phase 1 1 read-write SCBR Serial Clock Bit Rate 8 8 read-write CSR[1] Chip Select Register (CS_number = 0) 0x94 32 read-write n 0x0 0x0 BITS Bits Per Transfer 4 4 read-write 8_BIT 8 bits for transfer 0x0 9_BIT 9 bits for transfer 0x1 10_BIT 10 bits for transfer 0x2 11_BIT 11 bits for transfer 0x3 12_BIT 12 bits for transfer 0x4 13_BIT 13 bits for transfer 0x5 14_BIT 14 bits for transfer 0x6 15_BIT 15 bits for transfer 0x7 16_BIT 16 bits for transfer 0x8 CPOL Clock Polarity 0 1 read-write CSAAT Chip Select Active After Transfer 3 1 read-write CSNAAT Chip Select Not Active After Transfer (Ignored if CSAAT = 1) 2 1 read-write DLYBCT Delay Between Consecutive Transfers 24 8 read-write DLYBS Delay Before SPCK 16 8 read-write NCPHA Clock Phase 1 1 read-write SCBR Serial Clock Bit Rate 8 8 read-write CSR[2] Chip Select Register (CS_number = 0) 0xCC 32 read-write n 0x0 0x0 BITS Bits Per Transfer 4 4 read-write 8_BIT 8 bits for transfer 0x0 9_BIT 9 bits for transfer 0x1 10_BIT 10 bits for transfer 0x2 11_BIT 11 bits for transfer 0x3 12_BIT 12 bits for transfer 0x4 13_BIT 13 bits for transfer 0x5 14_BIT 14 bits for transfer 0x6 15_BIT 15 bits for transfer 0x7 16_BIT 16 bits for transfer 0x8 CPOL Clock Polarity 0 1 read-write CSAAT Chip Select Active After Transfer 3 1 read-write CSNAAT Chip Select Not Active After Transfer (Ignored if CSAAT = 1) 2 1 read-write DLYBCT Delay Between Consecutive Transfers 24 8 read-write DLYBS Delay Before SPCK 16 8 read-write NCPHA Clock Phase 1 1 read-write SCBR Serial Clock Bit Rate 8 8 read-write CSR[3] Chip Select Register (CS_number = 0) 0x108 32 read-write n 0x0 0x0 BITS Bits Per Transfer 4 4 read-write 8_BIT 8 bits for transfer 0x0 9_BIT 9 bits for transfer 0x1 10_BIT 10 bits for transfer 0x2 11_BIT 11 bits for transfer 0x3 12_BIT 12 bits for transfer 0x4 13_BIT 13 bits for transfer 0x5 14_BIT 14 bits for transfer 0x6 15_BIT 15 bits for transfer 0x7 16_BIT 16 bits for transfer 0x8 CPOL Clock Polarity 0 1 read-write CSAAT Chip Select Active After Transfer 3 1 read-write CSNAAT Chip Select Not Active After Transfer (Ignored if CSAAT = 1) 2 1 read-write DLYBCT Delay Between Consecutive Transfers 24 8 read-write DLYBS Delay Before SPCK 16 8 read-write NCPHA Clock Phase 1 1 read-write SCBR Serial Clock Bit Rate 8 8 read-write IDR Interrupt Disable Register 0x18 32 write-only n 0x0 0x0 MODF Mode Fault Error Interrupt Disable 2 1 write-only NSSR NSS Rising Interrupt Disable 8 1 write-only OVRES Overrun Error Interrupt Disable 3 1 write-only RDRF Receive Data Register Full Interrupt Disable 0 1 write-only TDRE SPI Transmit Data Register Empty Interrupt Disable 1 1 write-only TXEMPTY Transmission Registers Empty Disable 9 1 write-only UNDES Underrun Error Interrupt Disable 10 1 write-only IER Interrupt Enable Register 0x14 32 write-only n 0x0 0x0 MODF Mode Fault Error Interrupt Enable 2 1 write-only NSSR NSS Rising Interrupt Enable 8 1 write-only OVRES Overrun Error Interrupt Enable 3 1 write-only RDRF Receive Data Register Full Interrupt Enable 0 1 write-only TDRE SPI Transmit Data Register Empty Interrupt Enable 1 1 write-only TXEMPTY Transmission Registers Empty Enable 9 1 write-only UNDES Underrun Error Interrupt Enable 10 1 write-only IMR Interrupt Mask Register 0x1C 32 read-only n 0x0 0x0 MODF Mode Fault Error Interrupt Mask 2 1 read-only NSSR NSS Rising Interrupt Mask 8 1 read-only OVRES Overrun Error Interrupt Mask 3 1 read-only RDRF Receive Data Register Full Interrupt Mask 0 1 read-only TDRE SPI Transmit Data Register Empty Interrupt Mask 1 1 read-only TXEMPTY Transmission Registers Empty Mask 9 1 read-only UNDES Underrun Error Interrupt Mask 10 1 read-only MR Mode Register 0x4 32 read-write n 0x0 0x0 DLYBCS Delay Between Chip Selects 24 8 read-write LLB Local Loopback Enable 7 1 read-write MODFDIS Mode Fault Detection 4 1 read-write MSTR Master/Slave Mode 0 1 read-write PCS Peripheral Chip Select 16 4 read-write PCSDEC Chip Select Decode 2 1 read-write PS Peripheral Select 1 1 read-write WDRBT Wait Data Read Before Transfer 5 1 read-write RDR Receive Data Register 0x8 32 read-only n 0x0 0x0 PCS Peripheral Chip Select 16 4 read-only RD Receive Data 0 16 read-only SR Status Register 0x10 32 read-only n 0x0 0x0 MODF Mode Fault Error (cleared on read) 2 1 read-only NSSR NSS Rising (cleared on read) 8 1 read-only OVRES Overrun Error Status (cleared on read) 3 1 read-only RDRF Receive Data Register Full (cleared by reading SPI_RDR) 0 1 read-only SPIENS SPI Enable Status 16 1 read-only TDRE Transmit Data Register Empty (cleared by writing SPI_TDR) 1 1 read-only TXEMPTY Transmission Registers Empty (cleared by writing SPI_TDR) 9 1 read-only UNDES Underrun Error Status (Slave mode only) (cleared on read) 10 1 read-only TDR Transmit Data Register 0xC 32 write-only n 0x0 0x0 LASTXFER Last Transfer 24 1 write-only PCS Peripheral Chip Select 16 4 write-only TD Transmit Data 0 16 write-only WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 read-write WPKEY Write Protection Key 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 0x535049 WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 read-only WPVSRC Write Protection Violation Source 8 8 read-only SPI2 Serial Peripheral Interface 2 SPI 0x0 0x0 0x50 registers n SPI2 39 CR Control Register 0x0 32 write-only n 0x0 0x0 LASTXFER Last Transfer 24 1 write-only REQCLR Request to Clear the Comparison Trigger 12 1 write-only SPIDIS SPI Disable 1 1 write-only SPIEN SPI Enable 0 1 write-only SWRST SPI Software Reset 7 1 write-only CSR0 Chip Select Register (CS_number = 0) 0x30 32 read-write n BITS Bits Per Transfer 4 4 read-write 8_BIT 8 bits for transfer 0x0 9_BIT 9 bits for transfer 0x1 10_BIT 10 bits for transfer 0x2 11_BIT 11 bits for transfer 0x3 12_BIT 12 bits for transfer 0x4 13_BIT 13 bits for transfer 0x5 14_BIT 14 bits for transfer 0x6 15_BIT 15 bits for transfer 0x7 16_BIT 16 bits for transfer 0x8 CPOL Clock Polarity 0 1 read-write CSAAT Chip Select Active After Transfer 3 1 read-write CSNAAT Chip Select Not Active After Transfer (Ignored if CSAAT = 1) 2 1 read-write DLYBCT Delay Between Consecutive Transfers 24 8 read-write DLYBS Delay Before SPCK 16 8 read-write NCPHA Clock Phase 1 1 read-write SCBR Serial Clock Bit Rate 8 8 read-write CSR1 Chip Select Register (CS_number = 0) 0x34 32 read-write n BITS Bits Per Transfer 4 4 read-write 8_BIT 8 bits for transfer 0x0 9_BIT 9 bits for transfer 0x1 10_BIT 10 bits for transfer 0x2 11_BIT 11 bits for transfer 0x3 12_BIT 12 bits for transfer 0x4 13_BIT 13 bits for transfer 0x5 14_BIT 14 bits for transfer 0x6 15_BIT 15 bits for transfer 0x7 16_BIT 16 bits for transfer 0x8 CPOL Clock Polarity 0 1 read-write CSAAT Chip Select Active After Transfer 3 1 read-write CSNAAT Chip Select Not Active After Transfer (Ignored if CSAAT = 1) 2 1 read-write DLYBCT Delay Between Consecutive Transfers 24 8 read-write DLYBS Delay Before SPCK 16 8 read-write NCPHA Clock Phase 1 1 read-write SCBR Serial Clock Bit Rate 8 8 read-write CSR2 Chip Select Register (CS_number = 0) 0x38 32 read-write n BITS Bits Per Transfer 4 4 read-write 8_BIT 8 bits for transfer 0x0 9_BIT 9 bits for transfer 0x1 10_BIT 10 bits for transfer 0x2 11_BIT 11 bits for transfer 0x3 12_BIT 12 bits for transfer 0x4 13_BIT 13 bits for transfer 0x5 14_BIT 14 bits for transfer 0x6 15_BIT 15 bits for transfer 0x7 16_BIT 16 bits for transfer 0x8 CPOL Clock Polarity 0 1 read-write CSAAT Chip Select Active After Transfer 3 1 read-write CSNAAT Chip Select Not Active After Transfer (Ignored if CSAAT = 1) 2 1 read-write DLYBCT Delay Between Consecutive Transfers 24 8 read-write DLYBS Delay Before SPCK 16 8 read-write NCPHA Clock Phase 1 1 read-write SCBR Serial Clock Bit Rate 8 8 read-write CSR3 Chip Select Register (CS_number = 0) 0x3C 32 read-write n BITS Bits Per Transfer 4 4 read-write 8_BIT 8 bits for transfer 0x0 9_BIT 9 bits for transfer 0x1 10_BIT 10 bits for transfer 0x2 11_BIT 11 bits for transfer 0x3 12_BIT 12 bits for transfer 0x4 13_BIT 13 bits for transfer 0x5 14_BIT 14 bits for transfer 0x6 15_BIT 15 bits for transfer 0x7 16_BIT 16 bits for transfer 0x8 CPOL Clock Polarity 0 1 read-write CSAAT Chip Select Active After Transfer 3 1 read-write CSNAAT Chip Select Not Active After Transfer (Ignored if CSAAT = 1) 2 1 read-write DLYBCT Delay Between Consecutive Transfers 24 8 read-write DLYBS Delay Before SPCK 16 8 read-write NCPHA Clock Phase 1 1 read-write SCBR Serial Clock Bit Rate 8 8 read-write CSR[0] Chip Select Register (CS_number = 0) 0x60 32 read-write n 0x0 0x0 BITS Bits Per Transfer 4 4 read-write 8_BIT 8 bits for transfer 0x0 9_BIT 9 bits for transfer 0x1 10_BIT 10 bits for transfer 0x2 11_BIT 11 bits for transfer 0x3 12_BIT 12 bits for transfer 0x4 13_BIT 13 bits for transfer 0x5 14_BIT 14 bits for transfer 0x6 15_BIT 15 bits for transfer 0x7 16_BIT 16 bits for transfer 0x8 CPOL Clock Polarity 0 1 read-write CSAAT Chip Select Active After Transfer 3 1 read-write CSNAAT Chip Select Not Active After Transfer (Ignored if CSAAT = 1) 2 1 read-write DLYBCT Delay Between Consecutive Transfers 24 8 read-write DLYBS Delay Before SPCK 16 8 read-write NCPHA Clock Phase 1 1 read-write SCBR Serial Clock Bit Rate 8 8 read-write CSR[1] Chip Select Register (CS_number = 0) 0x94 32 read-write n 0x0 0x0 BITS Bits Per Transfer 4 4 read-write 8_BIT 8 bits for transfer 0x0 9_BIT 9 bits for transfer 0x1 10_BIT 10 bits for transfer 0x2 11_BIT 11 bits for transfer 0x3 12_BIT 12 bits for transfer 0x4 13_BIT 13 bits for transfer 0x5 14_BIT 14 bits for transfer 0x6 15_BIT 15 bits for transfer 0x7 16_BIT 16 bits for transfer 0x8 CPOL Clock Polarity 0 1 read-write CSAAT Chip Select Active After Transfer 3 1 read-write CSNAAT Chip Select Not Active After Transfer (Ignored if CSAAT = 1) 2 1 read-write DLYBCT Delay Between Consecutive Transfers 24 8 read-write DLYBS Delay Before SPCK 16 8 read-write NCPHA Clock Phase 1 1 read-write SCBR Serial Clock Bit Rate 8 8 read-write CSR[2] Chip Select Register (CS_number = 0) 0xCC 32 read-write n 0x0 0x0 BITS Bits Per Transfer 4 4 read-write 8_BIT 8 bits for transfer 0x0 9_BIT 9 bits for transfer 0x1 10_BIT 10 bits for transfer 0x2 11_BIT 11 bits for transfer 0x3 12_BIT 12 bits for transfer 0x4 13_BIT 13 bits for transfer 0x5 14_BIT 14 bits for transfer 0x6 15_BIT 15 bits for transfer 0x7 16_BIT 16 bits for transfer 0x8 CPOL Clock Polarity 0 1 read-write CSAAT Chip Select Active After Transfer 3 1 read-write CSNAAT Chip Select Not Active After Transfer (Ignored if CSAAT = 1) 2 1 read-write DLYBCT Delay Between Consecutive Transfers 24 8 read-write DLYBS Delay Before SPCK 16 8 read-write NCPHA Clock Phase 1 1 read-write SCBR Serial Clock Bit Rate 8 8 read-write CSR[3] Chip Select Register (CS_number = 0) 0x108 32 read-write n 0x0 0x0 BITS Bits Per Transfer 4 4 read-write 8_BIT 8 bits for transfer 0x0 9_BIT 9 bits for transfer 0x1 10_BIT 10 bits for transfer 0x2 11_BIT 11 bits for transfer 0x3 12_BIT 12 bits for transfer 0x4 13_BIT 13 bits for transfer 0x5 14_BIT 14 bits for transfer 0x6 15_BIT 15 bits for transfer 0x7 16_BIT 16 bits for transfer 0x8 CPOL Clock Polarity 0 1 read-write CSAAT Chip Select Active After Transfer 3 1 read-write CSNAAT Chip Select Not Active After Transfer (Ignored if CSAAT = 1) 2 1 read-write DLYBCT Delay Between Consecutive Transfers 24 8 read-write DLYBS Delay Before SPCK 16 8 read-write NCPHA Clock Phase 1 1 read-write SCBR Serial Clock Bit Rate 8 8 read-write IDR Interrupt Disable Register 0x18 32 write-only n 0x0 0x0 MODF Mode Fault Error Interrupt Disable 2 1 write-only NSSR NSS Rising Interrupt Disable 8 1 write-only OVRES Overrun Error Interrupt Disable 3 1 write-only RDRF Receive Data Register Full Interrupt Disable 0 1 write-only TDRE SPI Transmit Data Register Empty Interrupt Disable 1 1 write-only TXEMPTY Transmission Registers Empty Disable 9 1 write-only UNDES Underrun Error Interrupt Disable 10 1 write-only IER Interrupt Enable Register 0x14 32 write-only n 0x0 0x0 MODF Mode Fault Error Interrupt Enable 2 1 write-only NSSR NSS Rising Interrupt Enable 8 1 write-only OVRES Overrun Error Interrupt Enable 3 1 write-only RDRF Receive Data Register Full Interrupt Enable 0 1 write-only TDRE SPI Transmit Data Register Empty Interrupt Enable 1 1 write-only TXEMPTY Transmission Registers Empty Enable 9 1 write-only UNDES Underrun Error Interrupt Enable 10 1 write-only IMR Interrupt Mask Register 0x1C 32 read-only n 0x0 0x0 MODF Mode Fault Error Interrupt Mask 2 1 read-only NSSR NSS Rising Interrupt Mask 8 1 read-only OVRES Overrun Error Interrupt Mask 3 1 read-only RDRF Receive Data Register Full Interrupt Mask 0 1 read-only TDRE SPI Transmit Data Register Empty Interrupt Mask 1 1 read-only TXEMPTY Transmission Registers Empty Mask 9 1 read-only UNDES Underrun Error Interrupt Mask 10 1 read-only MR Mode Register 0x4 32 read-write n 0x0 0x0 DLYBCS Delay Between Chip Selects 24 8 read-write LLB Local Loopback Enable 7 1 read-write MODFDIS Mode Fault Detection 4 1 read-write MSTR Master/Slave Mode 0 1 read-write PCS Peripheral Chip Select 16 4 read-write PCSDEC Chip Select Decode 2 1 read-write PS Peripheral Select 1 1 read-write WDRBT Wait Data Read Before Transfer 5 1 read-write RDR Receive Data Register 0x8 32 read-only n 0x0 0x0 PCS Peripheral Chip Select 16 4 read-only RD Receive Data 0 16 read-only SR Status Register 0x10 32 read-only n 0x0 0x0 MODF Mode Fault Error (cleared on read) 2 1 read-only NSSR NSS Rising (cleared on read) 8 1 read-only OVRES Overrun Error Status (cleared on read) 3 1 read-only RDRF Receive Data Register Full (cleared by reading SPI_RDR) 0 1 read-only SPIENS SPI Enable Status 16 1 read-only TDRE Transmit Data Register Empty (cleared by writing SPI_TDR) 1 1 read-only TXEMPTY Transmission Registers Empty (cleared by writing SPI_TDR) 9 1 read-only UNDES Underrun Error Status (Slave mode only) (cleared on read) 10 1 read-only TDR Transmit Data Register 0xC 32 write-only n 0x0 0x0 LASTXFER Last Transfer 24 1 write-only PCS Peripheral Chip Select 16 4 write-only TD Transmit Data 0 16 write-only WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 read-write WPKEY Write Protection Key 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 0x535049 WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 read-only WPVSRC Write Protection Violation Source 8 8 read-only SSC0 Synchronous Serial Controller 0 SSC 0x0 0x0 0x50 registers n SSC0 48 CMR Clock Mode Register 0x4 32 read-write n 0x0 0x0 DIV Clock Divider 0 12 read-write CR Control Register 0x0 32 write-only n 0x0 0x0 RXDIS Receive Disable 1 1 write-only RXEN Receive Enable 0 1 write-only SWRST Software Reset 15 1 write-only TXDIS Transmit Disable 9 1 write-only TXEN Transmit Enable 8 1 write-only IDR Interrupt Disable Register 0x48 32 write-only n 0x0 0x0 CP0 Compare 0 Interrupt Disable 8 1 write-only CP1 Compare 1 Interrupt Disable 9 1 write-only OVRUN Receive Overrun Interrupt Disable 5 1 write-only RXRDY Receive Ready Interrupt Disable 4 1 write-only RXSYN Rx Sync Interrupt Enable 11 1 write-only TXEMPTY Transmit Empty Interrupt Disable 1 1 write-only TXRDY Transmit Ready Interrupt Disable 0 1 write-only TXSYN Tx Sync Interrupt Enable 10 1 write-only IER Interrupt Enable Register 0x44 32 write-only n 0x0 0x0 CP0 Compare 0 Interrupt Enable 8 1 write-only CP1 Compare 1 Interrupt Enable 9 1 write-only OVRUN Receive Overrun Interrupt Enable 5 1 write-only RXRDY Receive Ready Interrupt Enable 4 1 write-only RXSYN Rx Sync Interrupt Enable 11 1 write-only TXEMPTY Transmit Empty Interrupt Enable 1 1 write-only TXRDY Transmit Ready Interrupt Enable 0 1 write-only TXSYN Tx Sync Interrupt Enable 10 1 write-only IMR Interrupt Mask Register 0x4C 32 read-only n 0x0 0x0 CP0 Compare 0 Interrupt Mask 8 1 read-only CP1 Compare 1 Interrupt Mask 9 1 read-only OVRUN Receive Overrun Interrupt Mask 5 1 read-only RXRDY Receive Ready Interrupt Mask 4 1 read-only RXSYN Rx Sync Interrupt Mask 11 1 read-only TXEMPTY Transmit Empty Interrupt Mask 1 1 read-only TXRDY Transmit Ready Interrupt Mask 0 1 read-only TXSYN Tx Sync Interrupt Mask 10 1 read-only RC0R Receive Compare 0 Register 0x38 32 read-write n 0x0 0x0 CP0 Receive Compare Data 0 0 16 read-write RC1R Receive Compare 1 Register 0x3C 32 read-write n 0x0 0x0 CP1 Receive Compare Data 1 0 16 read-write RCMR Receive Clock Mode Register 0x10 32 read-write n 0x0 0x0 CKG Receive Clock Gating Selection 6 2 read-write CONTINUOUS None 0x0 EN_RF_LOW Receive Clock enabled only if RF Low 0x1 EN_RF_HIGH Receive Clock enabled only if RF High 0x2 CKI Receive Clock Inversion 5 1 read-write CKO Receive Clock Output Mode Selection 2 3 read-write NONE None, RK pin is an input 0x0 CONTINUOUS Continuous Receive Clock, RK pin is an output 0x1 TRANSFER Receive Clock only during data transfers, RK pin is an output 0x2 CKS Receive Clock Selection 0 2 read-write MCK Divided Clock 0x0 TK TK Clock signal 0x1 RK RK pin 0x2 PERIOD Receive Period Divider Selection 24 8 read-write START Receive Start Selection 8 4 read-write CONTINUOUS Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. 0x0 TRANSMIT Transmit start 0x1 RF_LOW Detection of a low level on RF signal 0x2 RF_HIGH Detection of a high level on RF signal 0x3 RF_FALLING Detection of a falling edge on RF signal 0x4 RF_RISING Detection of a rising edge on RF signal 0x5 RF_LEVEL Detection of any level change on RF signal 0x6 RF_EDGE Detection of any edge on RF signal 0x7 CMP_0 Compare 0 0x8 STOP Receive Stop Selection 12 1 read-write STTDLY Receive Start Delay 16 8 read-write RFMR Receive Frame Mode Register 0x14 32 read-write n 0x0 0x0 DATLEN Data Length 0 5 read-write DATNB Data Number per Frame 8 4 read-write FSEDGE Frame Sync Edge Detection 24 1 read-write POSITIVE Positive Edge Detection 0 NEGATIVE Negative Edge Detection 1 FSLEN Receive Frame Sync Length 16 4 read-write FSLEN_EXT FSLEN Field Extension 28 4 read-write FSOS Receive Frame Sync Output Selection 20 3 read-write NONE None, RF pin is an input 0x0 NEGATIVE Negative Pulse, RF pin is an output 0x1 POSITIVE Positive Pulse, RF pin is an output 0x2 LOW Driven Low during data transfer, RF pin is an output 0x3 HIGH Driven High during data transfer, RF pin is an output 0x4 TOGGLING Toggling at each start of data transfer, RF pin is an output 0x5 LOOP Loop Mode 5 1 read-write MSBF Most Significant Bit First 7 1 read-write RHR Receive Holding Register 0x20 32 read-only n 0x0 0x0 RDAT Receive Data 0 32 read-only RSHR Receive Sync. Holding Register 0x30 32 read-only n 0x0 0x0 RSDAT Receive Synchronization Data 0 16 read-only SR Status Register 0x40 32 read-only n 0x0 0x0 CP0 Compare 0 8 1 read-only CP1 Compare 1 9 1 read-only OVRUN Receive Overrun 5 1 read-only RXEN Receive Enable 17 1 read-only RXRDY Receive Ready 4 1 read-only RXSYN Receive Sync 11 1 read-only TXEMPTY Transmit Empty 1 1 read-only TXEN Transmit Enable 16 1 read-only TXRDY Transmit Ready 0 1 read-only TXSYN Transmit Sync 10 1 read-only TCMR Transmit Clock Mode Register 0x18 32 read-write n 0x0 0x0 CKG Transmit Clock Gating Selection 6 2 read-write CONTINUOUS None 0x0 EN_TF_LOW Transmit Clock enabled only if TF Low 0x1 EN_TF_HIGH Transmit Clock enabled only if TF High 0x2 CKI Transmit Clock Inversion 5 1 read-write CKO Transmit Clock Output Mode Selection 2 3 read-write NONE None, TK pin is an input 0x0 CONTINUOUS Continuous Transmit Clock, TK pin is an output 0x1 TRANSFER Transmit Clock only during data transfers, TK pin is an output 0x2 CKS Transmit Clock Selection 0 2 read-write MCK Divided Clock 0x0 RK RK Clock signal 0x1 TK TK pin 0x2 PERIOD Transmit Period Divider Selection 24 8 read-write START Transmit Start Selection 8 4 read-write CONTINUOUS Continuous, as soon as a word is written in the SSC_THR (if Transmit is enabled), and immediately after the end of transfer of the previous data 0x0 RECEIVE Receive start 0x1 TF_LOW Detection of a low level on TF signal 0x2 TF_HIGH Detection of a high level on TF signal 0x3 TF_FALLING Detection of a falling edge on TF signal 0x4 TF_RISING Detection of a rising edge on TF signal 0x5 TF_LEVEL Detection of any level change on TF signal 0x6 TF_EDGE Detection of any edge on TF signal 0x7 STTDLY Transmit Start Delay 16 8 read-write TFMR Transmit Frame Mode Register 0x1C 32 read-write n 0x0 0x0 DATDEF Data Default Value 5 1 read-write DATLEN Data Length 0 5 read-write DATNB Data Number per Frame 8 4 read-write FSDEN Frame Sync Data Enable 23 1 read-write FSEDGE Frame Sync Edge Detection 24 1 read-write POSITIVE Positive Edge Detection 0 NEGATIVE Negative Edge Detection 1 FSLEN Transmit Frame Sync Length 16 4 read-write FSLEN_EXT FSLEN Field Extension 28 4 read-write FSOS Transmit Frame Sync Output Selection 20 3 read-write NONE None, TF pin is an input 0x0 NEGATIVE Negative Pulse, TF pin is an output 0x1 POSITIVE Positive Pulse, TF pin is an output 0x2 LOW Driven Low during data transfer 0x3 HIGH Driven High during data transfer 0x4 TOGGLING Toggling at each start of data transfer 0x5 MSBF Most Significant Bit First 7 1 read-write THR Transmit Holding Register 0x24 32 write-only n 0x0 0x0 TDAT Transmit Data 0 32 write-only TSHR Transmit Sync. Holding Register 0x34 32 read-write n 0x0 0x0 TSDAT Transmit Synchronization Data 0 16 read-write WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 read-write WPKEY Write Protection Key 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 0x535343 WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 read-only WPVSRC Write Protect Violation Source 8 16 read-only SSC1 Synchronous Serial Controller 1 SSC 0x0 0x0 0x50 registers n SSC1 49 CMR Clock Mode Register 0x4 32 read-write n 0x0 0x0 DIV Clock Divider 0 12 read-write CR Control Register 0x0 32 write-only n 0x0 0x0 RXDIS Receive Disable 1 1 write-only RXEN Receive Enable 0 1 write-only SWRST Software Reset 15 1 write-only TXDIS Transmit Disable 9 1 write-only TXEN Transmit Enable 8 1 write-only IDR Interrupt Disable Register 0x48 32 write-only n 0x0 0x0 CP0 Compare 0 Interrupt Disable 8 1 write-only CP1 Compare 1 Interrupt Disable 9 1 write-only OVRUN Receive Overrun Interrupt Disable 5 1 write-only RXRDY Receive Ready Interrupt Disable 4 1 write-only RXSYN Rx Sync Interrupt Enable 11 1 write-only TXEMPTY Transmit Empty Interrupt Disable 1 1 write-only TXRDY Transmit Ready Interrupt Disable 0 1 write-only TXSYN Tx Sync Interrupt Enable 10 1 write-only IER Interrupt Enable Register 0x44 32 write-only n 0x0 0x0 CP0 Compare 0 Interrupt Enable 8 1 write-only CP1 Compare 1 Interrupt Enable 9 1 write-only OVRUN Receive Overrun Interrupt Enable 5 1 write-only RXRDY Receive Ready Interrupt Enable 4 1 write-only RXSYN Rx Sync Interrupt Enable 11 1 write-only TXEMPTY Transmit Empty Interrupt Enable 1 1 write-only TXRDY Transmit Ready Interrupt Enable 0 1 write-only TXSYN Tx Sync Interrupt Enable 10 1 write-only IMR Interrupt Mask Register 0x4C 32 read-only n 0x0 0x0 CP0 Compare 0 Interrupt Mask 8 1 read-only CP1 Compare 1 Interrupt Mask 9 1 read-only OVRUN Receive Overrun Interrupt Mask 5 1 read-only RXRDY Receive Ready Interrupt Mask 4 1 read-only RXSYN Rx Sync Interrupt Mask 11 1 read-only TXEMPTY Transmit Empty Interrupt Mask 1 1 read-only TXRDY Transmit Ready Interrupt Mask 0 1 read-only TXSYN Tx Sync Interrupt Mask 10 1 read-only RC0R Receive Compare 0 Register 0x38 32 read-write n 0x0 0x0 CP0 Receive Compare Data 0 0 16 read-write RC1R Receive Compare 1 Register 0x3C 32 read-write n 0x0 0x0 CP1 Receive Compare Data 1 0 16 read-write RCMR Receive Clock Mode Register 0x10 32 read-write n 0x0 0x0 CKG Receive Clock Gating Selection 6 2 read-write CONTINUOUS None 0x0 EN_RF_LOW Receive Clock enabled only if RF Low 0x1 EN_RF_HIGH Receive Clock enabled only if RF High 0x2 CKI Receive Clock Inversion 5 1 read-write CKO Receive Clock Output Mode Selection 2 3 read-write NONE None, RK pin is an input 0x0 CONTINUOUS Continuous Receive Clock, RK pin is an output 0x1 TRANSFER Receive Clock only during data transfers, RK pin is an output 0x2 CKS Receive Clock Selection 0 2 read-write MCK Divided Clock 0x0 TK TK Clock signal 0x1 RK RK pin 0x2 PERIOD Receive Period Divider Selection 24 8 read-write START Receive Start Selection 8 4 read-write CONTINUOUS Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. 0x0 TRANSMIT Transmit start 0x1 RF_LOW Detection of a low level on RF signal 0x2 RF_HIGH Detection of a high level on RF signal 0x3 RF_FALLING Detection of a falling edge on RF signal 0x4 RF_RISING Detection of a rising edge on RF signal 0x5 RF_LEVEL Detection of any level change on RF signal 0x6 RF_EDGE Detection of any edge on RF signal 0x7 CMP_0 Compare 0 0x8 STOP Receive Stop Selection 12 1 read-write STTDLY Receive Start Delay 16 8 read-write RFMR Receive Frame Mode Register 0x14 32 read-write n 0x0 0x0 DATLEN Data Length 0 5 read-write DATNB Data Number per Frame 8 4 read-write FSEDGE Frame Sync Edge Detection 24 1 read-write POSITIVE Positive Edge Detection 0 NEGATIVE Negative Edge Detection 1 FSLEN Receive Frame Sync Length 16 4 read-write FSLEN_EXT FSLEN Field Extension 28 4 read-write FSOS Receive Frame Sync Output Selection 20 3 read-write NONE None, RF pin is an input 0x0 NEGATIVE Negative Pulse, RF pin is an output 0x1 POSITIVE Positive Pulse, RF pin is an output 0x2 LOW Driven Low during data transfer, RF pin is an output 0x3 HIGH Driven High during data transfer, RF pin is an output 0x4 TOGGLING Toggling at each start of data transfer, RF pin is an output 0x5 LOOP Loop Mode 5 1 read-write MSBF Most Significant Bit First 7 1 read-write RHR Receive Holding Register 0x20 32 read-only n 0x0 0x0 RDAT Receive Data 0 32 read-only RSHR Receive Sync. Holding Register 0x30 32 read-only n 0x0 0x0 RSDAT Receive Synchronization Data 0 16 read-only SR Status Register 0x40 32 read-only n 0x0 0x0 CP0 Compare 0 8 1 read-only CP1 Compare 1 9 1 read-only OVRUN Receive Overrun 5 1 read-only RXEN Receive Enable 17 1 read-only RXRDY Receive Ready 4 1 read-only RXSYN Receive Sync 11 1 read-only TXEMPTY Transmit Empty 1 1 read-only TXEN Transmit Enable 16 1 read-only TXRDY Transmit Ready 0 1 read-only TXSYN Transmit Sync 10 1 read-only TCMR Transmit Clock Mode Register 0x18 32 read-write n 0x0 0x0 CKG Transmit Clock Gating Selection 6 2 read-write CONTINUOUS None 0x0 EN_TF_LOW Transmit Clock enabled only if TF Low 0x1 EN_TF_HIGH Transmit Clock enabled only if TF High 0x2 CKI Transmit Clock Inversion 5 1 read-write CKO Transmit Clock Output Mode Selection 2 3 read-write NONE None, TK pin is an input 0x0 CONTINUOUS Continuous Transmit Clock, TK pin is an output 0x1 TRANSFER Transmit Clock only during data transfers, TK pin is an output 0x2 CKS Transmit Clock Selection 0 2 read-write MCK Divided Clock 0x0 RK RK Clock signal 0x1 TK TK pin 0x2 PERIOD Transmit Period Divider Selection 24 8 read-write START Transmit Start Selection 8 4 read-write CONTINUOUS Continuous, as soon as a word is written in the SSC_THR (if Transmit is enabled), and immediately after the end of transfer of the previous data 0x0 RECEIVE Receive start 0x1 TF_LOW Detection of a low level on TF signal 0x2 TF_HIGH Detection of a high level on TF signal 0x3 TF_FALLING Detection of a falling edge on TF signal 0x4 TF_RISING Detection of a rising edge on TF signal 0x5 TF_LEVEL Detection of any level change on TF signal 0x6 TF_EDGE Detection of any edge on TF signal 0x7 STTDLY Transmit Start Delay 16 8 read-write TFMR Transmit Frame Mode Register 0x1C 32 read-write n 0x0 0x0 DATDEF Data Default Value 5 1 read-write DATLEN Data Length 0 5 read-write DATNB Data Number per Frame 8 4 read-write FSDEN Frame Sync Data Enable 23 1 read-write FSEDGE Frame Sync Edge Detection 24 1 read-write POSITIVE Positive Edge Detection 0 NEGATIVE Negative Edge Detection 1 FSLEN Transmit Frame Sync Length 16 4 read-write FSLEN_EXT FSLEN Field Extension 28 4 read-write FSOS Transmit Frame Sync Output Selection 20 3 read-write NONE None, TF pin is an input 0x0 NEGATIVE Negative Pulse, TF pin is an output 0x1 POSITIVE Positive Pulse, TF pin is an output 0x2 LOW Driven Low during data transfer 0x3 HIGH Driven High during data transfer 0x4 TOGGLING Toggling at each start of data transfer 0x5 MSBF Most Significant Bit First 7 1 read-write THR Transmit Holding Register 0x24 32 write-only n 0x0 0x0 TDAT Transmit Data 0 32 write-only TSHR Transmit Sync. Holding Register 0x34 32 read-write n 0x0 0x0 TSDAT Transmit Synchronization Data 0 16 read-write WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 read-write WPKEY Write Protection Key 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 0x535343 WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 read-only WPVSRC Write Protect Violation Source 8 16 read-only TC0 Timer Counter 0 TC 0x0 0x0 0x50 registers n TC0 40 TC1 41 TC2 42 BCR Block Control Register 0xC0 32 write-only n 0x0 0x0 SYNC Synchro Command 0 1 write-only BMR Block Mode Register 0xC4 32 read-write n 0x0 0x0 EDGPHA Edge on PHA Count Mode 12 1 read-write IDXPHB Index Pin is PHB Pin 17 1 read-write INVA Inverted PHA 13 1 read-write INVB Inverted PHB 14 1 read-write INVIDX Inverted Index 15 1 read-write MAXFILT Maximum Filter 20 6 read-write POSEN Position Enabled 9 1 read-write QDEN Quadrature Decoder Enabled 8 1 read-write QDTRANS Quadrature Decoding Transparent 11 1 read-write SPEEDEN Speed Enabled 10 1 read-write SWAP Swap PHA and PHB 16 1 read-write TC0XC0S External Clock Signal 0 Selection 0 2 read-write TCLK0 Signal connected to XC0: TCLK0 0x0 TIOA1 Signal connected to XC0: TIOA1 0x2 TIOA2 Signal connected to XC0: TIOA2 0x3 TC1XC1S External Clock Signal 1 Selection 2 2 read-write TCLK1 Signal connected to XC1: TCLK1 0x0 TIOA0 Signal connected to XC1: TIOA0 0x2 TIOA2 Signal connected to XC1: TIOA2 0x3 TC2XC2S External Clock Signal 2 Selection 4 2 read-write TCLK2 Signal connected to XC2: TCLK2 0x0 TIOA0 Signal connected to XC2: TIOA0 0x2 TIOA1 Signal connected to XC2: TIOA1 0x3 CCR0 Channel Control Register (channel = 0) 0x0 32 write-only n 0x0 0x0 CLKDIS Counter Clock Disable Command 1 1 write-only CLKEN Counter Clock Enable Command 0 1 write-only SWTRG Software Trigger Command 2 1 write-only CCR1 Channel Control Register (channel = 1) 0x40 32 write-only n 0x0 0x0 CLKDIS Counter Clock Disable Command 1 1 write-only CLKEN Counter Clock Enable Command 0 1 write-only SWTRG Software Trigger Command 2 1 write-only CCR2 Channel Control Register (channel = 2) 0x80 32 write-only n 0x0 0x0 CLKDIS Counter Clock Disable Command 1 1 write-only CLKEN Counter Clock Enable Command 0 1 write-only SWTRG Software Trigger Command 2 1 write-only CMR0 Channel Mode Register (channel = 0) 0x4 32 read-write n 0x0 0x0 ABETRG TIOAx or TIOBx External Trigger Selection 10 1 read-write BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 read-write CPCTRG RC Compare Trigger Enable 14 1 read-write ETRGEDG External Trigger Edge Selection 8 2 read-write NONE The clock is not gated by an external signal. 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 LDBDIS Counter Clock Disable with RB Loading 7 1 read-write LDBSTOP Counter Clock Stopped with RB Loading 6 1 read-write LDRA RA Loading Edge Selection 16 2 read-write NONE None 0x0 RISING Rising edge of TIOAx 0x1 FALLING Falling edge of TIOAx 0x2 EDGE Each edge of TIOAx 0x3 LDRB RB Loading Edge Selection 18 2 read-write NONE None 0x0 RISING Rising edge of TIOAx 0x1 FALLING Falling edge of TIOAx 0x2 EDGE Each edge of TIOAx 0x3 SBSMPLR Loading Edge Subsampling Ratio 20 3 read-write ONE Load a Capture Register each selected edge 0x0 HALF Load a Capture Register every 2 selected edges 0x1 FOURTH Load a Capture Register every 4 selected edges 0x2 EIGHTH Load a Capture Register every 8 selected edges 0x3 SIXTEENTH Load a Capture Register every 16 selected edges 0x4 TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: internal div2 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal div8 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal div32 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal div128 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal slow_clock clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 read-write CMR0_WAVEFORM_MODE Channel Mode Register (channel = 0) WAVEFORM_MODE 0x4 32 read-write n 0x0 0x0 ACPA RA Compare Effect on TIOAx 16 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ACPC RC Compare Effect on TIOAx 18 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 AEEVT External Event Effect on TIOAx 20 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ASWTRG Software Trigger Effect on TIOAx 22 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPB RB Compare Effect on TIOBx 24 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPC RC Compare Effect on TIOBx 26 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BEEVT External Event Effect on TIOBx 28 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BSWTRG Software Trigger Effect on TIOBx 30 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 read-write CPCDIS Counter Clock Disable with RC Compare 7 1 read-write CPCSTOP Counter Clock Stopped with RC Compare 6 1 read-write EEVT External Event Selection 10 2 read-write TIOB TIOB 0x0 XC0 XC0 0x1 XC1 XC1 0x2 XC2 XC2 0x3 EEVTEDG External Event Edge Selection 8 2 read-write NONE None 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 ENETRG External Event Trigger Enable 12 1 read-write TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: internal div2 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal div8 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal div32 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal div128 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal slow_clock clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 read-write WAVSEL Waveform Selection 13 2 read-write UP UP mode without automatic trigger on RC Compare 0x0 UPDOWN UPDOWN mode without automatic trigger on RC Compare 0x1 UP_RC UP mode with automatic trigger on RC Compare 0x2 UPDOWN_RC UPDOWN mode with automatic trigger on RC Compare 0x3 CMR1 Channel Mode Register (channel = 1) 0x44 32 read-write n 0x0 0x0 ABETRG TIOAx or TIOBx External Trigger Selection 10 1 read-write BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 read-write CPCTRG RC Compare Trigger Enable 14 1 read-write ETRGEDG External Trigger Edge Selection 8 2 read-write NONE The clock is not gated by an external signal. 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 LDBDIS Counter Clock Disable with RB Loading 7 1 read-write LDBSTOP Counter Clock Stopped with RB Loading 6 1 read-write LDRA RA Loading Edge Selection 16 2 read-write NONE None 0x0 RISING Rising edge of TIOAx 0x1 FALLING Falling edge of TIOAx 0x2 EDGE Each edge of TIOAx 0x3 LDRB RB Loading Edge Selection 18 2 read-write NONE None 0x0 RISING Rising edge of TIOAx 0x1 FALLING Falling edge of TIOAx 0x2 EDGE Each edge of TIOAx 0x3 SBSMPLR Loading Edge Subsampling Ratio 20 3 read-write ONE Load a Capture Register each selected edge 0x0 HALF Load a Capture Register every 2 selected edges 0x1 FOURTH Load a Capture Register every 4 selected edges 0x2 EIGHTH Load a Capture Register every 8 selected edges 0x3 SIXTEENTH Load a Capture Register every 16 selected edges 0x4 TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: internal div2 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal div8 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal div32 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal div128 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal slow_clock clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 read-write CMR1_WAVEFORM_MODE Channel Mode Register (channel = 1) WAVEFORM_MODE 0x44 32 read-write n 0x0 0x0 ACPA RA Compare Effect on TIOAx 16 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ACPC RC Compare Effect on TIOAx 18 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 AEEVT External Event Effect on TIOAx 20 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ASWTRG Software Trigger Effect on TIOAx 22 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPB RB Compare Effect on TIOBx 24 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPC RC Compare Effect on TIOBx 26 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BEEVT External Event Effect on TIOBx 28 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BSWTRG Software Trigger Effect on TIOBx 30 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 read-write CPCDIS Counter Clock Disable with RC Compare 7 1 read-write CPCSTOP Counter Clock Stopped with RC Compare 6 1 read-write EEVT External Event Selection 10 2 read-write TIOB TIOB 0x0 XC0 XC0 0x1 XC1 XC1 0x2 XC2 XC2 0x3 EEVTEDG External Event Edge Selection 8 2 read-write NONE None 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 ENETRG External Event Trigger Enable 12 1 read-write TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: internal div2 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal div8 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal div32 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal div128 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal slow_clock clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 read-write WAVSEL Waveform Selection 13 2 read-write UP UP mode without automatic trigger on RC Compare 0x0 UPDOWN UPDOWN mode without automatic trigger on RC Compare 0x1 UP_RC UP mode with automatic trigger on RC Compare 0x2 UPDOWN_RC UPDOWN mode with automatic trigger on RC Compare 0x3 CMR2 Channel Mode Register (channel = 2) 0x84 32 read-write n 0x0 0x0 ABETRG TIOAx or TIOBx External Trigger Selection 10 1 read-write BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 read-write CPCTRG RC Compare Trigger Enable 14 1 read-write ETRGEDG External Trigger Edge Selection 8 2 read-write NONE The clock is not gated by an external signal. 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 LDBDIS Counter Clock Disable with RB Loading 7 1 read-write LDBSTOP Counter Clock Stopped with RB Loading 6 1 read-write LDRA RA Loading Edge Selection 16 2 read-write NONE None 0x0 RISING Rising edge of TIOAx 0x1 FALLING Falling edge of TIOAx 0x2 EDGE Each edge of TIOAx 0x3 LDRB RB Loading Edge Selection 18 2 read-write NONE None 0x0 RISING Rising edge of TIOAx 0x1 FALLING Falling edge of TIOAx 0x2 EDGE Each edge of TIOAx 0x3 SBSMPLR Loading Edge Subsampling Ratio 20 3 read-write ONE Load a Capture Register each selected edge 0x0 HALF Load a Capture Register every 2 selected edges 0x1 FOURTH Load a Capture Register every 4 selected edges 0x2 EIGHTH Load a Capture Register every 8 selected edges 0x3 SIXTEENTH Load a Capture Register every 16 selected edges 0x4 TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: internal div2 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal div8 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal div32 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal div128 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal slow_clock clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 read-write CMR2_WAVEFORM_MODE Channel Mode Register (channel = 2) WAVEFORM_MODE 0x84 32 read-write n 0x0 0x0 ACPA RA Compare Effect on TIOAx 16 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ACPC RC Compare Effect on TIOAx 18 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 AEEVT External Event Effect on TIOAx 20 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ASWTRG Software Trigger Effect on TIOAx 22 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPB RB Compare Effect on TIOBx 24 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPC RC Compare Effect on TIOBx 26 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BEEVT External Event Effect on TIOBx 28 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BSWTRG Software Trigger Effect on TIOBx 30 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 read-write CPCDIS Counter Clock Disable with RC Compare 7 1 read-write CPCSTOP Counter Clock Stopped with RC Compare 6 1 read-write EEVT External Event Selection 10 2 read-write TIOB TIOB 0x0 XC0 XC0 0x1 XC1 XC1 0x2 XC2 XC2 0x3 EEVTEDG External Event Edge Selection 8 2 read-write NONE None 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 ENETRG External Event Trigger Enable 12 1 read-write TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: internal div2 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal div8 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal div32 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal div128 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal slow_clock clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 read-write WAVSEL Waveform Selection 13 2 read-write UP UP mode without automatic trigger on RC Compare 0x0 UPDOWN UPDOWN mode without automatic trigger on RC Compare 0x1 UP_RC UP mode with automatic trigger on RC Compare 0x2 UPDOWN_RC UPDOWN mode with automatic trigger on RC Compare 0x3 CV0 Counter Value (channel = 0) 0x10 32 read-only n 0x0 0x0 CV Counter Value 0 32 read-only CV1 Counter Value (channel = 1) 0x50 32 read-only n 0x0 0x0 CV Counter Value 0 32 read-only CV2 Counter Value (channel = 2) 0x90 32 read-only n 0x0 0x0 CV Counter Value 0 32 read-only EMR0 Extended Mode Register (channel = 0) 0x30 32 read-write n 0x0 0x0 NODIVCLK No Divided Clock 8 1 read-write TRIGSRCA Trigger Source for Input A 0 2 read-write EXTERNAL_TIOAx The trigger/capture input A is driven by external pin TIOAx 0 PWMx The trigger/capture input A is driven internally by PWMx 1 TRIGSRCB Trigger Source for Input B 4 2 read-write EXTERNAL_TIOBx The trigger/capture input B is driven by external pin TIOBx 0 PWMx The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx. 1 EMR1 Extended Mode Register (channel = 1) 0x70 32 read-write n 0x0 0x0 NODIVCLK No Divided Clock 8 1 read-write TRIGSRCA Trigger Source for Input A 0 2 read-write EXTERNAL_TIOAx The trigger/capture input A is driven by external pin TIOAx 0 PWMx The trigger/capture input A is driven internally by PWMx 1 TRIGSRCB Trigger Source for Input B 4 2 read-write EXTERNAL_TIOBx The trigger/capture input B is driven by external pin TIOBx 0 PWMx The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx. 1 EMR2 Extended Mode Register (channel = 2) 0xB0 32 read-write n 0x0 0x0 NODIVCLK No Divided Clock 8 1 read-write TRIGSRCA Trigger Source for Input A 0 2 read-write EXTERNAL_TIOAx The trigger/capture input A is driven by external pin TIOAx 0 PWMx The trigger/capture input A is driven internally by PWMx 1 TRIGSRCB Trigger Source for Input B 4 2 read-write EXTERNAL_TIOBx The trigger/capture input B is driven by external pin TIOBx 0 PWMx The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx. 1 FMR Fault Mode Register 0xD8 32 read-write n 0x0 0x0 ENCF0 Enable Compare Fault Channel 0 0 1 read-write ENCF1 Enable Compare Fault Channel 1 1 1 read-write IDR0 Interrupt Disable Register (channel = 0) 0x28 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only ETRGS External Trigger 7 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only LOVRS Load Overrun 1 1 write-only IDR1 Interrupt Disable Register (channel = 1) 0x68 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only ETRGS External Trigger 7 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only LOVRS Load Overrun 1 1 write-only IDR2 Interrupt Disable Register (channel = 2) 0xA8 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only ETRGS External Trigger 7 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only LOVRS Load Overrun 1 1 write-only IER0 Interrupt Enable Register (channel = 0) 0x24 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only ETRGS External Trigger 7 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only LOVRS Load Overrun 1 1 write-only IER1 Interrupt Enable Register (channel = 1) 0x64 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only ETRGS External Trigger 7 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only LOVRS Load Overrun 1 1 write-only IER2 Interrupt Enable Register (channel = 2) 0xA4 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only ETRGS External Trigger 7 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only LOVRS Load Overrun 1 1 write-only IMR0 Interrupt Mask Register (channel = 0) 0x2C 32 read-only n 0x0 0x0 COVFS Counter Overflow 0 1 read-only CPAS RA Compare 2 1 read-only CPBS RB Compare 3 1 read-only CPCS RC Compare 4 1 read-only ETRGS External Trigger 7 1 read-only LDRAS RA Loading 5 1 read-only LDRBS RB Loading 6 1 read-only LOVRS Load Overrun 1 1 read-only IMR1 Interrupt Mask Register (channel = 1) 0x6C 32 read-only n 0x0 0x0 COVFS Counter Overflow 0 1 read-only CPAS RA Compare 2 1 read-only CPBS RB Compare 3 1 read-only CPCS RC Compare 4 1 read-only ETRGS External Trigger 7 1 read-only LDRAS RA Loading 5 1 read-only LDRBS RB Loading 6 1 read-only LOVRS Load Overrun 1 1 read-only IMR2 Interrupt Mask Register (channel = 2) 0xAC 32 read-only n 0x0 0x0 COVFS Counter Overflow 0 1 read-only CPAS RA Compare 2 1 read-only CPBS RB Compare 3 1 read-only CPCS RC Compare 4 1 read-only ETRGS External Trigger 7 1 read-only LDRAS RA Loading 5 1 read-only LDRBS RB Loading 6 1 read-only LOVRS Load Overrun 1 1 read-only QIDR QDEC Interrupt Disable Register 0xCC 32 write-only n 0x0 0x0 DIRCHG Direction Change 1 1 write-only IDX Index 0 1 write-only QERR Quadrature Error 2 1 write-only QIER QDEC Interrupt Enable Register 0xC8 32 write-only n 0x0 0x0 DIRCHG Direction Change 1 1 write-only IDX Index 0 1 write-only QERR Quadrature Error 2 1 write-only QIMR QDEC Interrupt Mask Register 0xD0 32 read-only n 0x0 0x0 DIRCHG Direction Change 1 1 read-only IDX Index 0 1 read-only QERR Quadrature Error 2 1 read-only QISR QDEC Interrupt Status Register 0xD4 32 read-only n 0x0 0x0 DIR Direction 8 1 read-only DIRCHG Direction Change 1 1 read-only IDX Index 0 1 read-only QERR Quadrature Error 2 1 read-only RA0 Register A (channel = 0) 0x14 32 read-write n 0x0 0x0 RA Register A 0 32 read-write RA1 Register A (channel = 1) 0x54 32 read-write n 0x0 0x0 RA Register A 0 32 read-write RA2 Register A (channel = 2) 0x94 32 read-write n 0x0 0x0 RA Register A 0 32 read-write RAB0 Register AB (channel = 0) 0xC 32 read-only n 0x0 0x0 RAB Register A or Register B 0 32 read-only RAB1 Register AB (channel = 1) 0x4C 32 read-only n 0x0 0x0 RAB Register A or Register B 0 32 read-only RAB2 Register AB (channel = 2) 0x8C 32 read-only n 0x0 0x0 RAB Register A or Register B 0 32 read-only RB0 Register B (channel = 0) 0x18 32 read-write n 0x0 0x0 RB Register B 0 32 read-write RB1 Register B (channel = 1) 0x58 32 read-write n 0x0 0x0 RB Register B 0 32 read-write RB2 Register B (channel = 2) 0x98 32 read-write n 0x0 0x0 RB Register B 0 32 read-write RC0 Register C (channel = 0) 0x1C 32 read-write n 0x0 0x0 RC Register C 0 32 read-write RC1 Register C (channel = 1) 0x5C 32 read-write n 0x0 0x0 RC Register C 0 32 read-write RC2 Register C (channel = 2) 0x9C 32 read-write n 0x0 0x0 RC Register C 0 32 read-write SMMR0 Stepper Motor Mode Register (channel = 0) 0x8 32 read-write n 0x0 0x0 DOWN Down Count 1 1 read-write GCEN Gray Count Enable 0 1 read-write SMMR1 Stepper Motor Mode Register (channel = 1) 0x48 32 read-write n 0x0 0x0 DOWN Down Count 1 1 read-write GCEN Gray Count Enable 0 1 read-write SMMR2 Stepper Motor Mode Register (channel = 2) 0x88 32 read-write n 0x0 0x0 DOWN Down Count 1 1 read-write GCEN Gray Count Enable 0 1 read-write SR0 Status Register (channel = 0) 0x20 32 read-only n 0x0 0x0 CLKSTA Clock Enabling Status 16 1 read-only COVFS Counter Overflow Status (cleared on read) 0 1 read-only CPAS RA Compare Status (cleared on read) 2 1 read-only CPBS RB Compare Status (cleared on read) 3 1 read-only CPCS RC Compare Status (cleared on read) 4 1 read-only ETRGS External Trigger Status (cleared on read) 7 1 read-only LDRAS RA Loading Status (cleared on read) 5 1 read-only LDRBS RB Loading Status (cleared on read) 6 1 read-only LOVRS Load Overrun Status (cleared on read) 1 1 read-only MTIOA TIOAx Mirror 17 1 read-only MTIOB TIOBx Mirror 18 1 read-only SR1 Status Register (channel = 1) 0x60 32 read-only n 0x0 0x0 CLKSTA Clock Enabling Status 16 1 read-only COVFS Counter Overflow Status (cleared on read) 0 1 read-only CPAS RA Compare Status (cleared on read) 2 1 read-only CPBS RB Compare Status (cleared on read) 3 1 read-only CPCS RC Compare Status (cleared on read) 4 1 read-only ETRGS External Trigger Status (cleared on read) 7 1 read-only LDRAS RA Loading Status (cleared on read) 5 1 read-only LDRBS RB Loading Status (cleared on read) 6 1 read-only LOVRS Load Overrun Status (cleared on read) 1 1 read-only MTIOA TIOAx Mirror 17 1 read-only MTIOB TIOBx Mirror 18 1 read-only SR2 Status Register (channel = 2) 0xA0 32 read-only n 0x0 0x0 CLKSTA Clock Enabling Status 16 1 read-only COVFS Counter Overflow Status (cleared on read) 0 1 read-only CPAS RA Compare Status (cleared on read) 2 1 read-only CPBS RB Compare Status (cleared on read) 3 1 read-only CPCS RC Compare Status (cleared on read) 4 1 read-only ETRGS External Trigger Status (cleared on read) 7 1 read-only LDRAS RA Loading Status (cleared on read) 5 1 read-only LDRBS RB Loading Status (cleared on read) 6 1 read-only LOVRS Load Overrun Status (cleared on read) 1 1 read-only MTIOA TIOAx Mirror 17 1 read-only MTIOB TIOBx Mirror 18 1 read-only WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 read-write WPKEY Write Protection Key 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 0x54494D TC1 Timer Counter 1 TC 0x0 0x0 0x50 registers n BCR Block Control Register 0xC0 32 write-only n 0x0 0x0 SYNC Synchro Command 0 1 write-only BMR Block Mode Register 0xC4 32 read-write n 0x0 0x0 EDGPHA Edge on PHA Count Mode 12 1 read-write IDXPHB Index Pin is PHB Pin 17 1 read-write INVA Inverted PHA 13 1 read-write INVB Inverted PHB 14 1 read-write INVIDX Inverted Index 15 1 read-write MAXFILT Maximum Filter 20 6 read-write POSEN Position Enabled 9 1 read-write QDEN Quadrature Decoder Enabled 8 1 read-write QDTRANS Quadrature Decoding Transparent 11 1 read-write SPEEDEN Speed Enabled 10 1 read-write SWAP Swap PHA and PHB 16 1 read-write TC0XC0S External Clock Signal 0 Selection 0 2 read-write TCLK0 Signal connected to XC0: TCLK0 0x0 TIOA1 Signal connected to XC0: TIOA1 0x2 TIOA2 Signal connected to XC0: TIOA2 0x3 TC1XC1S External Clock Signal 1 Selection 2 2 read-write TCLK1 Signal connected to XC1: TCLK1 0x0 TIOA0 Signal connected to XC1: TIOA0 0x2 TIOA2 Signal connected to XC1: TIOA2 0x3 TC2XC2S External Clock Signal 2 Selection 4 2 read-write TCLK2 Signal connected to XC2: TCLK2 0x0 TIOA0 Signal connected to XC2: TIOA0 0x2 TIOA1 Signal connected to XC2: TIOA1 0x3 CCR0 Channel Control Register (channel = 0) 0x0 32 write-only n 0x0 0x0 CLKDIS Counter Clock Disable Command 1 1 write-only CLKEN Counter Clock Enable Command 0 1 write-only SWTRG Software Trigger Command 2 1 write-only CCR1 Channel Control Register (channel = 1) 0x40 32 write-only n 0x0 0x0 CLKDIS Counter Clock Disable Command 1 1 write-only CLKEN Counter Clock Enable Command 0 1 write-only SWTRG Software Trigger Command 2 1 write-only CCR2 Channel Control Register (channel = 2) 0x80 32 write-only n 0x0 0x0 CLKDIS Counter Clock Disable Command 1 1 write-only CLKEN Counter Clock Enable Command 0 1 write-only SWTRG Software Trigger Command 2 1 write-only CMR0 Channel Mode Register (channel = 0) 0x4 32 read-write n 0x0 0x0 ABETRG TIOAx or TIOBx External Trigger Selection 10 1 read-write BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 read-write CPCTRG RC Compare Trigger Enable 14 1 read-write ETRGEDG External Trigger Edge Selection 8 2 read-write NONE The clock is not gated by an external signal. 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 LDBDIS Counter Clock Disable with RB Loading 7 1 read-write LDBSTOP Counter Clock Stopped with RB Loading 6 1 read-write LDRA RA Loading Edge Selection 16 2 read-write NONE None 0x0 RISING Rising edge of TIOAx 0x1 FALLING Falling edge of TIOAx 0x2 EDGE Each edge of TIOAx 0x3 LDRB RB Loading Edge Selection 18 2 read-write NONE None 0x0 RISING Rising edge of TIOAx 0x1 FALLING Falling edge of TIOAx 0x2 EDGE Each edge of TIOAx 0x3 SBSMPLR Loading Edge Subsampling Ratio 20 3 read-write ONE Load a Capture Register each selected edge 0x0 HALF Load a Capture Register every 2 selected edges 0x1 FOURTH Load a Capture Register every 4 selected edges 0x2 EIGHTH Load a Capture Register every 8 selected edges 0x3 SIXTEENTH Load a Capture Register every 16 selected edges 0x4 TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: internal div2 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal div8 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal div32 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal div128 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal slow_clock clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 read-write CMR0_WAVEFORM_MODE Channel Mode Register (channel = 0) WAVEFORM_MODE 0x4 32 read-write n 0x0 0x0 ACPA RA Compare Effect on TIOAx 16 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ACPC RC Compare Effect on TIOAx 18 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 AEEVT External Event Effect on TIOAx 20 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ASWTRG Software Trigger Effect on TIOAx 22 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPB RB Compare Effect on TIOBx 24 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPC RC Compare Effect on TIOBx 26 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BEEVT External Event Effect on TIOBx 28 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BSWTRG Software Trigger Effect on TIOBx 30 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 read-write CPCDIS Counter Clock Disable with RC Compare 7 1 read-write CPCSTOP Counter Clock Stopped with RC Compare 6 1 read-write EEVT External Event Selection 10 2 read-write TIOB TIOB 0x0 XC0 XC0 0x1 XC1 XC1 0x2 XC2 XC2 0x3 EEVTEDG External Event Edge Selection 8 2 read-write NONE None 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 ENETRG External Event Trigger Enable 12 1 read-write TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: internal div2 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal div8 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal div32 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal div128 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal slow_clock clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 read-write WAVSEL Waveform Selection 13 2 read-write UP UP mode without automatic trigger on RC Compare 0x0 UPDOWN UPDOWN mode without automatic trigger on RC Compare 0x1 UP_RC UP mode with automatic trigger on RC Compare 0x2 UPDOWN_RC UPDOWN mode with automatic trigger on RC Compare 0x3 CMR1 Channel Mode Register (channel = 1) 0x44 32 read-write n 0x0 0x0 ABETRG TIOAx or TIOBx External Trigger Selection 10 1 read-write BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 read-write CPCTRG RC Compare Trigger Enable 14 1 read-write ETRGEDG External Trigger Edge Selection 8 2 read-write NONE The clock is not gated by an external signal. 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 LDBDIS Counter Clock Disable with RB Loading 7 1 read-write LDBSTOP Counter Clock Stopped with RB Loading 6 1 read-write LDRA RA Loading Edge Selection 16 2 read-write NONE None 0x0 RISING Rising edge of TIOAx 0x1 FALLING Falling edge of TIOAx 0x2 EDGE Each edge of TIOAx 0x3 LDRB RB Loading Edge Selection 18 2 read-write NONE None 0x0 RISING Rising edge of TIOAx 0x1 FALLING Falling edge of TIOAx 0x2 EDGE Each edge of TIOAx 0x3 SBSMPLR Loading Edge Subsampling Ratio 20 3 read-write ONE Load a Capture Register each selected edge 0x0 HALF Load a Capture Register every 2 selected edges 0x1 FOURTH Load a Capture Register every 4 selected edges 0x2 EIGHTH Load a Capture Register every 8 selected edges 0x3 SIXTEENTH Load a Capture Register every 16 selected edges 0x4 TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: internal div2 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal div8 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal div32 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal div128 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal slow_clock clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 read-write CMR1_WAVEFORM_MODE Channel Mode Register (channel = 1) WAVEFORM_MODE 0x44 32 read-write n 0x0 0x0 ACPA RA Compare Effect on TIOAx 16 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ACPC RC Compare Effect on TIOAx 18 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 AEEVT External Event Effect on TIOAx 20 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ASWTRG Software Trigger Effect on TIOAx 22 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPB RB Compare Effect on TIOBx 24 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPC RC Compare Effect on TIOBx 26 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BEEVT External Event Effect on TIOBx 28 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BSWTRG Software Trigger Effect on TIOBx 30 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 read-write CPCDIS Counter Clock Disable with RC Compare 7 1 read-write CPCSTOP Counter Clock Stopped with RC Compare 6 1 read-write EEVT External Event Selection 10 2 read-write TIOB TIOB 0x0 XC0 XC0 0x1 XC1 XC1 0x2 XC2 XC2 0x3 EEVTEDG External Event Edge Selection 8 2 read-write NONE None 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 ENETRG External Event Trigger Enable 12 1 read-write TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: internal div2 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal div8 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal div32 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal div128 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal slow_clock clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 read-write WAVSEL Waveform Selection 13 2 read-write UP UP mode without automatic trigger on RC Compare 0x0 UPDOWN UPDOWN mode without automatic trigger on RC Compare 0x1 UP_RC UP mode with automatic trigger on RC Compare 0x2 UPDOWN_RC UPDOWN mode with automatic trigger on RC Compare 0x3 CMR2 Channel Mode Register (channel = 2) 0x84 32 read-write n 0x0 0x0 ABETRG TIOAx or TIOBx External Trigger Selection 10 1 read-write BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 read-write CPCTRG RC Compare Trigger Enable 14 1 read-write ETRGEDG External Trigger Edge Selection 8 2 read-write NONE The clock is not gated by an external signal. 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 LDBDIS Counter Clock Disable with RB Loading 7 1 read-write LDBSTOP Counter Clock Stopped with RB Loading 6 1 read-write LDRA RA Loading Edge Selection 16 2 read-write NONE None 0x0 RISING Rising edge of TIOAx 0x1 FALLING Falling edge of TIOAx 0x2 EDGE Each edge of TIOAx 0x3 LDRB RB Loading Edge Selection 18 2 read-write NONE None 0x0 RISING Rising edge of TIOAx 0x1 FALLING Falling edge of TIOAx 0x2 EDGE Each edge of TIOAx 0x3 SBSMPLR Loading Edge Subsampling Ratio 20 3 read-write ONE Load a Capture Register each selected edge 0x0 HALF Load a Capture Register every 2 selected edges 0x1 FOURTH Load a Capture Register every 4 selected edges 0x2 EIGHTH Load a Capture Register every 8 selected edges 0x3 SIXTEENTH Load a Capture Register every 16 selected edges 0x4 TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: internal div2 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal div8 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal div32 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal div128 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal slow_clock clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 read-write CMR2_WAVEFORM_MODE Channel Mode Register (channel = 2) WAVEFORM_MODE 0x84 32 read-write n 0x0 0x0 ACPA RA Compare Effect on TIOAx 16 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ACPC RC Compare Effect on TIOAx 18 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 AEEVT External Event Effect on TIOAx 20 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ASWTRG Software Trigger Effect on TIOAx 22 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPB RB Compare Effect on TIOBx 24 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPC RC Compare Effect on TIOBx 26 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BEEVT External Event Effect on TIOBx 28 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BSWTRG Software Trigger Effect on TIOBx 30 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 read-write CPCDIS Counter Clock Disable with RC Compare 7 1 read-write CPCSTOP Counter Clock Stopped with RC Compare 6 1 read-write EEVT External Event Selection 10 2 read-write TIOB TIOB 0x0 XC0 XC0 0x1 XC1 XC1 0x2 XC2 XC2 0x3 EEVTEDG External Event Edge Selection 8 2 read-write NONE None 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 ENETRG External Event Trigger Enable 12 1 read-write TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: internal div2 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal div8 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal div32 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal div128 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal slow_clock clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 read-write WAVSEL Waveform Selection 13 2 read-write UP UP mode without automatic trigger on RC Compare 0x0 UPDOWN UPDOWN mode without automatic trigger on RC Compare 0x1 UP_RC UP mode with automatic trigger on RC Compare 0x2 UPDOWN_RC UPDOWN mode with automatic trigger on RC Compare 0x3 CV0 Counter Value (channel = 0) 0x10 32 read-only n 0x0 0x0 CV Counter Value 0 32 read-only CV1 Counter Value (channel = 1) 0x50 32 read-only n 0x0 0x0 CV Counter Value 0 32 read-only CV2 Counter Value (channel = 2) 0x90 32 read-only n 0x0 0x0 CV Counter Value 0 32 read-only EMR0 Extended Mode Register (channel = 0) 0x30 32 read-write n 0x0 0x0 NODIVCLK No Divided Clock 8 1 read-write TRIGSRCA Trigger Source for Input A 0 2 read-write EXTERNAL_TIOAx The trigger/capture input A is driven by external pin TIOAx 0 PWMx The trigger/capture input A is driven internally by PWMx 1 TRIGSRCB Trigger Source for Input B 4 2 read-write EXTERNAL_TIOBx The trigger/capture input B is driven by external pin TIOBx 0 PWMx The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx. 1 EMR1 Extended Mode Register (channel = 1) 0x70 32 read-write n 0x0 0x0 NODIVCLK No Divided Clock 8 1 read-write TRIGSRCA Trigger Source for Input A 0 2 read-write EXTERNAL_TIOAx The trigger/capture input A is driven by external pin TIOAx 0 PWMx The trigger/capture input A is driven internally by PWMx 1 TRIGSRCB Trigger Source for Input B 4 2 read-write EXTERNAL_TIOBx The trigger/capture input B is driven by external pin TIOBx 0 PWMx The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx. 1 EMR2 Extended Mode Register (channel = 2) 0xB0 32 read-write n 0x0 0x0 NODIVCLK No Divided Clock 8 1 read-write TRIGSRCA Trigger Source for Input A 0 2 read-write EXTERNAL_TIOAx The trigger/capture input A is driven by external pin TIOAx 0 PWMx The trigger/capture input A is driven internally by PWMx 1 TRIGSRCB Trigger Source for Input B 4 2 read-write EXTERNAL_TIOBx The trigger/capture input B is driven by external pin TIOBx 0 PWMx The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx. 1 FMR Fault Mode Register 0xD8 32 read-write n 0x0 0x0 ENCF0 Enable Compare Fault Channel 0 0 1 read-write ENCF1 Enable Compare Fault Channel 1 1 1 read-write IDR0 Interrupt Disable Register (channel = 0) 0x28 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only ETRGS External Trigger 7 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only LOVRS Load Overrun 1 1 write-only IDR1 Interrupt Disable Register (channel = 1) 0x68 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only ETRGS External Trigger 7 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only LOVRS Load Overrun 1 1 write-only IDR2 Interrupt Disable Register (channel = 2) 0xA8 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only ETRGS External Trigger 7 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only LOVRS Load Overrun 1 1 write-only IER0 Interrupt Enable Register (channel = 0) 0x24 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only ETRGS External Trigger 7 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only LOVRS Load Overrun 1 1 write-only IER1 Interrupt Enable Register (channel = 1) 0x64 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only ETRGS External Trigger 7 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only LOVRS Load Overrun 1 1 write-only IER2 Interrupt Enable Register (channel = 2) 0xA4 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only ETRGS External Trigger 7 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only LOVRS Load Overrun 1 1 write-only IMR0 Interrupt Mask Register (channel = 0) 0x2C 32 read-only n 0x0 0x0 COVFS Counter Overflow 0 1 read-only CPAS RA Compare 2 1 read-only CPBS RB Compare 3 1 read-only CPCS RC Compare 4 1 read-only ETRGS External Trigger 7 1 read-only LDRAS RA Loading 5 1 read-only LDRBS RB Loading 6 1 read-only LOVRS Load Overrun 1 1 read-only IMR1 Interrupt Mask Register (channel = 1) 0x6C 32 read-only n 0x0 0x0 COVFS Counter Overflow 0 1 read-only CPAS RA Compare 2 1 read-only CPBS RB Compare 3 1 read-only CPCS RC Compare 4 1 read-only ETRGS External Trigger 7 1 read-only LDRAS RA Loading 5 1 read-only LDRBS RB Loading 6 1 read-only LOVRS Load Overrun 1 1 read-only IMR2 Interrupt Mask Register (channel = 2) 0xAC 32 read-only n 0x0 0x0 COVFS Counter Overflow 0 1 read-only CPAS RA Compare 2 1 read-only CPBS RB Compare 3 1 read-only CPCS RC Compare 4 1 read-only ETRGS External Trigger 7 1 read-only LDRAS RA Loading 5 1 read-only LDRBS RB Loading 6 1 read-only LOVRS Load Overrun 1 1 read-only QIDR QDEC Interrupt Disable Register 0xCC 32 write-only n 0x0 0x0 DIRCHG Direction Change 1 1 write-only IDX Index 0 1 write-only QERR Quadrature Error 2 1 write-only QIER QDEC Interrupt Enable Register 0xC8 32 write-only n 0x0 0x0 DIRCHG Direction Change 1 1 write-only IDX Index 0 1 write-only QERR Quadrature Error 2 1 write-only QIMR QDEC Interrupt Mask Register 0xD0 32 read-only n 0x0 0x0 DIRCHG Direction Change 1 1 read-only IDX Index 0 1 read-only QERR Quadrature Error 2 1 read-only QISR QDEC Interrupt Status Register 0xD4 32 read-only n 0x0 0x0 DIR Direction 8 1 read-only DIRCHG Direction Change 1 1 read-only IDX Index 0 1 read-only QERR Quadrature Error 2 1 read-only RA0 Register A (channel = 0) 0x14 32 read-write n 0x0 0x0 RA Register A 0 32 read-write RA1 Register A (channel = 1) 0x54 32 read-write n 0x0 0x0 RA Register A 0 32 read-write RA2 Register A (channel = 2) 0x94 32 read-write n 0x0 0x0 RA Register A 0 32 read-write RAB0 Register AB (channel = 0) 0xC 32 read-only n 0x0 0x0 RAB Register A or Register B 0 32 read-only RAB1 Register AB (channel = 1) 0x4C 32 read-only n 0x0 0x0 RAB Register A or Register B 0 32 read-only RAB2 Register AB (channel = 2) 0x8C 32 read-only n 0x0 0x0 RAB Register A or Register B 0 32 read-only RB0 Register B (channel = 0) 0x18 32 read-write n 0x0 0x0 RB Register B 0 32 read-write RB1 Register B (channel = 1) 0x58 32 read-write n 0x0 0x0 RB Register B 0 32 read-write RB2 Register B (channel = 2) 0x98 32 read-write n 0x0 0x0 RB Register B 0 32 read-write RC0 Register C (channel = 0) 0x1C 32 read-write n 0x0 0x0 RC Register C 0 32 read-write RC1 Register C (channel = 1) 0x5C 32 read-write n 0x0 0x0 RC Register C 0 32 read-write RC2 Register C (channel = 2) 0x9C 32 read-write n 0x0 0x0 RC Register C 0 32 read-write SMMR0 Stepper Motor Mode Register (channel = 0) 0x8 32 read-write n 0x0 0x0 DOWN Down Count 1 1 read-write GCEN Gray Count Enable 0 1 read-write SMMR1 Stepper Motor Mode Register (channel = 1) 0x48 32 read-write n 0x0 0x0 DOWN Down Count 1 1 read-write GCEN Gray Count Enable 0 1 read-write SMMR2 Stepper Motor Mode Register (channel = 2) 0x88 32 read-write n 0x0 0x0 DOWN Down Count 1 1 read-write GCEN Gray Count Enable 0 1 read-write SR0 Status Register (channel = 0) 0x20 32 read-only n 0x0 0x0 CLKSTA Clock Enabling Status 16 1 read-only COVFS Counter Overflow Status (cleared on read) 0 1 read-only CPAS RA Compare Status (cleared on read) 2 1 read-only CPBS RB Compare Status (cleared on read) 3 1 read-only CPCS RC Compare Status (cleared on read) 4 1 read-only ETRGS External Trigger Status (cleared on read) 7 1 read-only LDRAS RA Loading Status (cleared on read) 5 1 read-only LDRBS RB Loading Status (cleared on read) 6 1 read-only LOVRS Load Overrun Status (cleared on read) 1 1 read-only MTIOA TIOAx Mirror 17 1 read-only MTIOB TIOBx Mirror 18 1 read-only SR1 Status Register (channel = 1) 0x60 32 read-only n 0x0 0x0 CLKSTA Clock Enabling Status 16 1 read-only COVFS Counter Overflow Status (cleared on read) 0 1 read-only CPAS RA Compare Status (cleared on read) 2 1 read-only CPBS RB Compare Status (cleared on read) 3 1 read-only CPCS RC Compare Status (cleared on read) 4 1 read-only ETRGS External Trigger Status (cleared on read) 7 1 read-only LDRAS RA Loading Status (cleared on read) 5 1 read-only LDRBS RB Loading Status (cleared on read) 6 1 read-only LOVRS Load Overrun Status (cleared on read) 1 1 read-only MTIOA TIOAx Mirror 17 1 read-only MTIOB TIOBx Mirror 18 1 read-only SR2 Status Register (channel = 2) 0xA0 32 read-only n 0x0 0x0 CLKSTA Clock Enabling Status 16 1 read-only COVFS Counter Overflow Status (cleared on read) 0 1 read-only CPAS RA Compare Status (cleared on read) 2 1 read-only CPBS RB Compare Status (cleared on read) 3 1 read-only CPCS RC Compare Status (cleared on read) 4 1 read-only ETRGS External Trigger Status (cleared on read) 7 1 read-only LDRAS RA Loading Status (cleared on read) 5 1 read-only LDRBS RB Loading Status (cleared on read) 6 1 read-only LOVRS Load Overrun Status (cleared on read) 1 1 read-only MTIOA TIOAx Mirror 17 1 read-only MTIOB TIOBx Mirror 18 1 read-only WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 read-write WPKEY Write Protection Key 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 0x54494D TC2 Timer Counter 2 TC 0x0 0x0 0x50 registers n BCR Block Control Register 0xC0 32 write-only n 0x0 0x0 SYNC Synchro Command 0 1 write-only BMR Block Mode Register 0xC4 32 read-write n 0x0 0x0 EDGPHA Edge on PHA Count Mode 12 1 read-write IDXPHB Index Pin is PHB Pin 17 1 read-write INVA Inverted PHA 13 1 read-write INVB Inverted PHB 14 1 read-write INVIDX Inverted Index 15 1 read-write MAXFILT Maximum Filter 20 6 read-write POSEN Position Enabled 9 1 read-write QDEN Quadrature Decoder Enabled 8 1 read-write QDTRANS Quadrature Decoding Transparent 11 1 read-write SPEEDEN Speed Enabled 10 1 read-write SWAP Swap PHA and PHB 16 1 read-write TC0XC0S External Clock Signal 0 Selection 0 2 read-write TCLK0 Signal connected to XC0: TCLK0 0x0 TIOA1 Signal connected to XC0: TIOA1 0x2 TIOA2 Signal connected to XC0: TIOA2 0x3 TC1XC1S External Clock Signal 1 Selection 2 2 read-write TCLK1 Signal connected to XC1: TCLK1 0x0 TIOA0 Signal connected to XC1: TIOA0 0x2 TIOA2 Signal connected to XC1: TIOA2 0x3 TC2XC2S External Clock Signal 2 Selection 4 2 read-write TCLK2 Signal connected to XC2: TCLK2 0x0 TIOA0 Signal connected to XC2: TIOA0 0x2 TIOA1 Signal connected to XC2: TIOA1 0x3 CCR0 Channel Control Register (channel = 0) 0x0 32 write-only n 0x0 0x0 CLKDIS Counter Clock Disable Command 1 1 write-only CLKEN Counter Clock Enable Command 0 1 write-only SWTRG Software Trigger Command 2 1 write-only CCR1 Channel Control Register (channel = 1) 0x40 32 write-only n 0x0 0x0 CLKDIS Counter Clock Disable Command 1 1 write-only CLKEN Counter Clock Enable Command 0 1 write-only SWTRG Software Trigger Command 2 1 write-only CCR2 Channel Control Register (channel = 2) 0x80 32 write-only n 0x0 0x0 CLKDIS Counter Clock Disable Command 1 1 write-only CLKEN Counter Clock Enable Command 0 1 write-only SWTRG Software Trigger Command 2 1 write-only CMR0 Channel Mode Register (channel = 0) 0x4 32 read-write n 0x0 0x0 ABETRG TIOAx or TIOBx External Trigger Selection 10 1 read-write BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 read-write CPCTRG RC Compare Trigger Enable 14 1 read-write ETRGEDG External Trigger Edge Selection 8 2 read-write NONE The clock is not gated by an external signal. 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 LDBDIS Counter Clock Disable with RB Loading 7 1 read-write LDBSTOP Counter Clock Stopped with RB Loading 6 1 read-write LDRA RA Loading Edge Selection 16 2 read-write NONE None 0x0 RISING Rising edge of TIOAx 0x1 FALLING Falling edge of TIOAx 0x2 EDGE Each edge of TIOAx 0x3 LDRB RB Loading Edge Selection 18 2 read-write NONE None 0x0 RISING Rising edge of TIOAx 0x1 FALLING Falling edge of TIOAx 0x2 EDGE Each edge of TIOAx 0x3 SBSMPLR Loading Edge Subsampling Ratio 20 3 read-write ONE Load a Capture Register each selected edge 0x0 HALF Load a Capture Register every 2 selected edges 0x1 FOURTH Load a Capture Register every 4 selected edges 0x2 EIGHTH Load a Capture Register every 8 selected edges 0x3 SIXTEENTH Load a Capture Register every 16 selected edges 0x4 TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: internal div2 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal div8 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal div32 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal div128 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal slow_clock clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 read-write CMR0_WAVEFORM_MODE Channel Mode Register (channel = 0) WAVEFORM_MODE 0x4 32 read-write n 0x0 0x0 ACPA RA Compare Effect on TIOAx 16 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ACPC RC Compare Effect on TIOAx 18 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 AEEVT External Event Effect on TIOAx 20 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ASWTRG Software Trigger Effect on TIOAx 22 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPB RB Compare Effect on TIOBx 24 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPC RC Compare Effect on TIOBx 26 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BEEVT External Event Effect on TIOBx 28 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BSWTRG Software Trigger Effect on TIOBx 30 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 read-write CPCDIS Counter Clock Disable with RC Compare 7 1 read-write CPCSTOP Counter Clock Stopped with RC Compare 6 1 read-write EEVT External Event Selection 10 2 read-write TIOB TIOB 0x0 XC0 XC0 0x1 XC1 XC1 0x2 XC2 XC2 0x3 EEVTEDG External Event Edge Selection 8 2 read-write NONE None 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 ENETRG External Event Trigger Enable 12 1 read-write TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: internal div2 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal div8 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal div32 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal div128 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal slow_clock clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 read-write WAVSEL Waveform Selection 13 2 read-write UP UP mode without automatic trigger on RC Compare 0x0 UPDOWN UPDOWN mode without automatic trigger on RC Compare 0x1 UP_RC UP mode with automatic trigger on RC Compare 0x2 UPDOWN_RC UPDOWN mode with automatic trigger on RC Compare 0x3 CMR1 Channel Mode Register (channel = 1) 0x44 32 read-write n 0x0 0x0 ABETRG TIOAx or TIOBx External Trigger Selection 10 1 read-write BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 read-write CPCTRG RC Compare Trigger Enable 14 1 read-write ETRGEDG External Trigger Edge Selection 8 2 read-write NONE The clock is not gated by an external signal. 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 LDBDIS Counter Clock Disable with RB Loading 7 1 read-write LDBSTOP Counter Clock Stopped with RB Loading 6 1 read-write LDRA RA Loading Edge Selection 16 2 read-write NONE None 0x0 RISING Rising edge of TIOAx 0x1 FALLING Falling edge of TIOAx 0x2 EDGE Each edge of TIOAx 0x3 LDRB RB Loading Edge Selection 18 2 read-write NONE None 0x0 RISING Rising edge of TIOAx 0x1 FALLING Falling edge of TIOAx 0x2 EDGE Each edge of TIOAx 0x3 SBSMPLR Loading Edge Subsampling Ratio 20 3 read-write ONE Load a Capture Register each selected edge 0x0 HALF Load a Capture Register every 2 selected edges 0x1 FOURTH Load a Capture Register every 4 selected edges 0x2 EIGHTH Load a Capture Register every 8 selected edges 0x3 SIXTEENTH Load a Capture Register every 16 selected edges 0x4 TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: internal div2 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal div8 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal div32 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal div128 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal slow_clock clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 read-write CMR1_WAVEFORM_MODE Channel Mode Register (channel = 1) WAVEFORM_MODE 0x44 32 read-write n 0x0 0x0 ACPA RA Compare Effect on TIOAx 16 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ACPC RC Compare Effect on TIOAx 18 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 AEEVT External Event Effect on TIOAx 20 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ASWTRG Software Trigger Effect on TIOAx 22 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPB RB Compare Effect on TIOBx 24 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPC RC Compare Effect on TIOBx 26 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BEEVT External Event Effect on TIOBx 28 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BSWTRG Software Trigger Effect on TIOBx 30 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 read-write CPCDIS Counter Clock Disable with RC Compare 7 1 read-write CPCSTOP Counter Clock Stopped with RC Compare 6 1 read-write EEVT External Event Selection 10 2 read-write TIOB TIOB 0x0 XC0 XC0 0x1 XC1 XC1 0x2 XC2 XC2 0x3 EEVTEDG External Event Edge Selection 8 2 read-write NONE None 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 ENETRG External Event Trigger Enable 12 1 read-write TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: internal div2 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal div8 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal div32 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal div128 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal slow_clock clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 read-write WAVSEL Waveform Selection 13 2 read-write UP UP mode without automatic trigger on RC Compare 0x0 UPDOWN UPDOWN mode without automatic trigger on RC Compare 0x1 UP_RC UP mode with automatic trigger on RC Compare 0x2 UPDOWN_RC UPDOWN mode with automatic trigger on RC Compare 0x3 CMR2 Channel Mode Register (channel = 2) 0x84 32 read-write n 0x0 0x0 ABETRG TIOAx or TIOBx External Trigger Selection 10 1 read-write BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 read-write CPCTRG RC Compare Trigger Enable 14 1 read-write ETRGEDG External Trigger Edge Selection 8 2 read-write NONE The clock is not gated by an external signal. 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 LDBDIS Counter Clock Disable with RB Loading 7 1 read-write LDBSTOP Counter Clock Stopped with RB Loading 6 1 read-write LDRA RA Loading Edge Selection 16 2 read-write NONE None 0x0 RISING Rising edge of TIOAx 0x1 FALLING Falling edge of TIOAx 0x2 EDGE Each edge of TIOAx 0x3 LDRB RB Loading Edge Selection 18 2 read-write NONE None 0x0 RISING Rising edge of TIOAx 0x1 FALLING Falling edge of TIOAx 0x2 EDGE Each edge of TIOAx 0x3 SBSMPLR Loading Edge Subsampling Ratio 20 3 read-write ONE Load a Capture Register each selected edge 0x0 HALF Load a Capture Register every 2 selected edges 0x1 FOURTH Load a Capture Register every 4 selected edges 0x2 EIGHTH Load a Capture Register every 8 selected edges 0x3 SIXTEENTH Load a Capture Register every 16 selected edges 0x4 TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: internal div2 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal div8 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal div32 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal div128 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal slow_clock clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 read-write CMR2_WAVEFORM_MODE Channel Mode Register (channel = 2) WAVEFORM_MODE 0x84 32 read-write n 0x0 0x0 ACPA RA Compare Effect on TIOAx 16 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ACPC RC Compare Effect on TIOAx 18 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 AEEVT External Event Effect on TIOAx 20 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ASWTRG Software Trigger Effect on TIOAx 22 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPB RB Compare Effect on TIOBx 24 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPC RC Compare Effect on TIOBx 26 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BEEVT External Event Effect on TIOBx 28 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BSWTRG Software Trigger Effect on TIOBx 30 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 read-write CPCDIS Counter Clock Disable with RC Compare 7 1 read-write CPCSTOP Counter Clock Stopped with RC Compare 6 1 read-write EEVT External Event Selection 10 2 read-write TIOB TIOB 0x0 XC0 XC0 0x1 XC1 XC1 0x2 XC2 XC2 0x3 EEVTEDG External Event Edge Selection 8 2 read-write NONE None 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 ENETRG External Event Trigger Enable 12 1 read-write TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: internal div2 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal div8 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal div32 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal div128 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal slow_clock clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 read-write WAVSEL Waveform Selection 13 2 read-write UP UP mode without automatic trigger on RC Compare 0x0 UPDOWN UPDOWN mode without automatic trigger on RC Compare 0x1 UP_RC UP mode with automatic trigger on RC Compare 0x2 UPDOWN_RC UPDOWN mode with automatic trigger on RC Compare 0x3 CV0 Counter Value (channel = 0) 0x10 32 read-only n 0x0 0x0 CV Counter Value 0 32 read-only CV1 Counter Value (channel = 1) 0x50 32 read-only n 0x0 0x0 CV Counter Value 0 32 read-only CV2 Counter Value (channel = 2) 0x90 32 read-only n 0x0 0x0 CV Counter Value 0 32 read-only EMR0 Extended Mode Register (channel = 0) 0x30 32 read-write n 0x0 0x0 NODIVCLK No Divided Clock 8 1 read-write TRIGSRCA Trigger Source for Input A 0 2 read-write EXTERNAL_TIOAx The trigger/capture input A is driven by external pin TIOAx 0 PWMx The trigger/capture input A is driven internally by PWMx 1 TRIGSRCB Trigger Source for Input B 4 2 read-write EXTERNAL_TIOBx The trigger/capture input B is driven by external pin TIOBx 0 PWMx The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx. 1 EMR1 Extended Mode Register (channel = 1) 0x70 32 read-write n 0x0 0x0 NODIVCLK No Divided Clock 8 1 read-write TRIGSRCA Trigger Source for Input A 0 2 read-write EXTERNAL_TIOAx The trigger/capture input A is driven by external pin TIOAx 0 PWMx The trigger/capture input A is driven internally by PWMx 1 TRIGSRCB Trigger Source for Input B 4 2 read-write EXTERNAL_TIOBx The trigger/capture input B is driven by external pin TIOBx 0 PWMx The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx. 1 EMR2 Extended Mode Register (channel = 2) 0xB0 32 read-write n 0x0 0x0 NODIVCLK No Divided Clock 8 1 read-write TRIGSRCA Trigger Source for Input A 0 2 read-write EXTERNAL_TIOAx The trigger/capture input A is driven by external pin TIOAx 0 PWMx The trigger/capture input A is driven internally by PWMx 1 TRIGSRCB Trigger Source for Input B 4 2 read-write EXTERNAL_TIOBx The trigger/capture input B is driven by external pin TIOBx 0 PWMx The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx. 1 FMR Fault Mode Register 0xD8 32 read-write n 0x0 0x0 ENCF0 Enable Compare Fault Channel 0 0 1 read-write ENCF1 Enable Compare Fault Channel 1 1 1 read-write IDR0 Interrupt Disable Register (channel = 0) 0x28 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only ETRGS External Trigger 7 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only LOVRS Load Overrun 1 1 write-only IDR1 Interrupt Disable Register (channel = 1) 0x68 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only ETRGS External Trigger 7 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only LOVRS Load Overrun 1 1 write-only IDR2 Interrupt Disable Register (channel = 2) 0xA8 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only ETRGS External Trigger 7 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only LOVRS Load Overrun 1 1 write-only IER0 Interrupt Enable Register (channel = 0) 0x24 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only ETRGS External Trigger 7 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only LOVRS Load Overrun 1 1 write-only IER1 Interrupt Enable Register (channel = 1) 0x64 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only ETRGS External Trigger 7 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only LOVRS Load Overrun 1 1 write-only IER2 Interrupt Enable Register (channel = 2) 0xA4 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only ETRGS External Trigger 7 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only LOVRS Load Overrun 1 1 write-only IMR0 Interrupt Mask Register (channel = 0) 0x2C 32 read-only n 0x0 0x0 COVFS Counter Overflow 0 1 read-only CPAS RA Compare 2 1 read-only CPBS RB Compare 3 1 read-only CPCS RC Compare 4 1 read-only ETRGS External Trigger 7 1 read-only LDRAS RA Loading 5 1 read-only LDRBS RB Loading 6 1 read-only LOVRS Load Overrun 1 1 read-only IMR1 Interrupt Mask Register (channel = 1) 0x6C 32 read-only n 0x0 0x0 COVFS Counter Overflow 0 1 read-only CPAS RA Compare 2 1 read-only CPBS RB Compare 3 1 read-only CPCS RC Compare 4 1 read-only ETRGS External Trigger 7 1 read-only LDRAS RA Loading 5 1 read-only LDRBS RB Loading 6 1 read-only LOVRS Load Overrun 1 1 read-only IMR2 Interrupt Mask Register (channel = 2) 0xAC 32 read-only n 0x0 0x0 COVFS Counter Overflow 0 1 read-only CPAS RA Compare 2 1 read-only CPBS RB Compare 3 1 read-only CPCS RC Compare 4 1 read-only ETRGS External Trigger 7 1 read-only LDRAS RA Loading 5 1 read-only LDRBS RB Loading 6 1 read-only LOVRS Load Overrun 1 1 read-only QIDR QDEC Interrupt Disable Register 0xCC 32 write-only n 0x0 0x0 DIRCHG Direction Change 1 1 write-only IDX Index 0 1 write-only QERR Quadrature Error 2 1 write-only QIER QDEC Interrupt Enable Register 0xC8 32 write-only n 0x0 0x0 DIRCHG Direction Change 1 1 write-only IDX Index 0 1 write-only QERR Quadrature Error 2 1 write-only QIMR QDEC Interrupt Mask Register 0xD0 32 read-only n 0x0 0x0 DIRCHG Direction Change 1 1 read-only IDX Index 0 1 read-only QERR Quadrature Error 2 1 read-only QISR QDEC Interrupt Status Register 0xD4 32 read-only n 0x0 0x0 DIR Direction 8 1 read-only DIRCHG Direction Change 1 1 read-only IDX Index 0 1 read-only QERR Quadrature Error 2 1 read-only RA0 Register A (channel = 0) 0x14 32 read-write n 0x0 0x0 RA Register A 0 32 read-write RA1 Register A (channel = 1) 0x54 32 read-write n 0x0 0x0 RA Register A 0 32 read-write RA2 Register A (channel = 2) 0x94 32 read-write n 0x0 0x0 RA Register A 0 32 read-write RAB0 Register AB (channel = 0) 0xC 32 read-only n 0x0 0x0 RAB Register A or Register B 0 32 read-only RAB1 Register AB (channel = 1) 0x4C 32 read-only n 0x0 0x0 RAB Register A or Register B 0 32 read-only RAB2 Register AB (channel = 2) 0x8C 32 read-only n 0x0 0x0 RAB Register A or Register B 0 32 read-only RB0 Register B (channel = 0) 0x18 32 read-write n 0x0 0x0 RB Register B 0 32 read-write RB1 Register B (channel = 1) 0x58 32 read-write n 0x0 0x0 RB Register B 0 32 read-write RB2 Register B (channel = 2) 0x98 32 read-write n 0x0 0x0 RB Register B 0 32 read-write RC0 Register C (channel = 0) 0x1C 32 read-write n 0x0 0x0 RC Register C 0 32 read-write RC1 Register C (channel = 1) 0x5C 32 read-write n 0x0 0x0 RC Register C 0 32 read-write RC2 Register C (channel = 2) 0x9C 32 read-write n 0x0 0x0 RC Register C 0 32 read-write SMMR0 Stepper Motor Mode Register (channel = 0) 0x8 32 read-write n 0x0 0x0 DOWN Down Count 1 1 read-write GCEN Gray Count Enable 0 1 read-write SMMR1 Stepper Motor Mode Register (channel = 1) 0x48 32 read-write n 0x0 0x0 DOWN Down Count 1 1 read-write GCEN Gray Count Enable 0 1 read-write SMMR2 Stepper Motor Mode Register (channel = 2) 0x88 32 read-write n 0x0 0x0 DOWN Down Count 1 1 read-write GCEN Gray Count Enable 0 1 read-write SR0 Status Register (channel = 0) 0x20 32 read-only n 0x0 0x0 CLKSTA Clock Enabling Status 16 1 read-only COVFS Counter Overflow Status (cleared on read) 0 1 read-only CPAS RA Compare Status (cleared on read) 2 1 read-only CPBS RB Compare Status (cleared on read) 3 1 read-only CPCS RC Compare Status (cleared on read) 4 1 read-only ETRGS External Trigger Status (cleared on read) 7 1 read-only LDRAS RA Loading Status (cleared on read) 5 1 read-only LDRBS RB Loading Status (cleared on read) 6 1 read-only LOVRS Load Overrun Status (cleared on read) 1 1 read-only MTIOA TIOAx Mirror 17 1 read-only MTIOB TIOBx Mirror 18 1 read-only SR1 Status Register (channel = 1) 0x60 32 read-only n 0x0 0x0 CLKSTA Clock Enabling Status 16 1 read-only COVFS Counter Overflow Status (cleared on read) 0 1 read-only CPAS RA Compare Status (cleared on read) 2 1 read-only CPBS RB Compare Status (cleared on read) 3 1 read-only CPCS RC Compare Status (cleared on read) 4 1 read-only ETRGS External Trigger Status (cleared on read) 7 1 read-only LDRAS RA Loading Status (cleared on read) 5 1 read-only LDRBS RB Loading Status (cleared on read) 6 1 read-only LOVRS Load Overrun Status (cleared on read) 1 1 read-only MTIOA TIOAx Mirror 17 1 read-only MTIOB TIOBx Mirror 18 1 read-only SR2 Status Register (channel = 2) 0xA0 32 read-only n 0x0 0x0 CLKSTA Clock Enabling Status 16 1 read-only COVFS Counter Overflow Status (cleared on read) 0 1 read-only CPAS RA Compare Status (cleared on read) 2 1 read-only CPBS RB Compare Status (cleared on read) 3 1 read-only CPCS RC Compare Status (cleared on read) 4 1 read-only ETRGS External Trigger Status (cleared on read) 7 1 read-only LDRAS RA Loading Status (cleared on read) 5 1 read-only LDRBS RB Loading Status (cleared on read) 6 1 read-only LOVRS Load Overrun Status (cleared on read) 1 1 read-only MTIOA TIOAx Mirror 17 1 read-only MTIOB TIOBx Mirror 18 1 read-only WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 read-write WPKEY Write Protection Key 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 0x54494D TDES Triple Data Encryption Standard TDES 0x0 0x0 0x50 registers n TDES 14 CR Control Register 0x0 32 write-only n 0x0 0x0 START Start Processing 0 1 write-only SWRST Software Reset 8 1 write-only IDATAR0 Input Data Register 0x40 32 write-only n IDATA Input Data 0 32 write-only IDATAR1 Input Data Register 0x44 32 write-only n IDATA Input Data 0 32 write-only IDATAR[0] Input Data Register 0x80 32 write-only n 0x0 0x0 IDATA Input Data 0 32 write-only IDATAR[1] Input Data Register 0xC4 32 write-only n 0x0 0x0 IDATA Input Data 0 32 write-only IDR Interrupt Disable Register 0x14 32 write-only n 0x0 0x0 DATRDY Data Ready Interrupt Disable 0 1 write-only URAD Unspecified Register Access Detection Interrupt Disable 8 1 write-only IER Interrupt Enable Register 0x10 32 write-only n 0x0 0x0 DATRDY Data Ready Interrupt Enable 0 1 write-only URAD Unspecified Register Access Detection Interrupt Enable 8 1 write-only IMR Interrupt Mask Register 0x18 32 read-only n 0x0 0x0 DATRDY Data Ready Interrupt Mask 0 1 read-only URAD Unspecified Register Access Detection Interrupt Mask 8 1 read-only ISR Interrupt Status Register 0x1C 32 read-only n 0x0 0x0 DATRDY Data Ready (cleared by setting bit START or bit SWRST in TDES_CR or by reading TDES_ODATARx) 0 1 read-only URAD Unspecified Register Access Detection Status (cleared by setting bit TDES_CR.SWRST) 8 1 read-only URAT Unspecified Register Access (cleared by setting bit TDES_CR.SWRST) 12 2 read-only IDR_WR_PROCESSING Input Data Register written during data processing when SMOD = 0x2 mode. 0x0 ODR_RD_PROCESSING Output Data Register read during data processing. 0x1 MR_WR_PROCESSING Mode Register written during data processing. 0x2 WOR_RD_ACCESS Write-only register read access. 0x3 IVR0 Initialization Vector Register 0x60 32 write-only n IV Initialization Vector 0 32 write-only IVR1 Initialization Vector Register 0x64 32 write-only n IV Initialization Vector 0 32 write-only IVR[0] Initialization Vector Register 0xC0 32 write-only n 0x0 0x0 IV Initialization Vector 0 32 write-only IVR[1] Initialization Vector Register 0x124 32 write-only n 0x0 0x0 IV Initialization Vector 0 32 write-only KEY1WR0 Key 1 Word Register 0x20 32 write-only n KEY1W Key 1 Word 0 32 write-only KEY1WR1 Key 1 Word Register 0x24 32 write-only n KEY1W Key 1 Word 0 32 write-only KEY1WR[0] Key 1 Word Register 0x40 32 write-only n 0x0 0x0 KEY1W Key 1 Word 0 32 write-only KEY1WR[1] Key 1 Word Register 0x64 32 write-only n 0x0 0x0 KEY1W Key 1 Word 0 32 write-only KEY2WR0 Key 2 Word Register 0x28 32 write-only n KEY2W Key 2 Word 0 32 write-only KEY2WR1 Key 2 Word Register 0x2C 32 write-only n KEY2W Key 2 Word 0 32 write-only KEY2WR[0] Key 2 Word Register 0x50 32 write-only n 0x0 0x0 KEY2W Key 2 Word 0 32 write-only KEY2WR[1] Key 2 Word Register 0x7C 32 write-only n 0x0 0x0 KEY2W Key 2 Word 0 32 write-only KEY3WR0 Key 3 Word Register 0x30 32 write-only n KEY3W Key 3 Word 0 32 write-only KEY3WR1 Key 3 Word Register 0x34 32 write-only n KEY3W Key 3 Word 0 32 write-only KEY3WR[0] Key 3 Word Register 0x60 32 write-only n 0x0 0x0 KEY3W Key 3 Word 0 32 write-only KEY3WR[1] Key 3 Word Register 0x94 32 write-only n 0x0 0x0 KEY3W Key 3 Word 0 32 write-only MR Mode Register 0x4 32 read-write n 0x0 0x0 CFBS Cipher Feedback Data Size 16 2 read-write SIZE_64BIT 64-bit 0x0 SIZE_32BIT 32-bit 0x1 SIZE_16BIT 16-bit 0x2 SIZE_8BIT 8-bit 0x3 CIPHER Processing Mode 0 1 read-write DECRYPT Decrypts data. 0 ENCRYPT Encrypts data. 1 KEYMOD Key Mode 4 1 read-write LOD Last Output Data Mode 15 1 read-write OPMOD Operating Mode 12 2 read-write ECB Electronic Code Book mode 0x0 CBC Cipher Block Chaining mode 0x1 OFB Output Feedback mode 0x2 CFB Cipher Feedback mode 0x3 SMOD Start Mode 8 2 read-write MANUAL_START Manual Mode 0x0 AUTO_START Auto Mode 0x1 IDATAR0_START TDES_IDATAR0 accesses only Auto Mode 0x2 TDESMOD ALGORITHM Mode 1 2 read-write SINGLE_DES Single DES processing using TDES_KEY1WRx registers 0x0 TRIPLE_DES Triple DES processing using TDES_KEY1WRx, TDES_KEY2WRx and TDES_KEY3WRx registers 0x1 XTEA XTEA processing using TDES_KEY1WRx, TDES_KEY2WRx 0x2 ODATAR0 Output Data Register 0x50 32 read-only n ODATA Output Data 0 32 read-only ODATAR1 Output Data Register 0x54 32 read-only n ODATA Output Data 0 32 read-only ODATAR[0] Output Data Register 0xA0 32 read-only n 0x0 0x0 ODATA Output Data 0 32 read-only ODATAR[1] Output Data Register 0xF4 32 read-only n 0x0 0x0 ODATA Output Data 0 32 read-only XTEA_RNDR XTEA Rounds Register 0x70 32 read-write n 0x0 0x0 XTEA_RNDS Number of Rounds 0 6 read-write TRNG True Random Number Generator TRNG 0x0 0x0 0x50 registers n TRNG 53 CR Control Register 0x0 32 write-only n 0x0 0x0 ENABLE Enables the TRNG to Provide Random Values 0 1 write-only KEY Security Key 8 24 write-only PASSWD Writing any other value in this field aborts the write operation. 0x524E47 IDR Interrupt Disable Register 0x14 32 write-only n 0x0 0x0 DATRDY Data Ready Interrupt Disable 0 1 write-only IER Interrupt Enable Register 0x10 32 write-only n 0x0 0x0 DATRDY Data Ready Interrupt Enable 0 1 write-only IMR Interrupt Mask Register 0x18 32 read-only n 0x0 0x0 DATRDY Data Ready Interrupt Mask 0 1 read-only ISR Interrupt Status Register 0x1C 32 read-only n 0x0 0x0 DATRDY Data Ready 0 1 read-only ODATA Output Data Register 0x50 32 read-only n 0x0 0x0 ODATA Output Data 0 32 read-only TWI0 Two-wire Interface 0 TWI 0x0 0x0 0x50 registers n TWI0 32 CR Control Register 0x0 32 write-only n 0x0 0x0 MSDIS TWI Master Mode Disabled 3 1 write-only MSEN TWI Master Mode Enabled 2 1 write-only START Send a START Condition 0 1 write-only STOP Send a STOP Condition 1 1 write-only SVDIS TWI Slave Mode Disabled 5 1 write-only SVEN TWI Slave Mode Enabled 4 1 write-only SWRST Software Reset 7 1 write-only CWGR Clock Waveform Generator Register 0x10 32 read-write n 0x0 0x0 CHDIV Clock High Divider 8 8 read-write CKDIV Clock Divider 16 3 read-write CLDIV Clock Low Divider 0 8 read-write HOLD TWD Hold Time versus TWCK falling 24 5 read-write IADR Internal Address Register 0xC 32 read-write n 0x0 0x0 IADR Internal Address 0 24 read-write IDR Interrupt Disable Register 0x28 32 write-only n 0x0 0x0 ARBLST Arbitration Lost Interrupt Disable 9 1 write-only EOSACC End Of Slave Access Interrupt Disable 11 1 write-only GACC General Call Access Interrupt Disable 5 1 write-only NACK Not Acknowledge Interrupt Disable 8 1 write-only OVRE Overrun Error Interrupt Disable 6 1 write-only RXRDY Receive Holding Register Ready Interrupt Disable 1 1 write-only SCL_WS Clock Wait State Interrupt Disable 10 1 write-only SVACC Slave Access Interrupt Disable 4 1 write-only TXCOMP Transmission Completed Interrupt Disable 0 1 write-only TXRDY Transmit Holding Register Ready Interrupt Disable 2 1 write-only IER Interrupt Enable Register 0x24 32 write-only n 0x0 0x0 ARBLST Arbitration Lost Interrupt Enable 9 1 write-only EOSACC End Of Slave Access Interrupt Enable 11 1 write-only GACC General Call Access Interrupt Enable 5 1 write-only NACK Not Acknowledge Interrupt Enable 8 1 write-only OVRE Overrun Error Interrupt Enable 6 1 write-only RXRDY Receive Holding Register Ready Interrupt Enable 1 1 write-only SCL_WS Clock Wait State Interrupt Enable 10 1 write-only SVACC Slave Access Interrupt Enable 4 1 write-only TXCOMP Transmission Completed Interrupt Enable 0 1 write-only TXRDY Transmit Holding Register Ready Interrupt Enable 2 1 write-only IMR Interrupt Mask Register 0x2C 32 read-only n 0x0 0x0 ARBLST Arbitration Lost Interrupt Mask 9 1 read-only EOSACC End Of Slave Access Interrupt Mask 11 1 read-only GACC General Call Access Interrupt Mask 5 1 read-only NACK Not Acknowledge Interrupt Mask 8 1 read-only OVRE Overrun Error Interrupt Mask 6 1 read-only RXRDY Receive Holding Register Ready Interrupt Mask 1 1 read-only SCL_WS Clock Wait State Interrupt Mask 10 1 read-only SVACC Slave Access Interrupt Mask 4 1 read-only TXCOMP Transmission Completed Interrupt Mask 0 1 read-only TXRDY Transmit Holding Register Ready Interrupt Mask 2 1 read-only MMR Master Mode Register 0x4 32 read-write n 0x0 0x0 DADR Device Address 16 7 read-write IADRSZ Internal Device Address Size 8 2 read-write NONE No internal device address 0x0 1_BYTE One-byte internal device address 0x1 2_BYTE Two-byte internal device address 0x2 3_BYTE Three-byte internal device address 0x3 MREAD Master Read Direction 12 1 read-write RHR Receive Holding Register 0x30 32 read-only n 0x0 0x0 RXDATA Master or Slave Receive Holding Data 0 8 read-only SMR Slave Mode Register 0x8 32 read-write n 0x0 0x0 SADR Slave Address 16 7 read-write SR Status Register 0x20 32 read-only n 0x0 0x0 ARBLST Arbitration Lost (cleared on read) 9 1 read-only EOSACC End Of Slave Access (cleared on read) 11 1 read-only GACC General Call Access (cleared on read) 5 1 read-only NACK Not Acknowledged (cleared on read) 8 1 read-only OVRE Overrun Error (cleared on read) 6 1 read-only RXRDY Receive Holding Register Ready (cleared by reading TWI_RHR) 1 1 read-only SCLWS Clock Wait State 10 1 read-only SVACC Slave Access 4 1 read-only SVREAD Slave Read 3 1 read-only TXCOMP Transmission Completed (cleared by writing TWI_THR) 0 1 read-only TXRDY Transmit Holding Register Ready (cleared by writing TWI_THR) 2 1 read-only THR Transmit Holding Register 0x34 32 write-only n 0x0 0x0 TXDATA Master or Slave Transmit Holding Data 0 8 write-only WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 read-write WPKEY Write Protection Key 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 0x545749 WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 read-only WPVSRC Write Protection Violation Source 8 24 read-only TWI1 Two-wire Interface 1 TWI 0x0 0x0 0x50 registers n TWI1 33 CR Control Register 0x0 32 write-only n 0x0 0x0 MSDIS TWI Master Mode Disabled 3 1 write-only MSEN TWI Master Mode Enabled 2 1 write-only START Send a START Condition 0 1 write-only STOP Send a STOP Condition 1 1 write-only SVDIS TWI Slave Mode Disabled 5 1 write-only SVEN TWI Slave Mode Enabled 4 1 write-only SWRST Software Reset 7 1 write-only CWGR Clock Waveform Generator Register 0x10 32 read-write n 0x0 0x0 CHDIV Clock High Divider 8 8 read-write CKDIV Clock Divider 16 3 read-write CLDIV Clock Low Divider 0 8 read-write HOLD TWD Hold Time versus TWCK falling 24 5 read-write IADR Internal Address Register 0xC 32 read-write n 0x0 0x0 IADR Internal Address 0 24 read-write IDR Interrupt Disable Register 0x28 32 write-only n 0x0 0x0 ARBLST Arbitration Lost Interrupt Disable 9 1 write-only EOSACC End Of Slave Access Interrupt Disable 11 1 write-only GACC General Call Access Interrupt Disable 5 1 write-only NACK Not Acknowledge Interrupt Disable 8 1 write-only OVRE Overrun Error Interrupt Disable 6 1 write-only RXRDY Receive Holding Register Ready Interrupt Disable 1 1 write-only SCL_WS Clock Wait State Interrupt Disable 10 1 write-only SVACC Slave Access Interrupt Disable 4 1 write-only TXCOMP Transmission Completed Interrupt Disable 0 1 write-only TXRDY Transmit Holding Register Ready Interrupt Disable 2 1 write-only IER Interrupt Enable Register 0x24 32 write-only n 0x0 0x0 ARBLST Arbitration Lost Interrupt Enable 9 1 write-only EOSACC End Of Slave Access Interrupt Enable 11 1 write-only GACC General Call Access Interrupt Enable 5 1 write-only NACK Not Acknowledge Interrupt Enable 8 1 write-only OVRE Overrun Error Interrupt Enable 6 1 write-only RXRDY Receive Holding Register Ready Interrupt Enable 1 1 write-only SCL_WS Clock Wait State Interrupt Enable 10 1 write-only SVACC Slave Access Interrupt Enable 4 1 write-only TXCOMP Transmission Completed Interrupt Enable 0 1 write-only TXRDY Transmit Holding Register Ready Interrupt Enable 2 1 write-only IMR Interrupt Mask Register 0x2C 32 read-only n 0x0 0x0 ARBLST Arbitration Lost Interrupt Mask 9 1 read-only EOSACC End Of Slave Access Interrupt Mask 11 1 read-only GACC General Call Access Interrupt Mask 5 1 read-only NACK Not Acknowledge Interrupt Mask 8 1 read-only OVRE Overrun Error Interrupt Mask 6 1 read-only RXRDY Receive Holding Register Ready Interrupt Mask 1 1 read-only SCL_WS Clock Wait State Interrupt Mask 10 1 read-only SVACC Slave Access Interrupt Mask 4 1 read-only TXCOMP Transmission Completed Interrupt Mask 0 1 read-only TXRDY Transmit Holding Register Ready Interrupt Mask 2 1 read-only MMR Master Mode Register 0x4 32 read-write n 0x0 0x0 DADR Device Address 16 7 read-write IADRSZ Internal Device Address Size 8 2 read-write NONE No internal device address 0x0 1_BYTE One-byte internal device address 0x1 2_BYTE Two-byte internal device address 0x2 3_BYTE Three-byte internal device address 0x3 MREAD Master Read Direction 12 1 read-write RHR Receive Holding Register 0x30 32 read-only n 0x0 0x0 RXDATA Master or Slave Receive Holding Data 0 8 read-only SMR Slave Mode Register 0x8 32 read-write n 0x0 0x0 SADR Slave Address 16 7 read-write SR Status Register 0x20 32 read-only n 0x0 0x0 ARBLST Arbitration Lost (cleared on read) 9 1 read-only EOSACC End Of Slave Access (cleared on read) 11 1 read-only GACC General Call Access (cleared on read) 5 1 read-only NACK Not Acknowledged (cleared on read) 8 1 read-only OVRE Overrun Error (cleared on read) 6 1 read-only RXRDY Receive Holding Register Ready (cleared by reading TWI_RHR) 1 1 read-only SCLWS Clock Wait State 10 1 read-only SVACC Slave Access 4 1 read-only SVREAD Slave Read 3 1 read-only TXCOMP Transmission Completed (cleared by writing TWI_THR) 0 1 read-only TXRDY Transmit Holding Register Ready (cleared by writing TWI_THR) 2 1 read-only THR Transmit Holding Register 0x34 32 write-only n 0x0 0x0 TXDATA Master or Slave Transmit Holding Data 0 8 write-only WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 read-write WPKEY Write Protection Key 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 0x545749 WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 read-only WPVSRC Write Protection Violation Source 8 24 read-only TWI2 Two-wire Interface 2 TWI 0x0 0x0 0x50 registers n TWI2 34 CR Control Register 0x0 32 write-only n 0x0 0x0 MSDIS TWI Master Mode Disabled 3 1 write-only MSEN TWI Master Mode Enabled 2 1 write-only START Send a START Condition 0 1 write-only STOP Send a STOP Condition 1 1 write-only SVDIS TWI Slave Mode Disabled 5 1 write-only SVEN TWI Slave Mode Enabled 4 1 write-only SWRST Software Reset 7 1 write-only CWGR Clock Waveform Generator Register 0x10 32 read-write n 0x0 0x0 CHDIV Clock High Divider 8 8 read-write CKDIV Clock Divider 16 3 read-write CLDIV Clock Low Divider 0 8 read-write HOLD TWD Hold Time versus TWCK falling 24 5 read-write IADR Internal Address Register 0xC 32 read-write n 0x0 0x0 IADR Internal Address 0 24 read-write IDR Interrupt Disable Register 0x28 32 write-only n 0x0 0x0 ARBLST Arbitration Lost Interrupt Disable 9 1 write-only EOSACC End Of Slave Access Interrupt Disable 11 1 write-only GACC General Call Access Interrupt Disable 5 1 write-only NACK Not Acknowledge Interrupt Disable 8 1 write-only OVRE Overrun Error Interrupt Disable 6 1 write-only RXRDY Receive Holding Register Ready Interrupt Disable 1 1 write-only SCL_WS Clock Wait State Interrupt Disable 10 1 write-only SVACC Slave Access Interrupt Disable 4 1 write-only TXCOMP Transmission Completed Interrupt Disable 0 1 write-only TXRDY Transmit Holding Register Ready Interrupt Disable 2 1 write-only IER Interrupt Enable Register 0x24 32 write-only n 0x0 0x0 ARBLST Arbitration Lost Interrupt Enable 9 1 write-only EOSACC End Of Slave Access Interrupt Enable 11 1 write-only GACC General Call Access Interrupt Enable 5 1 write-only NACK Not Acknowledge Interrupt Enable 8 1 write-only OVRE Overrun Error Interrupt Enable 6 1 write-only RXRDY Receive Holding Register Ready Interrupt Enable 1 1 write-only SCL_WS Clock Wait State Interrupt Enable 10 1 write-only SVACC Slave Access Interrupt Enable 4 1 write-only TXCOMP Transmission Completed Interrupt Enable 0 1 write-only TXRDY Transmit Holding Register Ready Interrupt Enable 2 1 write-only IMR Interrupt Mask Register 0x2C 32 read-only n 0x0 0x0 ARBLST Arbitration Lost Interrupt Mask 9 1 read-only EOSACC End Of Slave Access Interrupt Mask 11 1 read-only GACC General Call Access Interrupt Mask 5 1 read-only NACK Not Acknowledge Interrupt Mask 8 1 read-only OVRE Overrun Error Interrupt Mask 6 1 read-only RXRDY Receive Holding Register Ready Interrupt Mask 1 1 read-only SCL_WS Clock Wait State Interrupt Mask 10 1 read-only SVACC Slave Access Interrupt Mask 4 1 read-only TXCOMP Transmission Completed Interrupt Mask 0 1 read-only TXRDY Transmit Holding Register Ready Interrupt Mask 2 1 read-only MMR Master Mode Register 0x4 32 read-write n 0x0 0x0 DADR Device Address 16 7 read-write IADRSZ Internal Device Address Size 8 2 read-write NONE No internal device address 0x0 1_BYTE One-byte internal device address 0x1 2_BYTE Two-byte internal device address 0x2 3_BYTE Three-byte internal device address 0x3 MREAD Master Read Direction 12 1 read-write RHR Receive Holding Register 0x30 32 read-only n 0x0 0x0 RXDATA Master or Slave Receive Holding Data 0 8 read-only SMR Slave Mode Register 0x8 32 read-write n 0x0 0x0 SADR Slave Address 16 7 read-write SR Status Register 0x20 32 read-only n 0x0 0x0 ARBLST Arbitration Lost (cleared on read) 9 1 read-only EOSACC End Of Slave Access (cleared on read) 11 1 read-only GACC General Call Access (cleared on read) 5 1 read-only NACK Not Acknowledged (cleared on read) 8 1 read-only OVRE Overrun Error (cleared on read) 6 1 read-only RXRDY Receive Holding Register Ready (cleared by reading TWI_RHR) 1 1 read-only SCLWS Clock Wait State 10 1 read-only SVACC Slave Access 4 1 read-only SVREAD Slave Read 3 1 read-only TXCOMP Transmission Completed (cleared by writing TWI_THR) 0 1 read-only TXRDY Transmit Holding Register Ready (cleared by writing TWI_THR) 2 1 read-only THR Transmit Holding Register 0x34 32 write-only n 0x0 0x0 TXDATA Master or Slave Transmit Holding Data 0 8 write-only WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 read-write WPKEY Write Protection Key 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 0x545749 WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 read-only WPVSRC Write Protection Violation Source 8 24 read-only TWI3 Two-wire Interface 3 TWI 0x0 0x0 0x50 registers n TWI3 62 CR Control Register 0x0 32 write-only n 0x0 0x0 MSDIS TWI Master Mode Disabled 3 1 write-only MSEN TWI Master Mode Enabled 2 1 write-only START Send a START Condition 0 1 write-only STOP Send a STOP Condition 1 1 write-only SVDIS TWI Slave Mode Disabled 5 1 write-only SVEN TWI Slave Mode Enabled 4 1 write-only SWRST Software Reset 7 1 write-only CWGR Clock Waveform Generator Register 0x10 32 read-write n 0x0 0x0 CHDIV Clock High Divider 8 8 read-write CKDIV Clock Divider 16 3 read-write CLDIV Clock Low Divider 0 8 read-write HOLD TWD Hold Time versus TWCK falling 24 5 read-write IADR Internal Address Register 0xC 32 read-write n 0x0 0x0 IADR Internal Address 0 24 read-write IDR Interrupt Disable Register 0x28 32 write-only n 0x0 0x0 ARBLST Arbitration Lost Interrupt Disable 9 1 write-only EOSACC End Of Slave Access Interrupt Disable 11 1 write-only GACC General Call Access Interrupt Disable 5 1 write-only NACK Not Acknowledge Interrupt Disable 8 1 write-only OVRE Overrun Error Interrupt Disable 6 1 write-only RXRDY Receive Holding Register Ready Interrupt Disable 1 1 write-only SCL_WS Clock Wait State Interrupt Disable 10 1 write-only SVACC Slave Access Interrupt Disable 4 1 write-only TXCOMP Transmission Completed Interrupt Disable 0 1 write-only TXRDY Transmit Holding Register Ready Interrupt Disable 2 1 write-only IER Interrupt Enable Register 0x24 32 write-only n 0x0 0x0 ARBLST Arbitration Lost Interrupt Enable 9 1 write-only EOSACC End Of Slave Access Interrupt Enable 11 1 write-only GACC General Call Access Interrupt Enable 5 1 write-only NACK Not Acknowledge Interrupt Enable 8 1 write-only OVRE Overrun Error Interrupt Enable 6 1 write-only RXRDY Receive Holding Register Ready Interrupt Enable 1 1 write-only SCL_WS Clock Wait State Interrupt Enable 10 1 write-only SVACC Slave Access Interrupt Enable 4 1 write-only TXCOMP Transmission Completed Interrupt Enable 0 1 write-only TXRDY Transmit Holding Register Ready Interrupt Enable 2 1 write-only IMR Interrupt Mask Register 0x2C 32 read-only n 0x0 0x0 ARBLST Arbitration Lost Interrupt Mask 9 1 read-only EOSACC End Of Slave Access Interrupt Mask 11 1 read-only GACC General Call Access Interrupt Mask 5 1 read-only NACK Not Acknowledge Interrupt Mask 8 1 read-only OVRE Overrun Error Interrupt Mask 6 1 read-only RXRDY Receive Holding Register Ready Interrupt Mask 1 1 read-only SCL_WS Clock Wait State Interrupt Mask 10 1 read-only SVACC Slave Access Interrupt Mask 4 1 read-only TXCOMP Transmission Completed Interrupt Mask 0 1 read-only TXRDY Transmit Holding Register Ready Interrupt Mask 2 1 read-only MMR Master Mode Register 0x4 32 read-write n 0x0 0x0 DADR Device Address 16 7 read-write IADRSZ Internal Device Address Size 8 2 read-write NONE No internal device address 0x0 1_BYTE One-byte internal device address 0x1 2_BYTE Two-byte internal device address 0x2 3_BYTE Three-byte internal device address 0x3 MREAD Master Read Direction 12 1 read-write RHR Receive Holding Register 0x30 32 read-only n 0x0 0x0 RXDATA Master or Slave Receive Holding Data 0 8 read-only SMR Slave Mode Register 0x8 32 read-write n 0x0 0x0 SADR Slave Address 16 7 read-write SR Status Register 0x20 32 read-only n 0x0 0x0 ARBLST Arbitration Lost (cleared on read) 9 1 read-only EOSACC End Of Slave Access (cleared on read) 11 1 read-only GACC General Call Access (cleared on read) 5 1 read-only NACK Not Acknowledged (cleared on read) 8 1 read-only OVRE Overrun Error (cleared on read) 6 1 read-only RXRDY Receive Holding Register Ready (cleared by reading TWI_RHR) 1 1 read-only SCLWS Clock Wait State 10 1 read-only SVACC Slave Access 4 1 read-only SVREAD Slave Read 3 1 read-only TXCOMP Transmission Completed (cleared by writing TWI_THR) 0 1 read-only TXRDY Transmit Holding Register Ready (cleared by writing TWI_THR) 2 1 read-only THR Transmit Holding Register 0x34 32 write-only n 0x0 0x0 TXDATA Master or Slave Transmit Holding Data 0 8 write-only WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 read-write WPKEY Write Protection Key 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 0x545749 WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 read-only WPVSRC Write Protection Violation Source 8 24 read-only UART0 Universal Asynchronous Receiver Transmitter 0 UART 0x0 0x0 0x50 registers n UART0 27 BRGR Baud Rate Generator Register 0x20 32 read-write n 0x0 0x0 CD Clock Divisor 0 16 read-write CR Control Register 0x0 32 write-only n 0x0 0x0 RSTRX Reset Receiver 2 1 write-only RSTSTA Reset Status 8 1 write-only RSTTX Reset Transmitter 3 1 write-only RXDIS Receiver Disable 5 1 write-only RXEN Receiver Enable 4 1 write-only TXDIS Transmitter Disable 7 1 write-only TXEN Transmitter Enable 6 1 write-only IDR Interrupt Disable Register 0xC 32 write-only n 0x0 0x0 FRAME Disable Framing Error Interrupt 6 1 write-only OVRE Disable Overrun Error Interrupt 5 1 write-only PARE Disable Parity Error Interrupt 7 1 write-only RXRDY Disable RXRDY Interrupt 0 1 write-only TXEMPTY Disable TXEMPTY Interrupt 9 1 write-only TXRDY Disable TXRDY Interrupt 1 1 write-only IER Interrupt Enable Register 0x8 32 write-only n 0x0 0x0 FRAME Enable Framing Error Interrupt 6 1 write-only OVRE Enable Overrun Error Interrupt 5 1 write-only PARE Enable Parity Error Interrupt 7 1 write-only RXRDY Enable RXRDY Interrupt 0 1 write-only TXEMPTY Enable TXEMPTY Interrupt 9 1 write-only TXRDY Enable TXRDY Interrupt 1 1 write-only IMR Interrupt Mask Register 0x10 32 read-only n 0x0 0x0 FRAME Mask Framing Error Interrupt 6 1 read-only OVRE Mask Overrun Error Interrupt 5 1 read-only PARE Mask Parity Error Interrupt 7 1 read-only RXRDY Mask RXRDY Interrupt 0 1 read-only TXEMPTY Mask TXEMPTY Interrupt 9 1 read-only TXRDY Disable TXRDY Interrupt 1 1 read-only MR Mode Register 0x4 32 read-write n 0x0 0x0 CHMODE Channel Mode 14 2 read-write NORMAL Normal mode 0x0 AUTOMATIC Automatic echo 0x1 LOCAL_LOOPBACK Local loopback 0x2 REMOTE_LOOPBACK Remote loopback 0x3 PAR Parity Type 9 3 read-write EVEN Even Parity 0x0 ODD Odd Parity 0x1 SPACE Space: parity forced to 0 0x2 MARK Mark: parity forced to 1 0x3 NO No parity 0x4 RHR Receive Holding Register 0x18 32 read-only n 0x0 0x0 RXCHR Received Character 0 8 read-only SR Status Register 0x14 32 read-only n 0x0 0x0 FRAME Framing Error 6 1 read-only OVRE Overrun Error 5 1 read-only PARE Parity Error 7 1 read-only RXRDY Receiver Ready 0 1 read-only TXEMPTY Transmitter Empty 9 1 read-only TXRDY Transmitter Ready 1 1 read-only THR Transmit Holding Register 0x1C 32 write-only n 0x0 0x0 TXCHR Character to be Transmitted 0 8 write-only WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 read-write WPKEY Write Protection Key 8 24 read-write PASSWD Writing any other value in this field aborts the write operation.Always reads as 0. 0x554152 UART1 Universal Asynchronous Receiver Transmitter 1 UART 0x0 0x0 0x50 registers n UART1 28 BRGR Baud Rate Generator Register 0x20 32 read-write n 0x0 0x0 CD Clock Divisor 0 16 read-write CR Control Register 0x0 32 write-only n 0x0 0x0 RSTRX Reset Receiver 2 1 write-only RSTSTA Reset Status 8 1 write-only RSTTX Reset Transmitter 3 1 write-only RXDIS Receiver Disable 5 1 write-only RXEN Receiver Enable 4 1 write-only TXDIS Transmitter Disable 7 1 write-only TXEN Transmitter Enable 6 1 write-only IDR Interrupt Disable Register 0xC 32 write-only n 0x0 0x0 FRAME Disable Framing Error Interrupt 6 1 write-only OVRE Disable Overrun Error Interrupt 5 1 write-only PARE Disable Parity Error Interrupt 7 1 write-only RXRDY Disable RXRDY Interrupt 0 1 write-only TXEMPTY Disable TXEMPTY Interrupt 9 1 write-only TXRDY Disable TXRDY Interrupt 1 1 write-only IER Interrupt Enable Register 0x8 32 write-only n 0x0 0x0 FRAME Enable Framing Error Interrupt 6 1 write-only OVRE Enable Overrun Error Interrupt 5 1 write-only PARE Enable Parity Error Interrupt 7 1 write-only RXRDY Enable RXRDY Interrupt 0 1 write-only TXEMPTY Enable TXEMPTY Interrupt 9 1 write-only TXRDY Enable TXRDY Interrupt 1 1 write-only IMR Interrupt Mask Register 0x10 32 read-only n 0x0 0x0 FRAME Mask Framing Error Interrupt 6 1 read-only OVRE Mask Overrun Error Interrupt 5 1 read-only PARE Mask Parity Error Interrupt 7 1 read-only RXRDY Mask RXRDY Interrupt 0 1 read-only TXEMPTY Mask TXEMPTY Interrupt 9 1 read-only TXRDY Disable TXRDY Interrupt 1 1 read-only MR Mode Register 0x4 32 read-write n 0x0 0x0 CHMODE Channel Mode 14 2 read-write NORMAL Normal mode 0x0 AUTOMATIC Automatic echo 0x1 LOCAL_LOOPBACK Local loopback 0x2 REMOTE_LOOPBACK Remote loopback 0x3 PAR Parity Type 9 3 read-write EVEN Even Parity 0x0 ODD Odd Parity 0x1 SPACE Space: parity forced to 0 0x2 MARK Mark: parity forced to 1 0x3 NO No parity 0x4 RHR Receive Holding Register 0x18 32 read-only n 0x0 0x0 RXCHR Received Character 0 8 read-only SR Status Register 0x14 32 read-only n 0x0 0x0 FRAME Framing Error 6 1 read-only OVRE Overrun Error 5 1 read-only PARE Parity Error 7 1 read-only RXRDY Receiver Ready 0 1 read-only TXEMPTY Transmitter Empty 9 1 read-only TXRDY Transmitter Ready 1 1 read-only THR Transmit Holding Register 0x1C 32 write-only n 0x0 0x0 TXCHR Character to be Transmitted 0 8 write-only WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 read-write WPKEY Write Protection Key 8 24 read-write PASSWD Writing any other value in this field aborts the write operation.Always reads as 0. 0x554152 UDPHS USB High Speed Device Port UDPHS 0x0 0x0 0x50 registers n UDPHS 47 CLRINT UDPHS Clear Interrupt Register 0x18 32 write-only n 0x0 0x0 DET_SUSPD Suspend Interrupt Clear 1 1 write-only ENDOFRSM End Of Resume Interrupt Clear 6 1 write-only ENDRESET End Of Reset Interrupt Clear 4 1 write-only INT_SOF Start Of Frame Interrupt Clear 3 1 write-only MICRO_SOF Micro Start Of Frame Interrupt Clear 2 1 write-only UPSTR_RES Upstream Resume Interrupt Clear 7 1 write-only WAKE_UP Wake Up CPU Interrupt Clear 5 1 write-only CTRL UDPHS Control Register 0x0 32 read-write n 0x0 0x0 DETACH Detach Command 9 1 read-write DEV_ADDR UDPHS Address (cleared upon USB reset) 0 7 read-write EN_UDPHS UDPHS Enable 8 1 read-write FADDR_EN Function Address Enable (cleared upon USB reset) 7 1 read-write PULLD_DIS Pull-Down Disable (cleared upon USB reset) 11 1 read-write REWAKEUP Send Remote Wake Up (cleared upon USB reset) 10 1 read-write DMAADDRESS0 UDPHS DMA Channel Address Register (channel = 0) 0x304 32 read-write n 0x0 0x0 BUFF_ADD Buffer Address 0 32 read-write DMAADDRESS1 UDPHS DMA Channel Address Register (channel = 1) 0x314 32 read-write n 0x0 0x0 BUFF_ADD Buffer Address 0 32 read-write DMAADDRESS2 UDPHS DMA Channel Address Register (channel = 2) 0x324 32 read-write n 0x0 0x0 BUFF_ADD Buffer Address 0 32 read-write DMAADDRESS3 UDPHS DMA Channel Address Register (channel = 3) 0x334 32 read-write n 0x0 0x0 BUFF_ADD Buffer Address 0 32 read-write DMAADDRESS4 UDPHS DMA Channel Address Register (channel = 4) 0x344 32 read-write n 0x0 0x0 BUFF_ADD Buffer Address 0 32 read-write DMAADDRESS5 UDPHS DMA Channel Address Register (channel = 5) 0x354 32 read-write n 0x0 0x0 BUFF_ADD Buffer Address 0 32 read-write DMAADDRESS6 UDPHS DMA Channel Address Register (channel = 6) 0x364 32 read-write n 0x0 0x0 BUFF_ADD Buffer Address 0 32 read-write DMACONTROL0 UDPHS DMA Channel Control Register (channel = 0) 0x308 32 read-write n 0x0 0x0 BUFF_LENGTH Buffer Byte Length (Write-only) 16 16 read-write BURST_LCK Burst Lock Enable 7 1 read-write CHANN_ENB (Channel Enable Command) 0 1 read-write DESC_LD_IT Descriptor Loaded Interrupt Enable 6 1 read-write END_BUFFIT End of Buffer Interrupt Enable 5 1 read-write END_B_EN End of Buffer Enable (Control) 3 1 read-write END_TR_EN End of Transfer Enable (Control) 2 1 read-write END_TR_IT End of Transfer Interrupt Enable 4 1 read-write LDNXT_DSC Load Next Channel Transfer Descriptor Enable (Command) 1 1 read-write DMACONTROL1 UDPHS DMA Channel Control Register (channel = 1) 0x318 32 read-write n 0x0 0x0 BUFF_LENGTH Buffer Byte Length (Write-only) 16 16 read-write BURST_LCK Burst Lock Enable 7 1 read-write CHANN_ENB (Channel Enable Command) 0 1 read-write DESC_LD_IT Descriptor Loaded Interrupt Enable 6 1 read-write END_BUFFIT End of Buffer Interrupt Enable 5 1 read-write END_B_EN End of Buffer Enable (Control) 3 1 read-write END_TR_EN End of Transfer Enable (Control) 2 1 read-write END_TR_IT End of Transfer Interrupt Enable 4 1 read-write LDNXT_DSC Load Next Channel Transfer Descriptor Enable (Command) 1 1 read-write DMACONTROL2 UDPHS DMA Channel Control Register (channel = 2) 0x328 32 read-write n 0x0 0x0 BUFF_LENGTH Buffer Byte Length (Write-only) 16 16 read-write BURST_LCK Burst Lock Enable 7 1 read-write CHANN_ENB (Channel Enable Command) 0 1 read-write DESC_LD_IT Descriptor Loaded Interrupt Enable 6 1 read-write END_BUFFIT End of Buffer Interrupt Enable 5 1 read-write END_B_EN End of Buffer Enable (Control) 3 1 read-write END_TR_EN End of Transfer Enable (Control) 2 1 read-write END_TR_IT End of Transfer Interrupt Enable 4 1 read-write LDNXT_DSC Load Next Channel Transfer Descriptor Enable (Command) 1 1 read-write DMACONTROL3 UDPHS DMA Channel Control Register (channel = 3) 0x338 32 read-write n 0x0 0x0 BUFF_LENGTH Buffer Byte Length (Write-only) 16 16 read-write BURST_LCK Burst Lock Enable 7 1 read-write CHANN_ENB (Channel Enable Command) 0 1 read-write DESC_LD_IT Descriptor Loaded Interrupt Enable 6 1 read-write END_BUFFIT End of Buffer Interrupt Enable 5 1 read-write END_B_EN End of Buffer Enable (Control) 3 1 read-write END_TR_EN End of Transfer Enable (Control) 2 1 read-write END_TR_IT End of Transfer Interrupt Enable 4 1 read-write LDNXT_DSC Load Next Channel Transfer Descriptor Enable (Command) 1 1 read-write DMACONTROL4 UDPHS DMA Channel Control Register (channel = 4) 0x348 32 read-write n 0x0 0x0 BUFF_LENGTH Buffer Byte Length (Write-only) 16 16 read-write BURST_LCK Burst Lock Enable 7 1 read-write CHANN_ENB (Channel Enable Command) 0 1 read-write DESC_LD_IT Descriptor Loaded Interrupt Enable 6 1 read-write END_BUFFIT End of Buffer Interrupt Enable 5 1 read-write END_B_EN End of Buffer Enable (Control) 3 1 read-write END_TR_EN End of Transfer Enable (Control) 2 1 read-write END_TR_IT End of Transfer Interrupt Enable 4 1 read-write LDNXT_DSC Load Next Channel Transfer Descriptor Enable (Command) 1 1 read-write DMACONTROL5 UDPHS DMA Channel Control Register (channel = 5) 0x358 32 read-write n 0x0 0x0 BUFF_LENGTH Buffer Byte Length (Write-only) 16 16 read-write BURST_LCK Burst Lock Enable 7 1 read-write CHANN_ENB (Channel Enable Command) 0 1 read-write DESC_LD_IT Descriptor Loaded Interrupt Enable 6 1 read-write END_BUFFIT End of Buffer Interrupt Enable 5 1 read-write END_B_EN End of Buffer Enable (Control) 3 1 read-write END_TR_EN End of Transfer Enable (Control) 2 1 read-write END_TR_IT End of Transfer Interrupt Enable 4 1 read-write LDNXT_DSC Load Next Channel Transfer Descriptor Enable (Command) 1 1 read-write DMACONTROL6 UDPHS DMA Channel Control Register (channel = 6) 0x368 32 read-write n 0x0 0x0 BUFF_LENGTH Buffer Byte Length (Write-only) 16 16 read-write BURST_LCK Burst Lock Enable 7 1 read-write CHANN_ENB (Channel Enable Command) 0 1 read-write DESC_LD_IT Descriptor Loaded Interrupt Enable 6 1 read-write END_BUFFIT End of Buffer Interrupt Enable 5 1 read-write END_B_EN End of Buffer Enable (Control) 3 1 read-write END_TR_EN End of Transfer Enable (Control) 2 1 read-write END_TR_IT End of Transfer Interrupt Enable 4 1 read-write LDNXT_DSC Load Next Channel Transfer Descriptor Enable (Command) 1 1 read-write DMANXTDSC0 UDPHS DMA Next Descriptor Address Register (channel = 0) 0x300 32 read-write n 0x0 0x0 NXT_DSC_ADD Next Descriptor Address 0 32 read-write DMANXTDSC1 UDPHS DMA Next Descriptor Address Register (channel = 1) 0x310 32 read-write n 0x0 0x0 NXT_DSC_ADD Next Descriptor Address 0 32 read-write DMANXTDSC2 UDPHS DMA Next Descriptor Address Register (channel = 2) 0x320 32 read-write n 0x0 0x0 NXT_DSC_ADD Next Descriptor Address 0 32 read-write DMANXTDSC3 UDPHS DMA Next Descriptor Address Register (channel = 3) 0x330 32 read-write n 0x0 0x0 NXT_DSC_ADD Next Descriptor Address 0 32 read-write DMANXTDSC4 UDPHS DMA Next Descriptor Address Register (channel = 4) 0x340 32 read-write n 0x0 0x0 NXT_DSC_ADD Next Descriptor Address 0 32 read-write DMANXTDSC5 UDPHS DMA Next Descriptor Address Register (channel = 5) 0x350 32 read-write n 0x0 0x0 NXT_DSC_ADD Next Descriptor Address 0 32 read-write DMANXTDSC6 UDPHS DMA Next Descriptor Address Register (channel = 6) 0x360 32 read-write n 0x0 0x0 NXT_DSC_ADD Next Descriptor Address 0 32 read-write DMASTATUS0 UDPHS DMA Channel Status Register (channel = 0) 0x30C 32 read-write n 0x0 0x0 BUFF_COUNT Buffer Byte Count 16 16 read-write CHANN_ACT Channel Active Status 1 1 read-write CHANN_ENB Channel Enable Status 0 1 read-write DESC_LDST Descriptor Loaded Status 6 1 read-write END_BF_ST End of Channel Buffer Status 5 1 read-write END_TR_ST End of Channel Transfer Status 4 1 read-write DMASTATUS1 UDPHS DMA Channel Status Register (channel = 1) 0x31C 32 read-write n 0x0 0x0 BUFF_COUNT Buffer Byte Count 16 16 read-write CHANN_ACT Channel Active Status 1 1 read-write CHANN_ENB Channel Enable Status 0 1 read-write DESC_LDST Descriptor Loaded Status 6 1 read-write END_BF_ST End of Channel Buffer Status 5 1 read-write END_TR_ST End of Channel Transfer Status 4 1 read-write DMASTATUS2 UDPHS DMA Channel Status Register (channel = 2) 0x32C 32 read-write n 0x0 0x0 BUFF_COUNT Buffer Byte Count 16 16 read-write CHANN_ACT Channel Active Status 1 1 read-write CHANN_ENB Channel Enable Status 0 1 read-write DESC_LDST Descriptor Loaded Status 6 1 read-write END_BF_ST End of Channel Buffer Status 5 1 read-write END_TR_ST End of Channel Transfer Status 4 1 read-write DMASTATUS3 UDPHS DMA Channel Status Register (channel = 3) 0x33C 32 read-write n 0x0 0x0 BUFF_COUNT Buffer Byte Count 16 16 read-write CHANN_ACT Channel Active Status 1 1 read-write CHANN_ENB Channel Enable Status 0 1 read-write DESC_LDST Descriptor Loaded Status 6 1 read-write END_BF_ST End of Channel Buffer Status 5 1 read-write END_TR_ST End of Channel Transfer Status 4 1 read-write DMASTATUS4 UDPHS DMA Channel Status Register (channel = 4) 0x34C 32 read-write n 0x0 0x0 BUFF_COUNT Buffer Byte Count 16 16 read-write CHANN_ACT Channel Active Status 1 1 read-write CHANN_ENB Channel Enable Status 0 1 read-write DESC_LDST Descriptor Loaded Status 6 1 read-write END_BF_ST End of Channel Buffer Status 5 1 read-write END_TR_ST End of Channel Transfer Status 4 1 read-write DMASTATUS5 UDPHS DMA Channel Status Register (channel = 5) 0x35C 32 read-write n 0x0 0x0 BUFF_COUNT Buffer Byte Count 16 16 read-write CHANN_ACT Channel Active Status 1 1 read-write CHANN_ENB Channel Enable Status 0 1 read-write DESC_LDST Descriptor Loaded Status 6 1 read-write END_BF_ST End of Channel Buffer Status 5 1 read-write END_TR_ST End of Channel Transfer Status 4 1 read-write DMASTATUS6 UDPHS DMA Channel Status Register (channel = 6) 0x36C 32 read-write n 0x0 0x0 BUFF_COUNT Buffer Byte Count 16 16 read-write CHANN_ACT Channel Active Status 1 1 read-write CHANN_ENB Channel Enable Status 0 1 read-write DESC_LDST Descriptor Loaded Status 6 1 read-write END_BF_ST End of Channel Buffer Status 5 1 read-write END_TR_ST End of Channel Transfer Status 4 1 read-write EPTCFG0 UDPHS Endpoint Configuration Register (endpoint = 0) 0x100 32 read-write n 0x0 0x0 BK_NUMBER Number of Banks (cleared upon USB reset) 6 2 read-write 0 Zero bank, the endpoint is not mapped in memory 0x0 1 One bank (bank 0) 0x1 2 Double bank (Ping-Pong: bank0/bank1) 0x2 3 Triple bank (bank0/bank1/bank2) 0x3 EPT_DIR Endpoint Direction (cleared upon USB reset) 3 1 read-write EPT_MAPD Endpoint Mapped (cleared upon USB reset) 31 1 read-write EPT_SIZE Endpoint Size (cleared upon USB reset) 0 3 read-write 8 8 bytes 0x0 16 16 bytes 0x1 32 32 bytes 0x2 64 64 bytes 0x3 128 128 bytes 0x4 256 256 bytes 0x5 512 512 bytes 0x6 1024 1024 bytes 0x7 EPT_TYPE Endpoint Type (cleared upon USB reset) 4 2 read-write CTRL8 Control endpoint 0x0 ISO Isochronous endpoint 0x1 BULK Bulk endpoint 0x2 INT Interrupt endpoint 0x3 NB_TRANS Number Of Transaction per Microframe (cleared upon USB reset) 8 2 read-write EPTCFG1 UDPHS Endpoint Configuration Register (endpoint = 1) 0x120 32 read-write n 0x0 0x0 BK_NUMBER Number of Banks (cleared upon USB reset) 6 2 read-write 0 Zero bank, the endpoint is not mapped in memory 0x0 1 One bank (bank 0) 0x1 2 Double bank (Ping-Pong: bank0/bank1) 0x2 3 Triple bank (bank0/bank1/bank2) 0x3 EPT_DIR Endpoint Direction (cleared upon USB reset) 3 1 read-write EPT_MAPD Endpoint Mapped (cleared upon USB reset) 31 1 read-write EPT_SIZE Endpoint Size (cleared upon USB reset) 0 3 read-write 8 8 bytes 0x0 16 16 bytes 0x1 32 32 bytes 0x2 64 64 bytes 0x3 128 128 bytes 0x4 256 256 bytes 0x5 512 512 bytes 0x6 1024 1024 bytes 0x7 EPT_TYPE Endpoint Type (cleared upon USB reset) 4 2 read-write CTRL8 Control endpoint 0x0 ISO Isochronous endpoint 0x1 BULK Bulk endpoint 0x2 INT Interrupt endpoint 0x3 NB_TRANS Number Of Transaction per Microframe (cleared upon USB reset) 8 2 read-write EPTCFG10 UDPHS Endpoint Configuration Register (endpoint = 10) 0x240 32 read-write n 0x0 0x0 BK_NUMBER Number of Banks (cleared upon USB reset) 6 2 read-write 0 Zero bank, the endpoint is not mapped in memory 0x0 1 One bank (bank 0) 0x1 2 Double bank (Ping-Pong: bank0/bank1) 0x2 3 Triple bank (bank0/bank1/bank2) 0x3 EPT_DIR Endpoint Direction (cleared upon USB reset) 3 1 read-write EPT_MAPD Endpoint Mapped (cleared upon USB reset) 31 1 read-write EPT_SIZE Endpoint Size (cleared upon USB reset) 0 3 read-write 8 8 bytes 0x0 16 16 bytes 0x1 32 32 bytes 0x2 64 64 bytes 0x3 128 128 bytes 0x4 256 256 bytes 0x5 512 512 bytes 0x6 1024 1024 bytes 0x7 EPT_TYPE Endpoint Type (cleared upon USB reset) 4 2 read-write CTRL8 Control endpoint 0x0 ISO Isochronous endpoint 0x1 BULK Bulk endpoint 0x2 INT Interrupt endpoint 0x3 NB_TRANS Number Of Transaction per Microframe (cleared upon USB reset) 8 2 read-write EPTCFG11 UDPHS Endpoint Configuration Register (endpoint = 11) 0x260 32 read-write n 0x0 0x0 BK_NUMBER Number of Banks (cleared upon USB reset) 6 2 read-write 0 Zero bank, the endpoint is not mapped in memory 0x0 1 One bank (bank 0) 0x1 2 Double bank (Ping-Pong: bank0/bank1) 0x2 3 Triple bank (bank0/bank1/bank2) 0x3 EPT_DIR Endpoint Direction (cleared upon USB reset) 3 1 read-write EPT_MAPD Endpoint Mapped (cleared upon USB reset) 31 1 read-write EPT_SIZE Endpoint Size (cleared upon USB reset) 0 3 read-write 8 8 bytes 0x0 16 16 bytes 0x1 32 32 bytes 0x2 64 64 bytes 0x3 128 128 bytes 0x4 256 256 bytes 0x5 512 512 bytes 0x6 1024 1024 bytes 0x7 EPT_TYPE Endpoint Type (cleared upon USB reset) 4 2 read-write CTRL8 Control endpoint 0x0 ISO Isochronous endpoint 0x1 BULK Bulk endpoint 0x2 INT Interrupt endpoint 0x3 NB_TRANS Number Of Transaction per Microframe (cleared upon USB reset) 8 2 read-write EPTCFG12 UDPHS Endpoint Configuration Register (endpoint = 12) 0x280 32 read-write n 0x0 0x0 BK_NUMBER Number of Banks (cleared upon USB reset) 6 2 read-write 0 Zero bank, the endpoint is not mapped in memory 0x0 1 One bank (bank 0) 0x1 2 Double bank (Ping-Pong: bank0/bank1) 0x2 3 Triple bank (bank0/bank1/bank2) 0x3 EPT_DIR Endpoint Direction (cleared upon USB reset) 3 1 read-write EPT_MAPD Endpoint Mapped (cleared upon USB reset) 31 1 read-write EPT_SIZE Endpoint Size (cleared upon USB reset) 0 3 read-write 8 8 bytes 0x0 16 16 bytes 0x1 32 32 bytes 0x2 64 64 bytes 0x3 128 128 bytes 0x4 256 256 bytes 0x5 512 512 bytes 0x6 1024 1024 bytes 0x7 EPT_TYPE Endpoint Type (cleared upon USB reset) 4 2 read-write CTRL8 Control endpoint 0x0 ISO Isochronous endpoint 0x1 BULK Bulk endpoint 0x2 INT Interrupt endpoint 0x3 NB_TRANS Number Of Transaction per Microframe (cleared upon USB reset) 8 2 read-write EPTCFG13 UDPHS Endpoint Configuration Register (endpoint = 13) 0x2A0 32 read-write n 0x0 0x0 BK_NUMBER Number of Banks (cleared upon USB reset) 6 2 read-write 0 Zero bank, the endpoint is not mapped in memory 0x0 1 One bank (bank 0) 0x1 2 Double bank (Ping-Pong: bank0/bank1) 0x2 3 Triple bank (bank0/bank1/bank2) 0x3 EPT_DIR Endpoint Direction (cleared upon USB reset) 3 1 read-write EPT_MAPD Endpoint Mapped (cleared upon USB reset) 31 1 read-write EPT_SIZE Endpoint Size (cleared upon USB reset) 0 3 read-write 8 8 bytes 0x0 16 16 bytes 0x1 32 32 bytes 0x2 64 64 bytes 0x3 128 128 bytes 0x4 256 256 bytes 0x5 512 512 bytes 0x6 1024 1024 bytes 0x7 EPT_TYPE Endpoint Type (cleared upon USB reset) 4 2 read-write CTRL8 Control endpoint 0x0 ISO Isochronous endpoint 0x1 BULK Bulk endpoint 0x2 INT Interrupt endpoint 0x3 NB_TRANS Number Of Transaction per Microframe (cleared upon USB reset) 8 2 read-write EPTCFG14 UDPHS Endpoint Configuration Register (endpoint = 14) 0x2C0 32 read-write n 0x0 0x0 BK_NUMBER Number of Banks (cleared upon USB reset) 6 2 read-write 0 Zero bank, the endpoint is not mapped in memory 0x0 1 One bank (bank 0) 0x1 2 Double bank (Ping-Pong: bank0/bank1) 0x2 3 Triple bank (bank0/bank1/bank2) 0x3 EPT_DIR Endpoint Direction (cleared upon USB reset) 3 1 read-write EPT_MAPD Endpoint Mapped (cleared upon USB reset) 31 1 read-write EPT_SIZE Endpoint Size (cleared upon USB reset) 0 3 read-write 8 8 bytes 0x0 16 16 bytes 0x1 32 32 bytes 0x2 64 64 bytes 0x3 128 128 bytes 0x4 256 256 bytes 0x5 512 512 bytes 0x6 1024 1024 bytes 0x7 EPT_TYPE Endpoint Type (cleared upon USB reset) 4 2 read-write CTRL8 Control endpoint 0x0 ISO Isochronous endpoint 0x1 BULK Bulk endpoint 0x2 INT Interrupt endpoint 0x3 NB_TRANS Number Of Transaction per Microframe (cleared upon USB reset) 8 2 read-write EPTCFG15 UDPHS Endpoint Configuration Register (endpoint = 15) 0x2E0 32 read-write n 0x0 0x0 BK_NUMBER Number of Banks (cleared upon USB reset) 6 2 read-write 0 Zero bank, the endpoint is not mapped in memory 0x0 1 One bank (bank 0) 0x1 2 Double bank (Ping-Pong: bank0/bank1) 0x2 3 Triple bank (bank0/bank1/bank2) 0x3 EPT_DIR Endpoint Direction (cleared upon USB reset) 3 1 read-write EPT_MAPD Endpoint Mapped (cleared upon USB reset) 31 1 read-write EPT_SIZE Endpoint Size (cleared upon USB reset) 0 3 read-write 8 8 bytes 0x0 16 16 bytes 0x1 32 32 bytes 0x2 64 64 bytes 0x3 128 128 bytes 0x4 256 256 bytes 0x5 512 512 bytes 0x6 1024 1024 bytes 0x7 EPT_TYPE Endpoint Type (cleared upon USB reset) 4 2 read-write CTRL8 Control endpoint 0x0 ISO Isochronous endpoint 0x1 BULK Bulk endpoint 0x2 INT Interrupt endpoint 0x3 NB_TRANS Number Of Transaction per Microframe (cleared upon USB reset) 8 2 read-write EPTCFG2 UDPHS Endpoint Configuration Register (endpoint = 2) 0x140 32 read-write n 0x0 0x0 BK_NUMBER Number of Banks (cleared upon USB reset) 6 2 read-write 0 Zero bank, the endpoint is not mapped in memory 0x0 1 One bank (bank 0) 0x1 2 Double bank (Ping-Pong: bank0/bank1) 0x2 3 Triple bank (bank0/bank1/bank2) 0x3 EPT_DIR Endpoint Direction (cleared upon USB reset) 3 1 read-write EPT_MAPD Endpoint Mapped (cleared upon USB reset) 31 1 read-write EPT_SIZE Endpoint Size (cleared upon USB reset) 0 3 read-write 8 8 bytes 0x0 16 16 bytes 0x1 32 32 bytes 0x2 64 64 bytes 0x3 128 128 bytes 0x4 256 256 bytes 0x5 512 512 bytes 0x6 1024 1024 bytes 0x7 EPT_TYPE Endpoint Type (cleared upon USB reset) 4 2 read-write CTRL8 Control endpoint 0x0 ISO Isochronous endpoint 0x1 BULK Bulk endpoint 0x2 INT Interrupt endpoint 0x3 NB_TRANS Number Of Transaction per Microframe (cleared upon USB reset) 8 2 read-write EPTCFG3 UDPHS Endpoint Configuration Register (endpoint = 3) 0x160 32 read-write n 0x0 0x0 BK_NUMBER Number of Banks (cleared upon USB reset) 6 2 read-write 0 Zero bank, the endpoint is not mapped in memory 0x0 1 One bank (bank 0) 0x1 2 Double bank (Ping-Pong: bank0/bank1) 0x2 3 Triple bank (bank0/bank1/bank2) 0x3 EPT_DIR Endpoint Direction (cleared upon USB reset) 3 1 read-write EPT_MAPD Endpoint Mapped (cleared upon USB reset) 31 1 read-write EPT_SIZE Endpoint Size (cleared upon USB reset) 0 3 read-write 8 8 bytes 0x0 16 16 bytes 0x1 32 32 bytes 0x2 64 64 bytes 0x3 128 128 bytes 0x4 256 256 bytes 0x5 512 512 bytes 0x6 1024 1024 bytes 0x7 EPT_TYPE Endpoint Type (cleared upon USB reset) 4 2 read-write CTRL8 Control endpoint 0x0 ISO Isochronous endpoint 0x1 BULK Bulk endpoint 0x2 INT Interrupt endpoint 0x3 NB_TRANS Number Of Transaction per Microframe (cleared upon USB reset) 8 2 read-write EPTCFG4 UDPHS Endpoint Configuration Register (endpoint = 4) 0x180 32 read-write n 0x0 0x0 BK_NUMBER Number of Banks (cleared upon USB reset) 6 2 read-write 0 Zero bank, the endpoint is not mapped in memory 0x0 1 One bank (bank 0) 0x1 2 Double bank (Ping-Pong: bank0/bank1) 0x2 3 Triple bank (bank0/bank1/bank2) 0x3 EPT_DIR Endpoint Direction (cleared upon USB reset) 3 1 read-write EPT_MAPD Endpoint Mapped (cleared upon USB reset) 31 1 read-write EPT_SIZE Endpoint Size (cleared upon USB reset) 0 3 read-write 8 8 bytes 0x0 16 16 bytes 0x1 32 32 bytes 0x2 64 64 bytes 0x3 128 128 bytes 0x4 256 256 bytes 0x5 512 512 bytes 0x6 1024 1024 bytes 0x7 EPT_TYPE Endpoint Type (cleared upon USB reset) 4 2 read-write CTRL8 Control endpoint 0x0 ISO Isochronous endpoint 0x1 BULK Bulk endpoint 0x2 INT Interrupt endpoint 0x3 NB_TRANS Number Of Transaction per Microframe (cleared upon USB reset) 8 2 read-write EPTCFG5 UDPHS Endpoint Configuration Register (endpoint = 5) 0x1A0 32 read-write n 0x0 0x0 BK_NUMBER Number of Banks (cleared upon USB reset) 6 2 read-write 0 Zero bank, the endpoint is not mapped in memory 0x0 1 One bank (bank 0) 0x1 2 Double bank (Ping-Pong: bank0/bank1) 0x2 3 Triple bank (bank0/bank1/bank2) 0x3 EPT_DIR Endpoint Direction (cleared upon USB reset) 3 1 read-write EPT_MAPD Endpoint Mapped (cleared upon USB reset) 31 1 read-write EPT_SIZE Endpoint Size (cleared upon USB reset) 0 3 read-write 8 8 bytes 0x0 16 16 bytes 0x1 32 32 bytes 0x2 64 64 bytes 0x3 128 128 bytes 0x4 256 256 bytes 0x5 512 512 bytes 0x6 1024 1024 bytes 0x7 EPT_TYPE Endpoint Type (cleared upon USB reset) 4 2 read-write CTRL8 Control endpoint 0x0 ISO Isochronous endpoint 0x1 BULK Bulk endpoint 0x2 INT Interrupt endpoint 0x3 NB_TRANS Number Of Transaction per Microframe (cleared upon USB reset) 8 2 read-write EPTCFG6 UDPHS Endpoint Configuration Register (endpoint = 6) 0x1C0 32 read-write n 0x0 0x0 BK_NUMBER Number of Banks (cleared upon USB reset) 6 2 read-write 0 Zero bank, the endpoint is not mapped in memory 0x0 1 One bank (bank 0) 0x1 2 Double bank (Ping-Pong: bank0/bank1) 0x2 3 Triple bank (bank0/bank1/bank2) 0x3 EPT_DIR Endpoint Direction (cleared upon USB reset) 3 1 read-write EPT_MAPD Endpoint Mapped (cleared upon USB reset) 31 1 read-write EPT_SIZE Endpoint Size (cleared upon USB reset) 0 3 read-write 8 8 bytes 0x0 16 16 bytes 0x1 32 32 bytes 0x2 64 64 bytes 0x3 128 128 bytes 0x4 256 256 bytes 0x5 512 512 bytes 0x6 1024 1024 bytes 0x7 EPT_TYPE Endpoint Type (cleared upon USB reset) 4 2 read-write CTRL8 Control endpoint 0x0 ISO Isochronous endpoint 0x1 BULK Bulk endpoint 0x2 INT Interrupt endpoint 0x3 NB_TRANS Number Of Transaction per Microframe (cleared upon USB reset) 8 2 read-write EPTCFG7 UDPHS Endpoint Configuration Register (endpoint = 7) 0x1E0 32 read-write n 0x0 0x0 BK_NUMBER Number of Banks (cleared upon USB reset) 6 2 read-write 0 Zero bank, the endpoint is not mapped in memory 0x0 1 One bank (bank 0) 0x1 2 Double bank (Ping-Pong: bank0/bank1) 0x2 3 Triple bank (bank0/bank1/bank2) 0x3 EPT_DIR Endpoint Direction (cleared upon USB reset) 3 1 read-write EPT_MAPD Endpoint Mapped (cleared upon USB reset) 31 1 read-write EPT_SIZE Endpoint Size (cleared upon USB reset) 0 3 read-write 8 8 bytes 0x0 16 16 bytes 0x1 32 32 bytes 0x2 64 64 bytes 0x3 128 128 bytes 0x4 256 256 bytes 0x5 512 512 bytes 0x6 1024 1024 bytes 0x7 EPT_TYPE Endpoint Type (cleared upon USB reset) 4 2 read-write CTRL8 Control endpoint 0x0 ISO Isochronous endpoint 0x1 BULK Bulk endpoint 0x2 INT Interrupt endpoint 0x3 NB_TRANS Number Of Transaction per Microframe (cleared upon USB reset) 8 2 read-write EPTCFG8 UDPHS Endpoint Configuration Register (endpoint = 8) 0x200 32 read-write n 0x0 0x0 BK_NUMBER Number of Banks (cleared upon USB reset) 6 2 read-write 0 Zero bank, the endpoint is not mapped in memory 0x0 1 One bank (bank 0) 0x1 2 Double bank (Ping-Pong: bank0/bank1) 0x2 3 Triple bank (bank0/bank1/bank2) 0x3 EPT_DIR Endpoint Direction (cleared upon USB reset) 3 1 read-write EPT_MAPD Endpoint Mapped (cleared upon USB reset) 31 1 read-write EPT_SIZE Endpoint Size (cleared upon USB reset) 0 3 read-write 8 8 bytes 0x0 16 16 bytes 0x1 32 32 bytes 0x2 64 64 bytes 0x3 128 128 bytes 0x4 256 256 bytes 0x5 512 512 bytes 0x6 1024 1024 bytes 0x7 EPT_TYPE Endpoint Type (cleared upon USB reset) 4 2 read-write CTRL8 Control endpoint 0x0 ISO Isochronous endpoint 0x1 BULK Bulk endpoint 0x2 INT Interrupt endpoint 0x3 NB_TRANS Number Of Transaction per Microframe (cleared upon USB reset) 8 2 read-write EPTCFG9 UDPHS Endpoint Configuration Register (endpoint = 9) 0x220 32 read-write n 0x0 0x0 BK_NUMBER Number of Banks (cleared upon USB reset) 6 2 read-write 0 Zero bank, the endpoint is not mapped in memory 0x0 1 One bank (bank 0) 0x1 2 Double bank (Ping-Pong: bank0/bank1) 0x2 3 Triple bank (bank0/bank1/bank2) 0x3 EPT_DIR Endpoint Direction (cleared upon USB reset) 3 1 read-write EPT_MAPD Endpoint Mapped (cleared upon USB reset) 31 1 read-write EPT_SIZE Endpoint Size (cleared upon USB reset) 0 3 read-write 8 8 bytes 0x0 16 16 bytes 0x1 32 32 bytes 0x2 64 64 bytes 0x3 128 128 bytes 0x4 256 256 bytes 0x5 512 512 bytes 0x6 1024 1024 bytes 0x7 EPT_TYPE Endpoint Type (cleared upon USB reset) 4 2 read-write CTRL8 Control endpoint 0x0 ISO Isochronous endpoint 0x1 BULK Bulk endpoint 0x2 INT Interrupt endpoint 0x3 NB_TRANS Number Of Transaction per Microframe (cleared upon USB reset) 8 2 read-write EPTCLRSTA0 UDPHS Endpoint Clear Status Register (endpoint = 0) 0x118 32 write-only n 0x0 0x0 FRCESTALL Stall Handshake Request Clear 5 1 write-only NAK_IN NAKIN Clear 14 1 write-only NAK_OUT NAKOUT Clear 15 1 write-only RXRDY_TXKL Received OUT Data Clear 9 1 write-only RX_SETUP Received SETUP Clear 12 1 write-only STALL_SNT Stall Sent Clear 13 1 write-only TOGGLESQ Data Toggle Clear 6 1 write-only TX_COMPLT Transmitted IN Data Complete Clear 10 1 write-only EPTCLRSTA0_ISOENDPT UDPHS Endpoint Clear Status Register (endpoint = 0) ISOENDPT 0x118 32 write-only n 0x0 0x0 ERR_CRC_NTR Number of Transaction Error Clear 13 1 write-only ERR_FLUSH Bank Flush Error Clear 14 1 write-only ERR_FL_ISO Error Flow Clear 12 1 write-only RXRDY_TXKL Received OUT Data Clear 9 1 write-only TOGGLESQ Data Toggle Clear 6 1 write-only TX_COMPLT Transmitted IN Data Complete Clear 10 1 write-only EPTCLRSTA1 UDPHS Endpoint Clear Status Register (endpoint = 1) 0x138 32 write-only n 0x0 0x0 FRCESTALL Stall Handshake Request Clear 5 1 write-only NAK_IN NAKIN Clear 14 1 write-only NAK_OUT NAKOUT Clear 15 1 write-only RXRDY_TXKL Received OUT Data Clear 9 1 write-only RX_SETUP Received SETUP Clear 12 1 write-only STALL_SNT Stall Sent Clear 13 1 write-only TOGGLESQ Data Toggle Clear 6 1 write-only TX_COMPLT Transmitted IN Data Complete Clear 10 1 write-only EPTCLRSTA10 UDPHS Endpoint Clear Status Register (endpoint = 10) 0x258 32 write-only n 0x0 0x0 FRCESTALL Stall Handshake Request Clear 5 1 write-only NAK_IN NAKIN Clear 14 1 write-only NAK_OUT NAKOUT Clear 15 1 write-only RXRDY_TXKL Received OUT Data Clear 9 1 write-only RX_SETUP Received SETUP Clear 12 1 write-only STALL_SNT Stall Sent Clear 13 1 write-only TOGGLESQ Data Toggle Clear 6 1 write-only TX_COMPLT Transmitted IN Data Complete Clear 10 1 write-only EPTCLRSTA10_ISOENDPT UDPHS Endpoint Clear Status Register (endpoint = 10) ISOENDPT 0x258 32 write-only n 0x0 0x0 ERR_CRC_NTR Number of Transaction Error Clear 13 1 write-only ERR_FLUSH Bank Flush Error Clear 14 1 write-only ERR_FL_ISO Error Flow Clear 12 1 write-only RXRDY_TXKL Received OUT Data Clear 9 1 write-only TOGGLESQ Data Toggle Clear 6 1 write-only TX_COMPLT Transmitted IN Data Complete Clear 10 1 write-only EPTCLRSTA11 UDPHS Endpoint Clear Status Register (endpoint = 11) 0x278 32 write-only n 0x0 0x0 FRCESTALL Stall Handshake Request Clear 5 1 write-only NAK_IN NAKIN Clear 14 1 write-only NAK_OUT NAKOUT Clear 15 1 write-only RXRDY_TXKL Received OUT Data Clear 9 1 write-only RX_SETUP Received SETUP Clear 12 1 write-only STALL_SNT Stall Sent Clear 13 1 write-only TOGGLESQ Data Toggle Clear 6 1 write-only TX_COMPLT Transmitted IN Data Complete Clear 10 1 write-only EPTCLRSTA11_ISOENDPT UDPHS Endpoint Clear Status Register (endpoint = 11) ISOENDPT 0x278 32 write-only n 0x0 0x0 ERR_CRC_NTR Number of Transaction Error Clear 13 1 write-only ERR_FLUSH Bank Flush Error Clear 14 1 write-only ERR_FL_ISO Error Flow Clear 12 1 write-only RXRDY_TXKL Received OUT Data Clear 9 1 write-only TOGGLESQ Data Toggle Clear 6 1 write-only TX_COMPLT Transmitted IN Data Complete Clear 10 1 write-only EPTCLRSTA12 UDPHS Endpoint Clear Status Register (endpoint = 12) 0x298 32 write-only n 0x0 0x0 FRCESTALL Stall Handshake Request Clear 5 1 write-only NAK_IN NAKIN Clear 14 1 write-only NAK_OUT NAKOUT Clear 15 1 write-only RXRDY_TXKL Received OUT Data Clear 9 1 write-only RX_SETUP Received SETUP Clear 12 1 write-only STALL_SNT Stall Sent Clear 13 1 write-only TOGGLESQ Data Toggle Clear 6 1 write-only TX_COMPLT Transmitted IN Data Complete Clear 10 1 write-only EPTCLRSTA12_ISOENDPT UDPHS Endpoint Clear Status Register (endpoint = 12) ISOENDPT 0x298 32 write-only n 0x0 0x0 ERR_CRC_NTR Number of Transaction Error Clear 13 1 write-only ERR_FLUSH Bank Flush Error Clear 14 1 write-only ERR_FL_ISO Error Flow Clear 12 1 write-only RXRDY_TXKL Received OUT Data Clear 9 1 write-only TOGGLESQ Data Toggle Clear 6 1 write-only TX_COMPLT Transmitted IN Data Complete Clear 10 1 write-only EPTCLRSTA13 UDPHS Endpoint Clear Status Register (endpoint = 13) 0x2B8 32 write-only n 0x0 0x0 FRCESTALL Stall Handshake Request Clear 5 1 write-only NAK_IN NAKIN Clear 14 1 write-only NAK_OUT NAKOUT Clear 15 1 write-only RXRDY_TXKL Received OUT Data Clear 9 1 write-only RX_SETUP Received SETUP Clear 12 1 write-only STALL_SNT Stall Sent Clear 13 1 write-only TOGGLESQ Data Toggle Clear 6 1 write-only TX_COMPLT Transmitted IN Data Complete Clear 10 1 write-only EPTCLRSTA13_ISOENDPT UDPHS Endpoint Clear Status Register (endpoint = 13) ISOENDPT 0x2B8 32 write-only n 0x0 0x0 ERR_CRC_NTR Number of Transaction Error Clear 13 1 write-only ERR_FLUSH Bank Flush Error Clear 14 1 write-only ERR_FL_ISO Error Flow Clear 12 1 write-only RXRDY_TXKL Received OUT Data Clear 9 1 write-only TOGGLESQ Data Toggle Clear 6 1 write-only TX_COMPLT Transmitted IN Data Complete Clear 10 1 write-only EPTCLRSTA14 UDPHS Endpoint Clear Status Register (endpoint = 14) 0x2D8 32 write-only n 0x0 0x0 FRCESTALL Stall Handshake Request Clear 5 1 write-only NAK_IN NAKIN Clear 14 1 write-only NAK_OUT NAKOUT Clear 15 1 write-only RXRDY_TXKL Received OUT Data Clear 9 1 write-only RX_SETUP Received SETUP Clear 12 1 write-only STALL_SNT Stall Sent Clear 13 1 write-only TOGGLESQ Data Toggle Clear 6 1 write-only TX_COMPLT Transmitted IN Data Complete Clear 10 1 write-only EPTCLRSTA14_ISOENDPT UDPHS Endpoint Clear Status Register (endpoint = 14) ISOENDPT 0x2D8 32 write-only n 0x0 0x0 ERR_CRC_NTR Number of Transaction Error Clear 13 1 write-only ERR_FLUSH Bank Flush Error Clear 14 1 write-only ERR_FL_ISO Error Flow Clear 12 1 write-only RXRDY_TXKL Received OUT Data Clear 9 1 write-only TOGGLESQ Data Toggle Clear 6 1 write-only TX_COMPLT Transmitted IN Data Complete Clear 10 1 write-only EPTCLRSTA15 UDPHS Endpoint Clear Status Register (endpoint = 15) 0x2F8 32 write-only n 0x0 0x0 FRCESTALL Stall Handshake Request Clear 5 1 write-only NAK_IN NAKIN Clear 14 1 write-only NAK_OUT NAKOUT Clear 15 1 write-only RXRDY_TXKL Received OUT Data Clear 9 1 write-only RX_SETUP Received SETUP Clear 12 1 write-only STALL_SNT Stall Sent Clear 13 1 write-only TOGGLESQ Data Toggle Clear 6 1 write-only TX_COMPLT Transmitted IN Data Complete Clear 10 1 write-only EPTCLRSTA15_ISOENDPT UDPHS Endpoint Clear Status Register (endpoint = 15) ISOENDPT 0x2F8 32 write-only n 0x0 0x0 ERR_CRC_NTR Number of Transaction Error Clear 13 1 write-only ERR_FLUSH Bank Flush Error Clear 14 1 write-only ERR_FL_ISO Error Flow Clear 12 1 write-only RXRDY_TXKL Received OUT Data Clear 9 1 write-only TOGGLESQ Data Toggle Clear 6 1 write-only TX_COMPLT Transmitted IN Data Complete Clear 10 1 write-only EPTCLRSTA1_ISOENDPT UDPHS Endpoint Clear Status Register (endpoint = 1) ISOENDPT 0x138 32 write-only n 0x0 0x0 ERR_CRC_NTR Number of Transaction Error Clear 13 1 write-only ERR_FLUSH Bank Flush Error Clear 14 1 write-only ERR_FL_ISO Error Flow Clear 12 1 write-only RXRDY_TXKL Received OUT Data Clear 9 1 write-only TOGGLESQ Data Toggle Clear 6 1 write-only TX_COMPLT Transmitted IN Data Complete Clear 10 1 write-only EPTCLRSTA2 UDPHS Endpoint Clear Status Register (endpoint = 2) 0x158 32 write-only n 0x0 0x0 FRCESTALL Stall Handshake Request Clear 5 1 write-only NAK_IN NAKIN Clear 14 1 write-only NAK_OUT NAKOUT Clear 15 1 write-only RXRDY_TXKL Received OUT Data Clear 9 1 write-only RX_SETUP Received SETUP Clear 12 1 write-only STALL_SNT Stall Sent Clear 13 1 write-only TOGGLESQ Data Toggle Clear 6 1 write-only TX_COMPLT Transmitted IN Data Complete Clear 10 1 write-only EPTCLRSTA2_ISOENDPT UDPHS Endpoint Clear Status Register (endpoint = 2) ISOENDPT 0x158 32 write-only n 0x0 0x0 ERR_CRC_NTR Number of Transaction Error Clear 13 1 write-only ERR_FLUSH Bank Flush Error Clear 14 1 write-only ERR_FL_ISO Error Flow Clear 12 1 write-only RXRDY_TXKL Received OUT Data Clear 9 1 write-only TOGGLESQ Data Toggle Clear 6 1 write-only TX_COMPLT Transmitted IN Data Complete Clear 10 1 write-only EPTCLRSTA3 UDPHS Endpoint Clear Status Register (endpoint = 3) 0x178 32 write-only n 0x0 0x0 FRCESTALL Stall Handshake Request Clear 5 1 write-only NAK_IN NAKIN Clear 14 1 write-only NAK_OUT NAKOUT Clear 15 1 write-only RXRDY_TXKL Received OUT Data Clear 9 1 write-only RX_SETUP Received SETUP Clear 12 1 write-only STALL_SNT Stall Sent Clear 13 1 write-only TOGGLESQ Data Toggle Clear 6 1 write-only TX_COMPLT Transmitted IN Data Complete Clear 10 1 write-only EPTCLRSTA3_ISOENDPT UDPHS Endpoint Clear Status Register (endpoint = 3) ISOENDPT 0x178 32 write-only n 0x0 0x0 ERR_CRC_NTR Number of Transaction Error Clear 13 1 write-only ERR_FLUSH Bank Flush Error Clear 14 1 write-only ERR_FL_ISO Error Flow Clear 12 1 write-only RXRDY_TXKL Received OUT Data Clear 9 1 write-only TOGGLESQ Data Toggle Clear 6 1 write-only TX_COMPLT Transmitted IN Data Complete Clear 10 1 write-only EPTCLRSTA4 UDPHS Endpoint Clear Status Register (endpoint = 4) 0x198 32 write-only n 0x0 0x0 FRCESTALL Stall Handshake Request Clear 5 1 write-only NAK_IN NAKIN Clear 14 1 write-only NAK_OUT NAKOUT Clear 15 1 write-only RXRDY_TXKL Received OUT Data Clear 9 1 write-only RX_SETUP Received SETUP Clear 12 1 write-only STALL_SNT Stall Sent Clear 13 1 write-only TOGGLESQ Data Toggle Clear 6 1 write-only TX_COMPLT Transmitted IN Data Complete Clear 10 1 write-only EPTCLRSTA4_ISOENDPT UDPHS Endpoint Clear Status Register (endpoint = 4) ISOENDPT 0x198 32 write-only n 0x0 0x0 ERR_CRC_NTR Number of Transaction Error Clear 13 1 write-only ERR_FLUSH Bank Flush Error Clear 14 1 write-only ERR_FL_ISO Error Flow Clear 12 1 write-only RXRDY_TXKL Received OUT Data Clear 9 1 write-only TOGGLESQ Data Toggle Clear 6 1 write-only TX_COMPLT Transmitted IN Data Complete Clear 10 1 write-only EPTCLRSTA5 UDPHS Endpoint Clear Status Register (endpoint = 5) 0x1B8 32 write-only n 0x0 0x0 FRCESTALL Stall Handshake Request Clear 5 1 write-only NAK_IN NAKIN Clear 14 1 write-only NAK_OUT NAKOUT Clear 15 1 write-only RXRDY_TXKL Received OUT Data Clear 9 1 write-only RX_SETUP Received SETUP Clear 12 1 write-only STALL_SNT Stall Sent Clear 13 1 write-only TOGGLESQ Data Toggle Clear 6 1 write-only TX_COMPLT Transmitted IN Data Complete Clear 10 1 write-only EPTCLRSTA5_ISOENDPT UDPHS Endpoint Clear Status Register (endpoint = 5) ISOENDPT 0x1B8 32 write-only n 0x0 0x0 ERR_CRC_NTR Number of Transaction Error Clear 13 1 write-only ERR_FLUSH Bank Flush Error Clear 14 1 write-only ERR_FL_ISO Error Flow Clear 12 1 write-only RXRDY_TXKL Received OUT Data Clear 9 1 write-only TOGGLESQ Data Toggle Clear 6 1 write-only TX_COMPLT Transmitted IN Data Complete Clear 10 1 write-only EPTCLRSTA6 UDPHS Endpoint Clear Status Register (endpoint = 6) 0x1D8 32 write-only n 0x0 0x0 FRCESTALL Stall Handshake Request Clear 5 1 write-only NAK_IN NAKIN Clear 14 1 write-only NAK_OUT NAKOUT Clear 15 1 write-only RXRDY_TXKL Received OUT Data Clear 9 1 write-only RX_SETUP Received SETUP Clear 12 1 write-only STALL_SNT Stall Sent Clear 13 1 write-only TOGGLESQ Data Toggle Clear 6 1 write-only TX_COMPLT Transmitted IN Data Complete Clear 10 1 write-only EPTCLRSTA6_ISOENDPT UDPHS Endpoint Clear Status Register (endpoint = 6) ISOENDPT 0x1D8 32 write-only n 0x0 0x0 ERR_CRC_NTR Number of Transaction Error Clear 13 1 write-only ERR_FLUSH Bank Flush Error Clear 14 1 write-only ERR_FL_ISO Error Flow Clear 12 1 write-only RXRDY_TXKL Received OUT Data Clear 9 1 write-only TOGGLESQ Data Toggle Clear 6 1 write-only TX_COMPLT Transmitted IN Data Complete Clear 10 1 write-only EPTCLRSTA7 UDPHS Endpoint Clear Status Register (endpoint = 7) 0x1F8 32 write-only n 0x0 0x0 FRCESTALL Stall Handshake Request Clear 5 1 write-only NAK_IN NAKIN Clear 14 1 write-only NAK_OUT NAKOUT Clear 15 1 write-only RXRDY_TXKL Received OUT Data Clear 9 1 write-only RX_SETUP Received SETUP Clear 12 1 write-only STALL_SNT Stall Sent Clear 13 1 write-only TOGGLESQ Data Toggle Clear 6 1 write-only TX_COMPLT Transmitted IN Data Complete Clear 10 1 write-only EPTCLRSTA7_ISOENDPT UDPHS Endpoint Clear Status Register (endpoint = 7) ISOENDPT 0x1F8 32 write-only n 0x0 0x0 ERR_CRC_NTR Number of Transaction Error Clear 13 1 write-only ERR_FLUSH Bank Flush Error Clear 14 1 write-only ERR_FL_ISO Error Flow Clear 12 1 write-only RXRDY_TXKL Received OUT Data Clear 9 1 write-only TOGGLESQ Data Toggle Clear 6 1 write-only TX_COMPLT Transmitted IN Data Complete Clear 10 1 write-only EPTCLRSTA8 UDPHS Endpoint Clear Status Register (endpoint = 8) 0x218 32 write-only n 0x0 0x0 FRCESTALL Stall Handshake Request Clear 5 1 write-only NAK_IN NAKIN Clear 14 1 write-only NAK_OUT NAKOUT Clear 15 1 write-only RXRDY_TXKL Received OUT Data Clear 9 1 write-only RX_SETUP Received SETUP Clear 12 1 write-only STALL_SNT Stall Sent Clear 13 1 write-only TOGGLESQ Data Toggle Clear 6 1 write-only TX_COMPLT Transmitted IN Data Complete Clear 10 1 write-only EPTCLRSTA8_ISOENDPT UDPHS Endpoint Clear Status Register (endpoint = 8) ISOENDPT 0x218 32 write-only n 0x0 0x0 ERR_CRC_NTR Number of Transaction Error Clear 13 1 write-only ERR_FLUSH Bank Flush Error Clear 14 1 write-only ERR_FL_ISO Error Flow Clear 12 1 write-only RXRDY_TXKL Received OUT Data Clear 9 1 write-only TOGGLESQ Data Toggle Clear 6 1 write-only TX_COMPLT Transmitted IN Data Complete Clear 10 1 write-only EPTCLRSTA9 UDPHS Endpoint Clear Status Register (endpoint = 9) 0x238 32 write-only n 0x0 0x0 FRCESTALL Stall Handshake Request Clear 5 1 write-only NAK_IN NAKIN Clear 14 1 write-only NAK_OUT NAKOUT Clear 15 1 write-only RXRDY_TXKL Received OUT Data Clear 9 1 write-only RX_SETUP Received SETUP Clear 12 1 write-only STALL_SNT Stall Sent Clear 13 1 write-only TOGGLESQ Data Toggle Clear 6 1 write-only TX_COMPLT Transmitted IN Data Complete Clear 10 1 write-only EPTCLRSTA9_ISOENDPT UDPHS Endpoint Clear Status Register (endpoint = 9) ISOENDPT 0x238 32 write-only n 0x0 0x0 ERR_CRC_NTR Number of Transaction Error Clear 13 1 write-only ERR_FLUSH Bank Flush Error Clear 14 1 write-only ERR_FL_ISO Error Flow Clear 12 1 write-only RXRDY_TXKL Received OUT Data Clear 9 1 write-only TOGGLESQ Data Toggle Clear 6 1 write-only TX_COMPLT Transmitted IN Data Complete Clear 10 1 write-only EPTCTL0 UDPHS Endpoint Control Register (endpoint = 0) 0x10C 32 read-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Enabled (Not for CONTROL Endpoints) (cleared upon USB reset) 1 1 read-only BUSY_BANK Busy Bank Interrupt Enabled (cleared upon USB reset) 18 1 read-only EPT_ENABL Endpoint Enable (cleared upon USB reset) 0 1 read-only ERR_OVFLW Overflow Error Interrupt Enabled (cleared upon USB reset) 8 1 read-only INTDIS_DMA Interrupt Disables DMA (cleared upon USB reset) 3 1 read-only NAK_IN NAKIN Interrupt Enabled (cleared upon USB reset) 14 1 read-only NAK_OUT NAKOUT Interrupt Enabled (cleared upon USB reset) 15 1 read-only NYET_DIS NYET Disable (Only for High Speed Bulk OUT Endpoints) (cleared upon USB reset) 4 1 read-only RXRDY_TXKL Received OUT Data Interrupt Enabled (cleared upon USB reset) 9 1 read-only RX_SETUP Received SETUP Interrupt Enabled (cleared upon USB reset) 12 1 read-only SHRT_PCKT Short Packet Interrupt Enabled (cleared upon USB reset) 31 1 read-only STALL_SNT Stall Sent Interrupt Enabled (cleared upon USB reset) 13 1 read-only TXRDY TX Packet Ready Interrupt Enabled (cleared upon USB reset) 11 1 read-only TX_COMPLT Transmitted IN Data Complete Interrupt Enabled (cleared upon USB reset) 10 1 read-only EPTCTL0_ISOENDPT UDPHS Endpoint Control Register (endpoint = 0) ISOENDPT 0x10C 32 read-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Enabled (cleared upon USB reset) 1 1 read-only BUSY_BANK Busy Bank Interrupt Enabled (cleared upon USB reset) 18 1 read-only DATAX_RX DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) (cleared upon USB reset) 6 1 read-only EPT_ENABL Endpoint Enable (cleared upon USB reset) 0 1 read-only ERR_CRC_NTR ISO CRC Error/Number of Transaction Error Interrupt Enabled (cleared upon USB reset) 13 1 read-only ERR_FLUSH Bank Flush Error Interrupt Enabled (cleared upon USB reset) 14 1 read-only ERR_FL_ISO Error Flow Interrupt Enabled (cleared upon USB reset) 12 1 read-only ERR_OVFLW Overflow Error Interrupt Enabled (cleared upon USB reset) 8 1 read-only INTDIS_DMA Interrupt Disables DMA (cleared upon USB reset) 3 1 read-only MDATA_RX MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) (cleared upon USB reset) 7 1 read-only RXRDY_TXKL Received OUT Data Interrupt Enabled (cleared upon USB reset) 9 1 read-only SHRT_PCKT Short Packet Interrupt Enabled (cleared upon USB reset) 31 1 read-only TXRDY_TRER TX Packet Ready/Transaction Error Interrupt Enabled (cleared upon USB reset) 11 1 read-only TX_COMPLT Transmitted IN Data Complete Interrupt Enabled (cleared upon USB reset) 10 1 read-only EPTCTL1 UDPHS Endpoint Control Register (endpoint = 1) 0x12C 32 read-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Enabled (Not for CONTROL Endpoints) (cleared upon USB reset) 1 1 read-only BUSY_BANK Busy Bank Interrupt Enabled (cleared upon USB reset) 18 1 read-only EPT_ENABL Endpoint Enable (cleared upon USB reset) 0 1 read-only ERR_OVFLW Overflow Error Interrupt Enabled (cleared upon USB reset) 8 1 read-only INTDIS_DMA Interrupt Disables DMA (cleared upon USB reset) 3 1 read-only NAK_IN NAKIN Interrupt Enabled (cleared upon USB reset) 14 1 read-only NAK_OUT NAKOUT Interrupt Enabled (cleared upon USB reset) 15 1 read-only NYET_DIS NYET Disable (Only for High Speed Bulk OUT Endpoints) (cleared upon USB reset) 4 1 read-only RXRDY_TXKL Received OUT Data Interrupt Enabled (cleared upon USB reset) 9 1 read-only RX_SETUP Received SETUP Interrupt Enabled (cleared upon USB reset) 12 1 read-only SHRT_PCKT Short Packet Interrupt Enabled (cleared upon USB reset) 31 1 read-only STALL_SNT Stall Sent Interrupt Enabled (cleared upon USB reset) 13 1 read-only TXRDY TX Packet Ready Interrupt Enabled (cleared upon USB reset) 11 1 read-only TX_COMPLT Transmitted IN Data Complete Interrupt Enabled (cleared upon USB reset) 10 1 read-only EPTCTL10 UDPHS Endpoint Control Register (endpoint = 10) 0x24C 32 read-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Enabled (Not for CONTROL Endpoints) (cleared upon USB reset) 1 1 read-only BUSY_BANK Busy Bank Interrupt Enabled (cleared upon USB reset) 18 1 read-only EPT_ENABL Endpoint Enable (cleared upon USB reset) 0 1 read-only ERR_OVFLW Overflow Error Interrupt Enabled (cleared upon USB reset) 8 1 read-only INTDIS_DMA Interrupt Disables DMA (cleared upon USB reset) 3 1 read-only NAK_IN NAKIN Interrupt Enabled (cleared upon USB reset) 14 1 read-only NAK_OUT NAKOUT Interrupt Enabled (cleared upon USB reset) 15 1 read-only NYET_DIS NYET Disable (Only for High Speed Bulk OUT Endpoints) (cleared upon USB reset) 4 1 read-only RXRDY_TXKL Received OUT Data Interrupt Enabled (cleared upon USB reset) 9 1 read-only RX_SETUP Received SETUP Interrupt Enabled (cleared upon USB reset) 12 1 read-only SHRT_PCKT Short Packet Interrupt Enabled (cleared upon USB reset) 31 1 read-only STALL_SNT Stall Sent Interrupt Enabled (cleared upon USB reset) 13 1 read-only TXRDY TX Packet Ready Interrupt Enabled (cleared upon USB reset) 11 1 read-only TX_COMPLT Transmitted IN Data Complete Interrupt Enabled (cleared upon USB reset) 10 1 read-only EPTCTL10_ISOENDPT UDPHS Endpoint Control Register (endpoint = 10) ISOENDPT 0x24C 32 read-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Enabled (cleared upon USB reset) 1 1 read-only BUSY_BANK Busy Bank Interrupt Enabled (cleared upon USB reset) 18 1 read-only DATAX_RX DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) (cleared upon USB reset) 6 1 read-only EPT_ENABL Endpoint Enable (cleared upon USB reset) 0 1 read-only ERR_CRC_NTR ISO CRC Error/Number of Transaction Error Interrupt Enabled (cleared upon USB reset) 13 1 read-only ERR_FLUSH Bank Flush Error Interrupt Enabled (cleared upon USB reset) 14 1 read-only ERR_FL_ISO Error Flow Interrupt Enabled (cleared upon USB reset) 12 1 read-only ERR_OVFLW Overflow Error Interrupt Enabled (cleared upon USB reset) 8 1 read-only INTDIS_DMA Interrupt Disables DMA (cleared upon USB reset) 3 1 read-only MDATA_RX MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) (cleared upon USB reset) 7 1 read-only RXRDY_TXKL Received OUT Data Interrupt Enabled (cleared upon USB reset) 9 1 read-only SHRT_PCKT Short Packet Interrupt Enabled (cleared upon USB reset) 31 1 read-only TXRDY_TRER TX Packet Ready/Transaction Error Interrupt Enabled (cleared upon USB reset) 11 1 read-only TX_COMPLT Transmitted IN Data Complete Interrupt Enabled (cleared upon USB reset) 10 1 read-only EPTCTL11 UDPHS Endpoint Control Register (endpoint = 11) 0x26C 32 read-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Enabled (Not for CONTROL Endpoints) (cleared upon USB reset) 1 1 read-only BUSY_BANK Busy Bank Interrupt Enabled (cleared upon USB reset) 18 1 read-only EPT_ENABL Endpoint Enable (cleared upon USB reset) 0 1 read-only ERR_OVFLW Overflow Error Interrupt Enabled (cleared upon USB reset) 8 1 read-only INTDIS_DMA Interrupt Disables DMA (cleared upon USB reset) 3 1 read-only NAK_IN NAKIN Interrupt Enabled (cleared upon USB reset) 14 1 read-only NAK_OUT NAKOUT Interrupt Enabled (cleared upon USB reset) 15 1 read-only NYET_DIS NYET Disable (Only for High Speed Bulk OUT Endpoints) (cleared upon USB reset) 4 1 read-only RXRDY_TXKL Received OUT Data Interrupt Enabled (cleared upon USB reset) 9 1 read-only RX_SETUP Received SETUP Interrupt Enabled (cleared upon USB reset) 12 1 read-only SHRT_PCKT Short Packet Interrupt Enabled (cleared upon USB reset) 31 1 read-only STALL_SNT Stall Sent Interrupt Enabled (cleared upon USB reset) 13 1 read-only TXRDY TX Packet Ready Interrupt Enabled (cleared upon USB reset) 11 1 read-only TX_COMPLT Transmitted IN Data Complete Interrupt Enabled (cleared upon USB reset) 10 1 read-only EPTCTL11_ISOENDPT UDPHS Endpoint Control Register (endpoint = 11) ISOENDPT 0x26C 32 read-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Enabled (cleared upon USB reset) 1 1 read-only BUSY_BANK Busy Bank Interrupt Enabled (cleared upon USB reset) 18 1 read-only DATAX_RX DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) (cleared upon USB reset) 6 1 read-only EPT_ENABL Endpoint Enable (cleared upon USB reset) 0 1 read-only ERR_CRC_NTR ISO CRC Error/Number of Transaction Error Interrupt Enabled (cleared upon USB reset) 13 1 read-only ERR_FLUSH Bank Flush Error Interrupt Enabled (cleared upon USB reset) 14 1 read-only ERR_FL_ISO Error Flow Interrupt Enabled (cleared upon USB reset) 12 1 read-only ERR_OVFLW Overflow Error Interrupt Enabled (cleared upon USB reset) 8 1 read-only INTDIS_DMA Interrupt Disables DMA (cleared upon USB reset) 3 1 read-only MDATA_RX MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) (cleared upon USB reset) 7 1 read-only RXRDY_TXKL Received OUT Data Interrupt Enabled (cleared upon USB reset) 9 1 read-only SHRT_PCKT Short Packet Interrupt Enabled (cleared upon USB reset) 31 1 read-only TXRDY_TRER TX Packet Ready/Transaction Error Interrupt Enabled (cleared upon USB reset) 11 1 read-only TX_COMPLT Transmitted IN Data Complete Interrupt Enabled (cleared upon USB reset) 10 1 read-only EPTCTL12 UDPHS Endpoint Control Register (endpoint = 12) 0x28C 32 read-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Enabled (Not for CONTROL Endpoints) (cleared upon USB reset) 1 1 read-only BUSY_BANK Busy Bank Interrupt Enabled (cleared upon USB reset) 18 1 read-only EPT_ENABL Endpoint Enable (cleared upon USB reset) 0 1 read-only ERR_OVFLW Overflow Error Interrupt Enabled (cleared upon USB reset) 8 1 read-only INTDIS_DMA Interrupt Disables DMA (cleared upon USB reset) 3 1 read-only NAK_IN NAKIN Interrupt Enabled (cleared upon USB reset) 14 1 read-only NAK_OUT NAKOUT Interrupt Enabled (cleared upon USB reset) 15 1 read-only NYET_DIS NYET Disable (Only for High Speed Bulk OUT Endpoints) (cleared upon USB reset) 4 1 read-only RXRDY_TXKL Received OUT Data Interrupt Enabled (cleared upon USB reset) 9 1 read-only RX_SETUP Received SETUP Interrupt Enabled (cleared upon USB reset) 12 1 read-only SHRT_PCKT Short Packet Interrupt Enabled (cleared upon USB reset) 31 1 read-only STALL_SNT Stall Sent Interrupt Enabled (cleared upon USB reset) 13 1 read-only TXRDY TX Packet Ready Interrupt Enabled (cleared upon USB reset) 11 1 read-only TX_COMPLT Transmitted IN Data Complete Interrupt Enabled (cleared upon USB reset) 10 1 read-only EPTCTL12_ISOENDPT UDPHS Endpoint Control Register (endpoint = 12) ISOENDPT 0x28C 32 read-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Enabled (cleared upon USB reset) 1 1 read-only BUSY_BANK Busy Bank Interrupt Enabled (cleared upon USB reset) 18 1 read-only DATAX_RX DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) (cleared upon USB reset) 6 1 read-only EPT_ENABL Endpoint Enable (cleared upon USB reset) 0 1 read-only ERR_CRC_NTR ISO CRC Error/Number of Transaction Error Interrupt Enabled (cleared upon USB reset) 13 1 read-only ERR_FLUSH Bank Flush Error Interrupt Enabled (cleared upon USB reset) 14 1 read-only ERR_FL_ISO Error Flow Interrupt Enabled (cleared upon USB reset) 12 1 read-only ERR_OVFLW Overflow Error Interrupt Enabled (cleared upon USB reset) 8 1 read-only INTDIS_DMA Interrupt Disables DMA (cleared upon USB reset) 3 1 read-only MDATA_RX MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) (cleared upon USB reset) 7 1 read-only RXRDY_TXKL Received OUT Data Interrupt Enabled (cleared upon USB reset) 9 1 read-only SHRT_PCKT Short Packet Interrupt Enabled (cleared upon USB reset) 31 1 read-only TXRDY_TRER TX Packet Ready/Transaction Error Interrupt Enabled (cleared upon USB reset) 11 1 read-only TX_COMPLT Transmitted IN Data Complete Interrupt Enabled (cleared upon USB reset) 10 1 read-only EPTCTL13 UDPHS Endpoint Control Register (endpoint = 13) 0x2AC 32 read-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Enabled (Not for CONTROL Endpoints) (cleared upon USB reset) 1 1 read-only BUSY_BANK Busy Bank Interrupt Enabled (cleared upon USB reset) 18 1 read-only EPT_ENABL Endpoint Enable (cleared upon USB reset) 0 1 read-only ERR_OVFLW Overflow Error Interrupt Enabled (cleared upon USB reset) 8 1 read-only INTDIS_DMA Interrupt Disables DMA (cleared upon USB reset) 3 1 read-only NAK_IN NAKIN Interrupt Enabled (cleared upon USB reset) 14 1 read-only NAK_OUT NAKOUT Interrupt Enabled (cleared upon USB reset) 15 1 read-only NYET_DIS NYET Disable (Only for High Speed Bulk OUT Endpoints) (cleared upon USB reset) 4 1 read-only RXRDY_TXKL Received OUT Data Interrupt Enabled (cleared upon USB reset) 9 1 read-only RX_SETUP Received SETUP Interrupt Enabled (cleared upon USB reset) 12 1 read-only SHRT_PCKT Short Packet Interrupt Enabled (cleared upon USB reset) 31 1 read-only STALL_SNT Stall Sent Interrupt Enabled (cleared upon USB reset) 13 1 read-only TXRDY TX Packet Ready Interrupt Enabled (cleared upon USB reset) 11 1 read-only TX_COMPLT Transmitted IN Data Complete Interrupt Enabled (cleared upon USB reset) 10 1 read-only EPTCTL13_ISOENDPT UDPHS Endpoint Control Register (endpoint = 13) ISOENDPT 0x2AC 32 read-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Enabled (cleared upon USB reset) 1 1 read-only BUSY_BANK Busy Bank Interrupt Enabled (cleared upon USB reset) 18 1 read-only DATAX_RX DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) (cleared upon USB reset) 6 1 read-only EPT_ENABL Endpoint Enable (cleared upon USB reset) 0 1 read-only ERR_CRC_NTR ISO CRC Error/Number of Transaction Error Interrupt Enabled (cleared upon USB reset) 13 1 read-only ERR_FLUSH Bank Flush Error Interrupt Enabled (cleared upon USB reset) 14 1 read-only ERR_FL_ISO Error Flow Interrupt Enabled (cleared upon USB reset) 12 1 read-only ERR_OVFLW Overflow Error Interrupt Enabled (cleared upon USB reset) 8 1 read-only INTDIS_DMA Interrupt Disables DMA (cleared upon USB reset) 3 1 read-only MDATA_RX MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) (cleared upon USB reset) 7 1 read-only RXRDY_TXKL Received OUT Data Interrupt Enabled (cleared upon USB reset) 9 1 read-only SHRT_PCKT Short Packet Interrupt Enabled (cleared upon USB reset) 31 1 read-only TXRDY_TRER TX Packet Ready/Transaction Error Interrupt Enabled (cleared upon USB reset) 11 1 read-only TX_COMPLT Transmitted IN Data Complete Interrupt Enabled (cleared upon USB reset) 10 1 read-only EPTCTL14 UDPHS Endpoint Control Register (endpoint = 14) 0x2CC 32 read-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Enabled (Not for CONTROL Endpoints) (cleared upon USB reset) 1 1 read-only BUSY_BANK Busy Bank Interrupt Enabled (cleared upon USB reset) 18 1 read-only EPT_ENABL Endpoint Enable (cleared upon USB reset) 0 1 read-only ERR_OVFLW Overflow Error Interrupt Enabled (cleared upon USB reset) 8 1 read-only INTDIS_DMA Interrupt Disables DMA (cleared upon USB reset) 3 1 read-only NAK_IN NAKIN Interrupt Enabled (cleared upon USB reset) 14 1 read-only NAK_OUT NAKOUT Interrupt Enabled (cleared upon USB reset) 15 1 read-only NYET_DIS NYET Disable (Only for High Speed Bulk OUT Endpoints) (cleared upon USB reset) 4 1 read-only RXRDY_TXKL Received OUT Data Interrupt Enabled (cleared upon USB reset) 9 1 read-only RX_SETUP Received SETUP Interrupt Enabled (cleared upon USB reset) 12 1 read-only SHRT_PCKT Short Packet Interrupt Enabled (cleared upon USB reset) 31 1 read-only STALL_SNT Stall Sent Interrupt Enabled (cleared upon USB reset) 13 1 read-only TXRDY TX Packet Ready Interrupt Enabled (cleared upon USB reset) 11 1 read-only TX_COMPLT Transmitted IN Data Complete Interrupt Enabled (cleared upon USB reset) 10 1 read-only EPTCTL14_ISOENDPT UDPHS Endpoint Control Register (endpoint = 14) ISOENDPT 0x2CC 32 read-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Enabled (cleared upon USB reset) 1 1 read-only BUSY_BANK Busy Bank Interrupt Enabled (cleared upon USB reset) 18 1 read-only DATAX_RX DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) (cleared upon USB reset) 6 1 read-only EPT_ENABL Endpoint Enable (cleared upon USB reset) 0 1 read-only ERR_CRC_NTR ISO CRC Error/Number of Transaction Error Interrupt Enabled (cleared upon USB reset) 13 1 read-only ERR_FLUSH Bank Flush Error Interrupt Enabled (cleared upon USB reset) 14 1 read-only ERR_FL_ISO Error Flow Interrupt Enabled (cleared upon USB reset) 12 1 read-only ERR_OVFLW Overflow Error Interrupt Enabled (cleared upon USB reset) 8 1 read-only INTDIS_DMA Interrupt Disables DMA (cleared upon USB reset) 3 1 read-only MDATA_RX MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) (cleared upon USB reset) 7 1 read-only RXRDY_TXKL Received OUT Data Interrupt Enabled (cleared upon USB reset) 9 1 read-only SHRT_PCKT Short Packet Interrupt Enabled (cleared upon USB reset) 31 1 read-only TXRDY_TRER TX Packet Ready/Transaction Error Interrupt Enabled (cleared upon USB reset) 11 1 read-only TX_COMPLT Transmitted IN Data Complete Interrupt Enabled (cleared upon USB reset) 10 1 read-only EPTCTL15 UDPHS Endpoint Control Register (endpoint = 15) 0x2EC 32 read-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Enabled (Not for CONTROL Endpoints) (cleared upon USB reset) 1 1 read-only BUSY_BANK Busy Bank Interrupt Enabled (cleared upon USB reset) 18 1 read-only EPT_ENABL Endpoint Enable (cleared upon USB reset) 0 1 read-only ERR_OVFLW Overflow Error Interrupt Enabled (cleared upon USB reset) 8 1 read-only INTDIS_DMA Interrupt Disables DMA (cleared upon USB reset) 3 1 read-only NAK_IN NAKIN Interrupt Enabled (cleared upon USB reset) 14 1 read-only NAK_OUT NAKOUT Interrupt Enabled (cleared upon USB reset) 15 1 read-only NYET_DIS NYET Disable (Only for High Speed Bulk OUT Endpoints) (cleared upon USB reset) 4 1 read-only RXRDY_TXKL Received OUT Data Interrupt Enabled (cleared upon USB reset) 9 1 read-only RX_SETUP Received SETUP Interrupt Enabled (cleared upon USB reset) 12 1 read-only SHRT_PCKT Short Packet Interrupt Enabled (cleared upon USB reset) 31 1 read-only STALL_SNT Stall Sent Interrupt Enabled (cleared upon USB reset) 13 1 read-only TXRDY TX Packet Ready Interrupt Enabled (cleared upon USB reset) 11 1 read-only TX_COMPLT Transmitted IN Data Complete Interrupt Enabled (cleared upon USB reset) 10 1 read-only EPTCTL15_ISOENDPT UDPHS Endpoint Control Register (endpoint = 15) ISOENDPT 0x2EC 32 read-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Enabled (cleared upon USB reset) 1 1 read-only BUSY_BANK Busy Bank Interrupt Enabled (cleared upon USB reset) 18 1 read-only DATAX_RX DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) (cleared upon USB reset) 6 1 read-only EPT_ENABL Endpoint Enable (cleared upon USB reset) 0 1 read-only ERR_CRC_NTR ISO CRC Error/Number of Transaction Error Interrupt Enabled (cleared upon USB reset) 13 1 read-only ERR_FLUSH Bank Flush Error Interrupt Enabled (cleared upon USB reset) 14 1 read-only ERR_FL_ISO Error Flow Interrupt Enabled (cleared upon USB reset) 12 1 read-only ERR_OVFLW Overflow Error Interrupt Enabled (cleared upon USB reset) 8 1 read-only INTDIS_DMA Interrupt Disables DMA (cleared upon USB reset) 3 1 read-only MDATA_RX MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) (cleared upon USB reset) 7 1 read-only RXRDY_TXKL Received OUT Data Interrupt Enabled (cleared upon USB reset) 9 1 read-only SHRT_PCKT Short Packet Interrupt Enabled (cleared upon USB reset) 31 1 read-only TXRDY_TRER TX Packet Ready/Transaction Error Interrupt Enabled (cleared upon USB reset) 11 1 read-only TX_COMPLT Transmitted IN Data Complete Interrupt Enabled (cleared upon USB reset) 10 1 read-only EPTCTL1_ISOENDPT UDPHS Endpoint Control Register (endpoint = 1) ISOENDPT 0x12C 32 read-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Enabled (cleared upon USB reset) 1 1 read-only BUSY_BANK Busy Bank Interrupt Enabled (cleared upon USB reset) 18 1 read-only DATAX_RX DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) (cleared upon USB reset) 6 1 read-only EPT_ENABL Endpoint Enable (cleared upon USB reset) 0 1 read-only ERR_CRC_NTR ISO CRC Error/Number of Transaction Error Interrupt Enabled (cleared upon USB reset) 13 1 read-only ERR_FLUSH Bank Flush Error Interrupt Enabled (cleared upon USB reset) 14 1 read-only ERR_FL_ISO Error Flow Interrupt Enabled (cleared upon USB reset) 12 1 read-only ERR_OVFLW Overflow Error Interrupt Enabled (cleared upon USB reset) 8 1 read-only INTDIS_DMA Interrupt Disables DMA (cleared upon USB reset) 3 1 read-only MDATA_RX MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) (cleared upon USB reset) 7 1 read-only RXRDY_TXKL Received OUT Data Interrupt Enabled (cleared upon USB reset) 9 1 read-only SHRT_PCKT Short Packet Interrupt Enabled (cleared upon USB reset) 31 1 read-only TXRDY_TRER TX Packet Ready/Transaction Error Interrupt Enabled (cleared upon USB reset) 11 1 read-only TX_COMPLT Transmitted IN Data Complete Interrupt Enabled (cleared upon USB reset) 10 1 read-only EPTCTL2 UDPHS Endpoint Control Register (endpoint = 2) 0x14C 32 read-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Enabled (Not for CONTROL Endpoints) (cleared upon USB reset) 1 1 read-only BUSY_BANK Busy Bank Interrupt Enabled (cleared upon USB reset) 18 1 read-only EPT_ENABL Endpoint Enable (cleared upon USB reset) 0 1 read-only ERR_OVFLW Overflow Error Interrupt Enabled (cleared upon USB reset) 8 1 read-only INTDIS_DMA Interrupt Disables DMA (cleared upon USB reset) 3 1 read-only NAK_IN NAKIN Interrupt Enabled (cleared upon USB reset) 14 1 read-only NAK_OUT NAKOUT Interrupt Enabled (cleared upon USB reset) 15 1 read-only NYET_DIS NYET Disable (Only for High Speed Bulk OUT Endpoints) (cleared upon USB reset) 4 1 read-only RXRDY_TXKL Received OUT Data Interrupt Enabled (cleared upon USB reset) 9 1 read-only RX_SETUP Received SETUP Interrupt Enabled (cleared upon USB reset) 12 1 read-only SHRT_PCKT Short Packet Interrupt Enabled (cleared upon USB reset) 31 1 read-only STALL_SNT Stall Sent Interrupt Enabled (cleared upon USB reset) 13 1 read-only TXRDY TX Packet Ready Interrupt Enabled (cleared upon USB reset) 11 1 read-only TX_COMPLT Transmitted IN Data Complete Interrupt Enabled (cleared upon USB reset) 10 1 read-only EPTCTL2_ISOENDPT UDPHS Endpoint Control Register (endpoint = 2) ISOENDPT 0x14C 32 read-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Enabled (cleared upon USB reset) 1 1 read-only BUSY_BANK Busy Bank Interrupt Enabled (cleared upon USB reset) 18 1 read-only DATAX_RX DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) (cleared upon USB reset) 6 1 read-only EPT_ENABL Endpoint Enable (cleared upon USB reset) 0 1 read-only ERR_CRC_NTR ISO CRC Error/Number of Transaction Error Interrupt Enabled (cleared upon USB reset) 13 1 read-only ERR_FLUSH Bank Flush Error Interrupt Enabled (cleared upon USB reset) 14 1 read-only ERR_FL_ISO Error Flow Interrupt Enabled (cleared upon USB reset) 12 1 read-only ERR_OVFLW Overflow Error Interrupt Enabled (cleared upon USB reset) 8 1 read-only INTDIS_DMA Interrupt Disables DMA (cleared upon USB reset) 3 1 read-only MDATA_RX MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) (cleared upon USB reset) 7 1 read-only RXRDY_TXKL Received OUT Data Interrupt Enabled (cleared upon USB reset) 9 1 read-only SHRT_PCKT Short Packet Interrupt Enabled (cleared upon USB reset) 31 1 read-only TXRDY_TRER TX Packet Ready/Transaction Error Interrupt Enabled (cleared upon USB reset) 11 1 read-only TX_COMPLT Transmitted IN Data Complete Interrupt Enabled (cleared upon USB reset) 10 1 read-only EPTCTL3 UDPHS Endpoint Control Register (endpoint = 3) 0x16C 32 read-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Enabled (Not for CONTROL Endpoints) (cleared upon USB reset) 1 1 read-only BUSY_BANK Busy Bank Interrupt Enabled (cleared upon USB reset) 18 1 read-only EPT_ENABL Endpoint Enable (cleared upon USB reset) 0 1 read-only ERR_OVFLW Overflow Error Interrupt Enabled (cleared upon USB reset) 8 1 read-only INTDIS_DMA Interrupt Disables DMA (cleared upon USB reset) 3 1 read-only NAK_IN NAKIN Interrupt Enabled (cleared upon USB reset) 14 1 read-only NAK_OUT NAKOUT Interrupt Enabled (cleared upon USB reset) 15 1 read-only NYET_DIS NYET Disable (Only for High Speed Bulk OUT Endpoints) (cleared upon USB reset) 4 1 read-only RXRDY_TXKL Received OUT Data Interrupt Enabled (cleared upon USB reset) 9 1 read-only RX_SETUP Received SETUP Interrupt Enabled (cleared upon USB reset) 12 1 read-only SHRT_PCKT Short Packet Interrupt Enabled (cleared upon USB reset) 31 1 read-only STALL_SNT Stall Sent Interrupt Enabled (cleared upon USB reset) 13 1 read-only TXRDY TX Packet Ready Interrupt Enabled (cleared upon USB reset) 11 1 read-only TX_COMPLT Transmitted IN Data Complete Interrupt Enabled (cleared upon USB reset) 10 1 read-only EPTCTL3_ISOENDPT UDPHS Endpoint Control Register (endpoint = 3) ISOENDPT 0x16C 32 read-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Enabled (cleared upon USB reset) 1 1 read-only BUSY_BANK Busy Bank Interrupt Enabled (cleared upon USB reset) 18 1 read-only DATAX_RX DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) (cleared upon USB reset) 6 1 read-only EPT_ENABL Endpoint Enable (cleared upon USB reset) 0 1 read-only ERR_CRC_NTR ISO CRC Error/Number of Transaction Error Interrupt Enabled (cleared upon USB reset) 13 1 read-only ERR_FLUSH Bank Flush Error Interrupt Enabled (cleared upon USB reset) 14 1 read-only ERR_FL_ISO Error Flow Interrupt Enabled (cleared upon USB reset) 12 1 read-only ERR_OVFLW Overflow Error Interrupt Enabled (cleared upon USB reset) 8 1 read-only INTDIS_DMA Interrupt Disables DMA (cleared upon USB reset) 3 1 read-only MDATA_RX MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) (cleared upon USB reset) 7 1 read-only RXRDY_TXKL Received OUT Data Interrupt Enabled (cleared upon USB reset) 9 1 read-only SHRT_PCKT Short Packet Interrupt Enabled (cleared upon USB reset) 31 1 read-only TXRDY_TRER TX Packet Ready/Transaction Error Interrupt Enabled (cleared upon USB reset) 11 1 read-only TX_COMPLT Transmitted IN Data Complete Interrupt Enabled (cleared upon USB reset) 10 1 read-only EPTCTL4 UDPHS Endpoint Control Register (endpoint = 4) 0x18C 32 read-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Enabled (Not for CONTROL Endpoints) (cleared upon USB reset) 1 1 read-only BUSY_BANK Busy Bank Interrupt Enabled (cleared upon USB reset) 18 1 read-only EPT_ENABL Endpoint Enable (cleared upon USB reset) 0 1 read-only ERR_OVFLW Overflow Error Interrupt Enabled (cleared upon USB reset) 8 1 read-only INTDIS_DMA Interrupt Disables DMA (cleared upon USB reset) 3 1 read-only NAK_IN NAKIN Interrupt Enabled (cleared upon USB reset) 14 1 read-only NAK_OUT NAKOUT Interrupt Enabled (cleared upon USB reset) 15 1 read-only NYET_DIS NYET Disable (Only for High Speed Bulk OUT Endpoints) (cleared upon USB reset) 4 1 read-only RXRDY_TXKL Received OUT Data Interrupt Enabled (cleared upon USB reset) 9 1 read-only RX_SETUP Received SETUP Interrupt Enabled (cleared upon USB reset) 12 1 read-only SHRT_PCKT Short Packet Interrupt Enabled (cleared upon USB reset) 31 1 read-only STALL_SNT Stall Sent Interrupt Enabled (cleared upon USB reset) 13 1 read-only TXRDY TX Packet Ready Interrupt Enabled (cleared upon USB reset) 11 1 read-only TX_COMPLT Transmitted IN Data Complete Interrupt Enabled (cleared upon USB reset) 10 1 read-only EPTCTL4_ISOENDPT UDPHS Endpoint Control Register (endpoint = 4) ISOENDPT 0x18C 32 read-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Enabled (cleared upon USB reset) 1 1 read-only BUSY_BANK Busy Bank Interrupt Enabled (cleared upon USB reset) 18 1 read-only DATAX_RX DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) (cleared upon USB reset) 6 1 read-only EPT_ENABL Endpoint Enable (cleared upon USB reset) 0 1 read-only ERR_CRC_NTR ISO CRC Error/Number of Transaction Error Interrupt Enabled (cleared upon USB reset) 13 1 read-only ERR_FLUSH Bank Flush Error Interrupt Enabled (cleared upon USB reset) 14 1 read-only ERR_FL_ISO Error Flow Interrupt Enabled (cleared upon USB reset) 12 1 read-only ERR_OVFLW Overflow Error Interrupt Enabled (cleared upon USB reset) 8 1 read-only INTDIS_DMA Interrupt Disables DMA (cleared upon USB reset) 3 1 read-only MDATA_RX MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) (cleared upon USB reset) 7 1 read-only RXRDY_TXKL Received OUT Data Interrupt Enabled (cleared upon USB reset) 9 1 read-only SHRT_PCKT Short Packet Interrupt Enabled (cleared upon USB reset) 31 1 read-only TXRDY_TRER TX Packet Ready/Transaction Error Interrupt Enabled (cleared upon USB reset) 11 1 read-only TX_COMPLT Transmitted IN Data Complete Interrupt Enabled (cleared upon USB reset) 10 1 read-only EPTCTL5 UDPHS Endpoint Control Register (endpoint = 5) 0x1AC 32 read-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Enabled (Not for CONTROL Endpoints) (cleared upon USB reset) 1 1 read-only BUSY_BANK Busy Bank Interrupt Enabled (cleared upon USB reset) 18 1 read-only EPT_ENABL Endpoint Enable (cleared upon USB reset) 0 1 read-only ERR_OVFLW Overflow Error Interrupt Enabled (cleared upon USB reset) 8 1 read-only INTDIS_DMA Interrupt Disables DMA (cleared upon USB reset) 3 1 read-only NAK_IN NAKIN Interrupt Enabled (cleared upon USB reset) 14 1 read-only NAK_OUT NAKOUT Interrupt Enabled (cleared upon USB reset) 15 1 read-only NYET_DIS NYET Disable (Only for High Speed Bulk OUT Endpoints) (cleared upon USB reset) 4 1 read-only RXRDY_TXKL Received OUT Data Interrupt Enabled (cleared upon USB reset) 9 1 read-only RX_SETUP Received SETUP Interrupt Enabled (cleared upon USB reset) 12 1 read-only SHRT_PCKT Short Packet Interrupt Enabled (cleared upon USB reset) 31 1 read-only STALL_SNT Stall Sent Interrupt Enabled (cleared upon USB reset) 13 1 read-only TXRDY TX Packet Ready Interrupt Enabled (cleared upon USB reset) 11 1 read-only TX_COMPLT Transmitted IN Data Complete Interrupt Enabled (cleared upon USB reset) 10 1 read-only EPTCTL5_ISOENDPT UDPHS Endpoint Control Register (endpoint = 5) ISOENDPT 0x1AC 32 read-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Enabled (cleared upon USB reset) 1 1 read-only BUSY_BANK Busy Bank Interrupt Enabled (cleared upon USB reset) 18 1 read-only DATAX_RX DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) (cleared upon USB reset) 6 1 read-only EPT_ENABL Endpoint Enable (cleared upon USB reset) 0 1 read-only ERR_CRC_NTR ISO CRC Error/Number of Transaction Error Interrupt Enabled (cleared upon USB reset) 13 1 read-only ERR_FLUSH Bank Flush Error Interrupt Enabled (cleared upon USB reset) 14 1 read-only ERR_FL_ISO Error Flow Interrupt Enabled (cleared upon USB reset) 12 1 read-only ERR_OVFLW Overflow Error Interrupt Enabled (cleared upon USB reset) 8 1 read-only INTDIS_DMA Interrupt Disables DMA (cleared upon USB reset) 3 1 read-only MDATA_RX MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) (cleared upon USB reset) 7 1 read-only RXRDY_TXKL Received OUT Data Interrupt Enabled (cleared upon USB reset) 9 1 read-only SHRT_PCKT Short Packet Interrupt Enabled (cleared upon USB reset) 31 1 read-only TXRDY_TRER TX Packet Ready/Transaction Error Interrupt Enabled (cleared upon USB reset) 11 1 read-only TX_COMPLT Transmitted IN Data Complete Interrupt Enabled (cleared upon USB reset) 10 1 read-only EPTCTL6 UDPHS Endpoint Control Register (endpoint = 6) 0x1CC 32 read-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Enabled (Not for CONTROL Endpoints) (cleared upon USB reset) 1 1 read-only BUSY_BANK Busy Bank Interrupt Enabled (cleared upon USB reset) 18 1 read-only EPT_ENABL Endpoint Enable (cleared upon USB reset) 0 1 read-only ERR_OVFLW Overflow Error Interrupt Enabled (cleared upon USB reset) 8 1 read-only INTDIS_DMA Interrupt Disables DMA (cleared upon USB reset) 3 1 read-only NAK_IN NAKIN Interrupt Enabled (cleared upon USB reset) 14 1 read-only NAK_OUT NAKOUT Interrupt Enabled (cleared upon USB reset) 15 1 read-only NYET_DIS NYET Disable (Only for High Speed Bulk OUT Endpoints) (cleared upon USB reset) 4 1 read-only RXRDY_TXKL Received OUT Data Interrupt Enabled (cleared upon USB reset) 9 1 read-only RX_SETUP Received SETUP Interrupt Enabled (cleared upon USB reset) 12 1 read-only SHRT_PCKT Short Packet Interrupt Enabled (cleared upon USB reset) 31 1 read-only STALL_SNT Stall Sent Interrupt Enabled (cleared upon USB reset) 13 1 read-only TXRDY TX Packet Ready Interrupt Enabled (cleared upon USB reset) 11 1 read-only TX_COMPLT Transmitted IN Data Complete Interrupt Enabled (cleared upon USB reset) 10 1 read-only EPTCTL6_ISOENDPT UDPHS Endpoint Control Register (endpoint = 6) ISOENDPT 0x1CC 32 read-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Enabled (cleared upon USB reset) 1 1 read-only BUSY_BANK Busy Bank Interrupt Enabled (cleared upon USB reset) 18 1 read-only DATAX_RX DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) (cleared upon USB reset) 6 1 read-only EPT_ENABL Endpoint Enable (cleared upon USB reset) 0 1 read-only ERR_CRC_NTR ISO CRC Error/Number of Transaction Error Interrupt Enabled (cleared upon USB reset) 13 1 read-only ERR_FLUSH Bank Flush Error Interrupt Enabled (cleared upon USB reset) 14 1 read-only ERR_FL_ISO Error Flow Interrupt Enabled (cleared upon USB reset) 12 1 read-only ERR_OVFLW Overflow Error Interrupt Enabled (cleared upon USB reset) 8 1 read-only INTDIS_DMA Interrupt Disables DMA (cleared upon USB reset) 3 1 read-only MDATA_RX MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) (cleared upon USB reset) 7 1 read-only RXRDY_TXKL Received OUT Data Interrupt Enabled (cleared upon USB reset) 9 1 read-only SHRT_PCKT Short Packet Interrupt Enabled (cleared upon USB reset) 31 1 read-only TXRDY_TRER TX Packet Ready/Transaction Error Interrupt Enabled (cleared upon USB reset) 11 1 read-only TX_COMPLT Transmitted IN Data Complete Interrupt Enabled (cleared upon USB reset) 10 1 read-only EPTCTL7 UDPHS Endpoint Control Register (endpoint = 7) 0x1EC 32 read-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Enabled (Not for CONTROL Endpoints) (cleared upon USB reset) 1 1 read-only BUSY_BANK Busy Bank Interrupt Enabled (cleared upon USB reset) 18 1 read-only EPT_ENABL Endpoint Enable (cleared upon USB reset) 0 1 read-only ERR_OVFLW Overflow Error Interrupt Enabled (cleared upon USB reset) 8 1 read-only INTDIS_DMA Interrupt Disables DMA (cleared upon USB reset) 3 1 read-only NAK_IN NAKIN Interrupt Enabled (cleared upon USB reset) 14 1 read-only NAK_OUT NAKOUT Interrupt Enabled (cleared upon USB reset) 15 1 read-only NYET_DIS NYET Disable (Only for High Speed Bulk OUT Endpoints) (cleared upon USB reset) 4 1 read-only RXRDY_TXKL Received OUT Data Interrupt Enabled (cleared upon USB reset) 9 1 read-only RX_SETUP Received SETUP Interrupt Enabled (cleared upon USB reset) 12 1 read-only SHRT_PCKT Short Packet Interrupt Enabled (cleared upon USB reset) 31 1 read-only STALL_SNT Stall Sent Interrupt Enabled (cleared upon USB reset) 13 1 read-only TXRDY TX Packet Ready Interrupt Enabled (cleared upon USB reset) 11 1 read-only TX_COMPLT Transmitted IN Data Complete Interrupt Enabled (cleared upon USB reset) 10 1 read-only EPTCTL7_ISOENDPT UDPHS Endpoint Control Register (endpoint = 7) ISOENDPT 0x1EC 32 read-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Enabled (cleared upon USB reset) 1 1 read-only BUSY_BANK Busy Bank Interrupt Enabled (cleared upon USB reset) 18 1 read-only DATAX_RX DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) (cleared upon USB reset) 6 1 read-only EPT_ENABL Endpoint Enable (cleared upon USB reset) 0 1 read-only ERR_CRC_NTR ISO CRC Error/Number of Transaction Error Interrupt Enabled (cleared upon USB reset) 13 1 read-only ERR_FLUSH Bank Flush Error Interrupt Enabled (cleared upon USB reset) 14 1 read-only ERR_FL_ISO Error Flow Interrupt Enabled (cleared upon USB reset) 12 1 read-only ERR_OVFLW Overflow Error Interrupt Enabled (cleared upon USB reset) 8 1 read-only INTDIS_DMA Interrupt Disables DMA (cleared upon USB reset) 3 1 read-only MDATA_RX MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) (cleared upon USB reset) 7 1 read-only RXRDY_TXKL Received OUT Data Interrupt Enabled (cleared upon USB reset) 9 1 read-only SHRT_PCKT Short Packet Interrupt Enabled (cleared upon USB reset) 31 1 read-only TXRDY_TRER TX Packet Ready/Transaction Error Interrupt Enabled (cleared upon USB reset) 11 1 read-only TX_COMPLT Transmitted IN Data Complete Interrupt Enabled (cleared upon USB reset) 10 1 read-only EPTCTL8 UDPHS Endpoint Control Register (endpoint = 8) 0x20C 32 read-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Enabled (Not for CONTROL Endpoints) (cleared upon USB reset) 1 1 read-only BUSY_BANK Busy Bank Interrupt Enabled (cleared upon USB reset) 18 1 read-only EPT_ENABL Endpoint Enable (cleared upon USB reset) 0 1 read-only ERR_OVFLW Overflow Error Interrupt Enabled (cleared upon USB reset) 8 1 read-only INTDIS_DMA Interrupt Disables DMA (cleared upon USB reset) 3 1 read-only NAK_IN NAKIN Interrupt Enabled (cleared upon USB reset) 14 1 read-only NAK_OUT NAKOUT Interrupt Enabled (cleared upon USB reset) 15 1 read-only NYET_DIS NYET Disable (Only for High Speed Bulk OUT Endpoints) (cleared upon USB reset) 4 1 read-only RXRDY_TXKL Received OUT Data Interrupt Enabled (cleared upon USB reset) 9 1 read-only RX_SETUP Received SETUP Interrupt Enabled (cleared upon USB reset) 12 1 read-only SHRT_PCKT Short Packet Interrupt Enabled (cleared upon USB reset) 31 1 read-only STALL_SNT Stall Sent Interrupt Enabled (cleared upon USB reset) 13 1 read-only TXRDY TX Packet Ready Interrupt Enabled (cleared upon USB reset) 11 1 read-only TX_COMPLT Transmitted IN Data Complete Interrupt Enabled (cleared upon USB reset) 10 1 read-only EPTCTL8_ISOENDPT UDPHS Endpoint Control Register (endpoint = 8) ISOENDPT 0x20C 32 read-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Enabled (cleared upon USB reset) 1 1 read-only BUSY_BANK Busy Bank Interrupt Enabled (cleared upon USB reset) 18 1 read-only DATAX_RX DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) (cleared upon USB reset) 6 1 read-only EPT_ENABL Endpoint Enable (cleared upon USB reset) 0 1 read-only ERR_CRC_NTR ISO CRC Error/Number of Transaction Error Interrupt Enabled (cleared upon USB reset) 13 1 read-only ERR_FLUSH Bank Flush Error Interrupt Enabled (cleared upon USB reset) 14 1 read-only ERR_FL_ISO Error Flow Interrupt Enabled (cleared upon USB reset) 12 1 read-only ERR_OVFLW Overflow Error Interrupt Enabled (cleared upon USB reset) 8 1 read-only INTDIS_DMA Interrupt Disables DMA (cleared upon USB reset) 3 1 read-only MDATA_RX MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) (cleared upon USB reset) 7 1 read-only RXRDY_TXKL Received OUT Data Interrupt Enabled (cleared upon USB reset) 9 1 read-only SHRT_PCKT Short Packet Interrupt Enabled (cleared upon USB reset) 31 1 read-only TXRDY_TRER TX Packet Ready/Transaction Error Interrupt Enabled (cleared upon USB reset) 11 1 read-only TX_COMPLT Transmitted IN Data Complete Interrupt Enabled (cleared upon USB reset) 10 1 read-only EPTCTL9 UDPHS Endpoint Control Register (endpoint = 9) 0x22C 32 read-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Enabled (Not for CONTROL Endpoints) (cleared upon USB reset) 1 1 read-only BUSY_BANK Busy Bank Interrupt Enabled (cleared upon USB reset) 18 1 read-only EPT_ENABL Endpoint Enable (cleared upon USB reset) 0 1 read-only ERR_OVFLW Overflow Error Interrupt Enabled (cleared upon USB reset) 8 1 read-only INTDIS_DMA Interrupt Disables DMA (cleared upon USB reset) 3 1 read-only NAK_IN NAKIN Interrupt Enabled (cleared upon USB reset) 14 1 read-only NAK_OUT NAKOUT Interrupt Enabled (cleared upon USB reset) 15 1 read-only NYET_DIS NYET Disable (Only for High Speed Bulk OUT Endpoints) (cleared upon USB reset) 4 1 read-only RXRDY_TXKL Received OUT Data Interrupt Enabled (cleared upon USB reset) 9 1 read-only RX_SETUP Received SETUP Interrupt Enabled (cleared upon USB reset) 12 1 read-only SHRT_PCKT Short Packet Interrupt Enabled (cleared upon USB reset) 31 1 read-only STALL_SNT Stall Sent Interrupt Enabled (cleared upon USB reset) 13 1 read-only TXRDY TX Packet Ready Interrupt Enabled (cleared upon USB reset) 11 1 read-only TX_COMPLT Transmitted IN Data Complete Interrupt Enabled (cleared upon USB reset) 10 1 read-only EPTCTL9_ISOENDPT UDPHS Endpoint Control Register (endpoint = 9) ISOENDPT 0x22C 32 read-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Enabled (cleared upon USB reset) 1 1 read-only BUSY_BANK Busy Bank Interrupt Enabled (cleared upon USB reset) 18 1 read-only DATAX_RX DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) (cleared upon USB reset) 6 1 read-only EPT_ENABL Endpoint Enable (cleared upon USB reset) 0 1 read-only ERR_CRC_NTR ISO CRC Error/Number of Transaction Error Interrupt Enabled (cleared upon USB reset) 13 1 read-only ERR_FLUSH Bank Flush Error Interrupt Enabled (cleared upon USB reset) 14 1 read-only ERR_FL_ISO Error Flow Interrupt Enabled (cleared upon USB reset) 12 1 read-only ERR_OVFLW Overflow Error Interrupt Enabled (cleared upon USB reset) 8 1 read-only INTDIS_DMA Interrupt Disables DMA (cleared upon USB reset) 3 1 read-only MDATA_RX MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) (cleared upon USB reset) 7 1 read-only RXRDY_TXKL Received OUT Data Interrupt Enabled (cleared upon USB reset) 9 1 read-only SHRT_PCKT Short Packet Interrupt Enabled (cleared upon USB reset) 31 1 read-only TXRDY_TRER TX Packet Ready/Transaction Error Interrupt Enabled (cleared upon USB reset) 11 1 read-only TX_COMPLT Transmitted IN Data Complete Interrupt Enabled (cleared upon USB reset) 10 1 read-only EPTCTLDIS0 UDPHS Endpoint Control Disable Register (endpoint = 0) 0x108 32 write-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Disable 1 1 write-only BUSY_BANK Busy Bank Interrupt Disable 18 1 write-only EPT_DISABL Endpoint Disable 0 1 write-only ERR_OVFLW Overflow Error Interrupt Disable 8 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only NAK_IN NAKIN Interrupt Disable 14 1 write-only NAK_OUT NAKOUT Interrupt Disable 15 1 write-only NYET_DIS NYET Enable (Only for High Speed Bulk OUT endpoints) 4 1 write-only RXRDY_TXKL Received OUT Data Interrupt Disable 9 1 write-only RX_SETUP Received SETUP Interrupt Disable 12 1 write-only SHRT_PCKT Short Packet Interrupt Disable 31 1 write-only STALL_SNT Stall Sent Interrupt Disable 13 1 write-only TXRDY TX Packet Ready Interrupt Disable 11 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Disable 10 1 write-only EPTCTLDIS0_ISOENDPT UDPHS Endpoint Control Disable Register (endpoint = 0) ISOENDPT 0x108 32 write-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Disable 1 1 write-only BUSY_BANK Busy Bank Interrupt Disable 18 1 write-only DATAX_RX DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) 6 1 write-only EPT_DISABL Endpoint Disable 0 1 write-only ERR_CRC_NTR ISO CRC Error/Number of Transaction Error Interrupt Disable 13 1 write-only ERR_FLUSH bank flush error Interrupt Disable 14 1 write-only ERR_FL_ISO Error Flow Interrupt Disable 12 1 write-only ERR_OVFLW Overflow Error Interrupt Disable 8 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only MDATA_RX MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) 7 1 write-only RXRDY_TXKL Received OUT Data Interrupt Disable 9 1 write-only SHRT_PCKT Short Packet Interrupt Disable 31 1 write-only TXRDY_TRER TX Packet Ready/Transaction Error Interrupt Disable 11 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Disable 10 1 write-only EPTCTLDIS1 UDPHS Endpoint Control Disable Register (endpoint = 1) 0x128 32 write-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Disable 1 1 write-only BUSY_BANK Busy Bank Interrupt Disable 18 1 write-only EPT_DISABL Endpoint Disable 0 1 write-only ERR_OVFLW Overflow Error Interrupt Disable 8 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only NAK_IN NAKIN Interrupt Disable 14 1 write-only NAK_OUT NAKOUT Interrupt Disable 15 1 write-only NYET_DIS NYET Enable (Only for High Speed Bulk OUT endpoints) 4 1 write-only RXRDY_TXKL Received OUT Data Interrupt Disable 9 1 write-only RX_SETUP Received SETUP Interrupt Disable 12 1 write-only SHRT_PCKT Short Packet Interrupt Disable 31 1 write-only STALL_SNT Stall Sent Interrupt Disable 13 1 write-only TXRDY TX Packet Ready Interrupt Disable 11 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Disable 10 1 write-only EPTCTLDIS10 UDPHS Endpoint Control Disable Register (endpoint = 10) 0x248 32 write-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Disable 1 1 write-only BUSY_BANK Busy Bank Interrupt Disable 18 1 write-only EPT_DISABL Endpoint Disable 0 1 write-only ERR_OVFLW Overflow Error Interrupt Disable 8 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only NAK_IN NAKIN Interrupt Disable 14 1 write-only NAK_OUT NAKOUT Interrupt Disable 15 1 write-only NYET_DIS NYET Enable (Only for High Speed Bulk OUT endpoints) 4 1 write-only RXRDY_TXKL Received OUT Data Interrupt Disable 9 1 write-only RX_SETUP Received SETUP Interrupt Disable 12 1 write-only SHRT_PCKT Short Packet Interrupt Disable 31 1 write-only STALL_SNT Stall Sent Interrupt Disable 13 1 write-only TXRDY TX Packet Ready Interrupt Disable 11 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Disable 10 1 write-only EPTCTLDIS10_ISOENDPT UDPHS Endpoint Control Disable Register (endpoint = 10) ISOENDPT 0x248 32 write-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Disable 1 1 write-only BUSY_BANK Busy Bank Interrupt Disable 18 1 write-only DATAX_RX DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) 6 1 write-only EPT_DISABL Endpoint Disable 0 1 write-only ERR_CRC_NTR ISO CRC Error/Number of Transaction Error Interrupt Disable 13 1 write-only ERR_FLUSH bank flush error Interrupt Disable 14 1 write-only ERR_FL_ISO Error Flow Interrupt Disable 12 1 write-only ERR_OVFLW Overflow Error Interrupt Disable 8 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only MDATA_RX MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) 7 1 write-only RXRDY_TXKL Received OUT Data Interrupt Disable 9 1 write-only SHRT_PCKT Short Packet Interrupt Disable 31 1 write-only TXRDY_TRER TX Packet Ready/Transaction Error Interrupt Disable 11 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Disable 10 1 write-only EPTCTLDIS11 UDPHS Endpoint Control Disable Register (endpoint = 11) 0x268 32 write-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Disable 1 1 write-only BUSY_BANK Busy Bank Interrupt Disable 18 1 write-only EPT_DISABL Endpoint Disable 0 1 write-only ERR_OVFLW Overflow Error Interrupt Disable 8 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only NAK_IN NAKIN Interrupt Disable 14 1 write-only NAK_OUT NAKOUT Interrupt Disable 15 1 write-only NYET_DIS NYET Enable (Only for High Speed Bulk OUT endpoints) 4 1 write-only RXRDY_TXKL Received OUT Data Interrupt Disable 9 1 write-only RX_SETUP Received SETUP Interrupt Disable 12 1 write-only SHRT_PCKT Short Packet Interrupt Disable 31 1 write-only STALL_SNT Stall Sent Interrupt Disable 13 1 write-only TXRDY TX Packet Ready Interrupt Disable 11 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Disable 10 1 write-only EPTCTLDIS11_ISOENDPT UDPHS Endpoint Control Disable Register (endpoint = 11) ISOENDPT 0x268 32 write-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Disable 1 1 write-only BUSY_BANK Busy Bank Interrupt Disable 18 1 write-only DATAX_RX DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) 6 1 write-only EPT_DISABL Endpoint Disable 0 1 write-only ERR_CRC_NTR ISO CRC Error/Number of Transaction Error Interrupt Disable 13 1 write-only ERR_FLUSH bank flush error Interrupt Disable 14 1 write-only ERR_FL_ISO Error Flow Interrupt Disable 12 1 write-only ERR_OVFLW Overflow Error Interrupt Disable 8 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only MDATA_RX MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) 7 1 write-only RXRDY_TXKL Received OUT Data Interrupt Disable 9 1 write-only SHRT_PCKT Short Packet Interrupt Disable 31 1 write-only TXRDY_TRER TX Packet Ready/Transaction Error Interrupt Disable 11 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Disable 10 1 write-only EPTCTLDIS12 UDPHS Endpoint Control Disable Register (endpoint = 12) 0x288 32 write-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Disable 1 1 write-only BUSY_BANK Busy Bank Interrupt Disable 18 1 write-only EPT_DISABL Endpoint Disable 0 1 write-only ERR_OVFLW Overflow Error Interrupt Disable 8 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only NAK_IN NAKIN Interrupt Disable 14 1 write-only NAK_OUT NAKOUT Interrupt Disable 15 1 write-only NYET_DIS NYET Enable (Only for High Speed Bulk OUT endpoints) 4 1 write-only RXRDY_TXKL Received OUT Data Interrupt Disable 9 1 write-only RX_SETUP Received SETUP Interrupt Disable 12 1 write-only SHRT_PCKT Short Packet Interrupt Disable 31 1 write-only STALL_SNT Stall Sent Interrupt Disable 13 1 write-only TXRDY TX Packet Ready Interrupt Disable 11 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Disable 10 1 write-only EPTCTLDIS12_ISOENDPT UDPHS Endpoint Control Disable Register (endpoint = 12) ISOENDPT 0x288 32 write-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Disable 1 1 write-only BUSY_BANK Busy Bank Interrupt Disable 18 1 write-only DATAX_RX DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) 6 1 write-only EPT_DISABL Endpoint Disable 0 1 write-only ERR_CRC_NTR ISO CRC Error/Number of Transaction Error Interrupt Disable 13 1 write-only ERR_FLUSH bank flush error Interrupt Disable 14 1 write-only ERR_FL_ISO Error Flow Interrupt Disable 12 1 write-only ERR_OVFLW Overflow Error Interrupt Disable 8 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only MDATA_RX MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) 7 1 write-only RXRDY_TXKL Received OUT Data Interrupt Disable 9 1 write-only SHRT_PCKT Short Packet Interrupt Disable 31 1 write-only TXRDY_TRER TX Packet Ready/Transaction Error Interrupt Disable 11 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Disable 10 1 write-only EPTCTLDIS13 UDPHS Endpoint Control Disable Register (endpoint = 13) 0x2A8 32 write-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Disable 1 1 write-only BUSY_BANK Busy Bank Interrupt Disable 18 1 write-only EPT_DISABL Endpoint Disable 0 1 write-only ERR_OVFLW Overflow Error Interrupt Disable 8 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only NAK_IN NAKIN Interrupt Disable 14 1 write-only NAK_OUT NAKOUT Interrupt Disable 15 1 write-only NYET_DIS NYET Enable (Only for High Speed Bulk OUT endpoints) 4 1 write-only RXRDY_TXKL Received OUT Data Interrupt Disable 9 1 write-only RX_SETUP Received SETUP Interrupt Disable 12 1 write-only SHRT_PCKT Short Packet Interrupt Disable 31 1 write-only STALL_SNT Stall Sent Interrupt Disable 13 1 write-only TXRDY TX Packet Ready Interrupt Disable 11 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Disable 10 1 write-only EPTCTLDIS13_ISOENDPT UDPHS Endpoint Control Disable Register (endpoint = 13) ISOENDPT 0x2A8 32 write-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Disable 1 1 write-only BUSY_BANK Busy Bank Interrupt Disable 18 1 write-only DATAX_RX DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) 6 1 write-only EPT_DISABL Endpoint Disable 0 1 write-only ERR_CRC_NTR ISO CRC Error/Number of Transaction Error Interrupt Disable 13 1 write-only ERR_FLUSH bank flush error Interrupt Disable 14 1 write-only ERR_FL_ISO Error Flow Interrupt Disable 12 1 write-only ERR_OVFLW Overflow Error Interrupt Disable 8 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only MDATA_RX MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) 7 1 write-only RXRDY_TXKL Received OUT Data Interrupt Disable 9 1 write-only SHRT_PCKT Short Packet Interrupt Disable 31 1 write-only TXRDY_TRER TX Packet Ready/Transaction Error Interrupt Disable 11 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Disable 10 1 write-only EPTCTLDIS14 UDPHS Endpoint Control Disable Register (endpoint = 14) 0x2C8 32 write-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Disable 1 1 write-only BUSY_BANK Busy Bank Interrupt Disable 18 1 write-only EPT_DISABL Endpoint Disable 0 1 write-only ERR_OVFLW Overflow Error Interrupt Disable 8 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only NAK_IN NAKIN Interrupt Disable 14 1 write-only NAK_OUT NAKOUT Interrupt Disable 15 1 write-only NYET_DIS NYET Enable (Only for High Speed Bulk OUT endpoints) 4 1 write-only RXRDY_TXKL Received OUT Data Interrupt Disable 9 1 write-only RX_SETUP Received SETUP Interrupt Disable 12 1 write-only SHRT_PCKT Short Packet Interrupt Disable 31 1 write-only STALL_SNT Stall Sent Interrupt Disable 13 1 write-only TXRDY TX Packet Ready Interrupt Disable 11 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Disable 10 1 write-only EPTCTLDIS14_ISOENDPT UDPHS Endpoint Control Disable Register (endpoint = 14) ISOENDPT 0x2C8 32 write-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Disable 1 1 write-only BUSY_BANK Busy Bank Interrupt Disable 18 1 write-only DATAX_RX DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) 6 1 write-only EPT_DISABL Endpoint Disable 0 1 write-only ERR_CRC_NTR ISO CRC Error/Number of Transaction Error Interrupt Disable 13 1 write-only ERR_FLUSH bank flush error Interrupt Disable 14 1 write-only ERR_FL_ISO Error Flow Interrupt Disable 12 1 write-only ERR_OVFLW Overflow Error Interrupt Disable 8 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only MDATA_RX MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) 7 1 write-only RXRDY_TXKL Received OUT Data Interrupt Disable 9 1 write-only SHRT_PCKT Short Packet Interrupt Disable 31 1 write-only TXRDY_TRER TX Packet Ready/Transaction Error Interrupt Disable 11 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Disable 10 1 write-only EPTCTLDIS15 UDPHS Endpoint Control Disable Register (endpoint = 15) 0x2E8 32 write-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Disable 1 1 write-only BUSY_BANK Busy Bank Interrupt Disable 18 1 write-only EPT_DISABL Endpoint Disable 0 1 write-only ERR_OVFLW Overflow Error Interrupt Disable 8 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only NAK_IN NAKIN Interrupt Disable 14 1 write-only NAK_OUT NAKOUT Interrupt Disable 15 1 write-only NYET_DIS NYET Enable (Only for High Speed Bulk OUT endpoints) 4 1 write-only RXRDY_TXKL Received OUT Data Interrupt Disable 9 1 write-only RX_SETUP Received SETUP Interrupt Disable 12 1 write-only SHRT_PCKT Short Packet Interrupt Disable 31 1 write-only STALL_SNT Stall Sent Interrupt Disable 13 1 write-only TXRDY TX Packet Ready Interrupt Disable 11 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Disable 10 1 write-only EPTCTLDIS15_ISOENDPT UDPHS Endpoint Control Disable Register (endpoint = 15) ISOENDPT 0x2E8 32 write-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Disable 1 1 write-only BUSY_BANK Busy Bank Interrupt Disable 18 1 write-only DATAX_RX DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) 6 1 write-only EPT_DISABL Endpoint Disable 0 1 write-only ERR_CRC_NTR ISO CRC Error/Number of Transaction Error Interrupt Disable 13 1 write-only ERR_FLUSH bank flush error Interrupt Disable 14 1 write-only ERR_FL_ISO Error Flow Interrupt Disable 12 1 write-only ERR_OVFLW Overflow Error Interrupt Disable 8 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only MDATA_RX MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) 7 1 write-only RXRDY_TXKL Received OUT Data Interrupt Disable 9 1 write-only SHRT_PCKT Short Packet Interrupt Disable 31 1 write-only TXRDY_TRER TX Packet Ready/Transaction Error Interrupt Disable 11 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Disable 10 1 write-only EPTCTLDIS1_ISOENDPT UDPHS Endpoint Control Disable Register (endpoint = 1) ISOENDPT 0x128 32 write-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Disable 1 1 write-only BUSY_BANK Busy Bank Interrupt Disable 18 1 write-only DATAX_RX DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) 6 1 write-only EPT_DISABL Endpoint Disable 0 1 write-only ERR_CRC_NTR ISO CRC Error/Number of Transaction Error Interrupt Disable 13 1 write-only ERR_FLUSH bank flush error Interrupt Disable 14 1 write-only ERR_FL_ISO Error Flow Interrupt Disable 12 1 write-only ERR_OVFLW Overflow Error Interrupt Disable 8 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only MDATA_RX MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) 7 1 write-only RXRDY_TXKL Received OUT Data Interrupt Disable 9 1 write-only SHRT_PCKT Short Packet Interrupt Disable 31 1 write-only TXRDY_TRER TX Packet Ready/Transaction Error Interrupt Disable 11 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Disable 10 1 write-only EPTCTLDIS2 UDPHS Endpoint Control Disable Register (endpoint = 2) 0x148 32 write-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Disable 1 1 write-only BUSY_BANK Busy Bank Interrupt Disable 18 1 write-only EPT_DISABL Endpoint Disable 0 1 write-only ERR_OVFLW Overflow Error Interrupt Disable 8 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only NAK_IN NAKIN Interrupt Disable 14 1 write-only NAK_OUT NAKOUT Interrupt Disable 15 1 write-only NYET_DIS NYET Enable (Only for High Speed Bulk OUT endpoints) 4 1 write-only RXRDY_TXKL Received OUT Data Interrupt Disable 9 1 write-only RX_SETUP Received SETUP Interrupt Disable 12 1 write-only SHRT_PCKT Short Packet Interrupt Disable 31 1 write-only STALL_SNT Stall Sent Interrupt Disable 13 1 write-only TXRDY TX Packet Ready Interrupt Disable 11 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Disable 10 1 write-only EPTCTLDIS2_ISOENDPT UDPHS Endpoint Control Disable Register (endpoint = 2) ISOENDPT 0x148 32 write-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Disable 1 1 write-only BUSY_BANK Busy Bank Interrupt Disable 18 1 write-only DATAX_RX DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) 6 1 write-only EPT_DISABL Endpoint Disable 0 1 write-only ERR_CRC_NTR ISO CRC Error/Number of Transaction Error Interrupt Disable 13 1 write-only ERR_FLUSH bank flush error Interrupt Disable 14 1 write-only ERR_FL_ISO Error Flow Interrupt Disable 12 1 write-only ERR_OVFLW Overflow Error Interrupt Disable 8 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only MDATA_RX MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) 7 1 write-only RXRDY_TXKL Received OUT Data Interrupt Disable 9 1 write-only SHRT_PCKT Short Packet Interrupt Disable 31 1 write-only TXRDY_TRER TX Packet Ready/Transaction Error Interrupt Disable 11 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Disable 10 1 write-only EPTCTLDIS3 UDPHS Endpoint Control Disable Register (endpoint = 3) 0x168 32 write-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Disable 1 1 write-only BUSY_BANK Busy Bank Interrupt Disable 18 1 write-only EPT_DISABL Endpoint Disable 0 1 write-only ERR_OVFLW Overflow Error Interrupt Disable 8 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only NAK_IN NAKIN Interrupt Disable 14 1 write-only NAK_OUT NAKOUT Interrupt Disable 15 1 write-only NYET_DIS NYET Enable (Only for High Speed Bulk OUT endpoints) 4 1 write-only RXRDY_TXKL Received OUT Data Interrupt Disable 9 1 write-only RX_SETUP Received SETUP Interrupt Disable 12 1 write-only SHRT_PCKT Short Packet Interrupt Disable 31 1 write-only STALL_SNT Stall Sent Interrupt Disable 13 1 write-only TXRDY TX Packet Ready Interrupt Disable 11 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Disable 10 1 write-only EPTCTLDIS3_ISOENDPT UDPHS Endpoint Control Disable Register (endpoint = 3) ISOENDPT 0x168 32 write-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Disable 1 1 write-only BUSY_BANK Busy Bank Interrupt Disable 18 1 write-only DATAX_RX DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) 6 1 write-only EPT_DISABL Endpoint Disable 0 1 write-only ERR_CRC_NTR ISO CRC Error/Number of Transaction Error Interrupt Disable 13 1 write-only ERR_FLUSH bank flush error Interrupt Disable 14 1 write-only ERR_FL_ISO Error Flow Interrupt Disable 12 1 write-only ERR_OVFLW Overflow Error Interrupt Disable 8 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only MDATA_RX MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) 7 1 write-only RXRDY_TXKL Received OUT Data Interrupt Disable 9 1 write-only SHRT_PCKT Short Packet Interrupt Disable 31 1 write-only TXRDY_TRER TX Packet Ready/Transaction Error Interrupt Disable 11 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Disable 10 1 write-only EPTCTLDIS4 UDPHS Endpoint Control Disable Register (endpoint = 4) 0x188 32 write-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Disable 1 1 write-only BUSY_BANK Busy Bank Interrupt Disable 18 1 write-only EPT_DISABL Endpoint Disable 0 1 write-only ERR_OVFLW Overflow Error Interrupt Disable 8 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only NAK_IN NAKIN Interrupt Disable 14 1 write-only NAK_OUT NAKOUT Interrupt Disable 15 1 write-only NYET_DIS NYET Enable (Only for High Speed Bulk OUT endpoints) 4 1 write-only RXRDY_TXKL Received OUT Data Interrupt Disable 9 1 write-only RX_SETUP Received SETUP Interrupt Disable 12 1 write-only SHRT_PCKT Short Packet Interrupt Disable 31 1 write-only STALL_SNT Stall Sent Interrupt Disable 13 1 write-only TXRDY TX Packet Ready Interrupt Disable 11 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Disable 10 1 write-only EPTCTLDIS4_ISOENDPT UDPHS Endpoint Control Disable Register (endpoint = 4) ISOENDPT 0x188 32 write-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Disable 1 1 write-only BUSY_BANK Busy Bank Interrupt Disable 18 1 write-only DATAX_RX DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) 6 1 write-only EPT_DISABL Endpoint Disable 0 1 write-only ERR_CRC_NTR ISO CRC Error/Number of Transaction Error Interrupt Disable 13 1 write-only ERR_FLUSH bank flush error Interrupt Disable 14 1 write-only ERR_FL_ISO Error Flow Interrupt Disable 12 1 write-only ERR_OVFLW Overflow Error Interrupt Disable 8 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only MDATA_RX MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) 7 1 write-only RXRDY_TXKL Received OUT Data Interrupt Disable 9 1 write-only SHRT_PCKT Short Packet Interrupt Disable 31 1 write-only TXRDY_TRER TX Packet Ready/Transaction Error Interrupt Disable 11 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Disable 10 1 write-only EPTCTLDIS5 UDPHS Endpoint Control Disable Register (endpoint = 5) 0x1A8 32 write-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Disable 1 1 write-only BUSY_BANK Busy Bank Interrupt Disable 18 1 write-only EPT_DISABL Endpoint Disable 0 1 write-only ERR_OVFLW Overflow Error Interrupt Disable 8 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only NAK_IN NAKIN Interrupt Disable 14 1 write-only NAK_OUT NAKOUT Interrupt Disable 15 1 write-only NYET_DIS NYET Enable (Only for High Speed Bulk OUT endpoints) 4 1 write-only RXRDY_TXKL Received OUT Data Interrupt Disable 9 1 write-only RX_SETUP Received SETUP Interrupt Disable 12 1 write-only SHRT_PCKT Short Packet Interrupt Disable 31 1 write-only STALL_SNT Stall Sent Interrupt Disable 13 1 write-only TXRDY TX Packet Ready Interrupt Disable 11 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Disable 10 1 write-only EPTCTLDIS5_ISOENDPT UDPHS Endpoint Control Disable Register (endpoint = 5) ISOENDPT 0x1A8 32 write-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Disable 1 1 write-only BUSY_BANK Busy Bank Interrupt Disable 18 1 write-only DATAX_RX DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) 6 1 write-only EPT_DISABL Endpoint Disable 0 1 write-only ERR_CRC_NTR ISO CRC Error/Number of Transaction Error Interrupt Disable 13 1 write-only ERR_FLUSH bank flush error Interrupt Disable 14 1 write-only ERR_FL_ISO Error Flow Interrupt Disable 12 1 write-only ERR_OVFLW Overflow Error Interrupt Disable 8 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only MDATA_RX MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) 7 1 write-only RXRDY_TXKL Received OUT Data Interrupt Disable 9 1 write-only SHRT_PCKT Short Packet Interrupt Disable 31 1 write-only TXRDY_TRER TX Packet Ready/Transaction Error Interrupt Disable 11 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Disable 10 1 write-only EPTCTLDIS6 UDPHS Endpoint Control Disable Register (endpoint = 6) 0x1C8 32 write-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Disable 1 1 write-only BUSY_BANK Busy Bank Interrupt Disable 18 1 write-only EPT_DISABL Endpoint Disable 0 1 write-only ERR_OVFLW Overflow Error Interrupt Disable 8 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only NAK_IN NAKIN Interrupt Disable 14 1 write-only NAK_OUT NAKOUT Interrupt Disable 15 1 write-only NYET_DIS NYET Enable (Only for High Speed Bulk OUT endpoints) 4 1 write-only RXRDY_TXKL Received OUT Data Interrupt Disable 9 1 write-only RX_SETUP Received SETUP Interrupt Disable 12 1 write-only SHRT_PCKT Short Packet Interrupt Disable 31 1 write-only STALL_SNT Stall Sent Interrupt Disable 13 1 write-only TXRDY TX Packet Ready Interrupt Disable 11 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Disable 10 1 write-only EPTCTLDIS6_ISOENDPT UDPHS Endpoint Control Disable Register (endpoint = 6) ISOENDPT 0x1C8 32 write-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Disable 1 1 write-only BUSY_BANK Busy Bank Interrupt Disable 18 1 write-only DATAX_RX DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) 6 1 write-only EPT_DISABL Endpoint Disable 0 1 write-only ERR_CRC_NTR ISO CRC Error/Number of Transaction Error Interrupt Disable 13 1 write-only ERR_FLUSH bank flush error Interrupt Disable 14 1 write-only ERR_FL_ISO Error Flow Interrupt Disable 12 1 write-only ERR_OVFLW Overflow Error Interrupt Disable 8 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only MDATA_RX MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) 7 1 write-only RXRDY_TXKL Received OUT Data Interrupt Disable 9 1 write-only SHRT_PCKT Short Packet Interrupt Disable 31 1 write-only TXRDY_TRER TX Packet Ready/Transaction Error Interrupt Disable 11 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Disable 10 1 write-only EPTCTLDIS7 UDPHS Endpoint Control Disable Register (endpoint = 7) 0x1E8 32 write-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Disable 1 1 write-only BUSY_BANK Busy Bank Interrupt Disable 18 1 write-only EPT_DISABL Endpoint Disable 0 1 write-only ERR_OVFLW Overflow Error Interrupt Disable 8 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only NAK_IN NAKIN Interrupt Disable 14 1 write-only NAK_OUT NAKOUT Interrupt Disable 15 1 write-only NYET_DIS NYET Enable (Only for High Speed Bulk OUT endpoints) 4 1 write-only RXRDY_TXKL Received OUT Data Interrupt Disable 9 1 write-only RX_SETUP Received SETUP Interrupt Disable 12 1 write-only SHRT_PCKT Short Packet Interrupt Disable 31 1 write-only STALL_SNT Stall Sent Interrupt Disable 13 1 write-only TXRDY TX Packet Ready Interrupt Disable 11 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Disable 10 1 write-only EPTCTLDIS7_ISOENDPT UDPHS Endpoint Control Disable Register (endpoint = 7) ISOENDPT 0x1E8 32 write-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Disable 1 1 write-only BUSY_BANK Busy Bank Interrupt Disable 18 1 write-only DATAX_RX DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) 6 1 write-only EPT_DISABL Endpoint Disable 0 1 write-only ERR_CRC_NTR ISO CRC Error/Number of Transaction Error Interrupt Disable 13 1 write-only ERR_FLUSH bank flush error Interrupt Disable 14 1 write-only ERR_FL_ISO Error Flow Interrupt Disable 12 1 write-only ERR_OVFLW Overflow Error Interrupt Disable 8 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only MDATA_RX MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) 7 1 write-only RXRDY_TXKL Received OUT Data Interrupt Disable 9 1 write-only SHRT_PCKT Short Packet Interrupt Disable 31 1 write-only TXRDY_TRER TX Packet Ready/Transaction Error Interrupt Disable 11 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Disable 10 1 write-only EPTCTLDIS8 UDPHS Endpoint Control Disable Register (endpoint = 8) 0x208 32 write-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Disable 1 1 write-only BUSY_BANK Busy Bank Interrupt Disable 18 1 write-only EPT_DISABL Endpoint Disable 0 1 write-only ERR_OVFLW Overflow Error Interrupt Disable 8 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only NAK_IN NAKIN Interrupt Disable 14 1 write-only NAK_OUT NAKOUT Interrupt Disable 15 1 write-only NYET_DIS NYET Enable (Only for High Speed Bulk OUT endpoints) 4 1 write-only RXRDY_TXKL Received OUT Data Interrupt Disable 9 1 write-only RX_SETUP Received SETUP Interrupt Disable 12 1 write-only SHRT_PCKT Short Packet Interrupt Disable 31 1 write-only STALL_SNT Stall Sent Interrupt Disable 13 1 write-only TXRDY TX Packet Ready Interrupt Disable 11 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Disable 10 1 write-only EPTCTLDIS8_ISOENDPT UDPHS Endpoint Control Disable Register (endpoint = 8) ISOENDPT 0x208 32 write-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Disable 1 1 write-only BUSY_BANK Busy Bank Interrupt Disable 18 1 write-only DATAX_RX DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) 6 1 write-only EPT_DISABL Endpoint Disable 0 1 write-only ERR_CRC_NTR ISO CRC Error/Number of Transaction Error Interrupt Disable 13 1 write-only ERR_FLUSH bank flush error Interrupt Disable 14 1 write-only ERR_FL_ISO Error Flow Interrupt Disable 12 1 write-only ERR_OVFLW Overflow Error Interrupt Disable 8 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only MDATA_RX MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) 7 1 write-only RXRDY_TXKL Received OUT Data Interrupt Disable 9 1 write-only SHRT_PCKT Short Packet Interrupt Disable 31 1 write-only TXRDY_TRER TX Packet Ready/Transaction Error Interrupt Disable 11 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Disable 10 1 write-only EPTCTLDIS9 UDPHS Endpoint Control Disable Register (endpoint = 9) 0x228 32 write-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Disable 1 1 write-only BUSY_BANK Busy Bank Interrupt Disable 18 1 write-only EPT_DISABL Endpoint Disable 0 1 write-only ERR_OVFLW Overflow Error Interrupt Disable 8 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only NAK_IN NAKIN Interrupt Disable 14 1 write-only NAK_OUT NAKOUT Interrupt Disable 15 1 write-only NYET_DIS NYET Enable (Only for High Speed Bulk OUT endpoints) 4 1 write-only RXRDY_TXKL Received OUT Data Interrupt Disable 9 1 write-only RX_SETUP Received SETUP Interrupt Disable 12 1 write-only SHRT_PCKT Short Packet Interrupt Disable 31 1 write-only STALL_SNT Stall Sent Interrupt Disable 13 1 write-only TXRDY TX Packet Ready Interrupt Disable 11 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Disable 10 1 write-only EPTCTLDIS9_ISOENDPT UDPHS Endpoint Control Disable Register (endpoint = 9) ISOENDPT 0x228 32 write-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Disable 1 1 write-only BUSY_BANK Busy Bank Interrupt Disable 18 1 write-only DATAX_RX DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) 6 1 write-only EPT_DISABL Endpoint Disable 0 1 write-only ERR_CRC_NTR ISO CRC Error/Number of Transaction Error Interrupt Disable 13 1 write-only ERR_FLUSH bank flush error Interrupt Disable 14 1 write-only ERR_FL_ISO Error Flow Interrupt Disable 12 1 write-only ERR_OVFLW Overflow Error Interrupt Disable 8 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only MDATA_RX MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) 7 1 write-only RXRDY_TXKL Received OUT Data Interrupt Disable 9 1 write-only SHRT_PCKT Short Packet Interrupt Disable 31 1 write-only TXRDY_TRER TX Packet Ready/Transaction Error Interrupt Disable 11 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Disable 10 1 write-only EPTCTLENB0 UDPHS Endpoint Control Enable Register (endpoint = 0) 0x104 32 write-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Enable 1 1 write-only BUSY_BANK Busy Bank Interrupt Enable 18 1 write-only EPT_ENABL Endpoint Enable 0 1 write-only ERR_OVFLW Overflow Error Interrupt Enable 8 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only NAK_IN NAKIN Interrupt Enable 14 1 write-only NAK_OUT NAKOUT Interrupt Enable 15 1 write-only NYET_DIS NYET Disable (Only for High Speed Bulk OUT endpoints) 4 1 write-only RXRDY_TXKL Received OUT Data Interrupt Enable 9 1 write-only RX_SETUP Received SETUP 12 1 write-only SHRT_PCKT Short Packet Send/Short Packet Interrupt Enable 31 1 write-only STALL_SNT Stall Sent Interrupt Enable 13 1 write-only TXRDY TX Packet Ready Interrupt Enable 11 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Enable 10 1 write-only EPTCTLENB0_ISOENDPT UDPHS Endpoint Control Enable Register (endpoint = 0) ISOENDPT 0x104 32 write-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Enable 1 1 write-only BUSY_BANK Busy Bank Interrupt Enable 18 1 write-only DATAX_RX DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) 6 1 write-only EPT_ENABL Endpoint Enable 0 1 write-only ERR_CRC_NTR ISO CRC Error/Number of Transaction Error Interrupt Enable 13 1 write-only ERR_FLUSH Bank Flush Error Interrupt Enable 14 1 write-only ERR_FL_ISO Error Flow Interrupt Enable 12 1 write-only ERR_OVFLW Overflow Error Interrupt Enable 8 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only MDATA_RX MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) 7 1 write-only RXRDY_TXKL Received OUT Data Interrupt Enable 9 1 write-only SHRT_PCKT Short Packet Send/Short Packet Interrupt Enable 31 1 write-only TXRDY_TRER TX Packet Ready/Transaction Error Interrupt Enable 11 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Enable 10 1 write-only EPTCTLENB1 UDPHS Endpoint Control Enable Register (endpoint = 1) 0x124 32 write-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Enable 1 1 write-only BUSY_BANK Busy Bank Interrupt Enable 18 1 write-only EPT_ENABL Endpoint Enable 0 1 write-only ERR_OVFLW Overflow Error Interrupt Enable 8 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only NAK_IN NAKIN Interrupt Enable 14 1 write-only NAK_OUT NAKOUT Interrupt Enable 15 1 write-only NYET_DIS NYET Disable (Only for High Speed Bulk OUT endpoints) 4 1 write-only RXRDY_TXKL Received OUT Data Interrupt Enable 9 1 write-only RX_SETUP Received SETUP 12 1 write-only SHRT_PCKT Short Packet Send/Short Packet Interrupt Enable 31 1 write-only STALL_SNT Stall Sent Interrupt Enable 13 1 write-only TXRDY TX Packet Ready Interrupt Enable 11 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Enable 10 1 write-only EPTCTLENB10 UDPHS Endpoint Control Enable Register (endpoint = 10) 0x244 32 write-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Enable 1 1 write-only BUSY_BANK Busy Bank Interrupt Enable 18 1 write-only EPT_ENABL Endpoint Enable 0 1 write-only ERR_OVFLW Overflow Error Interrupt Enable 8 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only NAK_IN NAKIN Interrupt Enable 14 1 write-only NAK_OUT NAKOUT Interrupt Enable 15 1 write-only NYET_DIS NYET Disable (Only for High Speed Bulk OUT endpoints) 4 1 write-only RXRDY_TXKL Received OUT Data Interrupt Enable 9 1 write-only RX_SETUP Received SETUP 12 1 write-only SHRT_PCKT Short Packet Send/Short Packet Interrupt Enable 31 1 write-only STALL_SNT Stall Sent Interrupt Enable 13 1 write-only TXRDY TX Packet Ready Interrupt Enable 11 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Enable 10 1 write-only EPTCTLENB10_ISOENDPT UDPHS Endpoint Control Enable Register (endpoint = 10) ISOENDPT 0x244 32 write-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Enable 1 1 write-only BUSY_BANK Busy Bank Interrupt Enable 18 1 write-only DATAX_RX DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) 6 1 write-only EPT_ENABL Endpoint Enable 0 1 write-only ERR_CRC_NTR ISO CRC Error/Number of Transaction Error Interrupt Enable 13 1 write-only ERR_FLUSH Bank Flush Error Interrupt Enable 14 1 write-only ERR_FL_ISO Error Flow Interrupt Enable 12 1 write-only ERR_OVFLW Overflow Error Interrupt Enable 8 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only MDATA_RX MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) 7 1 write-only RXRDY_TXKL Received OUT Data Interrupt Enable 9 1 write-only SHRT_PCKT Short Packet Send/Short Packet Interrupt Enable 31 1 write-only TXRDY_TRER TX Packet Ready/Transaction Error Interrupt Enable 11 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Enable 10 1 write-only EPTCTLENB11 UDPHS Endpoint Control Enable Register (endpoint = 11) 0x264 32 write-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Enable 1 1 write-only BUSY_BANK Busy Bank Interrupt Enable 18 1 write-only EPT_ENABL Endpoint Enable 0 1 write-only ERR_OVFLW Overflow Error Interrupt Enable 8 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only NAK_IN NAKIN Interrupt Enable 14 1 write-only NAK_OUT NAKOUT Interrupt Enable 15 1 write-only NYET_DIS NYET Disable (Only for High Speed Bulk OUT endpoints) 4 1 write-only RXRDY_TXKL Received OUT Data Interrupt Enable 9 1 write-only RX_SETUP Received SETUP 12 1 write-only SHRT_PCKT Short Packet Send/Short Packet Interrupt Enable 31 1 write-only STALL_SNT Stall Sent Interrupt Enable 13 1 write-only TXRDY TX Packet Ready Interrupt Enable 11 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Enable 10 1 write-only EPTCTLENB11_ISOENDPT UDPHS Endpoint Control Enable Register (endpoint = 11) ISOENDPT 0x264 32 write-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Enable 1 1 write-only BUSY_BANK Busy Bank Interrupt Enable 18 1 write-only DATAX_RX DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) 6 1 write-only EPT_ENABL Endpoint Enable 0 1 write-only ERR_CRC_NTR ISO CRC Error/Number of Transaction Error Interrupt Enable 13 1 write-only ERR_FLUSH Bank Flush Error Interrupt Enable 14 1 write-only ERR_FL_ISO Error Flow Interrupt Enable 12 1 write-only ERR_OVFLW Overflow Error Interrupt Enable 8 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only MDATA_RX MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) 7 1 write-only RXRDY_TXKL Received OUT Data Interrupt Enable 9 1 write-only SHRT_PCKT Short Packet Send/Short Packet Interrupt Enable 31 1 write-only TXRDY_TRER TX Packet Ready/Transaction Error Interrupt Enable 11 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Enable 10 1 write-only EPTCTLENB12 UDPHS Endpoint Control Enable Register (endpoint = 12) 0x284 32 write-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Enable 1 1 write-only BUSY_BANK Busy Bank Interrupt Enable 18 1 write-only EPT_ENABL Endpoint Enable 0 1 write-only ERR_OVFLW Overflow Error Interrupt Enable 8 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only NAK_IN NAKIN Interrupt Enable 14 1 write-only NAK_OUT NAKOUT Interrupt Enable 15 1 write-only NYET_DIS NYET Disable (Only for High Speed Bulk OUT endpoints) 4 1 write-only RXRDY_TXKL Received OUT Data Interrupt Enable 9 1 write-only RX_SETUP Received SETUP 12 1 write-only SHRT_PCKT Short Packet Send/Short Packet Interrupt Enable 31 1 write-only STALL_SNT Stall Sent Interrupt Enable 13 1 write-only TXRDY TX Packet Ready Interrupt Enable 11 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Enable 10 1 write-only EPTCTLENB12_ISOENDPT UDPHS Endpoint Control Enable Register (endpoint = 12) ISOENDPT 0x284 32 write-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Enable 1 1 write-only BUSY_BANK Busy Bank Interrupt Enable 18 1 write-only DATAX_RX DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) 6 1 write-only EPT_ENABL Endpoint Enable 0 1 write-only ERR_CRC_NTR ISO CRC Error/Number of Transaction Error Interrupt Enable 13 1 write-only ERR_FLUSH Bank Flush Error Interrupt Enable 14 1 write-only ERR_FL_ISO Error Flow Interrupt Enable 12 1 write-only ERR_OVFLW Overflow Error Interrupt Enable 8 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only MDATA_RX MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) 7 1 write-only RXRDY_TXKL Received OUT Data Interrupt Enable 9 1 write-only SHRT_PCKT Short Packet Send/Short Packet Interrupt Enable 31 1 write-only TXRDY_TRER TX Packet Ready/Transaction Error Interrupt Enable 11 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Enable 10 1 write-only EPTCTLENB13 UDPHS Endpoint Control Enable Register (endpoint = 13) 0x2A4 32 write-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Enable 1 1 write-only BUSY_BANK Busy Bank Interrupt Enable 18 1 write-only EPT_ENABL Endpoint Enable 0 1 write-only ERR_OVFLW Overflow Error Interrupt Enable 8 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only NAK_IN NAKIN Interrupt Enable 14 1 write-only NAK_OUT NAKOUT Interrupt Enable 15 1 write-only NYET_DIS NYET Disable (Only for High Speed Bulk OUT endpoints) 4 1 write-only RXRDY_TXKL Received OUT Data Interrupt Enable 9 1 write-only RX_SETUP Received SETUP 12 1 write-only SHRT_PCKT Short Packet Send/Short Packet Interrupt Enable 31 1 write-only STALL_SNT Stall Sent Interrupt Enable 13 1 write-only TXRDY TX Packet Ready Interrupt Enable 11 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Enable 10 1 write-only EPTCTLENB13_ISOENDPT UDPHS Endpoint Control Enable Register (endpoint = 13) ISOENDPT 0x2A4 32 write-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Enable 1 1 write-only BUSY_BANK Busy Bank Interrupt Enable 18 1 write-only DATAX_RX DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) 6 1 write-only EPT_ENABL Endpoint Enable 0 1 write-only ERR_CRC_NTR ISO CRC Error/Number of Transaction Error Interrupt Enable 13 1 write-only ERR_FLUSH Bank Flush Error Interrupt Enable 14 1 write-only ERR_FL_ISO Error Flow Interrupt Enable 12 1 write-only ERR_OVFLW Overflow Error Interrupt Enable 8 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only MDATA_RX MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) 7 1 write-only RXRDY_TXKL Received OUT Data Interrupt Enable 9 1 write-only SHRT_PCKT Short Packet Send/Short Packet Interrupt Enable 31 1 write-only TXRDY_TRER TX Packet Ready/Transaction Error Interrupt Enable 11 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Enable 10 1 write-only EPTCTLENB14 UDPHS Endpoint Control Enable Register (endpoint = 14) 0x2C4 32 write-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Enable 1 1 write-only BUSY_BANK Busy Bank Interrupt Enable 18 1 write-only EPT_ENABL Endpoint Enable 0 1 write-only ERR_OVFLW Overflow Error Interrupt Enable 8 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only NAK_IN NAKIN Interrupt Enable 14 1 write-only NAK_OUT NAKOUT Interrupt Enable 15 1 write-only NYET_DIS NYET Disable (Only for High Speed Bulk OUT endpoints) 4 1 write-only RXRDY_TXKL Received OUT Data Interrupt Enable 9 1 write-only RX_SETUP Received SETUP 12 1 write-only SHRT_PCKT Short Packet Send/Short Packet Interrupt Enable 31 1 write-only STALL_SNT Stall Sent Interrupt Enable 13 1 write-only TXRDY TX Packet Ready Interrupt Enable 11 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Enable 10 1 write-only EPTCTLENB14_ISOENDPT UDPHS Endpoint Control Enable Register (endpoint = 14) ISOENDPT 0x2C4 32 write-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Enable 1 1 write-only BUSY_BANK Busy Bank Interrupt Enable 18 1 write-only DATAX_RX DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) 6 1 write-only EPT_ENABL Endpoint Enable 0 1 write-only ERR_CRC_NTR ISO CRC Error/Number of Transaction Error Interrupt Enable 13 1 write-only ERR_FLUSH Bank Flush Error Interrupt Enable 14 1 write-only ERR_FL_ISO Error Flow Interrupt Enable 12 1 write-only ERR_OVFLW Overflow Error Interrupt Enable 8 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only MDATA_RX MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) 7 1 write-only RXRDY_TXKL Received OUT Data Interrupt Enable 9 1 write-only SHRT_PCKT Short Packet Send/Short Packet Interrupt Enable 31 1 write-only TXRDY_TRER TX Packet Ready/Transaction Error Interrupt Enable 11 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Enable 10 1 write-only EPTCTLENB15 UDPHS Endpoint Control Enable Register (endpoint = 15) 0x2E4 32 write-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Enable 1 1 write-only BUSY_BANK Busy Bank Interrupt Enable 18 1 write-only EPT_ENABL Endpoint Enable 0 1 write-only ERR_OVFLW Overflow Error Interrupt Enable 8 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only NAK_IN NAKIN Interrupt Enable 14 1 write-only NAK_OUT NAKOUT Interrupt Enable 15 1 write-only NYET_DIS NYET Disable (Only for High Speed Bulk OUT endpoints) 4 1 write-only RXRDY_TXKL Received OUT Data Interrupt Enable 9 1 write-only RX_SETUP Received SETUP 12 1 write-only SHRT_PCKT Short Packet Send/Short Packet Interrupt Enable 31 1 write-only STALL_SNT Stall Sent Interrupt Enable 13 1 write-only TXRDY TX Packet Ready Interrupt Enable 11 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Enable 10 1 write-only EPTCTLENB15_ISOENDPT UDPHS Endpoint Control Enable Register (endpoint = 15) ISOENDPT 0x2E4 32 write-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Enable 1 1 write-only BUSY_BANK Busy Bank Interrupt Enable 18 1 write-only DATAX_RX DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) 6 1 write-only EPT_ENABL Endpoint Enable 0 1 write-only ERR_CRC_NTR ISO CRC Error/Number of Transaction Error Interrupt Enable 13 1 write-only ERR_FLUSH Bank Flush Error Interrupt Enable 14 1 write-only ERR_FL_ISO Error Flow Interrupt Enable 12 1 write-only ERR_OVFLW Overflow Error Interrupt Enable 8 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only MDATA_RX MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) 7 1 write-only RXRDY_TXKL Received OUT Data Interrupt Enable 9 1 write-only SHRT_PCKT Short Packet Send/Short Packet Interrupt Enable 31 1 write-only TXRDY_TRER TX Packet Ready/Transaction Error Interrupt Enable 11 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Enable 10 1 write-only EPTCTLENB1_ISOENDPT UDPHS Endpoint Control Enable Register (endpoint = 1) ISOENDPT 0x124 32 write-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Enable 1 1 write-only BUSY_BANK Busy Bank Interrupt Enable 18 1 write-only DATAX_RX DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) 6 1 write-only EPT_ENABL Endpoint Enable 0 1 write-only ERR_CRC_NTR ISO CRC Error/Number of Transaction Error Interrupt Enable 13 1 write-only ERR_FLUSH Bank Flush Error Interrupt Enable 14 1 write-only ERR_FL_ISO Error Flow Interrupt Enable 12 1 write-only ERR_OVFLW Overflow Error Interrupt Enable 8 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only MDATA_RX MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) 7 1 write-only RXRDY_TXKL Received OUT Data Interrupt Enable 9 1 write-only SHRT_PCKT Short Packet Send/Short Packet Interrupt Enable 31 1 write-only TXRDY_TRER TX Packet Ready/Transaction Error Interrupt Enable 11 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Enable 10 1 write-only EPTCTLENB2 UDPHS Endpoint Control Enable Register (endpoint = 2) 0x144 32 write-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Enable 1 1 write-only BUSY_BANK Busy Bank Interrupt Enable 18 1 write-only EPT_ENABL Endpoint Enable 0 1 write-only ERR_OVFLW Overflow Error Interrupt Enable 8 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only NAK_IN NAKIN Interrupt Enable 14 1 write-only NAK_OUT NAKOUT Interrupt Enable 15 1 write-only NYET_DIS NYET Disable (Only for High Speed Bulk OUT endpoints) 4 1 write-only RXRDY_TXKL Received OUT Data Interrupt Enable 9 1 write-only RX_SETUP Received SETUP 12 1 write-only SHRT_PCKT Short Packet Send/Short Packet Interrupt Enable 31 1 write-only STALL_SNT Stall Sent Interrupt Enable 13 1 write-only TXRDY TX Packet Ready Interrupt Enable 11 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Enable 10 1 write-only EPTCTLENB2_ISOENDPT UDPHS Endpoint Control Enable Register (endpoint = 2) ISOENDPT 0x144 32 write-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Enable 1 1 write-only BUSY_BANK Busy Bank Interrupt Enable 18 1 write-only DATAX_RX DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) 6 1 write-only EPT_ENABL Endpoint Enable 0 1 write-only ERR_CRC_NTR ISO CRC Error/Number of Transaction Error Interrupt Enable 13 1 write-only ERR_FLUSH Bank Flush Error Interrupt Enable 14 1 write-only ERR_FL_ISO Error Flow Interrupt Enable 12 1 write-only ERR_OVFLW Overflow Error Interrupt Enable 8 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only MDATA_RX MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) 7 1 write-only RXRDY_TXKL Received OUT Data Interrupt Enable 9 1 write-only SHRT_PCKT Short Packet Send/Short Packet Interrupt Enable 31 1 write-only TXRDY_TRER TX Packet Ready/Transaction Error Interrupt Enable 11 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Enable 10 1 write-only EPTCTLENB3 UDPHS Endpoint Control Enable Register (endpoint = 3) 0x164 32 write-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Enable 1 1 write-only BUSY_BANK Busy Bank Interrupt Enable 18 1 write-only EPT_ENABL Endpoint Enable 0 1 write-only ERR_OVFLW Overflow Error Interrupt Enable 8 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only NAK_IN NAKIN Interrupt Enable 14 1 write-only NAK_OUT NAKOUT Interrupt Enable 15 1 write-only NYET_DIS NYET Disable (Only for High Speed Bulk OUT endpoints) 4 1 write-only RXRDY_TXKL Received OUT Data Interrupt Enable 9 1 write-only RX_SETUP Received SETUP 12 1 write-only SHRT_PCKT Short Packet Send/Short Packet Interrupt Enable 31 1 write-only STALL_SNT Stall Sent Interrupt Enable 13 1 write-only TXRDY TX Packet Ready Interrupt Enable 11 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Enable 10 1 write-only EPTCTLENB3_ISOENDPT UDPHS Endpoint Control Enable Register (endpoint = 3) ISOENDPT 0x164 32 write-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Enable 1 1 write-only BUSY_BANK Busy Bank Interrupt Enable 18 1 write-only DATAX_RX DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) 6 1 write-only EPT_ENABL Endpoint Enable 0 1 write-only ERR_CRC_NTR ISO CRC Error/Number of Transaction Error Interrupt Enable 13 1 write-only ERR_FLUSH Bank Flush Error Interrupt Enable 14 1 write-only ERR_FL_ISO Error Flow Interrupt Enable 12 1 write-only ERR_OVFLW Overflow Error Interrupt Enable 8 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only MDATA_RX MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) 7 1 write-only RXRDY_TXKL Received OUT Data Interrupt Enable 9 1 write-only SHRT_PCKT Short Packet Send/Short Packet Interrupt Enable 31 1 write-only TXRDY_TRER TX Packet Ready/Transaction Error Interrupt Enable 11 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Enable 10 1 write-only EPTCTLENB4 UDPHS Endpoint Control Enable Register (endpoint = 4) 0x184 32 write-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Enable 1 1 write-only BUSY_BANK Busy Bank Interrupt Enable 18 1 write-only EPT_ENABL Endpoint Enable 0 1 write-only ERR_OVFLW Overflow Error Interrupt Enable 8 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only NAK_IN NAKIN Interrupt Enable 14 1 write-only NAK_OUT NAKOUT Interrupt Enable 15 1 write-only NYET_DIS NYET Disable (Only for High Speed Bulk OUT endpoints) 4 1 write-only RXRDY_TXKL Received OUT Data Interrupt Enable 9 1 write-only RX_SETUP Received SETUP 12 1 write-only SHRT_PCKT Short Packet Send/Short Packet Interrupt Enable 31 1 write-only STALL_SNT Stall Sent Interrupt Enable 13 1 write-only TXRDY TX Packet Ready Interrupt Enable 11 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Enable 10 1 write-only EPTCTLENB4_ISOENDPT UDPHS Endpoint Control Enable Register (endpoint = 4) ISOENDPT 0x184 32 write-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Enable 1 1 write-only BUSY_BANK Busy Bank Interrupt Enable 18 1 write-only DATAX_RX DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) 6 1 write-only EPT_ENABL Endpoint Enable 0 1 write-only ERR_CRC_NTR ISO CRC Error/Number of Transaction Error Interrupt Enable 13 1 write-only ERR_FLUSH Bank Flush Error Interrupt Enable 14 1 write-only ERR_FL_ISO Error Flow Interrupt Enable 12 1 write-only ERR_OVFLW Overflow Error Interrupt Enable 8 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only MDATA_RX MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) 7 1 write-only RXRDY_TXKL Received OUT Data Interrupt Enable 9 1 write-only SHRT_PCKT Short Packet Send/Short Packet Interrupt Enable 31 1 write-only TXRDY_TRER TX Packet Ready/Transaction Error Interrupt Enable 11 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Enable 10 1 write-only EPTCTLENB5 UDPHS Endpoint Control Enable Register (endpoint = 5) 0x1A4 32 write-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Enable 1 1 write-only BUSY_BANK Busy Bank Interrupt Enable 18 1 write-only EPT_ENABL Endpoint Enable 0 1 write-only ERR_OVFLW Overflow Error Interrupt Enable 8 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only NAK_IN NAKIN Interrupt Enable 14 1 write-only NAK_OUT NAKOUT Interrupt Enable 15 1 write-only NYET_DIS NYET Disable (Only for High Speed Bulk OUT endpoints) 4 1 write-only RXRDY_TXKL Received OUT Data Interrupt Enable 9 1 write-only RX_SETUP Received SETUP 12 1 write-only SHRT_PCKT Short Packet Send/Short Packet Interrupt Enable 31 1 write-only STALL_SNT Stall Sent Interrupt Enable 13 1 write-only TXRDY TX Packet Ready Interrupt Enable 11 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Enable 10 1 write-only EPTCTLENB5_ISOENDPT UDPHS Endpoint Control Enable Register (endpoint = 5) ISOENDPT 0x1A4 32 write-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Enable 1 1 write-only BUSY_BANK Busy Bank Interrupt Enable 18 1 write-only DATAX_RX DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) 6 1 write-only EPT_ENABL Endpoint Enable 0 1 write-only ERR_CRC_NTR ISO CRC Error/Number of Transaction Error Interrupt Enable 13 1 write-only ERR_FLUSH Bank Flush Error Interrupt Enable 14 1 write-only ERR_FL_ISO Error Flow Interrupt Enable 12 1 write-only ERR_OVFLW Overflow Error Interrupt Enable 8 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only MDATA_RX MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) 7 1 write-only RXRDY_TXKL Received OUT Data Interrupt Enable 9 1 write-only SHRT_PCKT Short Packet Send/Short Packet Interrupt Enable 31 1 write-only TXRDY_TRER TX Packet Ready/Transaction Error Interrupt Enable 11 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Enable 10 1 write-only EPTCTLENB6 UDPHS Endpoint Control Enable Register (endpoint = 6) 0x1C4 32 write-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Enable 1 1 write-only BUSY_BANK Busy Bank Interrupt Enable 18 1 write-only EPT_ENABL Endpoint Enable 0 1 write-only ERR_OVFLW Overflow Error Interrupt Enable 8 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only NAK_IN NAKIN Interrupt Enable 14 1 write-only NAK_OUT NAKOUT Interrupt Enable 15 1 write-only NYET_DIS NYET Disable (Only for High Speed Bulk OUT endpoints) 4 1 write-only RXRDY_TXKL Received OUT Data Interrupt Enable 9 1 write-only RX_SETUP Received SETUP 12 1 write-only SHRT_PCKT Short Packet Send/Short Packet Interrupt Enable 31 1 write-only STALL_SNT Stall Sent Interrupt Enable 13 1 write-only TXRDY TX Packet Ready Interrupt Enable 11 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Enable 10 1 write-only EPTCTLENB6_ISOENDPT UDPHS Endpoint Control Enable Register (endpoint = 6) ISOENDPT 0x1C4 32 write-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Enable 1 1 write-only BUSY_BANK Busy Bank Interrupt Enable 18 1 write-only DATAX_RX DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) 6 1 write-only EPT_ENABL Endpoint Enable 0 1 write-only ERR_CRC_NTR ISO CRC Error/Number of Transaction Error Interrupt Enable 13 1 write-only ERR_FLUSH Bank Flush Error Interrupt Enable 14 1 write-only ERR_FL_ISO Error Flow Interrupt Enable 12 1 write-only ERR_OVFLW Overflow Error Interrupt Enable 8 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only MDATA_RX MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) 7 1 write-only RXRDY_TXKL Received OUT Data Interrupt Enable 9 1 write-only SHRT_PCKT Short Packet Send/Short Packet Interrupt Enable 31 1 write-only TXRDY_TRER TX Packet Ready/Transaction Error Interrupt Enable 11 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Enable 10 1 write-only EPTCTLENB7 UDPHS Endpoint Control Enable Register (endpoint = 7) 0x1E4 32 write-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Enable 1 1 write-only BUSY_BANK Busy Bank Interrupt Enable 18 1 write-only EPT_ENABL Endpoint Enable 0 1 write-only ERR_OVFLW Overflow Error Interrupt Enable 8 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only NAK_IN NAKIN Interrupt Enable 14 1 write-only NAK_OUT NAKOUT Interrupt Enable 15 1 write-only NYET_DIS NYET Disable (Only for High Speed Bulk OUT endpoints) 4 1 write-only RXRDY_TXKL Received OUT Data Interrupt Enable 9 1 write-only RX_SETUP Received SETUP 12 1 write-only SHRT_PCKT Short Packet Send/Short Packet Interrupt Enable 31 1 write-only STALL_SNT Stall Sent Interrupt Enable 13 1 write-only TXRDY TX Packet Ready Interrupt Enable 11 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Enable 10 1 write-only EPTCTLENB7_ISOENDPT UDPHS Endpoint Control Enable Register (endpoint = 7) ISOENDPT 0x1E4 32 write-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Enable 1 1 write-only BUSY_BANK Busy Bank Interrupt Enable 18 1 write-only DATAX_RX DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) 6 1 write-only EPT_ENABL Endpoint Enable 0 1 write-only ERR_CRC_NTR ISO CRC Error/Number of Transaction Error Interrupt Enable 13 1 write-only ERR_FLUSH Bank Flush Error Interrupt Enable 14 1 write-only ERR_FL_ISO Error Flow Interrupt Enable 12 1 write-only ERR_OVFLW Overflow Error Interrupt Enable 8 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only MDATA_RX MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) 7 1 write-only RXRDY_TXKL Received OUT Data Interrupt Enable 9 1 write-only SHRT_PCKT Short Packet Send/Short Packet Interrupt Enable 31 1 write-only TXRDY_TRER TX Packet Ready/Transaction Error Interrupt Enable 11 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Enable 10 1 write-only EPTCTLENB8 UDPHS Endpoint Control Enable Register (endpoint = 8) 0x204 32 write-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Enable 1 1 write-only BUSY_BANK Busy Bank Interrupt Enable 18 1 write-only EPT_ENABL Endpoint Enable 0 1 write-only ERR_OVFLW Overflow Error Interrupt Enable 8 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only NAK_IN NAKIN Interrupt Enable 14 1 write-only NAK_OUT NAKOUT Interrupt Enable 15 1 write-only NYET_DIS NYET Disable (Only for High Speed Bulk OUT endpoints) 4 1 write-only RXRDY_TXKL Received OUT Data Interrupt Enable 9 1 write-only RX_SETUP Received SETUP 12 1 write-only SHRT_PCKT Short Packet Send/Short Packet Interrupt Enable 31 1 write-only STALL_SNT Stall Sent Interrupt Enable 13 1 write-only TXRDY TX Packet Ready Interrupt Enable 11 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Enable 10 1 write-only EPTCTLENB8_ISOENDPT UDPHS Endpoint Control Enable Register (endpoint = 8) ISOENDPT 0x204 32 write-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Enable 1 1 write-only BUSY_BANK Busy Bank Interrupt Enable 18 1 write-only DATAX_RX DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) 6 1 write-only EPT_ENABL Endpoint Enable 0 1 write-only ERR_CRC_NTR ISO CRC Error/Number of Transaction Error Interrupt Enable 13 1 write-only ERR_FLUSH Bank Flush Error Interrupt Enable 14 1 write-only ERR_FL_ISO Error Flow Interrupt Enable 12 1 write-only ERR_OVFLW Overflow Error Interrupt Enable 8 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only MDATA_RX MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) 7 1 write-only RXRDY_TXKL Received OUT Data Interrupt Enable 9 1 write-only SHRT_PCKT Short Packet Send/Short Packet Interrupt Enable 31 1 write-only TXRDY_TRER TX Packet Ready/Transaction Error Interrupt Enable 11 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Enable 10 1 write-only EPTCTLENB9 UDPHS Endpoint Control Enable Register (endpoint = 9) 0x224 32 write-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Enable 1 1 write-only BUSY_BANK Busy Bank Interrupt Enable 18 1 write-only EPT_ENABL Endpoint Enable 0 1 write-only ERR_OVFLW Overflow Error Interrupt Enable 8 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only NAK_IN NAKIN Interrupt Enable 14 1 write-only NAK_OUT NAKOUT Interrupt Enable 15 1 write-only NYET_DIS NYET Disable (Only for High Speed Bulk OUT endpoints) 4 1 write-only RXRDY_TXKL Received OUT Data Interrupt Enable 9 1 write-only RX_SETUP Received SETUP 12 1 write-only SHRT_PCKT Short Packet Send/Short Packet Interrupt Enable 31 1 write-only STALL_SNT Stall Sent Interrupt Enable 13 1 write-only TXRDY TX Packet Ready Interrupt Enable 11 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Enable 10 1 write-only EPTCTLENB9_ISOENDPT UDPHS Endpoint Control Enable Register (endpoint = 9) ISOENDPT 0x224 32 write-only n 0x0 0x0 AUTO_VALID Packet Auto-Valid Enable 1 1 write-only BUSY_BANK Busy Bank Interrupt Enable 18 1 write-only DATAX_RX DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) 6 1 write-only EPT_ENABL Endpoint Enable 0 1 write-only ERR_CRC_NTR ISO CRC Error/Number of Transaction Error Interrupt Enable 13 1 write-only ERR_FLUSH Bank Flush Error Interrupt Enable 14 1 write-only ERR_FL_ISO Error Flow Interrupt Enable 12 1 write-only ERR_OVFLW Overflow Error Interrupt Enable 8 1 write-only INTDIS_DMA Interrupts Disable DMA 3 1 write-only MDATA_RX MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) 7 1 write-only RXRDY_TXKL Received OUT Data Interrupt Enable 9 1 write-only SHRT_PCKT Short Packet Send/Short Packet Interrupt Enable 31 1 write-only TXRDY_TRER TX Packet Ready/Transaction Error Interrupt Enable 11 1 write-only TX_COMPLT Transmitted IN Data Complete Interrupt Enable 10 1 write-only EPTRST UDPHS Endpoints Reset Register 0x1C 32 write-only n 0x0 0x0 EPT_0 Endpoint 0 Reset 0 1 write-only EPT_1 Endpoint 1 Reset 1 1 write-only EPT_10 Endpoint 10 Reset 10 1 write-only EPT_11 Endpoint 11 Reset 11 1 write-only EPT_12 Endpoint 12 Reset 12 1 write-only EPT_13 Endpoint 13 Reset 13 1 write-only EPT_14 Endpoint 14 Reset 14 1 write-only EPT_15 Endpoint 15 Reset 15 1 write-only EPT_2 Endpoint 2 Reset 2 1 write-only EPT_3 Endpoint 3 Reset 3 1 write-only EPT_4 Endpoint 4 Reset 4 1 write-only EPT_5 Endpoint 5 Reset 5 1 write-only EPT_6 Endpoint 6 Reset 6 1 write-only EPT_7 Endpoint 7 Reset 7 1 write-only EPT_8 Endpoint 8 Reset 8 1 write-only EPT_9 Endpoint 9 Reset 9 1 write-only EPTSETSTA0 UDPHS Endpoint Set Status Register (endpoint = 0) 0x114 32 write-only n 0x0 0x0 FRCESTALL Stall Handshake Request Set 5 1 write-only RXRDY_TXKL KILL Bank Set (for IN Endpoint) 9 1 write-only TXRDY TX Packet Ready Set 11 1 write-only EPTSETSTA0_ISOENDPT UDPHS Endpoint Set Status Register (endpoint = 0) ISOENDPT 0x114 32 write-only n 0x0 0x0 RXRDY_TXKL KILL Bank Set (for IN Endpoint) 9 1 write-only TXRDY_TRER TX Packet Ready Set 11 1 write-only EPTSETSTA1 UDPHS Endpoint Set Status Register (endpoint = 1) 0x134 32 write-only n 0x0 0x0 FRCESTALL Stall Handshake Request Set 5 1 write-only RXRDY_TXKL KILL Bank Set (for IN Endpoint) 9 1 write-only TXRDY TX Packet Ready Set 11 1 write-only EPTSETSTA10 UDPHS Endpoint Set Status Register (endpoint = 10) 0x254 32 write-only n 0x0 0x0 FRCESTALL Stall Handshake Request Set 5 1 write-only RXRDY_TXKL KILL Bank Set (for IN Endpoint) 9 1 write-only TXRDY TX Packet Ready Set 11 1 write-only EPTSETSTA10_ISOENDPT UDPHS Endpoint Set Status Register (endpoint = 10) ISOENDPT 0x254 32 write-only n 0x0 0x0 RXRDY_TXKL KILL Bank Set (for IN Endpoint) 9 1 write-only TXRDY_TRER TX Packet Ready Set 11 1 write-only EPTSETSTA11 UDPHS Endpoint Set Status Register (endpoint = 11) 0x274 32 write-only n 0x0 0x0 FRCESTALL Stall Handshake Request Set 5 1 write-only RXRDY_TXKL KILL Bank Set (for IN Endpoint) 9 1 write-only TXRDY TX Packet Ready Set 11 1 write-only EPTSETSTA11_ISOENDPT UDPHS Endpoint Set Status Register (endpoint = 11) ISOENDPT 0x274 32 write-only n 0x0 0x0 RXRDY_TXKL KILL Bank Set (for IN Endpoint) 9 1 write-only TXRDY_TRER TX Packet Ready Set 11 1 write-only EPTSETSTA12 UDPHS Endpoint Set Status Register (endpoint = 12) 0x294 32 write-only n 0x0 0x0 FRCESTALL Stall Handshake Request Set 5 1 write-only RXRDY_TXKL KILL Bank Set (for IN Endpoint) 9 1 write-only TXRDY TX Packet Ready Set 11 1 write-only EPTSETSTA12_ISOENDPT UDPHS Endpoint Set Status Register (endpoint = 12) ISOENDPT 0x294 32 write-only n 0x0 0x0 RXRDY_TXKL KILL Bank Set (for IN Endpoint) 9 1 write-only TXRDY_TRER TX Packet Ready Set 11 1 write-only EPTSETSTA13 UDPHS Endpoint Set Status Register (endpoint = 13) 0x2B4 32 write-only n 0x0 0x0 FRCESTALL Stall Handshake Request Set 5 1 write-only RXRDY_TXKL KILL Bank Set (for IN Endpoint) 9 1 write-only TXRDY TX Packet Ready Set 11 1 write-only EPTSETSTA13_ISOENDPT UDPHS Endpoint Set Status Register (endpoint = 13) ISOENDPT 0x2B4 32 write-only n 0x0 0x0 RXRDY_TXKL KILL Bank Set (for IN Endpoint) 9 1 write-only TXRDY_TRER TX Packet Ready Set 11 1 write-only EPTSETSTA14 UDPHS Endpoint Set Status Register (endpoint = 14) 0x2D4 32 write-only n 0x0 0x0 FRCESTALL Stall Handshake Request Set 5 1 write-only RXRDY_TXKL KILL Bank Set (for IN Endpoint) 9 1 write-only TXRDY TX Packet Ready Set 11 1 write-only EPTSETSTA14_ISOENDPT UDPHS Endpoint Set Status Register (endpoint = 14) ISOENDPT 0x2D4 32 write-only n 0x0 0x0 RXRDY_TXKL KILL Bank Set (for IN Endpoint) 9 1 write-only TXRDY_TRER TX Packet Ready Set 11 1 write-only EPTSETSTA15 UDPHS Endpoint Set Status Register (endpoint = 15) 0x2F4 32 write-only n 0x0 0x0 FRCESTALL Stall Handshake Request Set 5 1 write-only RXRDY_TXKL KILL Bank Set (for IN Endpoint) 9 1 write-only TXRDY TX Packet Ready Set 11 1 write-only EPTSETSTA15_ISOENDPT UDPHS Endpoint Set Status Register (endpoint = 15) ISOENDPT 0x2F4 32 write-only n 0x0 0x0 RXRDY_TXKL KILL Bank Set (for IN Endpoint) 9 1 write-only TXRDY_TRER TX Packet Ready Set 11 1 write-only EPTSETSTA1_ISOENDPT UDPHS Endpoint Set Status Register (endpoint = 1) ISOENDPT 0x134 32 write-only n 0x0 0x0 RXRDY_TXKL KILL Bank Set (for IN Endpoint) 9 1 write-only TXRDY_TRER TX Packet Ready Set 11 1 write-only EPTSETSTA2 UDPHS Endpoint Set Status Register (endpoint = 2) 0x154 32 write-only n 0x0 0x0 FRCESTALL Stall Handshake Request Set 5 1 write-only RXRDY_TXKL KILL Bank Set (for IN Endpoint) 9 1 write-only TXRDY TX Packet Ready Set 11 1 write-only EPTSETSTA2_ISOENDPT UDPHS Endpoint Set Status Register (endpoint = 2) ISOENDPT 0x154 32 write-only n 0x0 0x0 RXRDY_TXKL KILL Bank Set (for IN Endpoint) 9 1 write-only TXRDY_TRER TX Packet Ready Set 11 1 write-only EPTSETSTA3 UDPHS Endpoint Set Status Register (endpoint = 3) 0x174 32 write-only n 0x0 0x0 FRCESTALL Stall Handshake Request Set 5 1 write-only RXRDY_TXKL KILL Bank Set (for IN Endpoint) 9 1 write-only TXRDY TX Packet Ready Set 11 1 write-only EPTSETSTA3_ISOENDPT UDPHS Endpoint Set Status Register (endpoint = 3) ISOENDPT 0x174 32 write-only n 0x0 0x0 RXRDY_TXKL KILL Bank Set (for IN Endpoint) 9 1 write-only TXRDY_TRER TX Packet Ready Set 11 1 write-only EPTSETSTA4 UDPHS Endpoint Set Status Register (endpoint = 4) 0x194 32 write-only n 0x0 0x0 FRCESTALL Stall Handshake Request Set 5 1 write-only RXRDY_TXKL KILL Bank Set (for IN Endpoint) 9 1 write-only TXRDY TX Packet Ready Set 11 1 write-only EPTSETSTA4_ISOENDPT UDPHS Endpoint Set Status Register (endpoint = 4) ISOENDPT 0x194 32 write-only n 0x0 0x0 RXRDY_TXKL KILL Bank Set (for IN Endpoint) 9 1 write-only TXRDY_TRER TX Packet Ready Set 11 1 write-only EPTSETSTA5 UDPHS Endpoint Set Status Register (endpoint = 5) 0x1B4 32 write-only n 0x0 0x0 FRCESTALL Stall Handshake Request Set 5 1 write-only RXRDY_TXKL KILL Bank Set (for IN Endpoint) 9 1 write-only TXRDY TX Packet Ready Set 11 1 write-only EPTSETSTA5_ISOENDPT UDPHS Endpoint Set Status Register (endpoint = 5) ISOENDPT 0x1B4 32 write-only n 0x0 0x0 RXRDY_TXKL KILL Bank Set (for IN Endpoint) 9 1 write-only TXRDY_TRER TX Packet Ready Set 11 1 write-only EPTSETSTA6 UDPHS Endpoint Set Status Register (endpoint = 6) 0x1D4 32 write-only n 0x0 0x0 FRCESTALL Stall Handshake Request Set 5 1 write-only RXRDY_TXKL KILL Bank Set (for IN Endpoint) 9 1 write-only TXRDY TX Packet Ready Set 11 1 write-only EPTSETSTA6_ISOENDPT UDPHS Endpoint Set Status Register (endpoint = 6) ISOENDPT 0x1D4 32 write-only n 0x0 0x0 RXRDY_TXKL KILL Bank Set (for IN Endpoint) 9 1 write-only TXRDY_TRER TX Packet Ready Set 11 1 write-only EPTSETSTA7 UDPHS Endpoint Set Status Register (endpoint = 7) 0x1F4 32 write-only n 0x0 0x0 FRCESTALL Stall Handshake Request Set 5 1 write-only RXRDY_TXKL KILL Bank Set (for IN Endpoint) 9 1 write-only TXRDY TX Packet Ready Set 11 1 write-only EPTSETSTA7_ISOENDPT UDPHS Endpoint Set Status Register (endpoint = 7) ISOENDPT 0x1F4 32 write-only n 0x0 0x0 RXRDY_TXKL KILL Bank Set (for IN Endpoint) 9 1 write-only TXRDY_TRER TX Packet Ready Set 11 1 write-only EPTSETSTA8 UDPHS Endpoint Set Status Register (endpoint = 8) 0x214 32 write-only n 0x0 0x0 FRCESTALL Stall Handshake Request Set 5 1 write-only RXRDY_TXKL KILL Bank Set (for IN Endpoint) 9 1 write-only TXRDY TX Packet Ready Set 11 1 write-only EPTSETSTA8_ISOENDPT UDPHS Endpoint Set Status Register (endpoint = 8) ISOENDPT 0x214 32 write-only n 0x0 0x0 RXRDY_TXKL KILL Bank Set (for IN Endpoint) 9 1 write-only TXRDY_TRER TX Packet Ready Set 11 1 write-only EPTSETSTA9 UDPHS Endpoint Set Status Register (endpoint = 9) 0x234 32 write-only n 0x0 0x0 FRCESTALL Stall Handshake Request Set 5 1 write-only RXRDY_TXKL KILL Bank Set (for IN Endpoint) 9 1 write-only TXRDY TX Packet Ready Set 11 1 write-only EPTSETSTA9_ISOENDPT UDPHS Endpoint Set Status Register (endpoint = 9) ISOENDPT 0x234 32 write-only n 0x0 0x0 RXRDY_TXKL KILL Bank Set (for IN Endpoint) 9 1 write-only TXRDY_TRER TX Packet Ready Set 11 1 write-only EPTSTA0 UDPHS Endpoint Status Register (endpoint = 0) 0x11C 32 read-only n 0x0 0x0 BUSY_BANK_STA Busy Bank Number (cleared upon USB reset) 18 2 read-only 0BUSYBANK All banks are free 0x0 1BUSYBANK 1 busy bank 0x1 2BUSYBANKS 2 busy banks 0x2 3BUSYBANKS 3 busy banks 0x3 BYTE_COUNT UDPHS Byte Count (cleared upon USB reset) 20 11 read-only CURBK_CTLDIR Current Bank/Control Direction (cleared upon USB reset) 16 2 read-only ERR_OVFLW Overflow Error (cleared upon USB reset) 8 1 read-only FRCESTALL Stall Handshake Request (cleared upon USB reset) 5 1 read-only NAK_IN NAK IN (cleared upon USB reset) 14 1 read-only NAK_OUT NAK OUT (cleared upon USB reset) 15 1 read-only RXRDY_TXKL Received OUT Data/KILL Bank (cleared upon USB reset) 9 1 read-only RX_SETUP Received SETUP (cleared upon USB reset) 12 1 read-only SHRT_PCKT Short Packet (cleared upon USB reset) 31 1 read-only STALL_SNT Stall Sent (cleared upon USB reset) 13 1 read-only TOGGLESQ_STA Toggle Sequencing (cleared upon USB reset) 6 2 read-only DATA0 DATA0 0x0 DATA1 DATA1 0x1 DATA2 Reserved for High Bandwidth Isochronous Endpoint 0x2 MDATA Reserved for High Bandwidth Isochronous Endpoint 0x3 TXRDY TX Packet Ready (cleared upon USB reset) 11 1 read-only TX_COMPLT Transmitted IN Data Complete (cleared upon USB reset) 10 1 read-only EPTSTA0_ISOENDPT UDPHS Endpoint Status Register (endpoint = 0) ISOENDPT 0x11C 32 read-only n 0x0 0x0 BUSY_BANK_STA Busy Bank Number (cleared upon USB reset) 18 2 read-only 0BUSYBANK All banks are free 0x0 1BUSYBANK 1 busy bank 0x1 2BUSYBANKS 2 busy banks 0x2 3BUSYBANKS 3 busy banks 0x3 BYTE_COUNT UDPHS Byte Count (cleared upon USB reset) 20 11 read-only CURBK Current Bank (cleared upon USB reset) 16 2 read-only BANK0 Bank 0 (or single bank) 0x0 BANK1 Bank 1 0x1 BANK2 Bank 2 0x2 ERR_CRC_NTR CRC ISO Error/Number of Transaction Error (cleared upon USB reset) 13 1 read-only ERR_FLUSH Bank Flush Error (cleared upon USB reset) 14 1 read-only ERR_FL_ISO Error Flow (cleared upon USB reset) 12 1 read-only ERR_OVFLW Overflow Error (cleared upon USB reset) 8 1 read-only RXRDY_TXKL Received OUT Data/KILL Bank (cleared upon USB reset) 9 1 read-only SHRT_PCKT Short Packet (cleared upon USB reset) 31 1 read-only TOGGLESQ_STA Toggle Sequencing (cleared upon USB reset) 6 2 read-only DATA0 DATA0 0x0 DATA1 DATA1 0x1 DATA2 Data2 (only for High Bandwidth Isochronous Endpoint) 0x2 MDATA MData (only for High Bandwidth Isochronous Endpoint) 0x3 TXRDY_TRER TX Packet Ready/Transaction Error (cleared upon USB reset) 11 1 read-only TX_COMPLT Transmitted IN Data Complete (cleared upon USB reset) 10 1 read-only EPTSTA1 UDPHS Endpoint Status Register (endpoint = 1) 0x13C 32 read-only n 0x0 0x0 BUSY_BANK_STA Busy Bank Number (cleared upon USB reset) 18 2 read-only 0BUSYBANK All banks are free 0x0 1BUSYBANK 1 busy bank 0x1 2BUSYBANKS 2 busy banks 0x2 3BUSYBANKS 3 busy banks 0x3 BYTE_COUNT UDPHS Byte Count (cleared upon USB reset) 20 11 read-only CURBK_CTLDIR Current Bank/Control Direction (cleared upon USB reset) 16 2 read-only ERR_OVFLW Overflow Error (cleared upon USB reset) 8 1 read-only FRCESTALL Stall Handshake Request (cleared upon USB reset) 5 1 read-only NAK_IN NAK IN (cleared upon USB reset) 14 1 read-only NAK_OUT NAK OUT (cleared upon USB reset) 15 1 read-only RXRDY_TXKL Received OUT Data/KILL Bank (cleared upon USB reset) 9 1 read-only RX_SETUP Received SETUP (cleared upon USB reset) 12 1 read-only SHRT_PCKT Short Packet (cleared upon USB reset) 31 1 read-only STALL_SNT Stall Sent (cleared upon USB reset) 13 1 read-only TOGGLESQ_STA Toggle Sequencing (cleared upon USB reset) 6 2 read-only DATA0 DATA0 0x0 DATA1 DATA1 0x1 DATA2 Reserved for High Bandwidth Isochronous Endpoint 0x2 MDATA Reserved for High Bandwidth Isochronous Endpoint 0x3 TXRDY TX Packet Ready (cleared upon USB reset) 11 1 read-only TX_COMPLT Transmitted IN Data Complete (cleared upon USB reset) 10 1 read-only EPTSTA10 UDPHS Endpoint Status Register (endpoint = 10) 0x25C 32 read-only n 0x0 0x0 BUSY_BANK_STA Busy Bank Number (cleared upon USB reset) 18 2 read-only 0BUSYBANK All banks are free 0x0 1BUSYBANK 1 busy bank 0x1 2BUSYBANKS 2 busy banks 0x2 3BUSYBANKS 3 busy banks 0x3 BYTE_COUNT UDPHS Byte Count (cleared upon USB reset) 20 11 read-only CURBK_CTLDIR Current Bank/Control Direction (cleared upon USB reset) 16 2 read-only ERR_OVFLW Overflow Error (cleared upon USB reset) 8 1 read-only FRCESTALL Stall Handshake Request (cleared upon USB reset) 5 1 read-only NAK_IN NAK IN (cleared upon USB reset) 14 1 read-only NAK_OUT NAK OUT (cleared upon USB reset) 15 1 read-only RXRDY_TXKL Received OUT Data/KILL Bank (cleared upon USB reset) 9 1 read-only RX_SETUP Received SETUP (cleared upon USB reset) 12 1 read-only SHRT_PCKT Short Packet (cleared upon USB reset) 31 1 read-only STALL_SNT Stall Sent (cleared upon USB reset) 13 1 read-only TOGGLESQ_STA Toggle Sequencing (cleared upon USB reset) 6 2 read-only DATA0 DATA0 0x0 DATA1 DATA1 0x1 DATA2 Reserved for High Bandwidth Isochronous Endpoint 0x2 MDATA Reserved for High Bandwidth Isochronous Endpoint 0x3 TXRDY TX Packet Ready (cleared upon USB reset) 11 1 read-only TX_COMPLT Transmitted IN Data Complete (cleared upon USB reset) 10 1 read-only EPTSTA10_ISOENDPT UDPHS Endpoint Status Register (endpoint = 10) ISOENDPT 0x25C 32 read-only n 0x0 0x0 BUSY_BANK_STA Busy Bank Number (cleared upon USB reset) 18 2 read-only 0BUSYBANK All banks are free 0x0 1BUSYBANK 1 busy bank 0x1 2BUSYBANKS 2 busy banks 0x2 3BUSYBANKS 3 busy banks 0x3 BYTE_COUNT UDPHS Byte Count (cleared upon USB reset) 20 11 read-only CURBK Current Bank (cleared upon USB reset) 16 2 read-only BANK0 Bank 0 (or single bank) 0x0 BANK1 Bank 1 0x1 BANK2 Bank 2 0x2 ERR_CRC_NTR CRC ISO Error/Number of Transaction Error (cleared upon USB reset) 13 1 read-only ERR_FLUSH Bank Flush Error (cleared upon USB reset) 14 1 read-only ERR_FL_ISO Error Flow (cleared upon USB reset) 12 1 read-only ERR_OVFLW Overflow Error (cleared upon USB reset) 8 1 read-only RXRDY_TXKL Received OUT Data/KILL Bank (cleared upon USB reset) 9 1 read-only SHRT_PCKT Short Packet (cleared upon USB reset) 31 1 read-only TOGGLESQ_STA Toggle Sequencing (cleared upon USB reset) 6 2 read-only DATA0 DATA0 0x0 DATA1 DATA1 0x1 DATA2 Data2 (only for High Bandwidth Isochronous Endpoint) 0x2 MDATA MData (only for High Bandwidth Isochronous Endpoint) 0x3 TXRDY_TRER TX Packet Ready/Transaction Error (cleared upon USB reset) 11 1 read-only TX_COMPLT Transmitted IN Data Complete (cleared upon USB reset) 10 1 read-only EPTSTA11 UDPHS Endpoint Status Register (endpoint = 11) 0x27C 32 read-only n 0x0 0x0 BUSY_BANK_STA Busy Bank Number (cleared upon USB reset) 18 2 read-only 0BUSYBANK All banks are free 0x0 1BUSYBANK 1 busy bank 0x1 2BUSYBANKS 2 busy banks 0x2 3BUSYBANKS 3 busy banks 0x3 BYTE_COUNT UDPHS Byte Count (cleared upon USB reset) 20 11 read-only CURBK_CTLDIR Current Bank/Control Direction (cleared upon USB reset) 16 2 read-only ERR_OVFLW Overflow Error (cleared upon USB reset) 8 1 read-only FRCESTALL Stall Handshake Request (cleared upon USB reset) 5 1 read-only NAK_IN NAK IN (cleared upon USB reset) 14 1 read-only NAK_OUT NAK OUT (cleared upon USB reset) 15 1 read-only RXRDY_TXKL Received OUT Data/KILL Bank (cleared upon USB reset) 9 1 read-only RX_SETUP Received SETUP (cleared upon USB reset) 12 1 read-only SHRT_PCKT Short Packet (cleared upon USB reset) 31 1 read-only STALL_SNT Stall Sent (cleared upon USB reset) 13 1 read-only TOGGLESQ_STA Toggle Sequencing (cleared upon USB reset) 6 2 read-only DATA0 DATA0 0x0 DATA1 DATA1 0x1 DATA2 Reserved for High Bandwidth Isochronous Endpoint 0x2 MDATA Reserved for High Bandwidth Isochronous Endpoint 0x3 TXRDY TX Packet Ready (cleared upon USB reset) 11 1 read-only TX_COMPLT Transmitted IN Data Complete (cleared upon USB reset) 10 1 read-only EPTSTA11_ISOENDPT UDPHS Endpoint Status Register (endpoint = 11) ISOENDPT 0x27C 32 read-only n 0x0 0x0 BUSY_BANK_STA Busy Bank Number (cleared upon USB reset) 18 2 read-only 0BUSYBANK All banks are free 0x0 1BUSYBANK 1 busy bank 0x1 2BUSYBANKS 2 busy banks 0x2 3BUSYBANKS 3 busy banks 0x3 BYTE_COUNT UDPHS Byte Count (cleared upon USB reset) 20 11 read-only CURBK Current Bank (cleared upon USB reset) 16 2 read-only BANK0 Bank 0 (or single bank) 0x0 BANK1 Bank 1 0x1 BANK2 Bank 2 0x2 ERR_CRC_NTR CRC ISO Error/Number of Transaction Error (cleared upon USB reset) 13 1 read-only ERR_FLUSH Bank Flush Error (cleared upon USB reset) 14 1 read-only ERR_FL_ISO Error Flow (cleared upon USB reset) 12 1 read-only ERR_OVFLW Overflow Error (cleared upon USB reset) 8 1 read-only RXRDY_TXKL Received OUT Data/KILL Bank (cleared upon USB reset) 9 1 read-only SHRT_PCKT Short Packet (cleared upon USB reset) 31 1 read-only TOGGLESQ_STA Toggle Sequencing (cleared upon USB reset) 6 2 read-only DATA0 DATA0 0x0 DATA1 DATA1 0x1 DATA2 Data2 (only for High Bandwidth Isochronous Endpoint) 0x2 MDATA MData (only for High Bandwidth Isochronous Endpoint) 0x3 TXRDY_TRER TX Packet Ready/Transaction Error (cleared upon USB reset) 11 1 read-only TX_COMPLT Transmitted IN Data Complete (cleared upon USB reset) 10 1 read-only EPTSTA12 UDPHS Endpoint Status Register (endpoint = 12) 0x29C 32 read-only n 0x0 0x0 BUSY_BANK_STA Busy Bank Number (cleared upon USB reset) 18 2 read-only 0BUSYBANK All banks are free 0x0 1BUSYBANK 1 busy bank 0x1 2BUSYBANKS 2 busy banks 0x2 3BUSYBANKS 3 busy banks 0x3 BYTE_COUNT UDPHS Byte Count (cleared upon USB reset) 20 11 read-only CURBK_CTLDIR Current Bank/Control Direction (cleared upon USB reset) 16 2 read-only ERR_OVFLW Overflow Error (cleared upon USB reset) 8 1 read-only FRCESTALL Stall Handshake Request (cleared upon USB reset) 5 1 read-only NAK_IN NAK IN (cleared upon USB reset) 14 1 read-only NAK_OUT NAK OUT (cleared upon USB reset) 15 1 read-only RXRDY_TXKL Received OUT Data/KILL Bank (cleared upon USB reset) 9 1 read-only RX_SETUP Received SETUP (cleared upon USB reset) 12 1 read-only SHRT_PCKT Short Packet (cleared upon USB reset) 31 1 read-only STALL_SNT Stall Sent (cleared upon USB reset) 13 1 read-only TOGGLESQ_STA Toggle Sequencing (cleared upon USB reset) 6 2 read-only DATA0 DATA0 0x0 DATA1 DATA1 0x1 DATA2 Reserved for High Bandwidth Isochronous Endpoint 0x2 MDATA Reserved for High Bandwidth Isochronous Endpoint 0x3 TXRDY TX Packet Ready (cleared upon USB reset) 11 1 read-only TX_COMPLT Transmitted IN Data Complete (cleared upon USB reset) 10 1 read-only EPTSTA12_ISOENDPT UDPHS Endpoint Status Register (endpoint = 12) ISOENDPT 0x29C 32 read-only n 0x0 0x0 BUSY_BANK_STA Busy Bank Number (cleared upon USB reset) 18 2 read-only 0BUSYBANK All banks are free 0x0 1BUSYBANK 1 busy bank 0x1 2BUSYBANKS 2 busy banks 0x2 3BUSYBANKS 3 busy banks 0x3 BYTE_COUNT UDPHS Byte Count (cleared upon USB reset) 20 11 read-only CURBK Current Bank (cleared upon USB reset) 16 2 read-only BANK0 Bank 0 (or single bank) 0x0 BANK1 Bank 1 0x1 BANK2 Bank 2 0x2 ERR_CRC_NTR CRC ISO Error/Number of Transaction Error (cleared upon USB reset) 13 1 read-only ERR_FLUSH Bank Flush Error (cleared upon USB reset) 14 1 read-only ERR_FL_ISO Error Flow (cleared upon USB reset) 12 1 read-only ERR_OVFLW Overflow Error (cleared upon USB reset) 8 1 read-only RXRDY_TXKL Received OUT Data/KILL Bank (cleared upon USB reset) 9 1 read-only SHRT_PCKT Short Packet (cleared upon USB reset) 31 1 read-only TOGGLESQ_STA Toggle Sequencing (cleared upon USB reset) 6 2 read-only DATA0 DATA0 0x0 DATA1 DATA1 0x1 DATA2 Data2 (only for High Bandwidth Isochronous Endpoint) 0x2 MDATA MData (only for High Bandwidth Isochronous Endpoint) 0x3 TXRDY_TRER TX Packet Ready/Transaction Error (cleared upon USB reset) 11 1 read-only TX_COMPLT Transmitted IN Data Complete (cleared upon USB reset) 10 1 read-only EPTSTA13 UDPHS Endpoint Status Register (endpoint = 13) 0x2BC 32 read-only n 0x0 0x0 BUSY_BANK_STA Busy Bank Number (cleared upon USB reset) 18 2 read-only 0BUSYBANK All banks are free 0x0 1BUSYBANK 1 busy bank 0x1 2BUSYBANKS 2 busy banks 0x2 3BUSYBANKS 3 busy banks 0x3 BYTE_COUNT UDPHS Byte Count (cleared upon USB reset) 20 11 read-only CURBK_CTLDIR Current Bank/Control Direction (cleared upon USB reset) 16 2 read-only ERR_OVFLW Overflow Error (cleared upon USB reset) 8 1 read-only FRCESTALL Stall Handshake Request (cleared upon USB reset) 5 1 read-only NAK_IN NAK IN (cleared upon USB reset) 14 1 read-only NAK_OUT NAK OUT (cleared upon USB reset) 15 1 read-only RXRDY_TXKL Received OUT Data/KILL Bank (cleared upon USB reset) 9 1 read-only RX_SETUP Received SETUP (cleared upon USB reset) 12 1 read-only SHRT_PCKT Short Packet (cleared upon USB reset) 31 1 read-only STALL_SNT Stall Sent (cleared upon USB reset) 13 1 read-only TOGGLESQ_STA Toggle Sequencing (cleared upon USB reset) 6 2 read-only DATA0 DATA0 0x0 DATA1 DATA1 0x1 DATA2 Reserved for High Bandwidth Isochronous Endpoint 0x2 MDATA Reserved for High Bandwidth Isochronous Endpoint 0x3 TXRDY TX Packet Ready (cleared upon USB reset) 11 1 read-only TX_COMPLT Transmitted IN Data Complete (cleared upon USB reset) 10 1 read-only EPTSTA13_ISOENDPT UDPHS Endpoint Status Register (endpoint = 13) ISOENDPT 0x2BC 32 read-only n 0x0 0x0 BUSY_BANK_STA Busy Bank Number (cleared upon USB reset) 18 2 read-only 0BUSYBANK All banks are free 0x0 1BUSYBANK 1 busy bank 0x1 2BUSYBANKS 2 busy banks 0x2 3BUSYBANKS 3 busy banks 0x3 BYTE_COUNT UDPHS Byte Count (cleared upon USB reset) 20 11 read-only CURBK Current Bank (cleared upon USB reset) 16 2 read-only BANK0 Bank 0 (or single bank) 0x0 BANK1 Bank 1 0x1 BANK2 Bank 2 0x2 ERR_CRC_NTR CRC ISO Error/Number of Transaction Error (cleared upon USB reset) 13 1 read-only ERR_FLUSH Bank Flush Error (cleared upon USB reset) 14 1 read-only ERR_FL_ISO Error Flow (cleared upon USB reset) 12 1 read-only ERR_OVFLW Overflow Error (cleared upon USB reset) 8 1 read-only RXRDY_TXKL Received OUT Data/KILL Bank (cleared upon USB reset) 9 1 read-only SHRT_PCKT Short Packet (cleared upon USB reset) 31 1 read-only TOGGLESQ_STA Toggle Sequencing (cleared upon USB reset) 6 2 read-only DATA0 DATA0 0x0 DATA1 DATA1 0x1 DATA2 Data2 (only for High Bandwidth Isochronous Endpoint) 0x2 MDATA MData (only for High Bandwidth Isochronous Endpoint) 0x3 TXRDY_TRER TX Packet Ready/Transaction Error (cleared upon USB reset) 11 1 read-only TX_COMPLT Transmitted IN Data Complete (cleared upon USB reset) 10 1 read-only EPTSTA14 UDPHS Endpoint Status Register (endpoint = 14) 0x2DC 32 read-only n 0x0 0x0 BUSY_BANK_STA Busy Bank Number (cleared upon USB reset) 18 2 read-only 0BUSYBANK All banks are free 0x0 1BUSYBANK 1 busy bank 0x1 2BUSYBANKS 2 busy banks 0x2 3BUSYBANKS 3 busy banks 0x3 BYTE_COUNT UDPHS Byte Count (cleared upon USB reset) 20 11 read-only CURBK_CTLDIR Current Bank/Control Direction (cleared upon USB reset) 16 2 read-only ERR_OVFLW Overflow Error (cleared upon USB reset) 8 1 read-only FRCESTALL Stall Handshake Request (cleared upon USB reset) 5 1 read-only NAK_IN NAK IN (cleared upon USB reset) 14 1 read-only NAK_OUT NAK OUT (cleared upon USB reset) 15 1 read-only RXRDY_TXKL Received OUT Data/KILL Bank (cleared upon USB reset) 9 1 read-only RX_SETUP Received SETUP (cleared upon USB reset) 12 1 read-only SHRT_PCKT Short Packet (cleared upon USB reset) 31 1 read-only STALL_SNT Stall Sent (cleared upon USB reset) 13 1 read-only TOGGLESQ_STA Toggle Sequencing (cleared upon USB reset) 6 2 read-only DATA0 DATA0 0x0 DATA1 DATA1 0x1 DATA2 Reserved for High Bandwidth Isochronous Endpoint 0x2 MDATA Reserved for High Bandwidth Isochronous Endpoint 0x3 TXRDY TX Packet Ready (cleared upon USB reset) 11 1 read-only TX_COMPLT Transmitted IN Data Complete (cleared upon USB reset) 10 1 read-only EPTSTA14_ISOENDPT UDPHS Endpoint Status Register (endpoint = 14) ISOENDPT 0x2DC 32 read-only n 0x0 0x0 BUSY_BANK_STA Busy Bank Number (cleared upon USB reset) 18 2 read-only 0BUSYBANK All banks are free 0x0 1BUSYBANK 1 busy bank 0x1 2BUSYBANKS 2 busy banks 0x2 3BUSYBANKS 3 busy banks 0x3 BYTE_COUNT UDPHS Byte Count (cleared upon USB reset) 20 11 read-only CURBK Current Bank (cleared upon USB reset) 16 2 read-only BANK0 Bank 0 (or single bank) 0x0 BANK1 Bank 1 0x1 BANK2 Bank 2 0x2 ERR_CRC_NTR CRC ISO Error/Number of Transaction Error (cleared upon USB reset) 13 1 read-only ERR_FLUSH Bank Flush Error (cleared upon USB reset) 14 1 read-only ERR_FL_ISO Error Flow (cleared upon USB reset) 12 1 read-only ERR_OVFLW Overflow Error (cleared upon USB reset) 8 1 read-only RXRDY_TXKL Received OUT Data/KILL Bank (cleared upon USB reset) 9 1 read-only SHRT_PCKT Short Packet (cleared upon USB reset) 31 1 read-only TOGGLESQ_STA Toggle Sequencing (cleared upon USB reset) 6 2 read-only DATA0 DATA0 0x0 DATA1 DATA1 0x1 DATA2 Data2 (only for High Bandwidth Isochronous Endpoint) 0x2 MDATA MData (only for High Bandwidth Isochronous Endpoint) 0x3 TXRDY_TRER TX Packet Ready/Transaction Error (cleared upon USB reset) 11 1 read-only TX_COMPLT Transmitted IN Data Complete (cleared upon USB reset) 10 1 read-only EPTSTA15 UDPHS Endpoint Status Register (endpoint = 15) 0x2FC 32 read-only n 0x0 0x0 BUSY_BANK_STA Busy Bank Number (cleared upon USB reset) 18 2 read-only 0BUSYBANK All banks are free 0x0 1BUSYBANK 1 busy bank 0x1 2BUSYBANKS 2 busy banks 0x2 3BUSYBANKS 3 busy banks 0x3 BYTE_COUNT UDPHS Byte Count (cleared upon USB reset) 20 11 read-only CURBK_CTLDIR Current Bank/Control Direction (cleared upon USB reset) 16 2 read-only ERR_OVFLW Overflow Error (cleared upon USB reset) 8 1 read-only FRCESTALL Stall Handshake Request (cleared upon USB reset) 5 1 read-only NAK_IN NAK IN (cleared upon USB reset) 14 1 read-only NAK_OUT NAK OUT (cleared upon USB reset) 15 1 read-only RXRDY_TXKL Received OUT Data/KILL Bank (cleared upon USB reset) 9 1 read-only RX_SETUP Received SETUP (cleared upon USB reset) 12 1 read-only SHRT_PCKT Short Packet (cleared upon USB reset) 31 1 read-only STALL_SNT Stall Sent (cleared upon USB reset) 13 1 read-only TOGGLESQ_STA Toggle Sequencing (cleared upon USB reset) 6 2 read-only DATA0 DATA0 0x0 DATA1 DATA1 0x1 DATA2 Reserved for High Bandwidth Isochronous Endpoint 0x2 MDATA Reserved for High Bandwidth Isochronous Endpoint 0x3 TXRDY TX Packet Ready (cleared upon USB reset) 11 1 read-only TX_COMPLT Transmitted IN Data Complete (cleared upon USB reset) 10 1 read-only EPTSTA15_ISOENDPT UDPHS Endpoint Status Register (endpoint = 15) ISOENDPT 0x2FC 32 read-only n 0x0 0x0 BUSY_BANK_STA Busy Bank Number (cleared upon USB reset) 18 2 read-only 0BUSYBANK All banks are free 0x0 1BUSYBANK 1 busy bank 0x1 2BUSYBANKS 2 busy banks 0x2 3BUSYBANKS 3 busy banks 0x3 BYTE_COUNT UDPHS Byte Count (cleared upon USB reset) 20 11 read-only CURBK Current Bank (cleared upon USB reset) 16 2 read-only BANK0 Bank 0 (or single bank) 0x0 BANK1 Bank 1 0x1 BANK2 Bank 2 0x2 ERR_CRC_NTR CRC ISO Error/Number of Transaction Error (cleared upon USB reset) 13 1 read-only ERR_FLUSH Bank Flush Error (cleared upon USB reset) 14 1 read-only ERR_FL_ISO Error Flow (cleared upon USB reset) 12 1 read-only ERR_OVFLW Overflow Error (cleared upon USB reset) 8 1 read-only RXRDY_TXKL Received OUT Data/KILL Bank (cleared upon USB reset) 9 1 read-only SHRT_PCKT Short Packet (cleared upon USB reset) 31 1 read-only TOGGLESQ_STA Toggle Sequencing (cleared upon USB reset) 6 2 read-only DATA0 DATA0 0x0 DATA1 DATA1 0x1 DATA2 Data2 (only for High Bandwidth Isochronous Endpoint) 0x2 MDATA MData (only for High Bandwidth Isochronous Endpoint) 0x3 TXRDY_TRER TX Packet Ready/Transaction Error (cleared upon USB reset) 11 1 read-only TX_COMPLT Transmitted IN Data Complete (cleared upon USB reset) 10 1 read-only EPTSTA1_ISOENDPT UDPHS Endpoint Status Register (endpoint = 1) ISOENDPT 0x13C 32 read-only n 0x0 0x0 BUSY_BANK_STA Busy Bank Number (cleared upon USB reset) 18 2 read-only 0BUSYBANK All banks are free 0x0 1BUSYBANK 1 busy bank 0x1 2BUSYBANKS 2 busy banks 0x2 3BUSYBANKS 3 busy banks 0x3 BYTE_COUNT UDPHS Byte Count (cleared upon USB reset) 20 11 read-only CURBK Current Bank (cleared upon USB reset) 16 2 read-only BANK0 Bank 0 (or single bank) 0x0 BANK1 Bank 1 0x1 BANK2 Bank 2 0x2 ERR_CRC_NTR CRC ISO Error/Number of Transaction Error (cleared upon USB reset) 13 1 read-only ERR_FLUSH Bank Flush Error (cleared upon USB reset) 14 1 read-only ERR_FL_ISO Error Flow (cleared upon USB reset) 12 1 read-only ERR_OVFLW Overflow Error (cleared upon USB reset) 8 1 read-only RXRDY_TXKL Received OUT Data/KILL Bank (cleared upon USB reset) 9 1 read-only SHRT_PCKT Short Packet (cleared upon USB reset) 31 1 read-only TOGGLESQ_STA Toggle Sequencing (cleared upon USB reset) 6 2 read-only DATA0 DATA0 0x0 DATA1 DATA1 0x1 DATA2 Data2 (only for High Bandwidth Isochronous Endpoint) 0x2 MDATA MData (only for High Bandwidth Isochronous Endpoint) 0x3 TXRDY_TRER TX Packet Ready/Transaction Error (cleared upon USB reset) 11 1 read-only TX_COMPLT Transmitted IN Data Complete (cleared upon USB reset) 10 1 read-only EPTSTA2 UDPHS Endpoint Status Register (endpoint = 2) 0x15C 32 read-only n 0x0 0x0 BUSY_BANK_STA Busy Bank Number (cleared upon USB reset) 18 2 read-only 0BUSYBANK All banks are free 0x0 1BUSYBANK 1 busy bank 0x1 2BUSYBANKS 2 busy banks 0x2 3BUSYBANKS 3 busy banks 0x3 BYTE_COUNT UDPHS Byte Count (cleared upon USB reset) 20 11 read-only CURBK_CTLDIR Current Bank/Control Direction (cleared upon USB reset) 16 2 read-only ERR_OVFLW Overflow Error (cleared upon USB reset) 8 1 read-only FRCESTALL Stall Handshake Request (cleared upon USB reset) 5 1 read-only NAK_IN NAK IN (cleared upon USB reset) 14 1 read-only NAK_OUT NAK OUT (cleared upon USB reset) 15 1 read-only RXRDY_TXKL Received OUT Data/KILL Bank (cleared upon USB reset) 9 1 read-only RX_SETUP Received SETUP (cleared upon USB reset) 12 1 read-only SHRT_PCKT Short Packet (cleared upon USB reset) 31 1 read-only STALL_SNT Stall Sent (cleared upon USB reset) 13 1 read-only TOGGLESQ_STA Toggle Sequencing (cleared upon USB reset) 6 2 read-only DATA0 DATA0 0x0 DATA1 DATA1 0x1 DATA2 Reserved for High Bandwidth Isochronous Endpoint 0x2 MDATA Reserved for High Bandwidth Isochronous Endpoint 0x3 TXRDY TX Packet Ready (cleared upon USB reset) 11 1 read-only TX_COMPLT Transmitted IN Data Complete (cleared upon USB reset) 10 1 read-only EPTSTA2_ISOENDPT UDPHS Endpoint Status Register (endpoint = 2) ISOENDPT 0x15C 32 read-only n 0x0 0x0 BUSY_BANK_STA Busy Bank Number (cleared upon USB reset) 18 2 read-only 0BUSYBANK All banks are free 0x0 1BUSYBANK 1 busy bank 0x1 2BUSYBANKS 2 busy banks 0x2 3BUSYBANKS 3 busy banks 0x3 BYTE_COUNT UDPHS Byte Count (cleared upon USB reset) 20 11 read-only CURBK Current Bank (cleared upon USB reset) 16 2 read-only BANK0 Bank 0 (or single bank) 0x0 BANK1 Bank 1 0x1 BANK2 Bank 2 0x2 ERR_CRC_NTR CRC ISO Error/Number of Transaction Error (cleared upon USB reset) 13 1 read-only ERR_FLUSH Bank Flush Error (cleared upon USB reset) 14 1 read-only ERR_FL_ISO Error Flow (cleared upon USB reset) 12 1 read-only ERR_OVFLW Overflow Error (cleared upon USB reset) 8 1 read-only RXRDY_TXKL Received OUT Data/KILL Bank (cleared upon USB reset) 9 1 read-only SHRT_PCKT Short Packet (cleared upon USB reset) 31 1 read-only TOGGLESQ_STA Toggle Sequencing (cleared upon USB reset) 6 2 read-only DATA0 DATA0 0x0 DATA1 DATA1 0x1 DATA2 Data2 (only for High Bandwidth Isochronous Endpoint) 0x2 MDATA MData (only for High Bandwidth Isochronous Endpoint) 0x3 TXRDY_TRER TX Packet Ready/Transaction Error (cleared upon USB reset) 11 1 read-only TX_COMPLT Transmitted IN Data Complete (cleared upon USB reset) 10 1 read-only EPTSTA3 UDPHS Endpoint Status Register (endpoint = 3) 0x17C 32 read-only n 0x0 0x0 BUSY_BANK_STA Busy Bank Number (cleared upon USB reset) 18 2 read-only 0BUSYBANK All banks are free 0x0 1BUSYBANK 1 busy bank 0x1 2BUSYBANKS 2 busy banks 0x2 3BUSYBANKS 3 busy banks 0x3 BYTE_COUNT UDPHS Byte Count (cleared upon USB reset) 20 11 read-only CURBK_CTLDIR Current Bank/Control Direction (cleared upon USB reset) 16 2 read-only ERR_OVFLW Overflow Error (cleared upon USB reset) 8 1 read-only FRCESTALL Stall Handshake Request (cleared upon USB reset) 5 1 read-only NAK_IN NAK IN (cleared upon USB reset) 14 1 read-only NAK_OUT NAK OUT (cleared upon USB reset) 15 1 read-only RXRDY_TXKL Received OUT Data/KILL Bank (cleared upon USB reset) 9 1 read-only RX_SETUP Received SETUP (cleared upon USB reset) 12 1 read-only SHRT_PCKT Short Packet (cleared upon USB reset) 31 1 read-only STALL_SNT Stall Sent (cleared upon USB reset) 13 1 read-only TOGGLESQ_STA Toggle Sequencing (cleared upon USB reset) 6 2 read-only DATA0 DATA0 0x0 DATA1 DATA1 0x1 DATA2 Reserved for High Bandwidth Isochronous Endpoint 0x2 MDATA Reserved for High Bandwidth Isochronous Endpoint 0x3 TXRDY TX Packet Ready (cleared upon USB reset) 11 1 read-only TX_COMPLT Transmitted IN Data Complete (cleared upon USB reset) 10 1 read-only EPTSTA3_ISOENDPT UDPHS Endpoint Status Register (endpoint = 3) ISOENDPT 0x17C 32 read-only n 0x0 0x0 BUSY_BANK_STA Busy Bank Number (cleared upon USB reset) 18 2 read-only 0BUSYBANK All banks are free 0x0 1BUSYBANK 1 busy bank 0x1 2BUSYBANKS 2 busy banks 0x2 3BUSYBANKS 3 busy banks 0x3 BYTE_COUNT UDPHS Byte Count (cleared upon USB reset) 20 11 read-only CURBK Current Bank (cleared upon USB reset) 16 2 read-only BANK0 Bank 0 (or single bank) 0x0 BANK1 Bank 1 0x1 BANK2 Bank 2 0x2 ERR_CRC_NTR CRC ISO Error/Number of Transaction Error (cleared upon USB reset) 13 1 read-only ERR_FLUSH Bank Flush Error (cleared upon USB reset) 14 1 read-only ERR_FL_ISO Error Flow (cleared upon USB reset) 12 1 read-only ERR_OVFLW Overflow Error (cleared upon USB reset) 8 1 read-only RXRDY_TXKL Received OUT Data/KILL Bank (cleared upon USB reset) 9 1 read-only SHRT_PCKT Short Packet (cleared upon USB reset) 31 1 read-only TOGGLESQ_STA Toggle Sequencing (cleared upon USB reset) 6 2 read-only DATA0 DATA0 0x0 DATA1 DATA1 0x1 DATA2 Data2 (only for High Bandwidth Isochronous Endpoint) 0x2 MDATA MData (only for High Bandwidth Isochronous Endpoint) 0x3 TXRDY_TRER TX Packet Ready/Transaction Error (cleared upon USB reset) 11 1 read-only TX_COMPLT Transmitted IN Data Complete (cleared upon USB reset) 10 1 read-only EPTSTA4 UDPHS Endpoint Status Register (endpoint = 4) 0x19C 32 read-only n 0x0 0x0 BUSY_BANK_STA Busy Bank Number (cleared upon USB reset) 18 2 read-only 0BUSYBANK All banks are free 0x0 1BUSYBANK 1 busy bank 0x1 2BUSYBANKS 2 busy banks 0x2 3BUSYBANKS 3 busy banks 0x3 BYTE_COUNT UDPHS Byte Count (cleared upon USB reset) 20 11 read-only CURBK_CTLDIR Current Bank/Control Direction (cleared upon USB reset) 16 2 read-only ERR_OVFLW Overflow Error (cleared upon USB reset) 8 1 read-only FRCESTALL Stall Handshake Request (cleared upon USB reset) 5 1 read-only NAK_IN NAK IN (cleared upon USB reset) 14 1 read-only NAK_OUT NAK OUT (cleared upon USB reset) 15 1 read-only RXRDY_TXKL Received OUT Data/KILL Bank (cleared upon USB reset) 9 1 read-only RX_SETUP Received SETUP (cleared upon USB reset) 12 1 read-only SHRT_PCKT Short Packet (cleared upon USB reset) 31 1 read-only STALL_SNT Stall Sent (cleared upon USB reset) 13 1 read-only TOGGLESQ_STA Toggle Sequencing (cleared upon USB reset) 6 2 read-only DATA0 DATA0 0x0 DATA1 DATA1 0x1 DATA2 Reserved for High Bandwidth Isochronous Endpoint 0x2 MDATA Reserved for High Bandwidth Isochronous Endpoint 0x3 TXRDY TX Packet Ready (cleared upon USB reset) 11 1 read-only TX_COMPLT Transmitted IN Data Complete (cleared upon USB reset) 10 1 read-only EPTSTA4_ISOENDPT UDPHS Endpoint Status Register (endpoint = 4) ISOENDPT 0x19C 32 read-only n 0x0 0x0 BUSY_BANK_STA Busy Bank Number (cleared upon USB reset) 18 2 read-only 0BUSYBANK All banks are free 0x0 1BUSYBANK 1 busy bank 0x1 2BUSYBANKS 2 busy banks 0x2 3BUSYBANKS 3 busy banks 0x3 BYTE_COUNT UDPHS Byte Count (cleared upon USB reset) 20 11 read-only CURBK Current Bank (cleared upon USB reset) 16 2 read-only BANK0 Bank 0 (or single bank) 0x0 BANK1 Bank 1 0x1 BANK2 Bank 2 0x2 ERR_CRC_NTR CRC ISO Error/Number of Transaction Error (cleared upon USB reset) 13 1 read-only ERR_FLUSH Bank Flush Error (cleared upon USB reset) 14 1 read-only ERR_FL_ISO Error Flow (cleared upon USB reset) 12 1 read-only ERR_OVFLW Overflow Error (cleared upon USB reset) 8 1 read-only RXRDY_TXKL Received OUT Data/KILL Bank (cleared upon USB reset) 9 1 read-only SHRT_PCKT Short Packet (cleared upon USB reset) 31 1 read-only TOGGLESQ_STA Toggle Sequencing (cleared upon USB reset) 6 2 read-only DATA0 DATA0 0x0 DATA1 DATA1 0x1 DATA2 Data2 (only for High Bandwidth Isochronous Endpoint) 0x2 MDATA MData (only for High Bandwidth Isochronous Endpoint) 0x3 TXRDY_TRER TX Packet Ready/Transaction Error (cleared upon USB reset) 11 1 read-only TX_COMPLT Transmitted IN Data Complete (cleared upon USB reset) 10 1 read-only EPTSTA5 UDPHS Endpoint Status Register (endpoint = 5) 0x1BC 32 read-only n 0x0 0x0 BUSY_BANK_STA Busy Bank Number (cleared upon USB reset) 18 2 read-only 0BUSYBANK All banks are free 0x0 1BUSYBANK 1 busy bank 0x1 2BUSYBANKS 2 busy banks 0x2 3BUSYBANKS 3 busy banks 0x3 BYTE_COUNT UDPHS Byte Count (cleared upon USB reset) 20 11 read-only CURBK_CTLDIR Current Bank/Control Direction (cleared upon USB reset) 16 2 read-only ERR_OVFLW Overflow Error (cleared upon USB reset) 8 1 read-only FRCESTALL Stall Handshake Request (cleared upon USB reset) 5 1 read-only NAK_IN NAK IN (cleared upon USB reset) 14 1 read-only NAK_OUT NAK OUT (cleared upon USB reset) 15 1 read-only RXRDY_TXKL Received OUT Data/KILL Bank (cleared upon USB reset) 9 1 read-only RX_SETUP Received SETUP (cleared upon USB reset) 12 1 read-only SHRT_PCKT Short Packet (cleared upon USB reset) 31 1 read-only STALL_SNT Stall Sent (cleared upon USB reset) 13 1 read-only TOGGLESQ_STA Toggle Sequencing (cleared upon USB reset) 6 2 read-only DATA0 DATA0 0x0 DATA1 DATA1 0x1 DATA2 Reserved for High Bandwidth Isochronous Endpoint 0x2 MDATA Reserved for High Bandwidth Isochronous Endpoint 0x3 TXRDY TX Packet Ready (cleared upon USB reset) 11 1 read-only TX_COMPLT Transmitted IN Data Complete (cleared upon USB reset) 10 1 read-only EPTSTA5_ISOENDPT UDPHS Endpoint Status Register (endpoint = 5) ISOENDPT 0x1BC 32 read-only n 0x0 0x0 BUSY_BANK_STA Busy Bank Number (cleared upon USB reset) 18 2 read-only 0BUSYBANK All banks are free 0x0 1BUSYBANK 1 busy bank 0x1 2BUSYBANKS 2 busy banks 0x2 3BUSYBANKS 3 busy banks 0x3 BYTE_COUNT UDPHS Byte Count (cleared upon USB reset) 20 11 read-only CURBK Current Bank (cleared upon USB reset) 16 2 read-only BANK0 Bank 0 (or single bank) 0x0 BANK1 Bank 1 0x1 BANK2 Bank 2 0x2 ERR_CRC_NTR CRC ISO Error/Number of Transaction Error (cleared upon USB reset) 13 1 read-only ERR_FLUSH Bank Flush Error (cleared upon USB reset) 14 1 read-only ERR_FL_ISO Error Flow (cleared upon USB reset) 12 1 read-only ERR_OVFLW Overflow Error (cleared upon USB reset) 8 1 read-only RXRDY_TXKL Received OUT Data/KILL Bank (cleared upon USB reset) 9 1 read-only SHRT_PCKT Short Packet (cleared upon USB reset) 31 1 read-only TOGGLESQ_STA Toggle Sequencing (cleared upon USB reset) 6 2 read-only DATA0 DATA0 0x0 DATA1 DATA1 0x1 DATA2 Data2 (only for High Bandwidth Isochronous Endpoint) 0x2 MDATA MData (only for High Bandwidth Isochronous Endpoint) 0x3 TXRDY_TRER TX Packet Ready/Transaction Error (cleared upon USB reset) 11 1 read-only TX_COMPLT Transmitted IN Data Complete (cleared upon USB reset) 10 1 read-only EPTSTA6 UDPHS Endpoint Status Register (endpoint = 6) 0x1DC 32 read-only n 0x0 0x0 BUSY_BANK_STA Busy Bank Number (cleared upon USB reset) 18 2 read-only 0BUSYBANK All banks are free 0x0 1BUSYBANK 1 busy bank 0x1 2BUSYBANKS 2 busy banks 0x2 3BUSYBANKS 3 busy banks 0x3 BYTE_COUNT UDPHS Byte Count (cleared upon USB reset) 20 11 read-only CURBK_CTLDIR Current Bank/Control Direction (cleared upon USB reset) 16 2 read-only ERR_OVFLW Overflow Error (cleared upon USB reset) 8 1 read-only FRCESTALL Stall Handshake Request (cleared upon USB reset) 5 1 read-only NAK_IN NAK IN (cleared upon USB reset) 14 1 read-only NAK_OUT NAK OUT (cleared upon USB reset) 15 1 read-only RXRDY_TXKL Received OUT Data/KILL Bank (cleared upon USB reset) 9 1 read-only RX_SETUP Received SETUP (cleared upon USB reset) 12 1 read-only SHRT_PCKT Short Packet (cleared upon USB reset) 31 1 read-only STALL_SNT Stall Sent (cleared upon USB reset) 13 1 read-only TOGGLESQ_STA Toggle Sequencing (cleared upon USB reset) 6 2 read-only DATA0 DATA0 0x0 DATA1 DATA1 0x1 DATA2 Reserved for High Bandwidth Isochronous Endpoint 0x2 MDATA Reserved for High Bandwidth Isochronous Endpoint 0x3 TXRDY TX Packet Ready (cleared upon USB reset) 11 1 read-only TX_COMPLT Transmitted IN Data Complete (cleared upon USB reset) 10 1 read-only EPTSTA6_ISOENDPT UDPHS Endpoint Status Register (endpoint = 6) ISOENDPT 0x1DC 32 read-only n 0x0 0x0 BUSY_BANK_STA Busy Bank Number (cleared upon USB reset) 18 2 read-only 0BUSYBANK All banks are free 0x0 1BUSYBANK 1 busy bank 0x1 2BUSYBANKS 2 busy banks 0x2 3BUSYBANKS 3 busy banks 0x3 BYTE_COUNT UDPHS Byte Count (cleared upon USB reset) 20 11 read-only CURBK Current Bank (cleared upon USB reset) 16 2 read-only BANK0 Bank 0 (or single bank) 0x0 BANK1 Bank 1 0x1 BANK2 Bank 2 0x2 ERR_CRC_NTR CRC ISO Error/Number of Transaction Error (cleared upon USB reset) 13 1 read-only ERR_FLUSH Bank Flush Error (cleared upon USB reset) 14 1 read-only ERR_FL_ISO Error Flow (cleared upon USB reset) 12 1 read-only ERR_OVFLW Overflow Error (cleared upon USB reset) 8 1 read-only RXRDY_TXKL Received OUT Data/KILL Bank (cleared upon USB reset) 9 1 read-only SHRT_PCKT Short Packet (cleared upon USB reset) 31 1 read-only TOGGLESQ_STA Toggle Sequencing (cleared upon USB reset) 6 2 read-only DATA0 DATA0 0x0 DATA1 DATA1 0x1 DATA2 Data2 (only for High Bandwidth Isochronous Endpoint) 0x2 MDATA MData (only for High Bandwidth Isochronous Endpoint) 0x3 TXRDY_TRER TX Packet Ready/Transaction Error (cleared upon USB reset) 11 1 read-only TX_COMPLT Transmitted IN Data Complete (cleared upon USB reset) 10 1 read-only EPTSTA7 UDPHS Endpoint Status Register (endpoint = 7) 0x1FC 32 read-only n 0x0 0x0 BUSY_BANK_STA Busy Bank Number (cleared upon USB reset) 18 2 read-only 0BUSYBANK All banks are free 0x0 1BUSYBANK 1 busy bank 0x1 2BUSYBANKS 2 busy banks 0x2 3BUSYBANKS 3 busy banks 0x3 BYTE_COUNT UDPHS Byte Count (cleared upon USB reset) 20 11 read-only CURBK_CTLDIR Current Bank/Control Direction (cleared upon USB reset) 16 2 read-only ERR_OVFLW Overflow Error (cleared upon USB reset) 8 1 read-only FRCESTALL Stall Handshake Request (cleared upon USB reset) 5 1 read-only NAK_IN NAK IN (cleared upon USB reset) 14 1 read-only NAK_OUT NAK OUT (cleared upon USB reset) 15 1 read-only RXRDY_TXKL Received OUT Data/KILL Bank (cleared upon USB reset) 9 1 read-only RX_SETUP Received SETUP (cleared upon USB reset) 12 1 read-only SHRT_PCKT Short Packet (cleared upon USB reset) 31 1 read-only STALL_SNT Stall Sent (cleared upon USB reset) 13 1 read-only TOGGLESQ_STA Toggle Sequencing (cleared upon USB reset) 6 2 read-only DATA0 DATA0 0x0 DATA1 DATA1 0x1 DATA2 Reserved for High Bandwidth Isochronous Endpoint 0x2 MDATA Reserved for High Bandwidth Isochronous Endpoint 0x3 TXRDY TX Packet Ready (cleared upon USB reset) 11 1 read-only TX_COMPLT Transmitted IN Data Complete (cleared upon USB reset) 10 1 read-only EPTSTA7_ISOENDPT UDPHS Endpoint Status Register (endpoint = 7) ISOENDPT 0x1FC 32 read-only n 0x0 0x0 BUSY_BANK_STA Busy Bank Number (cleared upon USB reset) 18 2 read-only 0BUSYBANK All banks are free 0x0 1BUSYBANK 1 busy bank 0x1 2BUSYBANKS 2 busy banks 0x2 3BUSYBANKS 3 busy banks 0x3 BYTE_COUNT UDPHS Byte Count (cleared upon USB reset) 20 11 read-only CURBK Current Bank (cleared upon USB reset) 16 2 read-only BANK0 Bank 0 (or single bank) 0x0 BANK1 Bank 1 0x1 BANK2 Bank 2 0x2 ERR_CRC_NTR CRC ISO Error/Number of Transaction Error (cleared upon USB reset) 13 1 read-only ERR_FLUSH Bank Flush Error (cleared upon USB reset) 14 1 read-only ERR_FL_ISO Error Flow (cleared upon USB reset) 12 1 read-only ERR_OVFLW Overflow Error (cleared upon USB reset) 8 1 read-only RXRDY_TXKL Received OUT Data/KILL Bank (cleared upon USB reset) 9 1 read-only SHRT_PCKT Short Packet (cleared upon USB reset) 31 1 read-only TOGGLESQ_STA Toggle Sequencing (cleared upon USB reset) 6 2 read-only DATA0 DATA0 0x0 DATA1 DATA1 0x1 DATA2 Data2 (only for High Bandwidth Isochronous Endpoint) 0x2 MDATA MData (only for High Bandwidth Isochronous Endpoint) 0x3 TXRDY_TRER TX Packet Ready/Transaction Error (cleared upon USB reset) 11 1 read-only TX_COMPLT Transmitted IN Data Complete (cleared upon USB reset) 10 1 read-only EPTSTA8 UDPHS Endpoint Status Register (endpoint = 8) 0x21C 32 read-only n 0x0 0x0 BUSY_BANK_STA Busy Bank Number (cleared upon USB reset) 18 2 read-only 0BUSYBANK All banks are free 0x0 1BUSYBANK 1 busy bank 0x1 2BUSYBANKS 2 busy banks 0x2 3BUSYBANKS 3 busy banks 0x3 BYTE_COUNT UDPHS Byte Count (cleared upon USB reset) 20 11 read-only CURBK_CTLDIR Current Bank/Control Direction (cleared upon USB reset) 16 2 read-only ERR_OVFLW Overflow Error (cleared upon USB reset) 8 1 read-only FRCESTALL Stall Handshake Request (cleared upon USB reset) 5 1 read-only NAK_IN NAK IN (cleared upon USB reset) 14 1 read-only NAK_OUT NAK OUT (cleared upon USB reset) 15 1 read-only RXRDY_TXKL Received OUT Data/KILL Bank (cleared upon USB reset) 9 1 read-only RX_SETUP Received SETUP (cleared upon USB reset) 12 1 read-only SHRT_PCKT Short Packet (cleared upon USB reset) 31 1 read-only STALL_SNT Stall Sent (cleared upon USB reset) 13 1 read-only TOGGLESQ_STA Toggle Sequencing (cleared upon USB reset) 6 2 read-only DATA0 DATA0 0x0 DATA1 DATA1 0x1 DATA2 Reserved for High Bandwidth Isochronous Endpoint 0x2 MDATA Reserved for High Bandwidth Isochronous Endpoint 0x3 TXRDY TX Packet Ready (cleared upon USB reset) 11 1 read-only TX_COMPLT Transmitted IN Data Complete (cleared upon USB reset) 10 1 read-only EPTSTA8_ISOENDPT UDPHS Endpoint Status Register (endpoint = 8) ISOENDPT 0x21C 32 read-only n 0x0 0x0 BUSY_BANK_STA Busy Bank Number (cleared upon USB reset) 18 2 read-only 0BUSYBANK All banks are free 0x0 1BUSYBANK 1 busy bank 0x1 2BUSYBANKS 2 busy banks 0x2 3BUSYBANKS 3 busy banks 0x3 BYTE_COUNT UDPHS Byte Count (cleared upon USB reset) 20 11 read-only CURBK Current Bank (cleared upon USB reset) 16 2 read-only BANK0 Bank 0 (or single bank) 0x0 BANK1 Bank 1 0x1 BANK2 Bank 2 0x2 ERR_CRC_NTR CRC ISO Error/Number of Transaction Error (cleared upon USB reset) 13 1 read-only ERR_FLUSH Bank Flush Error (cleared upon USB reset) 14 1 read-only ERR_FL_ISO Error Flow (cleared upon USB reset) 12 1 read-only ERR_OVFLW Overflow Error (cleared upon USB reset) 8 1 read-only RXRDY_TXKL Received OUT Data/KILL Bank (cleared upon USB reset) 9 1 read-only SHRT_PCKT Short Packet (cleared upon USB reset) 31 1 read-only TOGGLESQ_STA Toggle Sequencing (cleared upon USB reset) 6 2 read-only DATA0 DATA0 0x0 DATA1 DATA1 0x1 DATA2 Data2 (only for High Bandwidth Isochronous Endpoint) 0x2 MDATA MData (only for High Bandwidth Isochronous Endpoint) 0x3 TXRDY_TRER TX Packet Ready/Transaction Error (cleared upon USB reset) 11 1 read-only TX_COMPLT Transmitted IN Data Complete (cleared upon USB reset) 10 1 read-only EPTSTA9 UDPHS Endpoint Status Register (endpoint = 9) 0x23C 32 read-only n 0x0 0x0 BUSY_BANK_STA Busy Bank Number (cleared upon USB reset) 18 2 read-only 0BUSYBANK All banks are free 0x0 1BUSYBANK 1 busy bank 0x1 2BUSYBANKS 2 busy banks 0x2 3BUSYBANKS 3 busy banks 0x3 BYTE_COUNT UDPHS Byte Count (cleared upon USB reset) 20 11 read-only CURBK_CTLDIR Current Bank/Control Direction (cleared upon USB reset) 16 2 read-only ERR_OVFLW Overflow Error (cleared upon USB reset) 8 1 read-only FRCESTALL Stall Handshake Request (cleared upon USB reset) 5 1 read-only NAK_IN NAK IN (cleared upon USB reset) 14 1 read-only NAK_OUT NAK OUT (cleared upon USB reset) 15 1 read-only RXRDY_TXKL Received OUT Data/KILL Bank (cleared upon USB reset) 9 1 read-only RX_SETUP Received SETUP (cleared upon USB reset) 12 1 read-only SHRT_PCKT Short Packet (cleared upon USB reset) 31 1 read-only STALL_SNT Stall Sent (cleared upon USB reset) 13 1 read-only TOGGLESQ_STA Toggle Sequencing (cleared upon USB reset) 6 2 read-only DATA0 DATA0 0x0 DATA1 DATA1 0x1 DATA2 Reserved for High Bandwidth Isochronous Endpoint 0x2 MDATA Reserved for High Bandwidth Isochronous Endpoint 0x3 TXRDY TX Packet Ready (cleared upon USB reset) 11 1 read-only TX_COMPLT Transmitted IN Data Complete (cleared upon USB reset) 10 1 read-only EPTSTA9_ISOENDPT UDPHS Endpoint Status Register (endpoint = 9) ISOENDPT 0x23C 32 read-only n 0x0 0x0 BUSY_BANK_STA Busy Bank Number (cleared upon USB reset) 18 2 read-only 0BUSYBANK All banks are free 0x0 1BUSYBANK 1 busy bank 0x1 2BUSYBANKS 2 busy banks 0x2 3BUSYBANKS 3 busy banks 0x3 BYTE_COUNT UDPHS Byte Count (cleared upon USB reset) 20 11 read-only CURBK Current Bank (cleared upon USB reset) 16 2 read-only BANK0 Bank 0 (or single bank) 0x0 BANK1 Bank 1 0x1 BANK2 Bank 2 0x2 ERR_CRC_NTR CRC ISO Error/Number of Transaction Error (cleared upon USB reset) 13 1 read-only ERR_FLUSH Bank Flush Error (cleared upon USB reset) 14 1 read-only ERR_FL_ISO Error Flow (cleared upon USB reset) 12 1 read-only ERR_OVFLW Overflow Error (cleared upon USB reset) 8 1 read-only RXRDY_TXKL Received OUT Data/KILL Bank (cleared upon USB reset) 9 1 read-only SHRT_PCKT Short Packet (cleared upon USB reset) 31 1 read-only TOGGLESQ_STA Toggle Sequencing (cleared upon USB reset) 6 2 read-only DATA0 DATA0 0x0 DATA1 DATA1 0x1 DATA2 Data2 (only for High Bandwidth Isochronous Endpoint) 0x2 MDATA MData (only for High Bandwidth Isochronous Endpoint) 0x3 TXRDY_TRER TX Packet Ready/Transaction Error (cleared upon USB reset) 11 1 read-only TX_COMPLT Transmitted IN Data Complete (cleared upon USB reset) 10 1 read-only FNUM UDPHS Frame Number Register 0x4 32 read-only n 0x0 0x0 FNUM_ERR Frame Number CRC Error (cleared upon USB reset) 31 1 read-only FRAME_NUMBER Frame Number as defined in the Packet Field Formats (cleared upon USB reset) 3 11 read-only MICRO_FRAME_NUM Microframe Number (cleared upon USB reset) 0 3 read-only IEN UDPHS Interrupt Enable Register 0x10 32 read-write n 0x0 0x0 DET_SUSPD Suspend Interrupt Enable (cleared upon USB reset) 1 1 read-write DMA_1 DMA Channel 1 Interrupt Enable (cleared upon USB reset) 25 1 read-write DMA_2 DMA Channel 2 Interrupt Enable (cleared upon USB reset) 26 1 read-write DMA_3 DMA Channel 3 Interrupt Enable (cleared upon USB reset) 27 1 read-write DMA_4 DMA Channel 4 Interrupt Enable (cleared upon USB reset) 28 1 read-write DMA_5 DMA Channel 5 Interrupt Enable (cleared upon USB reset) 29 1 read-write DMA_6 DMA Channel 6 Interrupt Enable (cleared upon USB reset) 30 1 read-write DMA_7 DMA Channel 7 Interrupt Enable (cleared upon USB reset) 31 1 read-write ENDOFRSM End Of Resume Interrupt Enable (cleared upon USB reset) 6 1 read-write ENDRESET End Of Reset Interrupt Enable (cleared upon USB reset) 4 1 read-write EPT_0 Endpoint 0 Interrupt Enable (cleared upon USB reset) 8 1 read-write EPT_1 Endpoint 1 Interrupt Enable (cleared upon USB reset) 9 1 read-write EPT_10 Endpoint 10 Interrupt Enable (cleared upon USB reset) 18 1 read-write EPT_11 Endpoint 11 Interrupt Enable (cleared upon USB reset) 19 1 read-write EPT_12 Endpoint 12 Interrupt Enable (cleared upon USB reset) 20 1 read-write EPT_13 Endpoint 13 Interrupt Enable (cleared upon USB reset) 21 1 read-write EPT_14 Endpoint 14 Interrupt Enable (cleared upon USB reset) 22 1 read-write EPT_15 Endpoint 15 Interrupt Enable (cleared upon USB reset) 23 1 read-write EPT_2 Endpoint 2 Interrupt Enable (cleared upon USB reset) 10 1 read-write EPT_3 Endpoint 3 Interrupt Enable (cleared upon USB reset) 11 1 read-write EPT_4 Endpoint 4 Interrupt Enable (cleared upon USB reset) 12 1 read-write EPT_5 Endpoint 5 Interrupt Enable (cleared upon USB reset) 13 1 read-write EPT_6 Endpoint 6 Interrupt Enable (cleared upon USB reset) 14 1 read-write EPT_7 Endpoint 7 Interrupt Enable (cleared upon USB reset) 15 1 read-write EPT_8 Endpoint 8 Interrupt Enable (cleared upon USB reset) 16 1 read-write EPT_9 Endpoint 9 Interrupt Enable (cleared upon USB reset) 17 1 read-write INT_SOF SOF Interrupt Enable (cleared upon USB reset) 3 1 read-write MICRO_SOF Micro-SOF Interrupt Enable (cleared upon USB reset) 2 1 read-write UPSTR_RES Upstream Resume Interrupt Enable (cleared upon USB reset) 7 1 read-write WAKE_UP Wake Up CPU Interrupt Enable (cleared upon USB reset) 5 1 read-write INTSTA UDPHS Interrupt Status Register 0x14 32 read-only n 0x0 0x0 DET_SUSPD Suspend Interrupt 1 1 read-only DMA_1 DMA Channel 1 Interrupt 25 1 read-only DMA_2 DMA Channel 2 Interrupt 26 1 read-only DMA_3 DMA Channel 3 Interrupt 27 1 read-only DMA_4 DMA Channel 4 Interrupt 28 1 read-only DMA_5 DMA Channel 5 Interrupt 29 1 read-only DMA_6 DMA Channel 6 Interrupt 30 1 read-only DMA_7 DMA Channel 7 Interrupt 31 1 read-only ENDOFRSM End Of Resume Interrupt 6 1 read-only ENDRESET End Of Reset Interrupt 4 1 read-only EPT_0 Endpoint 0 Interrupt (cleared upon USB reset) 8 1 read-only EPT_1 Endpoint 1 Interrupt (cleared upon USB reset) 9 1 read-only EPT_10 Endpoint 10 Interrupt (cleared upon USB reset) 18 1 read-only EPT_11 Endpoint 11 Interrupt (cleared upon USB reset) 19 1 read-only EPT_12 Endpoint 12 Interrupt (cleared upon USB reset) 20 1 read-only EPT_13 Endpoint 13 Interrupt (cleared upon USB reset) 21 1 read-only EPT_14 Endpoint 14 Interrupt (cleared upon USB reset) 22 1 read-only EPT_15 Endpoint 15 Interrupt (cleared upon USB reset) 23 1 read-only EPT_2 Endpoint 2 Interrupt (cleared upon USB reset) 10 1 read-only EPT_3 Endpoint 3 Interrupt (cleared upon USB reset) 11 1 read-only EPT_4 Endpoint 4 Interrupt (cleared upon USB reset) 12 1 read-only EPT_5 Endpoint 5 Interrupt (cleared upon USB reset) 13 1 read-only EPT_6 Endpoint 6 Interrupt (cleared upon USB reset) 14 1 read-only EPT_7 Endpoint 7 Interrupt (cleared upon USB reset) 15 1 read-only EPT_8 Endpoint 8 Interrupt (cleared upon USB reset) 16 1 read-only EPT_9 Endpoint 9 Interrupt (cleared upon USB reset) 17 1 read-only INT_SOF Start Of Frame Interrupt 3 1 read-only MICRO_SOF Micro Start Of Frame Interrupt 2 1 read-only SPEED Speed Status 0 1 read-only UPSTR_RES Upstream Resume Interrupt 7 1 read-only WAKE_UP Wake Up CPU Interrupt 5 1 read-only TST UDPHS Test Register 0xE0 32 read-write n 0x0 0x0 OPMODE2 OpMode2 5 1 read-write SPEED_CFG Speed Configuration 0 2 read-write NORMAL Normal mode: The macro is in Full Speed mode, ready to make a High Speed identification, if the host supports it and then to automatically switch to High Speed mode. 0x0 HIGH_SPEED Force High Speed: Set this value to force the hardware to work in High Speed mode. Only for debug or test purpose. 0x2 FULL_SPEED Force Full Speed: Set this value to force the hardware to work only in Full Speed mode. In this configuration, the macro will not respond to a High Speed reset handshake. 0x3 TST_J Test J Mode 2 1 read-write TST_K Test K Mode 3 1 read-write TST_PKT Test Packet Mode 4 1 read-write USART0 Universal Synchronous Asynchronous Receiver Transmitter 0 USART 0x0 0x0 0x50 registers n USART0 6 BRGR Baud Rate Generator Register 0x20 32 read-write n 0x0 0x0 CD Clock Divider 0 16 read-write FP Fractional Part 16 3 read-write CR Control Register 0x0 32 write-only n 0x0 0x0 RETTO Start Timeout Immediately 15 1 write-only RSTIT Reset Iterations 13 1 write-only RSTNACK Reset Non Acknowledge 14 1 write-only RSTRX Reset Receiver 2 1 write-only RSTSTA Reset Status Bits 8 1 write-only RSTTX Reset Transmitter 3 1 write-only RTSDIS Request to Send Pin Control 19 1 write-only RTSEN Request to Send Pin Control 18 1 write-only RXDIS Receiver Disable 5 1 write-only RXEN Receiver Enable 4 1 write-only SENDA Send Address 12 1 write-only STPBRK Stop Break 10 1 write-only STTBRK Start Break 9 1 write-only STTTO Clear TIMEOUT Flag and Start Timeout After Next Character Received 11 1 write-only TXDIS Transmitter Disable 7 1 write-only TXEN Transmitter Enable 6 1 write-only CR_SPI_MODE Control Register SPI_MODE 0x0 32 write-only n 0x0 0x0 FCS Force SPI Chip Select 18 1 write-only RCS Release SPI Chip Select 19 1 write-only RSTRX Reset Receiver 2 1 write-only RSTSTA Reset Status Bits 8 1 write-only RSTTX Reset Transmitter 3 1 write-only RXDIS Receiver Disable 5 1 write-only RXEN Receiver Enable 4 1 write-only TXDIS Transmitter Disable 7 1 write-only TXEN Transmitter Enable 6 1 write-only CSR Channel Status Register 0x14 32 read-only n 0x0 0x0 CTS Image of CTS Input 23 1 read-only CTSIC Clear to Send Input Change Flag (cleared on read) 19 1 read-only FRAME Framing Error (cleared by writing a one to bit US_CR.RSTSTA) 6 1 read-only ITER Max Number of Repetitions Reached (cleared by writing a one to bit US_CR.RSTIT) 10 1 read-only MANERR Manchester Error (cleared by writing a one to the bit US_CR.RSTSTA) 24 1 read-only NACK Non Acknowledge Interrupt (cleared by writing a one to bit US_CR.RSTNACK) 13 1 read-only OVRE Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) 5 1 read-only PARE Parity Error (cleared by writing a one to bit US_CR.RSTSTA) 7 1 read-only RXBRK Break Received/End of Break (cleared by writing a one to bit US_CR.RSTSTA) 2 1 read-only RXRDY Receiver Ready (cleared by reading US_RHR) 0 1 read-only TIMEOUT Receiver Timeout (cleared by writing a one to bit US_CR.STTTO) 8 1 read-only TXEMPTY Transmitter Empty (cleared by writing US_THR) 9 1 read-only TXRDY Transmitter Ready (cleared by writing US_THR) 1 1 read-only CSR_SPI_MODE Channel Status Register SPI_MODE 0x14 32 read-only n 0x0 0x0 NSS NSS Line (Driving CTS Pin) Rising or Falling Edge Event (cleared on read) 23 1 read-only NSSE NSS Line (Driving CTS Pin) Rising or Falling Edge Event (cleared on read) 19 1 read-only OVRE Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) 5 1 read-only RXRDY Receiver Ready (cleared by reading US_RHR) 0 1 read-only TXEMPTY Transmitter Empty (cleared by writing US_THR) 9 1 read-only TXRDY Transmitter Ready (cleared by writing US_THR) 1 1 read-only UNRE Underrun Error (cleared by writing a one to bit US_CR.RSTSTA) 10 1 read-only FIDI FI DI Ratio Register 0x40 32 read-write n 0x0 0x0 FI_DI_RATIO FI Over DI Ratio Value 0 11 read-write IDR Interrupt Disable Register 0xC 32 write-only n 0x0 0x0 CTSIC Clear to Send Input Change Interrupt Disable 19 1 write-only FRAME Framing Error Interrupt Disable 6 1 write-only ITER Max Number of Repetitions Reached Interrupt Disable 10 1 write-only MANE Manchester Error Interrupt Disable 24 1 write-only NACK Non Acknowledge Interrupt Disable 13 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only PARE Parity Error Interrupt Disable 7 1 write-only RXBRK Receiver Break Interrupt Disable 2 1 write-only RXRDY RXRDY Interrupt Disable 0 1 write-only TIMEOUT Timeout Interrupt Disable 8 1 write-only TXEMPTY TXEMPTY Interrupt Disable 9 1 write-only TXRDY TXRDY Interrupt Disable 1 1 write-only IDR_SPI_MODE Interrupt Disable Register SPI_MODE 0xC 32 write-only n 0x0 0x0 NSSE NSS Line (Driving CTS Pin) Rising or Falling Edge Event Interrupt Disable 19 1 write-only OVRE Overrun Error Interrupt Disable 5 1 write-only RXRDY RXRDY Interrupt Disable 0 1 write-only TXEMPTY TXEMPTY Interrupt Disable 9 1 write-only TXRDY TXRDY Interrupt Disable 1 1 write-only UNRE SPI Underrun Error Interrupt Disable 10 1 write-only IER Interrupt Enable Register 0x8 32 write-only n 0x0 0x0 CTSIC Clear to Send Input Change Interrupt Enable 19 1 write-only FRAME Framing Error Interrupt Enable 6 1 write-only ITER Max number of Repetitions Reached Interrupt Enable 10 1 write-only MANE Manchester Error Interrupt Enable 24 1 write-only NACK Non Acknowledge Interrupt Enable 13 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only PARE Parity Error Interrupt Enable 7 1 write-only RXBRK Receiver Break Interrupt Enable 2 1 write-only RXRDY RXRDY Interrupt Enable 0 1 write-only TIMEOUT Timeout Interrupt Enable 8 1 write-only TXEMPTY TXEMPTY Interrupt Enable 9 1 write-only TXRDY TXRDY Interrupt Enable 1 1 write-only IER_SPI_MODE Interrupt Enable Register SPI_MODE 0x8 32 write-only n 0x0 0x0 NSSE NSS Line (Driving CTS Pin) Rising or Falling Edge Event Interrupt Enable 19 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only RXRDY RXRDY Interrupt Enable 0 1 write-only TXEMPTY TXEMPTY Interrupt Enable 9 1 write-only TXRDY TXRDY Interrupt Enable 1 1 write-only UNRE SPI Underrun Error Interrupt Enable 10 1 write-only IF IrDA Filter Register 0x4C 32 read-write n 0x0 0x0 IRDA_FILTER IrDA Filter 0 8 read-write IMR Interrupt Mask Register 0x10 32 read-only n 0x0 0x0 CTSIC Clear to Send Input Change Interrupt Mask 19 1 read-only FRAME Framing Error Interrupt Mask 6 1 read-only ITER Max Number of Repetitions Reached Interrupt Mask 10 1 read-only MANE Manchester Error Interrupt Mask 24 1 read-only NACK Non Acknowledge Interrupt Mask 13 1 read-only OVRE Overrun Error Interrupt Mask 5 1 read-only PARE Parity Error Interrupt Mask 7 1 read-only RXBRK Receiver Break Interrupt Mask 2 1 read-only RXRDY RXRDY Interrupt Mask 0 1 read-only TIMEOUT Timeout Interrupt Mask 8 1 read-only TXEMPTY TXEMPTY Interrupt Mask 9 1 read-only TXRDY TXRDY Interrupt Mask 1 1 read-only IMR_SPI_MODE Interrupt Mask Register SPI_MODE 0x10 32 read-only n 0x0 0x0 NSSE NSS Line (Driving CTS Pin) Rising or Falling Edge Event Interrupt Mask 19 1 read-only OVRE Overrun Error Interrupt Mask 5 1 read-only RXRDY RXRDY Interrupt Mask 0 1 read-only TXEMPTY TXEMPTY Interrupt Mask 9 1 read-only TXRDY TXRDY Interrupt Mask 1 1 read-only UNRE SPI Underrun Error Interrupt Mask 10 1 read-only MAN Manchester Configuration Register 0x50 32 read-write n 0x0 0x0 DRIFT Drift Compensation 30 1 read-write ONE Must Be Set to 1 29 1 read-write RX_MPOL Receiver Manchester Polarity 28 1 read-write RX_PL Receiver Preamble Length 16 4 read-write RX_PP Receiver Preamble Pattern detected 24 2 read-write ALL_ONE The preamble is composed of '1's 0x0 ALL_ZERO The preamble is composed of '0's 0x1 ZERO_ONE The preamble is composed of '01's 0x2 ONE_ZERO The preamble is composed of '10's 0x3 TX_MPOL Transmitter Manchester Polarity 12 1 read-write TX_PL Transmitter Preamble Length 0 4 read-write TX_PP Transmitter Preamble Pattern 8 2 read-write ALL_ONE The preamble is composed of '1's 0x0 ALL_ZERO The preamble is composed of '0's 0x1 ZERO_ONE The preamble is composed of '01's 0x2 ONE_ZERO The preamble is composed of '10's 0x3 MR Mode Register 0x4 32 read-write n 0x0 0x0 CHMODE Channel Mode 14 2 read-write NORMAL Normal mode 0x0 AUTOMATIC Automatic Echo. Receiver input is connected to the TXD pin. 0x1 LOCAL_LOOPBACK Local Loopback. Transmitter output is connected to the Receiver Input. 0x2 REMOTE_LOOPBACK Remote Loopback. RXD pin is internally connected to the TXD pin. 0x3 CHRL Character Length 6 2 read-write 5_BIT Character length is 5 bits 0x0 6_BIT Character length is 6 bits 0x1 7_BIT Character length is 7 bits 0x2 8_BIT Character length is 8 bits 0x3 CLKO Clock Output Select 18 1 read-write DSNACK Disable Successive NACK 21 1 read-write FILTER Receive Line Filter 28 1 read-write INACK Inhibit Non Acknowledge 20 1 read-write INVDATA Inverted Data 23 1 read-write MAN Manchester Encoder/Decoder Enable 29 1 read-write MAX_ITERATION Maximum Number of Automatic Iteration 24 3 read-write MODE9 9-bit Character Length 17 1 read-write MODSYNC Manchester Synchronization Mode 30 1 read-write MSBF Bit Order 16 1 read-write NBSTOP Number of Stop Bits 12 2 read-write 1_BIT 1 stop bit 0x0 1_5_BIT 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) 0x1 2_BIT 2 stop bits 0x2 ONEBIT Start Frame Delimiter Selector 31 1 read-write OVER Oversampling Mode 19 1 read-write PAR Parity Type 9 3 read-write EVEN Even parity 0x0 ODD Odd parity 0x1 SPACE Parity forced to 0 (Space) 0x2 MARK Parity forced to 1 (Mark) 0x3 NO No parity 0x4 MULTIDROP Multidrop mode 0x6 SYNC Synchronous Mode Select 8 1 read-write USART_MODE USART Mode of Operation 0 4 read-write NORMAL Normal mode 0x0 RS485 RS485 0x1 HW_HANDSHAKING Hardware Handshaking 0x2 IS07816_T_0 IS07816 Protocol: T = 0 0x4 IS07816_T_1 IS07816 Protocol: T = 1 0x6 IRDA IrDA 0x8 SPI_MASTER SPI Master mode (CLKO must be written to 1 and USCLKS = 0, 1 or 2) 0xE SPI_SLAVE SPI Slave mode 0xF USCLKS Clock Selection 4 2 read-write MCK Peripheral clock is selected 0x0 DIV Peripheral clock divided (DIV=8) is selected 0x1 SCK Serial clock (SCK) is selected 0x3 VAR_SYNC Variable Synchronization of Command/Data Sync Start Frame Delimiter 22 1 read-write MR_SPI_MODE Mode Register SPI_MODE 0x4 32 read-write n 0x0 0x0 CHRL Character Length 6 2 read-write 8_BIT Character length is 8 bits 0x3 CLKO Clock Output Select 18 1 read-write CPHA SPI Clock Phase 8 1 read-write CPOL SPI Clock Polarity 16 1 read-write USART_MODE USART Mode of Operation 0 4 read-write SPI_MASTER SPI master 0xE SPI_SLAVE SPI Slave 0xF USCLKS Clock Selection 4 2 read-write MCK Peripheral clock is selected 0x0 DIV Peripheral clock divided (DIV=8) is selected 0x1 SCK Serial Clock (SCK) is selected 0x3 WRDBT Wait Read Data Before Transfer 20 1 read-write NER Number of Errors Register 0x44 32 read-only n 0x0 0x0 NB_ERRORS Number of Errors 0 8 read-only RHR Receive Holding Register 0x18 32 read-only n 0x0 0x0 RXCHR Received Character 0 9 read-only RXSYNH Received Sync 15 1 read-only RTOR Receiver Timeout Register 0x24 32 read-write n 0x0 0x0 TO Timeout Value 0 16 read-write THR Transmit Holding Register 0x1C 32 write-only n 0x0 0x0 TXCHR Character to be Transmitted 0 9 write-only TXSYNH Sync Field to be Transmitted 15 1 write-only TTGR Transmitter Timeguard Register 0x28 32 read-write n 0x0 0x0 TG Timeguard Value 0 8 read-write WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 read-write WPKEY Write Protection Key 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. 0x555341 WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 read-only WPVSRC Write Protection Violation Source 8 16 read-only USART1 Universal Synchronous Asynchronous Receiver Transmitter 1 USART 0x0 0x0 0x50 registers n USART1 7 BRGR Baud Rate Generator Register 0x20 32 read-write n 0x0 0x0 CD Clock Divider 0 16 read-write FP Fractional Part 16 3 read-write CR Control Register 0x0 32 write-only n 0x0 0x0 RETTO Start Timeout Immediately 15 1 write-only RSTIT Reset Iterations 13 1 write-only RSTNACK Reset Non Acknowledge 14 1 write-only RSTRX Reset Receiver 2 1 write-only RSTSTA Reset Status Bits 8 1 write-only RSTTX Reset Transmitter 3 1 write-only RTSDIS Request to Send Pin Control 19 1 write-only RTSEN Request to Send Pin Control 18 1 write-only RXDIS Receiver Disable 5 1 write-only RXEN Receiver Enable 4 1 write-only SENDA Send Address 12 1 write-only STPBRK Stop Break 10 1 write-only STTBRK Start Break 9 1 write-only STTTO Clear TIMEOUT Flag and Start Timeout After Next Character Received 11 1 write-only TXDIS Transmitter Disable 7 1 write-only TXEN Transmitter Enable 6 1 write-only CR_SPI_MODE Control Register SPI_MODE 0x0 32 write-only n 0x0 0x0 FCS Force SPI Chip Select 18 1 write-only RCS Release SPI Chip Select 19 1 write-only RSTRX Reset Receiver 2 1 write-only RSTSTA Reset Status Bits 8 1 write-only RSTTX Reset Transmitter 3 1 write-only RXDIS Receiver Disable 5 1 write-only RXEN Receiver Enable 4 1 write-only TXDIS Transmitter Disable 7 1 write-only TXEN Transmitter Enable 6 1 write-only CSR Channel Status Register 0x14 32 read-only n 0x0 0x0 CTS Image of CTS Input 23 1 read-only CTSIC Clear to Send Input Change Flag (cleared on read) 19 1 read-only FRAME Framing Error (cleared by writing a one to bit US_CR.RSTSTA) 6 1 read-only ITER Max Number of Repetitions Reached (cleared by writing a one to bit US_CR.RSTIT) 10 1 read-only MANERR Manchester Error (cleared by writing a one to the bit US_CR.RSTSTA) 24 1 read-only NACK Non Acknowledge Interrupt (cleared by writing a one to bit US_CR.RSTNACK) 13 1 read-only OVRE Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) 5 1 read-only PARE Parity Error (cleared by writing a one to bit US_CR.RSTSTA) 7 1 read-only RXBRK Break Received/End of Break (cleared by writing a one to bit US_CR.RSTSTA) 2 1 read-only RXRDY Receiver Ready (cleared by reading US_RHR) 0 1 read-only TIMEOUT Receiver Timeout (cleared by writing a one to bit US_CR.STTTO) 8 1 read-only TXEMPTY Transmitter Empty (cleared by writing US_THR) 9 1 read-only TXRDY Transmitter Ready (cleared by writing US_THR) 1 1 read-only CSR_SPI_MODE Channel Status Register SPI_MODE 0x14 32 read-only n 0x0 0x0 NSS NSS Line (Driving CTS Pin) Rising or Falling Edge Event (cleared on read) 23 1 read-only NSSE NSS Line (Driving CTS Pin) Rising or Falling Edge Event (cleared on read) 19 1 read-only OVRE Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) 5 1 read-only RXRDY Receiver Ready (cleared by reading US_RHR) 0 1 read-only TXEMPTY Transmitter Empty (cleared by writing US_THR) 9 1 read-only TXRDY Transmitter Ready (cleared by writing US_THR) 1 1 read-only UNRE Underrun Error (cleared by writing a one to bit US_CR.RSTSTA) 10 1 read-only FIDI FI DI Ratio Register 0x40 32 read-write n 0x0 0x0 FI_DI_RATIO FI Over DI Ratio Value 0 11 read-write IDR Interrupt Disable Register 0xC 32 write-only n 0x0 0x0 CTSIC Clear to Send Input Change Interrupt Disable 19 1 write-only FRAME Framing Error Interrupt Disable 6 1 write-only ITER Max Number of Repetitions Reached Interrupt Disable 10 1 write-only MANE Manchester Error Interrupt Disable 24 1 write-only NACK Non Acknowledge Interrupt Disable 13 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only PARE Parity Error Interrupt Disable 7 1 write-only RXBRK Receiver Break Interrupt Disable 2 1 write-only RXRDY RXRDY Interrupt Disable 0 1 write-only TIMEOUT Timeout Interrupt Disable 8 1 write-only TXEMPTY TXEMPTY Interrupt Disable 9 1 write-only TXRDY TXRDY Interrupt Disable 1 1 write-only IDR_SPI_MODE Interrupt Disable Register SPI_MODE 0xC 32 write-only n 0x0 0x0 NSSE NSS Line (Driving CTS Pin) Rising or Falling Edge Event Interrupt Disable 19 1 write-only OVRE Overrun Error Interrupt Disable 5 1 write-only RXRDY RXRDY Interrupt Disable 0 1 write-only TXEMPTY TXEMPTY Interrupt Disable 9 1 write-only TXRDY TXRDY Interrupt Disable 1 1 write-only UNRE SPI Underrun Error Interrupt Disable 10 1 write-only IER Interrupt Enable Register 0x8 32 write-only n 0x0 0x0 CTSIC Clear to Send Input Change Interrupt Enable 19 1 write-only FRAME Framing Error Interrupt Enable 6 1 write-only ITER Max number of Repetitions Reached Interrupt Enable 10 1 write-only MANE Manchester Error Interrupt Enable 24 1 write-only NACK Non Acknowledge Interrupt Enable 13 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only PARE Parity Error Interrupt Enable 7 1 write-only RXBRK Receiver Break Interrupt Enable 2 1 write-only RXRDY RXRDY Interrupt Enable 0 1 write-only TIMEOUT Timeout Interrupt Enable 8 1 write-only TXEMPTY TXEMPTY Interrupt Enable 9 1 write-only TXRDY TXRDY Interrupt Enable 1 1 write-only IER_SPI_MODE Interrupt Enable Register SPI_MODE 0x8 32 write-only n 0x0 0x0 NSSE NSS Line (Driving CTS Pin) Rising or Falling Edge Event Interrupt Enable 19 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only RXRDY RXRDY Interrupt Enable 0 1 write-only TXEMPTY TXEMPTY Interrupt Enable 9 1 write-only TXRDY TXRDY Interrupt Enable 1 1 write-only UNRE SPI Underrun Error Interrupt Enable 10 1 write-only IF IrDA Filter Register 0x4C 32 read-write n 0x0 0x0 IRDA_FILTER IrDA Filter 0 8 read-write IMR Interrupt Mask Register 0x10 32 read-only n 0x0 0x0 CTSIC Clear to Send Input Change Interrupt Mask 19 1 read-only FRAME Framing Error Interrupt Mask 6 1 read-only ITER Max Number of Repetitions Reached Interrupt Mask 10 1 read-only MANE Manchester Error Interrupt Mask 24 1 read-only NACK Non Acknowledge Interrupt Mask 13 1 read-only OVRE Overrun Error Interrupt Mask 5 1 read-only PARE Parity Error Interrupt Mask 7 1 read-only RXBRK Receiver Break Interrupt Mask 2 1 read-only RXRDY RXRDY Interrupt Mask 0 1 read-only TIMEOUT Timeout Interrupt Mask 8 1 read-only TXEMPTY TXEMPTY Interrupt Mask 9 1 read-only TXRDY TXRDY Interrupt Mask 1 1 read-only IMR_SPI_MODE Interrupt Mask Register SPI_MODE 0x10 32 read-only n 0x0 0x0 NSSE NSS Line (Driving CTS Pin) Rising or Falling Edge Event Interrupt Mask 19 1 read-only OVRE Overrun Error Interrupt Mask 5 1 read-only RXRDY RXRDY Interrupt Mask 0 1 read-only TXEMPTY TXEMPTY Interrupt Mask 9 1 read-only TXRDY TXRDY Interrupt Mask 1 1 read-only UNRE SPI Underrun Error Interrupt Mask 10 1 read-only MAN Manchester Configuration Register 0x50 32 read-write n 0x0 0x0 DRIFT Drift Compensation 30 1 read-write ONE Must Be Set to 1 29 1 read-write RX_MPOL Receiver Manchester Polarity 28 1 read-write RX_PL Receiver Preamble Length 16 4 read-write RX_PP Receiver Preamble Pattern detected 24 2 read-write ALL_ONE The preamble is composed of '1's 0x0 ALL_ZERO The preamble is composed of '0's 0x1 ZERO_ONE The preamble is composed of '01's 0x2 ONE_ZERO The preamble is composed of '10's 0x3 TX_MPOL Transmitter Manchester Polarity 12 1 read-write TX_PL Transmitter Preamble Length 0 4 read-write TX_PP Transmitter Preamble Pattern 8 2 read-write ALL_ONE The preamble is composed of '1's 0x0 ALL_ZERO The preamble is composed of '0's 0x1 ZERO_ONE The preamble is composed of '01's 0x2 ONE_ZERO The preamble is composed of '10's 0x3 MR Mode Register 0x4 32 read-write n 0x0 0x0 CHMODE Channel Mode 14 2 read-write NORMAL Normal mode 0x0 AUTOMATIC Automatic Echo. Receiver input is connected to the TXD pin. 0x1 LOCAL_LOOPBACK Local Loopback. Transmitter output is connected to the Receiver Input. 0x2 REMOTE_LOOPBACK Remote Loopback. RXD pin is internally connected to the TXD pin. 0x3 CHRL Character Length 6 2 read-write 5_BIT Character length is 5 bits 0x0 6_BIT Character length is 6 bits 0x1 7_BIT Character length is 7 bits 0x2 8_BIT Character length is 8 bits 0x3 CLKO Clock Output Select 18 1 read-write DSNACK Disable Successive NACK 21 1 read-write FILTER Receive Line Filter 28 1 read-write INACK Inhibit Non Acknowledge 20 1 read-write INVDATA Inverted Data 23 1 read-write MAN Manchester Encoder/Decoder Enable 29 1 read-write MAX_ITERATION Maximum Number of Automatic Iteration 24 3 read-write MODE9 9-bit Character Length 17 1 read-write MODSYNC Manchester Synchronization Mode 30 1 read-write MSBF Bit Order 16 1 read-write NBSTOP Number of Stop Bits 12 2 read-write 1_BIT 1 stop bit 0x0 1_5_BIT 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) 0x1 2_BIT 2 stop bits 0x2 ONEBIT Start Frame Delimiter Selector 31 1 read-write OVER Oversampling Mode 19 1 read-write PAR Parity Type 9 3 read-write EVEN Even parity 0x0 ODD Odd parity 0x1 SPACE Parity forced to 0 (Space) 0x2 MARK Parity forced to 1 (Mark) 0x3 NO No parity 0x4 MULTIDROP Multidrop mode 0x6 SYNC Synchronous Mode Select 8 1 read-write USART_MODE USART Mode of Operation 0 4 read-write NORMAL Normal mode 0x0 RS485 RS485 0x1 HW_HANDSHAKING Hardware Handshaking 0x2 IS07816_T_0 IS07816 Protocol: T = 0 0x4 IS07816_T_1 IS07816 Protocol: T = 1 0x6 IRDA IrDA 0x8 SPI_MASTER SPI Master mode (CLKO must be written to 1 and USCLKS = 0, 1 or 2) 0xE SPI_SLAVE SPI Slave mode 0xF USCLKS Clock Selection 4 2 read-write MCK Peripheral clock is selected 0x0 DIV Peripheral clock divided (DIV=8) is selected 0x1 SCK Serial clock (SCK) is selected 0x3 VAR_SYNC Variable Synchronization of Command/Data Sync Start Frame Delimiter 22 1 read-write MR_SPI_MODE Mode Register SPI_MODE 0x4 32 read-write n 0x0 0x0 CHRL Character Length 6 2 read-write 8_BIT Character length is 8 bits 0x3 CLKO Clock Output Select 18 1 read-write CPHA SPI Clock Phase 8 1 read-write CPOL SPI Clock Polarity 16 1 read-write USART_MODE USART Mode of Operation 0 4 read-write SPI_MASTER SPI master 0xE SPI_SLAVE SPI Slave 0xF USCLKS Clock Selection 4 2 read-write MCK Peripheral clock is selected 0x0 DIV Peripheral clock divided (DIV=8) is selected 0x1 SCK Serial Clock (SCK) is selected 0x3 WRDBT Wait Read Data Before Transfer 20 1 read-write NER Number of Errors Register 0x44 32 read-only n 0x0 0x0 NB_ERRORS Number of Errors 0 8 read-only RHR Receive Holding Register 0x18 32 read-only n 0x0 0x0 RXCHR Received Character 0 9 read-only RXSYNH Received Sync 15 1 read-only RTOR Receiver Timeout Register 0x24 32 read-write n 0x0 0x0 TO Timeout Value 0 16 read-write THR Transmit Holding Register 0x1C 32 write-only n 0x0 0x0 TXCHR Character to be Transmitted 0 9 write-only TXSYNH Sync Field to be Transmitted 15 1 write-only TTGR Transmitter Timeguard Register 0x28 32 read-write n 0x0 0x0 TG Timeguard Value 0 8 read-write WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 read-write WPKEY Write Protection Key 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. 0x555341 WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 read-only WPVSRC Write Protection Violation Source 8 16 read-only USART2 Universal Synchronous Asynchronous Receiver Transmitter 2 USART 0x0 0x0 0x50 registers n USART2 29 BRGR Baud Rate Generator Register 0x20 32 read-write n 0x0 0x0 CD Clock Divider 0 16 read-write FP Fractional Part 16 3 read-write CR Control Register 0x0 32 write-only n 0x0 0x0 RETTO Start Timeout Immediately 15 1 write-only RSTIT Reset Iterations 13 1 write-only RSTNACK Reset Non Acknowledge 14 1 write-only RSTRX Reset Receiver 2 1 write-only RSTSTA Reset Status Bits 8 1 write-only RSTTX Reset Transmitter 3 1 write-only RTSDIS Request to Send Pin Control 19 1 write-only RTSEN Request to Send Pin Control 18 1 write-only RXDIS Receiver Disable 5 1 write-only RXEN Receiver Enable 4 1 write-only SENDA Send Address 12 1 write-only STPBRK Stop Break 10 1 write-only STTBRK Start Break 9 1 write-only STTTO Clear TIMEOUT Flag and Start Timeout After Next Character Received 11 1 write-only TXDIS Transmitter Disable 7 1 write-only TXEN Transmitter Enable 6 1 write-only CR_SPI_MODE Control Register SPI_MODE 0x0 32 write-only n 0x0 0x0 FCS Force SPI Chip Select 18 1 write-only RCS Release SPI Chip Select 19 1 write-only RSTRX Reset Receiver 2 1 write-only RSTSTA Reset Status Bits 8 1 write-only RSTTX Reset Transmitter 3 1 write-only RXDIS Receiver Disable 5 1 write-only RXEN Receiver Enable 4 1 write-only TXDIS Transmitter Disable 7 1 write-only TXEN Transmitter Enable 6 1 write-only CSR Channel Status Register 0x14 32 read-only n 0x0 0x0 CTS Image of CTS Input 23 1 read-only CTSIC Clear to Send Input Change Flag (cleared on read) 19 1 read-only FRAME Framing Error (cleared by writing a one to bit US_CR.RSTSTA) 6 1 read-only ITER Max Number of Repetitions Reached (cleared by writing a one to bit US_CR.RSTIT) 10 1 read-only MANERR Manchester Error (cleared by writing a one to the bit US_CR.RSTSTA) 24 1 read-only NACK Non Acknowledge Interrupt (cleared by writing a one to bit US_CR.RSTNACK) 13 1 read-only OVRE Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) 5 1 read-only PARE Parity Error (cleared by writing a one to bit US_CR.RSTSTA) 7 1 read-only RXBRK Break Received/End of Break (cleared by writing a one to bit US_CR.RSTSTA) 2 1 read-only RXRDY Receiver Ready (cleared by reading US_RHR) 0 1 read-only TIMEOUT Receiver Timeout (cleared by writing a one to bit US_CR.STTTO) 8 1 read-only TXEMPTY Transmitter Empty (cleared by writing US_THR) 9 1 read-only TXRDY Transmitter Ready (cleared by writing US_THR) 1 1 read-only CSR_SPI_MODE Channel Status Register SPI_MODE 0x14 32 read-only n 0x0 0x0 NSS NSS Line (Driving CTS Pin) Rising or Falling Edge Event (cleared on read) 23 1 read-only NSSE NSS Line (Driving CTS Pin) Rising or Falling Edge Event (cleared on read) 19 1 read-only OVRE Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) 5 1 read-only RXRDY Receiver Ready (cleared by reading US_RHR) 0 1 read-only TXEMPTY Transmitter Empty (cleared by writing US_THR) 9 1 read-only TXRDY Transmitter Ready (cleared by writing US_THR) 1 1 read-only UNRE Underrun Error (cleared by writing a one to bit US_CR.RSTSTA) 10 1 read-only FIDI FI DI Ratio Register 0x40 32 read-write n 0x0 0x0 FI_DI_RATIO FI Over DI Ratio Value 0 11 read-write IDR Interrupt Disable Register 0xC 32 write-only n 0x0 0x0 CTSIC Clear to Send Input Change Interrupt Disable 19 1 write-only FRAME Framing Error Interrupt Disable 6 1 write-only ITER Max Number of Repetitions Reached Interrupt Disable 10 1 write-only MANE Manchester Error Interrupt Disable 24 1 write-only NACK Non Acknowledge Interrupt Disable 13 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only PARE Parity Error Interrupt Disable 7 1 write-only RXBRK Receiver Break Interrupt Disable 2 1 write-only RXRDY RXRDY Interrupt Disable 0 1 write-only TIMEOUT Timeout Interrupt Disable 8 1 write-only TXEMPTY TXEMPTY Interrupt Disable 9 1 write-only TXRDY TXRDY Interrupt Disable 1 1 write-only IDR_SPI_MODE Interrupt Disable Register SPI_MODE 0xC 32 write-only n 0x0 0x0 NSSE NSS Line (Driving CTS Pin) Rising or Falling Edge Event Interrupt Disable 19 1 write-only OVRE Overrun Error Interrupt Disable 5 1 write-only RXRDY RXRDY Interrupt Disable 0 1 write-only TXEMPTY TXEMPTY Interrupt Disable 9 1 write-only TXRDY TXRDY Interrupt Disable 1 1 write-only UNRE SPI Underrun Error Interrupt Disable 10 1 write-only IER Interrupt Enable Register 0x8 32 write-only n 0x0 0x0 CTSIC Clear to Send Input Change Interrupt Enable 19 1 write-only FRAME Framing Error Interrupt Enable 6 1 write-only ITER Max number of Repetitions Reached Interrupt Enable 10 1 write-only MANE Manchester Error Interrupt Enable 24 1 write-only NACK Non Acknowledge Interrupt Enable 13 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only PARE Parity Error Interrupt Enable 7 1 write-only RXBRK Receiver Break Interrupt Enable 2 1 write-only RXRDY RXRDY Interrupt Enable 0 1 write-only TIMEOUT Timeout Interrupt Enable 8 1 write-only TXEMPTY TXEMPTY Interrupt Enable 9 1 write-only TXRDY TXRDY Interrupt Enable 1 1 write-only IER_SPI_MODE Interrupt Enable Register SPI_MODE 0x8 32 write-only n 0x0 0x0 NSSE NSS Line (Driving CTS Pin) Rising or Falling Edge Event Interrupt Enable 19 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only RXRDY RXRDY Interrupt Enable 0 1 write-only TXEMPTY TXEMPTY Interrupt Enable 9 1 write-only TXRDY TXRDY Interrupt Enable 1 1 write-only UNRE SPI Underrun Error Interrupt Enable 10 1 write-only IF IrDA Filter Register 0x4C 32 read-write n 0x0 0x0 IRDA_FILTER IrDA Filter 0 8 read-write IMR Interrupt Mask Register 0x10 32 read-only n 0x0 0x0 CTSIC Clear to Send Input Change Interrupt Mask 19 1 read-only FRAME Framing Error Interrupt Mask 6 1 read-only ITER Max Number of Repetitions Reached Interrupt Mask 10 1 read-only MANE Manchester Error Interrupt Mask 24 1 read-only NACK Non Acknowledge Interrupt Mask 13 1 read-only OVRE Overrun Error Interrupt Mask 5 1 read-only PARE Parity Error Interrupt Mask 7 1 read-only RXBRK Receiver Break Interrupt Mask 2 1 read-only RXRDY RXRDY Interrupt Mask 0 1 read-only TIMEOUT Timeout Interrupt Mask 8 1 read-only TXEMPTY TXEMPTY Interrupt Mask 9 1 read-only TXRDY TXRDY Interrupt Mask 1 1 read-only IMR_SPI_MODE Interrupt Mask Register SPI_MODE 0x10 32 read-only n 0x0 0x0 NSSE NSS Line (Driving CTS Pin) Rising or Falling Edge Event Interrupt Mask 19 1 read-only OVRE Overrun Error Interrupt Mask 5 1 read-only RXRDY RXRDY Interrupt Mask 0 1 read-only TXEMPTY TXEMPTY Interrupt Mask 9 1 read-only TXRDY TXRDY Interrupt Mask 1 1 read-only UNRE SPI Underrun Error Interrupt Mask 10 1 read-only MAN Manchester Configuration Register 0x50 32 read-write n 0x0 0x0 DRIFT Drift Compensation 30 1 read-write ONE Must Be Set to 1 29 1 read-write RX_MPOL Receiver Manchester Polarity 28 1 read-write RX_PL Receiver Preamble Length 16 4 read-write RX_PP Receiver Preamble Pattern detected 24 2 read-write ALL_ONE The preamble is composed of '1's 0x0 ALL_ZERO The preamble is composed of '0's 0x1 ZERO_ONE The preamble is composed of '01's 0x2 ONE_ZERO The preamble is composed of '10's 0x3 TX_MPOL Transmitter Manchester Polarity 12 1 read-write TX_PL Transmitter Preamble Length 0 4 read-write TX_PP Transmitter Preamble Pattern 8 2 read-write ALL_ONE The preamble is composed of '1's 0x0 ALL_ZERO The preamble is composed of '0's 0x1 ZERO_ONE The preamble is composed of '01's 0x2 ONE_ZERO The preamble is composed of '10's 0x3 MR Mode Register 0x4 32 read-write n 0x0 0x0 CHMODE Channel Mode 14 2 read-write NORMAL Normal mode 0x0 AUTOMATIC Automatic Echo. Receiver input is connected to the TXD pin. 0x1 LOCAL_LOOPBACK Local Loopback. Transmitter output is connected to the Receiver Input. 0x2 REMOTE_LOOPBACK Remote Loopback. RXD pin is internally connected to the TXD pin. 0x3 CHRL Character Length 6 2 read-write 5_BIT Character length is 5 bits 0x0 6_BIT Character length is 6 bits 0x1 7_BIT Character length is 7 bits 0x2 8_BIT Character length is 8 bits 0x3 CLKO Clock Output Select 18 1 read-write DSNACK Disable Successive NACK 21 1 read-write FILTER Receive Line Filter 28 1 read-write INACK Inhibit Non Acknowledge 20 1 read-write INVDATA Inverted Data 23 1 read-write MAN Manchester Encoder/Decoder Enable 29 1 read-write MAX_ITERATION Maximum Number of Automatic Iteration 24 3 read-write MODE9 9-bit Character Length 17 1 read-write MODSYNC Manchester Synchronization Mode 30 1 read-write MSBF Bit Order 16 1 read-write NBSTOP Number of Stop Bits 12 2 read-write 1_BIT 1 stop bit 0x0 1_5_BIT 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) 0x1 2_BIT 2 stop bits 0x2 ONEBIT Start Frame Delimiter Selector 31 1 read-write OVER Oversampling Mode 19 1 read-write PAR Parity Type 9 3 read-write EVEN Even parity 0x0 ODD Odd parity 0x1 SPACE Parity forced to 0 (Space) 0x2 MARK Parity forced to 1 (Mark) 0x3 NO No parity 0x4 MULTIDROP Multidrop mode 0x6 SYNC Synchronous Mode Select 8 1 read-write USART_MODE USART Mode of Operation 0 4 read-write NORMAL Normal mode 0x0 RS485 RS485 0x1 HW_HANDSHAKING Hardware Handshaking 0x2 IS07816_T_0 IS07816 Protocol: T = 0 0x4 IS07816_T_1 IS07816 Protocol: T = 1 0x6 IRDA IrDA 0x8 SPI_MASTER SPI Master mode (CLKO must be written to 1 and USCLKS = 0, 1 or 2) 0xE SPI_SLAVE SPI Slave mode 0xF USCLKS Clock Selection 4 2 read-write MCK Peripheral clock is selected 0x0 DIV Peripheral clock divided (DIV=8) is selected 0x1 SCK Serial clock (SCK) is selected 0x3 VAR_SYNC Variable Synchronization of Command/Data Sync Start Frame Delimiter 22 1 read-write MR_SPI_MODE Mode Register SPI_MODE 0x4 32 read-write n 0x0 0x0 CHRL Character Length 6 2 read-write 8_BIT Character length is 8 bits 0x3 CLKO Clock Output Select 18 1 read-write CPHA SPI Clock Phase 8 1 read-write CPOL SPI Clock Polarity 16 1 read-write USART_MODE USART Mode of Operation 0 4 read-write SPI_MASTER SPI master 0xE SPI_SLAVE SPI Slave 0xF USCLKS Clock Selection 4 2 read-write MCK Peripheral clock is selected 0x0 DIV Peripheral clock divided (DIV=8) is selected 0x1 SCK Serial Clock (SCK) is selected 0x3 WRDBT Wait Read Data Before Transfer 20 1 read-write NER Number of Errors Register 0x44 32 read-only n 0x0 0x0 NB_ERRORS Number of Errors 0 8 read-only RHR Receive Holding Register 0x18 32 read-only n 0x0 0x0 RXCHR Received Character 0 9 read-only RXSYNH Received Sync 15 1 read-only RTOR Receiver Timeout Register 0x24 32 read-write n 0x0 0x0 TO Timeout Value 0 16 read-write THR Transmit Holding Register 0x1C 32 write-only n 0x0 0x0 TXCHR Character to be Transmitted 0 9 write-only TXSYNH Sync Field to be Transmitted 15 1 write-only TTGR Transmitter Timeguard Register 0x28 32 read-write n 0x0 0x0 TG Timeguard Value 0 8 read-write WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 read-write WPKEY Write Protection Key 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. 0x555341 WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 read-only WPVSRC Write Protection Violation Source 8 16 read-only USART3 Universal Synchronous Asynchronous Receiver Transmitter 3 USART 0x0 0x0 0x50 registers n USART3 30 BRGR Baud Rate Generator Register 0x20 32 read-write n 0x0 0x0 CD Clock Divider 0 16 read-write FP Fractional Part 16 3 read-write CR Control Register 0x0 32 write-only n 0x0 0x0 RETTO Start Timeout Immediately 15 1 write-only RSTIT Reset Iterations 13 1 write-only RSTNACK Reset Non Acknowledge 14 1 write-only RSTRX Reset Receiver 2 1 write-only RSTSTA Reset Status Bits 8 1 write-only RSTTX Reset Transmitter 3 1 write-only RTSDIS Request to Send Pin Control 19 1 write-only RTSEN Request to Send Pin Control 18 1 write-only RXDIS Receiver Disable 5 1 write-only RXEN Receiver Enable 4 1 write-only SENDA Send Address 12 1 write-only STPBRK Stop Break 10 1 write-only STTBRK Start Break 9 1 write-only STTTO Clear TIMEOUT Flag and Start Timeout After Next Character Received 11 1 write-only TXDIS Transmitter Disable 7 1 write-only TXEN Transmitter Enable 6 1 write-only CR_SPI_MODE Control Register SPI_MODE 0x0 32 write-only n 0x0 0x0 FCS Force SPI Chip Select 18 1 write-only RCS Release SPI Chip Select 19 1 write-only RSTRX Reset Receiver 2 1 write-only RSTSTA Reset Status Bits 8 1 write-only RSTTX Reset Transmitter 3 1 write-only RXDIS Receiver Disable 5 1 write-only RXEN Receiver Enable 4 1 write-only TXDIS Transmitter Disable 7 1 write-only TXEN Transmitter Enable 6 1 write-only CSR Channel Status Register 0x14 32 read-only n 0x0 0x0 CTS Image of CTS Input 23 1 read-only CTSIC Clear to Send Input Change Flag (cleared on read) 19 1 read-only FRAME Framing Error (cleared by writing a one to bit US_CR.RSTSTA) 6 1 read-only ITER Max Number of Repetitions Reached (cleared by writing a one to bit US_CR.RSTIT) 10 1 read-only MANERR Manchester Error (cleared by writing a one to the bit US_CR.RSTSTA) 24 1 read-only NACK Non Acknowledge Interrupt (cleared by writing a one to bit US_CR.RSTNACK) 13 1 read-only OVRE Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) 5 1 read-only PARE Parity Error (cleared by writing a one to bit US_CR.RSTSTA) 7 1 read-only RXBRK Break Received/End of Break (cleared by writing a one to bit US_CR.RSTSTA) 2 1 read-only RXRDY Receiver Ready (cleared by reading US_RHR) 0 1 read-only TIMEOUT Receiver Timeout (cleared by writing a one to bit US_CR.STTTO) 8 1 read-only TXEMPTY Transmitter Empty (cleared by writing US_THR) 9 1 read-only TXRDY Transmitter Ready (cleared by writing US_THR) 1 1 read-only CSR_SPI_MODE Channel Status Register SPI_MODE 0x14 32 read-only n 0x0 0x0 NSS NSS Line (Driving CTS Pin) Rising or Falling Edge Event (cleared on read) 23 1 read-only NSSE NSS Line (Driving CTS Pin) Rising or Falling Edge Event (cleared on read) 19 1 read-only OVRE Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) 5 1 read-only RXRDY Receiver Ready (cleared by reading US_RHR) 0 1 read-only TXEMPTY Transmitter Empty (cleared by writing US_THR) 9 1 read-only TXRDY Transmitter Ready (cleared by writing US_THR) 1 1 read-only UNRE Underrun Error (cleared by writing a one to bit US_CR.RSTSTA) 10 1 read-only FIDI FI DI Ratio Register 0x40 32 read-write n 0x0 0x0 FI_DI_RATIO FI Over DI Ratio Value 0 11 read-write IDR Interrupt Disable Register 0xC 32 write-only n 0x0 0x0 CTSIC Clear to Send Input Change Interrupt Disable 19 1 write-only FRAME Framing Error Interrupt Disable 6 1 write-only ITER Max Number of Repetitions Reached Interrupt Disable 10 1 write-only MANE Manchester Error Interrupt Disable 24 1 write-only NACK Non Acknowledge Interrupt Disable 13 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only PARE Parity Error Interrupt Disable 7 1 write-only RXBRK Receiver Break Interrupt Disable 2 1 write-only RXRDY RXRDY Interrupt Disable 0 1 write-only TIMEOUT Timeout Interrupt Disable 8 1 write-only TXEMPTY TXEMPTY Interrupt Disable 9 1 write-only TXRDY TXRDY Interrupt Disable 1 1 write-only IDR_SPI_MODE Interrupt Disable Register SPI_MODE 0xC 32 write-only n 0x0 0x0 NSSE NSS Line (Driving CTS Pin) Rising or Falling Edge Event Interrupt Disable 19 1 write-only OVRE Overrun Error Interrupt Disable 5 1 write-only RXRDY RXRDY Interrupt Disable 0 1 write-only TXEMPTY TXEMPTY Interrupt Disable 9 1 write-only TXRDY TXRDY Interrupt Disable 1 1 write-only UNRE SPI Underrun Error Interrupt Disable 10 1 write-only IER Interrupt Enable Register 0x8 32 write-only n 0x0 0x0 CTSIC Clear to Send Input Change Interrupt Enable 19 1 write-only FRAME Framing Error Interrupt Enable 6 1 write-only ITER Max number of Repetitions Reached Interrupt Enable 10 1 write-only MANE Manchester Error Interrupt Enable 24 1 write-only NACK Non Acknowledge Interrupt Enable 13 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only PARE Parity Error Interrupt Enable 7 1 write-only RXBRK Receiver Break Interrupt Enable 2 1 write-only RXRDY RXRDY Interrupt Enable 0 1 write-only TIMEOUT Timeout Interrupt Enable 8 1 write-only TXEMPTY TXEMPTY Interrupt Enable 9 1 write-only TXRDY TXRDY Interrupt Enable 1 1 write-only IER_SPI_MODE Interrupt Enable Register SPI_MODE 0x8 32 write-only n 0x0 0x0 NSSE NSS Line (Driving CTS Pin) Rising or Falling Edge Event Interrupt Enable 19 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only RXRDY RXRDY Interrupt Enable 0 1 write-only TXEMPTY TXEMPTY Interrupt Enable 9 1 write-only TXRDY TXRDY Interrupt Enable 1 1 write-only UNRE SPI Underrun Error Interrupt Enable 10 1 write-only IF IrDA Filter Register 0x4C 32 read-write n 0x0 0x0 IRDA_FILTER IrDA Filter 0 8 read-write IMR Interrupt Mask Register 0x10 32 read-only n 0x0 0x0 CTSIC Clear to Send Input Change Interrupt Mask 19 1 read-only FRAME Framing Error Interrupt Mask 6 1 read-only ITER Max Number of Repetitions Reached Interrupt Mask 10 1 read-only MANE Manchester Error Interrupt Mask 24 1 read-only NACK Non Acknowledge Interrupt Mask 13 1 read-only OVRE Overrun Error Interrupt Mask 5 1 read-only PARE Parity Error Interrupt Mask 7 1 read-only RXBRK Receiver Break Interrupt Mask 2 1 read-only RXRDY RXRDY Interrupt Mask 0 1 read-only TIMEOUT Timeout Interrupt Mask 8 1 read-only TXEMPTY TXEMPTY Interrupt Mask 9 1 read-only TXRDY TXRDY Interrupt Mask 1 1 read-only IMR_SPI_MODE Interrupt Mask Register SPI_MODE 0x10 32 read-only n 0x0 0x0 NSSE NSS Line (Driving CTS Pin) Rising or Falling Edge Event Interrupt Mask 19 1 read-only OVRE Overrun Error Interrupt Mask 5 1 read-only RXRDY RXRDY Interrupt Mask 0 1 read-only TXEMPTY TXEMPTY Interrupt Mask 9 1 read-only TXRDY TXRDY Interrupt Mask 1 1 read-only UNRE SPI Underrun Error Interrupt Mask 10 1 read-only MAN Manchester Configuration Register 0x50 32 read-write n 0x0 0x0 DRIFT Drift Compensation 30 1 read-write ONE Must Be Set to 1 29 1 read-write RX_MPOL Receiver Manchester Polarity 28 1 read-write RX_PL Receiver Preamble Length 16 4 read-write RX_PP Receiver Preamble Pattern detected 24 2 read-write ALL_ONE The preamble is composed of '1's 0x0 ALL_ZERO The preamble is composed of '0's 0x1 ZERO_ONE The preamble is composed of '01's 0x2 ONE_ZERO The preamble is composed of '10's 0x3 TX_MPOL Transmitter Manchester Polarity 12 1 read-write TX_PL Transmitter Preamble Length 0 4 read-write TX_PP Transmitter Preamble Pattern 8 2 read-write ALL_ONE The preamble is composed of '1's 0x0 ALL_ZERO The preamble is composed of '0's 0x1 ZERO_ONE The preamble is composed of '01's 0x2 ONE_ZERO The preamble is composed of '10's 0x3 MR Mode Register 0x4 32 read-write n 0x0 0x0 CHMODE Channel Mode 14 2 read-write NORMAL Normal mode 0x0 AUTOMATIC Automatic Echo. Receiver input is connected to the TXD pin. 0x1 LOCAL_LOOPBACK Local Loopback. Transmitter output is connected to the Receiver Input. 0x2 REMOTE_LOOPBACK Remote Loopback. RXD pin is internally connected to the TXD pin. 0x3 CHRL Character Length 6 2 read-write 5_BIT Character length is 5 bits 0x0 6_BIT Character length is 6 bits 0x1 7_BIT Character length is 7 bits 0x2 8_BIT Character length is 8 bits 0x3 CLKO Clock Output Select 18 1 read-write DSNACK Disable Successive NACK 21 1 read-write FILTER Receive Line Filter 28 1 read-write INACK Inhibit Non Acknowledge 20 1 read-write INVDATA Inverted Data 23 1 read-write MAN Manchester Encoder/Decoder Enable 29 1 read-write MAX_ITERATION Maximum Number of Automatic Iteration 24 3 read-write MODE9 9-bit Character Length 17 1 read-write MODSYNC Manchester Synchronization Mode 30 1 read-write MSBF Bit Order 16 1 read-write NBSTOP Number of Stop Bits 12 2 read-write 1_BIT 1 stop bit 0x0 1_5_BIT 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) 0x1 2_BIT 2 stop bits 0x2 ONEBIT Start Frame Delimiter Selector 31 1 read-write OVER Oversampling Mode 19 1 read-write PAR Parity Type 9 3 read-write EVEN Even parity 0x0 ODD Odd parity 0x1 SPACE Parity forced to 0 (Space) 0x2 MARK Parity forced to 1 (Mark) 0x3 NO No parity 0x4 MULTIDROP Multidrop mode 0x6 SYNC Synchronous Mode Select 8 1 read-write USART_MODE USART Mode of Operation 0 4 read-write NORMAL Normal mode 0x0 RS485 RS485 0x1 HW_HANDSHAKING Hardware Handshaking 0x2 IS07816_T_0 IS07816 Protocol: T = 0 0x4 IS07816_T_1 IS07816 Protocol: T = 1 0x6 IRDA IrDA 0x8 SPI_MASTER SPI Master mode (CLKO must be written to 1 and USCLKS = 0, 1 or 2) 0xE SPI_SLAVE SPI Slave mode 0xF USCLKS Clock Selection 4 2 read-write MCK Peripheral clock is selected 0x0 DIV Peripheral clock divided (DIV=8) is selected 0x1 SCK Serial clock (SCK) is selected 0x3 VAR_SYNC Variable Synchronization of Command/Data Sync Start Frame Delimiter 22 1 read-write MR_SPI_MODE Mode Register SPI_MODE 0x4 32 read-write n 0x0 0x0 CHRL Character Length 6 2 read-write 8_BIT Character length is 8 bits 0x3 CLKO Clock Output Select 18 1 read-write CPHA SPI Clock Phase 8 1 read-write CPOL SPI Clock Polarity 16 1 read-write USART_MODE USART Mode of Operation 0 4 read-write SPI_MASTER SPI master 0xE SPI_SLAVE SPI Slave 0xF USCLKS Clock Selection 4 2 read-write MCK Peripheral clock is selected 0x0 DIV Peripheral clock divided (DIV=8) is selected 0x1 SCK Serial Clock (SCK) is selected 0x3 WRDBT Wait Read Data Before Transfer 20 1 read-write NER Number of Errors Register 0x44 32 read-only n 0x0 0x0 NB_ERRORS Number of Errors 0 8 read-only RHR Receive Holding Register 0x18 32 read-only n 0x0 0x0 RXCHR Received Character 0 9 read-only RXSYNH Received Sync 15 1 read-only RTOR Receiver Timeout Register 0x24 32 read-write n 0x0 0x0 TO Timeout Value 0 16 read-write THR Transmit Holding Register 0x1C 32 write-only n 0x0 0x0 TXCHR Character to be Transmitted 0 9 write-only TXSYNH Sync Field to be Transmitted 15 1 write-only TTGR Transmitter Timeguard Register 0x28 32 read-write n 0x0 0x0 TG Timeguard Value 0 8 read-write WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 read-write WPKEY Write Protection Key 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. 0x555341 WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 read-only WPVSRC Write Protection Violation Source 8 16 read-only USART4 Universal Synchronous Asynchronous Receiver Transmitter 4 USART 0x0 0x0 0x50 registers n USART4 31 BRGR Baud Rate Generator Register 0x20 32 read-write n 0x0 0x0 CD Clock Divider 0 16 read-write FP Fractional Part 16 3 read-write CR Control Register 0x0 32 write-only n 0x0 0x0 RETTO Start Timeout Immediately 15 1 write-only RSTIT Reset Iterations 13 1 write-only RSTNACK Reset Non Acknowledge 14 1 write-only RSTRX Reset Receiver 2 1 write-only RSTSTA Reset Status Bits 8 1 write-only RSTTX Reset Transmitter 3 1 write-only RTSDIS Request to Send Pin Control 19 1 write-only RTSEN Request to Send Pin Control 18 1 write-only RXDIS Receiver Disable 5 1 write-only RXEN Receiver Enable 4 1 write-only SENDA Send Address 12 1 write-only STPBRK Stop Break 10 1 write-only STTBRK Start Break 9 1 write-only STTTO Clear TIMEOUT Flag and Start Timeout After Next Character Received 11 1 write-only TXDIS Transmitter Disable 7 1 write-only TXEN Transmitter Enable 6 1 write-only CR_SPI_MODE Control Register SPI_MODE 0x0 32 write-only n 0x0 0x0 FCS Force SPI Chip Select 18 1 write-only RCS Release SPI Chip Select 19 1 write-only RSTRX Reset Receiver 2 1 write-only RSTSTA Reset Status Bits 8 1 write-only RSTTX Reset Transmitter 3 1 write-only RXDIS Receiver Disable 5 1 write-only RXEN Receiver Enable 4 1 write-only TXDIS Transmitter Disable 7 1 write-only TXEN Transmitter Enable 6 1 write-only CSR Channel Status Register 0x14 32 read-only n 0x0 0x0 CTS Image of CTS Input 23 1 read-only CTSIC Clear to Send Input Change Flag (cleared on read) 19 1 read-only FRAME Framing Error (cleared by writing a one to bit US_CR.RSTSTA) 6 1 read-only ITER Max Number of Repetitions Reached (cleared by writing a one to bit US_CR.RSTIT) 10 1 read-only MANERR Manchester Error (cleared by writing a one to the bit US_CR.RSTSTA) 24 1 read-only NACK Non Acknowledge Interrupt (cleared by writing a one to bit US_CR.RSTNACK) 13 1 read-only OVRE Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) 5 1 read-only PARE Parity Error (cleared by writing a one to bit US_CR.RSTSTA) 7 1 read-only RXBRK Break Received/End of Break (cleared by writing a one to bit US_CR.RSTSTA) 2 1 read-only RXRDY Receiver Ready (cleared by reading US_RHR) 0 1 read-only TIMEOUT Receiver Timeout (cleared by writing a one to bit US_CR.STTTO) 8 1 read-only TXEMPTY Transmitter Empty (cleared by writing US_THR) 9 1 read-only TXRDY Transmitter Ready (cleared by writing US_THR) 1 1 read-only CSR_SPI_MODE Channel Status Register SPI_MODE 0x14 32 read-only n 0x0 0x0 NSS NSS Line (Driving CTS Pin) Rising or Falling Edge Event (cleared on read) 23 1 read-only NSSE NSS Line (Driving CTS Pin) Rising or Falling Edge Event (cleared on read) 19 1 read-only OVRE Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) 5 1 read-only RXRDY Receiver Ready (cleared by reading US_RHR) 0 1 read-only TXEMPTY Transmitter Empty (cleared by writing US_THR) 9 1 read-only TXRDY Transmitter Ready (cleared by writing US_THR) 1 1 read-only UNRE Underrun Error (cleared by writing a one to bit US_CR.RSTSTA) 10 1 read-only FIDI FI DI Ratio Register 0x40 32 read-write n 0x0 0x0 FI_DI_RATIO FI Over DI Ratio Value 0 11 read-write IDR Interrupt Disable Register 0xC 32 write-only n 0x0 0x0 CTSIC Clear to Send Input Change Interrupt Disable 19 1 write-only FRAME Framing Error Interrupt Disable 6 1 write-only ITER Max Number of Repetitions Reached Interrupt Disable 10 1 write-only MANE Manchester Error Interrupt Disable 24 1 write-only NACK Non Acknowledge Interrupt Disable 13 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only PARE Parity Error Interrupt Disable 7 1 write-only RXBRK Receiver Break Interrupt Disable 2 1 write-only RXRDY RXRDY Interrupt Disable 0 1 write-only TIMEOUT Timeout Interrupt Disable 8 1 write-only TXEMPTY TXEMPTY Interrupt Disable 9 1 write-only TXRDY TXRDY Interrupt Disable 1 1 write-only IDR_SPI_MODE Interrupt Disable Register SPI_MODE 0xC 32 write-only n 0x0 0x0 NSSE NSS Line (Driving CTS Pin) Rising or Falling Edge Event Interrupt Disable 19 1 write-only OVRE Overrun Error Interrupt Disable 5 1 write-only RXRDY RXRDY Interrupt Disable 0 1 write-only TXEMPTY TXEMPTY Interrupt Disable 9 1 write-only TXRDY TXRDY Interrupt Disable 1 1 write-only UNRE SPI Underrun Error Interrupt Disable 10 1 write-only IER Interrupt Enable Register 0x8 32 write-only n 0x0 0x0 CTSIC Clear to Send Input Change Interrupt Enable 19 1 write-only FRAME Framing Error Interrupt Enable 6 1 write-only ITER Max number of Repetitions Reached Interrupt Enable 10 1 write-only MANE Manchester Error Interrupt Enable 24 1 write-only NACK Non Acknowledge Interrupt Enable 13 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only PARE Parity Error Interrupt Enable 7 1 write-only RXBRK Receiver Break Interrupt Enable 2 1 write-only RXRDY RXRDY Interrupt Enable 0 1 write-only TIMEOUT Timeout Interrupt Enable 8 1 write-only TXEMPTY TXEMPTY Interrupt Enable 9 1 write-only TXRDY TXRDY Interrupt Enable 1 1 write-only IER_SPI_MODE Interrupt Enable Register SPI_MODE 0x8 32 write-only n 0x0 0x0 NSSE NSS Line (Driving CTS Pin) Rising or Falling Edge Event Interrupt Enable 19 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only RXRDY RXRDY Interrupt Enable 0 1 write-only TXEMPTY TXEMPTY Interrupt Enable 9 1 write-only TXRDY TXRDY Interrupt Enable 1 1 write-only UNRE SPI Underrun Error Interrupt Enable 10 1 write-only IF IrDA Filter Register 0x4C 32 read-write n 0x0 0x0 IRDA_FILTER IrDA Filter 0 8 read-write IMR Interrupt Mask Register 0x10 32 read-only n 0x0 0x0 CTSIC Clear to Send Input Change Interrupt Mask 19 1 read-only FRAME Framing Error Interrupt Mask 6 1 read-only ITER Max Number of Repetitions Reached Interrupt Mask 10 1 read-only MANE Manchester Error Interrupt Mask 24 1 read-only NACK Non Acknowledge Interrupt Mask 13 1 read-only OVRE Overrun Error Interrupt Mask 5 1 read-only PARE Parity Error Interrupt Mask 7 1 read-only RXBRK Receiver Break Interrupt Mask 2 1 read-only RXRDY RXRDY Interrupt Mask 0 1 read-only TIMEOUT Timeout Interrupt Mask 8 1 read-only TXEMPTY TXEMPTY Interrupt Mask 9 1 read-only TXRDY TXRDY Interrupt Mask 1 1 read-only IMR_SPI_MODE Interrupt Mask Register SPI_MODE 0x10 32 read-only n 0x0 0x0 NSSE NSS Line (Driving CTS Pin) Rising or Falling Edge Event Interrupt Mask 19 1 read-only OVRE Overrun Error Interrupt Mask 5 1 read-only RXRDY RXRDY Interrupt Mask 0 1 read-only TXEMPTY TXEMPTY Interrupt Mask 9 1 read-only TXRDY TXRDY Interrupt Mask 1 1 read-only UNRE SPI Underrun Error Interrupt Mask 10 1 read-only MAN Manchester Configuration Register 0x50 32 read-write n 0x0 0x0 DRIFT Drift Compensation 30 1 read-write ONE Must Be Set to 1 29 1 read-write RX_MPOL Receiver Manchester Polarity 28 1 read-write RX_PL Receiver Preamble Length 16 4 read-write RX_PP Receiver Preamble Pattern detected 24 2 read-write ALL_ONE The preamble is composed of '1's 0x0 ALL_ZERO The preamble is composed of '0's 0x1 ZERO_ONE The preamble is composed of '01's 0x2 ONE_ZERO The preamble is composed of '10's 0x3 TX_MPOL Transmitter Manchester Polarity 12 1 read-write TX_PL Transmitter Preamble Length 0 4 read-write TX_PP Transmitter Preamble Pattern 8 2 read-write ALL_ONE The preamble is composed of '1's 0x0 ALL_ZERO The preamble is composed of '0's 0x1 ZERO_ONE The preamble is composed of '01's 0x2 ONE_ZERO The preamble is composed of '10's 0x3 MR Mode Register 0x4 32 read-write n 0x0 0x0 CHMODE Channel Mode 14 2 read-write NORMAL Normal mode 0x0 AUTOMATIC Automatic Echo. Receiver input is connected to the TXD pin. 0x1 LOCAL_LOOPBACK Local Loopback. Transmitter output is connected to the Receiver Input. 0x2 REMOTE_LOOPBACK Remote Loopback. RXD pin is internally connected to the TXD pin. 0x3 CHRL Character Length 6 2 read-write 5_BIT Character length is 5 bits 0x0 6_BIT Character length is 6 bits 0x1 7_BIT Character length is 7 bits 0x2 8_BIT Character length is 8 bits 0x3 CLKO Clock Output Select 18 1 read-write DSNACK Disable Successive NACK 21 1 read-write FILTER Receive Line Filter 28 1 read-write INACK Inhibit Non Acknowledge 20 1 read-write INVDATA Inverted Data 23 1 read-write MAN Manchester Encoder/Decoder Enable 29 1 read-write MAX_ITERATION Maximum Number of Automatic Iteration 24 3 read-write MODE9 9-bit Character Length 17 1 read-write MODSYNC Manchester Synchronization Mode 30 1 read-write MSBF Bit Order 16 1 read-write NBSTOP Number of Stop Bits 12 2 read-write 1_BIT 1 stop bit 0x0 1_5_BIT 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) 0x1 2_BIT 2 stop bits 0x2 ONEBIT Start Frame Delimiter Selector 31 1 read-write OVER Oversampling Mode 19 1 read-write PAR Parity Type 9 3 read-write EVEN Even parity 0x0 ODD Odd parity 0x1 SPACE Parity forced to 0 (Space) 0x2 MARK Parity forced to 1 (Mark) 0x3 NO No parity 0x4 MULTIDROP Multidrop mode 0x6 SYNC Synchronous Mode Select 8 1 read-write USART_MODE USART Mode of Operation 0 4 read-write NORMAL Normal mode 0x0 RS485 RS485 0x1 HW_HANDSHAKING Hardware Handshaking 0x2 IS07816_T_0 IS07816 Protocol: T = 0 0x4 IS07816_T_1 IS07816 Protocol: T = 1 0x6 IRDA IrDA 0x8 SPI_MASTER SPI Master mode (CLKO must be written to 1 and USCLKS = 0, 1 or 2) 0xE SPI_SLAVE SPI Slave mode 0xF USCLKS Clock Selection 4 2 read-write MCK Peripheral clock is selected 0x0 DIV Peripheral clock divided (DIV=8) is selected 0x1 SCK Serial clock (SCK) is selected 0x3 VAR_SYNC Variable Synchronization of Command/Data Sync Start Frame Delimiter 22 1 read-write MR_SPI_MODE Mode Register SPI_MODE 0x4 32 read-write n 0x0 0x0 CHRL Character Length 6 2 read-write 8_BIT Character length is 8 bits 0x3 CLKO Clock Output Select 18 1 read-write CPHA SPI Clock Phase 8 1 read-write CPOL SPI Clock Polarity 16 1 read-write USART_MODE USART Mode of Operation 0 4 read-write SPI_MASTER SPI master 0xE SPI_SLAVE SPI Slave 0xF USCLKS Clock Selection 4 2 read-write MCK Peripheral clock is selected 0x0 DIV Peripheral clock divided (DIV=8) is selected 0x1 SCK Serial Clock (SCK) is selected 0x3 WRDBT Wait Read Data Before Transfer 20 1 read-write NER Number of Errors Register 0x44 32 read-only n 0x0 0x0 NB_ERRORS Number of Errors 0 8 read-only RHR Receive Holding Register 0x18 32 read-only n 0x0 0x0 RXCHR Received Character 0 9 read-only RXSYNH Received Sync 15 1 read-only RTOR Receiver Timeout Register 0x24 32 read-write n 0x0 0x0 TO Timeout Value 0 16 read-write THR Transmit Holding Register 0x1C 32 write-only n 0x0 0x0 TXCHR Character to be Transmitted 0 9 write-only TXSYNH Sync Field to be Transmitted 15 1 write-only TTGR Transmitter Timeguard Register 0x28 32 read-write n 0x0 0x0 TG Timeguard Value 0 8 read-write WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 read-write WPKEY Write Protection Key 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. 0x555341 WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 read-only WPVSRC Write Protection Violation Source 8 16 read-only WDT Watchdog Timer SYSC 0x0 0x0 0x200 registers n CR Control Register 0x0 32 write-only n 0x0 0x0 KEY Password 24 8 write-only PASSWD Writing any other value in this field aborts the write operation. 0xA5 LOCKMR Lock Mode Register Write Access 4 1 write-only WDRSTT Watchdog Restart 0 1 write-only MR Mode Register 0x4 32 read-write n 0x0 0x0 WDD Watchdog Delta Value 16 12 read-write WDDBGHLT Watchdog Debug Halt 28 1 read-write WDDIS Watchdog Disable 15 1 read-write WDFIEN Watchdog Fault Interrupt Enable 12 1 read-write WDIDLEHLT Watchdog Idle Halt 29 1 read-write WDRSTEN Watchdog Reset Enable 13 1 read-write WDV Watchdog Counter Value 0 12 read-write SR Status Register 0x8 32 read-only n 0x0 0x0 WDERR Watchdog Error (cleared on read) 1 1 read-only WDUNF Watchdog Underflow (cleared on read) 0 1 read-only XDMAC0 Extensible DMA Controller 0 XDMAC 0x0 0x0 0x50 registers n XDMAC0 8 CBC0 Channel Block Control Register (chid = 0) 0x74 32 read-write n 0x0 0x0 BLEN Channel x Block Length 0 12 read-write CBC1 Channel Block Control Register (chid = 1) 0xB4 32 read-write n 0x0 0x0 BLEN Channel x Block Length 0 12 read-write CBC10 Channel Block Control Register (chid = 10) 0x2F4 32 read-write n 0x0 0x0 BLEN Channel x Block Length 0 12 read-write CBC11 Channel Block Control Register (chid = 11) 0x334 32 read-write n 0x0 0x0 BLEN Channel x Block Length 0 12 read-write CBC12 Channel Block Control Register (chid = 12) 0x374 32 read-write n 0x0 0x0 BLEN Channel x Block Length 0 12 read-write CBC13 Channel Block Control Register (chid = 13) 0x3B4 32 read-write n 0x0 0x0 BLEN Channel x Block Length 0 12 read-write CBC14 Channel Block Control Register (chid = 14) 0x3F4 32 read-write n 0x0 0x0 BLEN Channel x Block Length 0 12 read-write CBC15 Channel Block Control Register (chid = 15) 0x434 32 read-write n 0x0 0x0 BLEN Channel x Block Length 0 12 read-write CBC2 Channel Block Control Register (chid = 2) 0xF4 32 read-write n 0x0 0x0 BLEN Channel x Block Length 0 12 read-write CBC3 Channel Block Control Register (chid = 3) 0x134 32 read-write n 0x0 0x0 BLEN Channel x Block Length 0 12 read-write CBC4 Channel Block Control Register (chid = 4) 0x174 32 read-write n 0x0 0x0 BLEN Channel x Block Length 0 12 read-write CBC5 Channel Block Control Register (chid = 5) 0x1B4 32 read-write n 0x0 0x0 BLEN Channel x Block Length 0 12 read-write CBC6 Channel Block Control Register (chid = 6) 0x1F4 32 read-write n 0x0 0x0 BLEN Channel x Block Length 0 12 read-write CBC7 Channel Block Control Register (chid = 7) 0x234 32 read-write n 0x0 0x0 BLEN Channel x Block Length 0 12 read-write CBC8 Channel Block Control Register (chid = 8) 0x274 32 read-write n 0x0 0x0 BLEN Channel x Block Length 0 12 read-write CBC9 Channel Block Control Register (chid = 9) 0x2B4 32 read-write n 0x0 0x0 BLEN Channel x Block Length 0 12 read-write CC0 Channel Configuration Register (chid = 0) 0x78 32 read-write n 0x0 0x0 CSIZE Channel x Chunk Size 8 3 read-write CHK_1 1 data transferred 0x0 CHK_2 2 data transferred 0x1 CHK_4 4 data transferred 0x2 CHK_8 8 data transferred 0x3 CHK_16 16 data transferred 0x4 DAM Channel x Destination Addressing Mode 18 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary; the data stride is added at the data boundary. 0x3 DIF Channel x Destination Interface Identifier 14 1 read-write AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 read-write PER2MEM Peripheral-to-memory transfer. 0 MEM2PER Memory-to-peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 read-write BYTE The data size is set to 8 bits 0x0 HALFWORD The data size is set to 16 bits 0x1 WORD The data size is set to 32 bits 0x2 DWORD The data size is set to 64 bits 0x3 INITD Channel Initialization Done (this bit is read-only) 21 1 read-write IN_PROGRESS Channel initialization is in progress. 0 TERMINATED Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 read-write SINGLE The memory burst size is set to one. 0x0 FOUR The memory burst size is set to four. 0x1 EIGHT The memory burst size is set to eight. 0x2 SIXTEEN The memory burst size is set to sixteen. 0x3 MEMSET Channel x Fill Block of Memory 7 1 read-write NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 read-write PROT Channel x Protection 5 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 RDIP Read in Progress (this bit is read-only) 22 1 read-write DONE No active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 SIF Channel x Source Interface Identifier 13 1 read-write AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 read-write MEM_TRAN Self-triggered mode (memory-to-memory transfer). 0 PER_TRAN Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 read-write DONE No active write transaction on the bus. 0 IN_PROGRESS A write transaction is in progress. 1 CC1 Channel Configuration Register (chid = 1) 0xB8 32 read-write n 0x0 0x0 CSIZE Channel x Chunk Size 8 3 read-write CHK_1 1 data transferred 0x0 CHK_2 2 data transferred 0x1 CHK_4 4 data transferred 0x2 CHK_8 8 data transferred 0x3 CHK_16 16 data transferred 0x4 DAM Channel x Destination Addressing Mode 18 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary; the data stride is added at the data boundary. 0x3 DIF Channel x Destination Interface Identifier 14 1 read-write AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 read-write PER2MEM Peripheral-to-memory transfer. 0 MEM2PER Memory-to-peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 read-write BYTE The data size is set to 8 bits 0x0 HALFWORD The data size is set to 16 bits 0x1 WORD The data size is set to 32 bits 0x2 DWORD The data size is set to 64 bits 0x3 INITD Channel Initialization Done (this bit is read-only) 21 1 read-write IN_PROGRESS Channel initialization is in progress. 0 TERMINATED Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 read-write SINGLE The memory burst size is set to one. 0x0 FOUR The memory burst size is set to four. 0x1 EIGHT The memory burst size is set to eight. 0x2 SIXTEEN The memory burst size is set to sixteen. 0x3 MEMSET Channel x Fill Block of Memory 7 1 read-write NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 read-write PROT Channel x Protection 5 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 RDIP Read in Progress (this bit is read-only) 22 1 read-write DONE No active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 SIF Channel x Source Interface Identifier 13 1 read-write AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 read-write MEM_TRAN Self-triggered mode (memory-to-memory transfer). 0 PER_TRAN Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 read-write DONE No active write transaction on the bus. 0 IN_PROGRESS A write transaction is in progress. 1 CC10 Channel Configuration Register (chid = 10) 0x2F8 32 read-write n 0x0 0x0 CSIZE Channel x Chunk Size 8 3 read-write CHK_1 1 data transferred 0x0 CHK_2 2 data transferred 0x1 CHK_4 4 data transferred 0x2 CHK_8 8 data transferred 0x3 CHK_16 16 data transferred 0x4 DAM Channel x Destination Addressing Mode 18 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary; the data stride is added at the data boundary. 0x3 DIF Channel x Destination Interface Identifier 14 1 read-write AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 read-write PER2MEM Peripheral-to-memory transfer. 0 MEM2PER Memory-to-peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 read-write BYTE The data size is set to 8 bits 0x0 HALFWORD The data size is set to 16 bits 0x1 WORD The data size is set to 32 bits 0x2 DWORD The data size is set to 64 bits 0x3 INITD Channel Initialization Done (this bit is read-only) 21 1 read-write IN_PROGRESS Channel initialization is in progress. 0 TERMINATED Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 read-write SINGLE The memory burst size is set to one. 0x0 FOUR The memory burst size is set to four. 0x1 EIGHT The memory burst size is set to eight. 0x2 SIXTEEN The memory burst size is set to sixteen. 0x3 MEMSET Channel x Fill Block of Memory 7 1 read-write NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 read-write PROT Channel x Protection 5 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 RDIP Read in Progress (this bit is read-only) 22 1 read-write DONE No active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 SIF Channel x Source Interface Identifier 13 1 read-write AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 read-write MEM_TRAN Self-triggered mode (memory-to-memory transfer). 0 PER_TRAN Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 read-write DONE No active write transaction on the bus. 0 IN_PROGRESS A write transaction is in progress. 1 CC11 Channel Configuration Register (chid = 11) 0x338 32 read-write n 0x0 0x0 CSIZE Channel x Chunk Size 8 3 read-write CHK_1 1 data transferred 0x0 CHK_2 2 data transferred 0x1 CHK_4 4 data transferred 0x2 CHK_8 8 data transferred 0x3 CHK_16 16 data transferred 0x4 DAM Channel x Destination Addressing Mode 18 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary; the data stride is added at the data boundary. 0x3 DIF Channel x Destination Interface Identifier 14 1 read-write AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 read-write PER2MEM Peripheral-to-memory transfer. 0 MEM2PER Memory-to-peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 read-write BYTE The data size is set to 8 bits 0x0 HALFWORD The data size is set to 16 bits 0x1 WORD The data size is set to 32 bits 0x2 DWORD The data size is set to 64 bits 0x3 INITD Channel Initialization Done (this bit is read-only) 21 1 read-write IN_PROGRESS Channel initialization is in progress. 0 TERMINATED Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 read-write SINGLE The memory burst size is set to one. 0x0 FOUR The memory burst size is set to four. 0x1 EIGHT The memory burst size is set to eight. 0x2 SIXTEEN The memory burst size is set to sixteen. 0x3 MEMSET Channel x Fill Block of Memory 7 1 read-write NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 read-write PROT Channel x Protection 5 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 RDIP Read in Progress (this bit is read-only) 22 1 read-write DONE No active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 SIF Channel x Source Interface Identifier 13 1 read-write AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 read-write MEM_TRAN Self-triggered mode (memory-to-memory transfer). 0 PER_TRAN Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 read-write DONE No active write transaction on the bus. 0 IN_PROGRESS A write transaction is in progress. 1 CC12 Channel Configuration Register (chid = 12) 0x378 32 read-write n 0x0 0x0 CSIZE Channel x Chunk Size 8 3 read-write CHK_1 1 data transferred 0x0 CHK_2 2 data transferred 0x1 CHK_4 4 data transferred 0x2 CHK_8 8 data transferred 0x3 CHK_16 16 data transferred 0x4 DAM Channel x Destination Addressing Mode 18 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary; the data stride is added at the data boundary. 0x3 DIF Channel x Destination Interface Identifier 14 1 read-write AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 read-write PER2MEM Peripheral-to-memory transfer. 0 MEM2PER Memory-to-peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 read-write BYTE The data size is set to 8 bits 0x0 HALFWORD The data size is set to 16 bits 0x1 WORD The data size is set to 32 bits 0x2 DWORD The data size is set to 64 bits 0x3 INITD Channel Initialization Done (this bit is read-only) 21 1 read-write IN_PROGRESS Channel initialization is in progress. 0 TERMINATED Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 read-write SINGLE The memory burst size is set to one. 0x0 FOUR The memory burst size is set to four. 0x1 EIGHT The memory burst size is set to eight. 0x2 SIXTEEN The memory burst size is set to sixteen. 0x3 MEMSET Channel x Fill Block of Memory 7 1 read-write NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 read-write PROT Channel x Protection 5 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 RDIP Read in Progress (this bit is read-only) 22 1 read-write DONE No active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 SIF Channel x Source Interface Identifier 13 1 read-write AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 read-write MEM_TRAN Self-triggered mode (memory-to-memory transfer). 0 PER_TRAN Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 read-write DONE No active write transaction on the bus. 0 IN_PROGRESS A write transaction is in progress. 1 CC13 Channel Configuration Register (chid = 13) 0x3B8 32 read-write n 0x0 0x0 CSIZE Channel x Chunk Size 8 3 read-write CHK_1 1 data transferred 0x0 CHK_2 2 data transferred 0x1 CHK_4 4 data transferred 0x2 CHK_8 8 data transferred 0x3 CHK_16 16 data transferred 0x4 DAM Channel x Destination Addressing Mode 18 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary; the data stride is added at the data boundary. 0x3 DIF Channel x Destination Interface Identifier 14 1 read-write AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 read-write PER2MEM Peripheral-to-memory transfer. 0 MEM2PER Memory-to-peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 read-write BYTE The data size is set to 8 bits 0x0 HALFWORD The data size is set to 16 bits 0x1 WORD The data size is set to 32 bits 0x2 DWORD The data size is set to 64 bits 0x3 INITD Channel Initialization Done (this bit is read-only) 21 1 read-write IN_PROGRESS Channel initialization is in progress. 0 TERMINATED Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 read-write SINGLE The memory burst size is set to one. 0x0 FOUR The memory burst size is set to four. 0x1 EIGHT The memory burst size is set to eight. 0x2 SIXTEEN The memory burst size is set to sixteen. 0x3 MEMSET Channel x Fill Block of Memory 7 1 read-write NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 read-write PROT Channel x Protection 5 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 RDIP Read in Progress (this bit is read-only) 22 1 read-write DONE No active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 SIF Channel x Source Interface Identifier 13 1 read-write AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 read-write MEM_TRAN Self-triggered mode (memory-to-memory transfer). 0 PER_TRAN Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 read-write DONE No active write transaction on the bus. 0 IN_PROGRESS A write transaction is in progress. 1 CC14 Channel Configuration Register (chid = 14) 0x3F8 32 read-write n 0x0 0x0 CSIZE Channel x Chunk Size 8 3 read-write CHK_1 1 data transferred 0x0 CHK_2 2 data transferred 0x1 CHK_4 4 data transferred 0x2 CHK_8 8 data transferred 0x3 CHK_16 16 data transferred 0x4 DAM Channel x Destination Addressing Mode 18 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary; the data stride is added at the data boundary. 0x3 DIF Channel x Destination Interface Identifier 14 1 read-write AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 read-write PER2MEM Peripheral-to-memory transfer. 0 MEM2PER Memory-to-peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 read-write BYTE The data size is set to 8 bits 0x0 HALFWORD The data size is set to 16 bits 0x1 WORD The data size is set to 32 bits 0x2 DWORD The data size is set to 64 bits 0x3 INITD Channel Initialization Done (this bit is read-only) 21 1 read-write IN_PROGRESS Channel initialization is in progress. 0 TERMINATED Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 read-write SINGLE The memory burst size is set to one. 0x0 FOUR The memory burst size is set to four. 0x1 EIGHT The memory burst size is set to eight. 0x2 SIXTEEN The memory burst size is set to sixteen. 0x3 MEMSET Channel x Fill Block of Memory 7 1 read-write NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 read-write PROT Channel x Protection 5 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 RDIP Read in Progress (this bit is read-only) 22 1 read-write DONE No active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 SIF Channel x Source Interface Identifier 13 1 read-write AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 read-write MEM_TRAN Self-triggered mode (memory-to-memory transfer). 0 PER_TRAN Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 read-write DONE No active write transaction on the bus. 0 IN_PROGRESS A write transaction is in progress. 1 CC15 Channel Configuration Register (chid = 15) 0x438 32 read-write n 0x0 0x0 CSIZE Channel x Chunk Size 8 3 read-write CHK_1 1 data transferred 0x0 CHK_2 2 data transferred 0x1 CHK_4 4 data transferred 0x2 CHK_8 8 data transferred 0x3 CHK_16 16 data transferred 0x4 DAM Channel x Destination Addressing Mode 18 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary; the data stride is added at the data boundary. 0x3 DIF Channel x Destination Interface Identifier 14 1 read-write AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 read-write PER2MEM Peripheral-to-memory transfer. 0 MEM2PER Memory-to-peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 read-write BYTE The data size is set to 8 bits 0x0 HALFWORD The data size is set to 16 bits 0x1 WORD The data size is set to 32 bits 0x2 DWORD The data size is set to 64 bits 0x3 INITD Channel Initialization Done (this bit is read-only) 21 1 read-write IN_PROGRESS Channel initialization is in progress. 0 TERMINATED Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 read-write SINGLE The memory burst size is set to one. 0x0 FOUR The memory burst size is set to four. 0x1 EIGHT The memory burst size is set to eight. 0x2 SIXTEEN The memory burst size is set to sixteen. 0x3 MEMSET Channel x Fill Block of Memory 7 1 read-write NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 read-write PROT Channel x Protection 5 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 RDIP Read in Progress (this bit is read-only) 22 1 read-write DONE No active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 SIF Channel x Source Interface Identifier 13 1 read-write AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 read-write MEM_TRAN Self-triggered mode (memory-to-memory transfer). 0 PER_TRAN Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 read-write DONE No active write transaction on the bus. 0 IN_PROGRESS A write transaction is in progress. 1 CC2 Channel Configuration Register (chid = 2) 0xF8 32 read-write n 0x0 0x0 CSIZE Channel x Chunk Size 8 3 read-write CHK_1 1 data transferred 0x0 CHK_2 2 data transferred 0x1 CHK_4 4 data transferred 0x2 CHK_8 8 data transferred 0x3 CHK_16 16 data transferred 0x4 DAM Channel x Destination Addressing Mode 18 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary; the data stride is added at the data boundary. 0x3 DIF Channel x Destination Interface Identifier 14 1 read-write AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 read-write PER2MEM Peripheral-to-memory transfer. 0 MEM2PER Memory-to-peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 read-write BYTE The data size is set to 8 bits 0x0 HALFWORD The data size is set to 16 bits 0x1 WORD The data size is set to 32 bits 0x2 DWORD The data size is set to 64 bits 0x3 INITD Channel Initialization Done (this bit is read-only) 21 1 read-write IN_PROGRESS Channel initialization is in progress. 0 TERMINATED Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 read-write SINGLE The memory burst size is set to one. 0x0 FOUR The memory burst size is set to four. 0x1 EIGHT The memory burst size is set to eight. 0x2 SIXTEEN The memory burst size is set to sixteen. 0x3 MEMSET Channel x Fill Block of Memory 7 1 read-write NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 read-write PROT Channel x Protection 5 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 RDIP Read in Progress (this bit is read-only) 22 1 read-write DONE No active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 SIF Channel x Source Interface Identifier 13 1 read-write AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 read-write MEM_TRAN Self-triggered mode (memory-to-memory transfer). 0 PER_TRAN Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 read-write DONE No active write transaction on the bus. 0 IN_PROGRESS A write transaction is in progress. 1 CC3 Channel Configuration Register (chid = 3) 0x138 32 read-write n 0x0 0x0 CSIZE Channel x Chunk Size 8 3 read-write CHK_1 1 data transferred 0x0 CHK_2 2 data transferred 0x1 CHK_4 4 data transferred 0x2 CHK_8 8 data transferred 0x3 CHK_16 16 data transferred 0x4 DAM Channel x Destination Addressing Mode 18 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary; the data stride is added at the data boundary. 0x3 DIF Channel x Destination Interface Identifier 14 1 read-write AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 read-write PER2MEM Peripheral-to-memory transfer. 0 MEM2PER Memory-to-peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 read-write BYTE The data size is set to 8 bits 0x0 HALFWORD The data size is set to 16 bits 0x1 WORD The data size is set to 32 bits 0x2 DWORD The data size is set to 64 bits 0x3 INITD Channel Initialization Done (this bit is read-only) 21 1 read-write IN_PROGRESS Channel initialization is in progress. 0 TERMINATED Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 read-write SINGLE The memory burst size is set to one. 0x0 FOUR The memory burst size is set to four. 0x1 EIGHT The memory burst size is set to eight. 0x2 SIXTEEN The memory burst size is set to sixteen. 0x3 MEMSET Channel x Fill Block of Memory 7 1 read-write NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 read-write PROT Channel x Protection 5 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 RDIP Read in Progress (this bit is read-only) 22 1 read-write DONE No active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 SIF Channel x Source Interface Identifier 13 1 read-write AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 read-write MEM_TRAN Self-triggered mode (memory-to-memory transfer). 0 PER_TRAN Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 read-write DONE No active write transaction on the bus. 0 IN_PROGRESS A write transaction is in progress. 1 CC4 Channel Configuration Register (chid = 4) 0x178 32 read-write n 0x0 0x0 CSIZE Channel x Chunk Size 8 3 read-write CHK_1 1 data transferred 0x0 CHK_2 2 data transferred 0x1 CHK_4 4 data transferred 0x2 CHK_8 8 data transferred 0x3 CHK_16 16 data transferred 0x4 DAM Channel x Destination Addressing Mode 18 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary; the data stride is added at the data boundary. 0x3 DIF Channel x Destination Interface Identifier 14 1 read-write AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 read-write PER2MEM Peripheral-to-memory transfer. 0 MEM2PER Memory-to-peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 read-write BYTE The data size is set to 8 bits 0x0 HALFWORD The data size is set to 16 bits 0x1 WORD The data size is set to 32 bits 0x2 DWORD The data size is set to 64 bits 0x3 INITD Channel Initialization Done (this bit is read-only) 21 1 read-write IN_PROGRESS Channel initialization is in progress. 0 TERMINATED Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 read-write SINGLE The memory burst size is set to one. 0x0 FOUR The memory burst size is set to four. 0x1 EIGHT The memory burst size is set to eight. 0x2 SIXTEEN The memory burst size is set to sixteen. 0x3 MEMSET Channel x Fill Block of Memory 7 1 read-write NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 read-write PROT Channel x Protection 5 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 RDIP Read in Progress (this bit is read-only) 22 1 read-write DONE No active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 SIF Channel x Source Interface Identifier 13 1 read-write AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 read-write MEM_TRAN Self-triggered mode (memory-to-memory transfer). 0 PER_TRAN Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 read-write DONE No active write transaction on the bus. 0 IN_PROGRESS A write transaction is in progress. 1 CC5 Channel Configuration Register (chid = 5) 0x1B8 32 read-write n 0x0 0x0 CSIZE Channel x Chunk Size 8 3 read-write CHK_1 1 data transferred 0x0 CHK_2 2 data transferred 0x1 CHK_4 4 data transferred 0x2 CHK_8 8 data transferred 0x3 CHK_16 16 data transferred 0x4 DAM Channel x Destination Addressing Mode 18 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary; the data stride is added at the data boundary. 0x3 DIF Channel x Destination Interface Identifier 14 1 read-write AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 read-write PER2MEM Peripheral-to-memory transfer. 0 MEM2PER Memory-to-peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 read-write BYTE The data size is set to 8 bits 0x0 HALFWORD The data size is set to 16 bits 0x1 WORD The data size is set to 32 bits 0x2 DWORD The data size is set to 64 bits 0x3 INITD Channel Initialization Done (this bit is read-only) 21 1 read-write IN_PROGRESS Channel initialization is in progress. 0 TERMINATED Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 read-write SINGLE The memory burst size is set to one. 0x0 FOUR The memory burst size is set to four. 0x1 EIGHT The memory burst size is set to eight. 0x2 SIXTEEN The memory burst size is set to sixteen. 0x3 MEMSET Channel x Fill Block of Memory 7 1 read-write NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 read-write PROT Channel x Protection 5 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 RDIP Read in Progress (this bit is read-only) 22 1 read-write DONE No active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 SIF Channel x Source Interface Identifier 13 1 read-write AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 read-write MEM_TRAN Self-triggered mode (memory-to-memory transfer). 0 PER_TRAN Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 read-write DONE No active write transaction on the bus. 0 IN_PROGRESS A write transaction is in progress. 1 CC6 Channel Configuration Register (chid = 6) 0x1F8 32 read-write n 0x0 0x0 CSIZE Channel x Chunk Size 8 3 read-write CHK_1 1 data transferred 0x0 CHK_2 2 data transferred 0x1 CHK_4 4 data transferred 0x2 CHK_8 8 data transferred 0x3 CHK_16 16 data transferred 0x4 DAM Channel x Destination Addressing Mode 18 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary; the data stride is added at the data boundary. 0x3 DIF Channel x Destination Interface Identifier 14 1 read-write AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 read-write PER2MEM Peripheral-to-memory transfer. 0 MEM2PER Memory-to-peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 read-write BYTE The data size is set to 8 bits 0x0 HALFWORD The data size is set to 16 bits 0x1 WORD The data size is set to 32 bits 0x2 DWORD The data size is set to 64 bits 0x3 INITD Channel Initialization Done (this bit is read-only) 21 1 read-write IN_PROGRESS Channel initialization is in progress. 0 TERMINATED Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 read-write SINGLE The memory burst size is set to one. 0x0 FOUR The memory burst size is set to four. 0x1 EIGHT The memory burst size is set to eight. 0x2 SIXTEEN The memory burst size is set to sixteen. 0x3 MEMSET Channel x Fill Block of Memory 7 1 read-write NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 read-write PROT Channel x Protection 5 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 RDIP Read in Progress (this bit is read-only) 22 1 read-write DONE No active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 SIF Channel x Source Interface Identifier 13 1 read-write AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 read-write MEM_TRAN Self-triggered mode (memory-to-memory transfer). 0 PER_TRAN Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 read-write DONE No active write transaction on the bus. 0 IN_PROGRESS A write transaction is in progress. 1 CC7 Channel Configuration Register (chid = 7) 0x238 32 read-write n 0x0 0x0 CSIZE Channel x Chunk Size 8 3 read-write CHK_1 1 data transferred 0x0 CHK_2 2 data transferred 0x1 CHK_4 4 data transferred 0x2 CHK_8 8 data transferred 0x3 CHK_16 16 data transferred 0x4 DAM Channel x Destination Addressing Mode 18 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary; the data stride is added at the data boundary. 0x3 DIF Channel x Destination Interface Identifier 14 1 read-write AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 read-write PER2MEM Peripheral-to-memory transfer. 0 MEM2PER Memory-to-peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 read-write BYTE The data size is set to 8 bits 0x0 HALFWORD The data size is set to 16 bits 0x1 WORD The data size is set to 32 bits 0x2 DWORD The data size is set to 64 bits 0x3 INITD Channel Initialization Done (this bit is read-only) 21 1 read-write IN_PROGRESS Channel initialization is in progress. 0 TERMINATED Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 read-write SINGLE The memory burst size is set to one. 0x0 FOUR The memory burst size is set to four. 0x1 EIGHT The memory burst size is set to eight. 0x2 SIXTEEN The memory burst size is set to sixteen. 0x3 MEMSET Channel x Fill Block of Memory 7 1 read-write NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 read-write PROT Channel x Protection 5 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 RDIP Read in Progress (this bit is read-only) 22 1 read-write DONE No active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 SIF Channel x Source Interface Identifier 13 1 read-write AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 read-write MEM_TRAN Self-triggered mode (memory-to-memory transfer). 0 PER_TRAN Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 read-write DONE No active write transaction on the bus. 0 IN_PROGRESS A write transaction is in progress. 1 CC8 Channel Configuration Register (chid = 8) 0x278 32 read-write n 0x0 0x0 CSIZE Channel x Chunk Size 8 3 read-write CHK_1 1 data transferred 0x0 CHK_2 2 data transferred 0x1 CHK_4 4 data transferred 0x2 CHK_8 8 data transferred 0x3 CHK_16 16 data transferred 0x4 DAM Channel x Destination Addressing Mode 18 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary; the data stride is added at the data boundary. 0x3 DIF Channel x Destination Interface Identifier 14 1 read-write AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 read-write PER2MEM Peripheral-to-memory transfer. 0 MEM2PER Memory-to-peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 read-write BYTE The data size is set to 8 bits 0x0 HALFWORD The data size is set to 16 bits 0x1 WORD The data size is set to 32 bits 0x2 DWORD The data size is set to 64 bits 0x3 INITD Channel Initialization Done (this bit is read-only) 21 1 read-write IN_PROGRESS Channel initialization is in progress. 0 TERMINATED Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 read-write SINGLE The memory burst size is set to one. 0x0 FOUR The memory burst size is set to four. 0x1 EIGHT The memory burst size is set to eight. 0x2 SIXTEEN The memory burst size is set to sixteen. 0x3 MEMSET Channel x Fill Block of Memory 7 1 read-write NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 read-write PROT Channel x Protection 5 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 RDIP Read in Progress (this bit is read-only) 22 1 read-write DONE No active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 SIF Channel x Source Interface Identifier 13 1 read-write AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 read-write MEM_TRAN Self-triggered mode (memory-to-memory transfer). 0 PER_TRAN Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 read-write DONE No active write transaction on the bus. 0 IN_PROGRESS A write transaction is in progress. 1 CC9 Channel Configuration Register (chid = 9) 0x2B8 32 read-write n 0x0 0x0 CSIZE Channel x Chunk Size 8 3 read-write CHK_1 1 data transferred 0x0 CHK_2 2 data transferred 0x1 CHK_4 4 data transferred 0x2 CHK_8 8 data transferred 0x3 CHK_16 16 data transferred 0x4 DAM Channel x Destination Addressing Mode 18 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary; the data stride is added at the data boundary. 0x3 DIF Channel x Destination Interface Identifier 14 1 read-write AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 read-write PER2MEM Peripheral-to-memory transfer. 0 MEM2PER Memory-to-peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 read-write BYTE The data size is set to 8 bits 0x0 HALFWORD The data size is set to 16 bits 0x1 WORD The data size is set to 32 bits 0x2 DWORD The data size is set to 64 bits 0x3 INITD Channel Initialization Done (this bit is read-only) 21 1 read-write IN_PROGRESS Channel initialization is in progress. 0 TERMINATED Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 read-write SINGLE The memory burst size is set to one. 0x0 FOUR The memory burst size is set to four. 0x1 EIGHT The memory burst size is set to eight. 0x2 SIXTEEN The memory burst size is set to sixteen. 0x3 MEMSET Channel x Fill Block of Memory 7 1 read-write NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 read-write PROT Channel x Protection 5 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 RDIP Read in Progress (this bit is read-only) 22 1 read-write DONE No active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 SIF Channel x Source Interface Identifier 13 1 read-write AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 read-write MEM_TRAN Self-triggered mode (memory-to-memory transfer). 0 PER_TRAN Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 read-write DONE No active write transaction on the bus. 0 IN_PROGRESS A write transaction is in progress. 1 CDA0 Channel Destination Address Register (chid = 0) 0x64 32 read-write n 0x0 0x0 DA Channel x Destination Address 0 32 read-write CDA1 Channel Destination Address Register (chid = 1) 0xA4 32 read-write n 0x0 0x0 DA Channel x Destination Address 0 32 read-write CDA10 Channel Destination Address Register (chid = 10) 0x2E4 32 read-write n 0x0 0x0 DA Channel x Destination Address 0 32 read-write CDA11 Channel Destination Address Register (chid = 11) 0x324 32 read-write n 0x0 0x0 DA Channel x Destination Address 0 32 read-write CDA12 Channel Destination Address Register (chid = 12) 0x364 32 read-write n 0x0 0x0 DA Channel x Destination Address 0 32 read-write CDA13 Channel Destination Address Register (chid = 13) 0x3A4 32 read-write n 0x0 0x0 DA Channel x Destination Address 0 32 read-write CDA14 Channel Destination Address Register (chid = 14) 0x3E4 32 read-write n 0x0 0x0 DA Channel x Destination Address 0 32 read-write CDA15 Channel Destination Address Register (chid = 15) 0x424 32 read-write n 0x0 0x0 DA Channel x Destination Address 0 32 read-write CDA2 Channel Destination Address Register (chid = 2) 0xE4 32 read-write n 0x0 0x0 DA Channel x Destination Address 0 32 read-write CDA3 Channel Destination Address Register (chid = 3) 0x124 32 read-write n 0x0 0x0 DA Channel x Destination Address 0 32 read-write CDA4 Channel Destination Address Register (chid = 4) 0x164 32 read-write n 0x0 0x0 DA Channel x Destination Address 0 32 read-write CDA5 Channel Destination Address Register (chid = 5) 0x1A4 32 read-write n 0x0 0x0 DA Channel x Destination Address 0 32 read-write CDA6 Channel Destination Address Register (chid = 6) 0x1E4 32 read-write n 0x0 0x0 DA Channel x Destination Address 0 32 read-write CDA7 Channel Destination Address Register (chid = 7) 0x224 32 read-write n 0x0 0x0 DA Channel x Destination Address 0 32 read-write CDA8 Channel Destination Address Register (chid = 8) 0x264 32 read-write n 0x0 0x0 DA Channel x Destination Address 0 32 read-write CDA9 Channel Destination Address Register (chid = 9) 0x2A4 32 read-write n 0x0 0x0 DA Channel x Destination Address 0 32 read-write CDS_MSP0 Channel Data Stride Memory Set Pattern (chid = 0) 0x7C 32 read-write n 0x0 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 read-write SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 read-write CDS_MSP1 Channel Data Stride Memory Set Pattern (chid = 1) 0xBC 32 read-write n 0x0 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 read-write SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 read-write CDS_MSP10 Channel Data Stride Memory Set Pattern (chid = 10) 0x2FC 32 read-write n 0x0 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 read-write SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 read-write CDS_MSP11 Channel Data Stride Memory Set Pattern (chid = 11) 0x33C 32 read-write n 0x0 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 read-write SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 read-write CDS_MSP12 Channel Data Stride Memory Set Pattern (chid = 12) 0x37C 32 read-write n 0x0 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 read-write SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 read-write CDS_MSP13 Channel Data Stride Memory Set Pattern (chid = 13) 0x3BC 32 read-write n 0x0 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 read-write SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 read-write CDS_MSP14 Channel Data Stride Memory Set Pattern (chid = 14) 0x3FC 32 read-write n 0x0 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 read-write SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 read-write CDS_MSP15 Channel Data Stride Memory Set Pattern (chid = 15) 0x43C 32 read-write n 0x0 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 read-write SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 read-write CDS_MSP2 Channel Data Stride Memory Set Pattern (chid = 2) 0xFC 32 read-write n 0x0 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 read-write SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 read-write CDS_MSP3 Channel Data Stride Memory Set Pattern (chid = 3) 0x13C 32 read-write n 0x0 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 read-write SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 read-write CDS_MSP4 Channel Data Stride Memory Set Pattern (chid = 4) 0x17C 32 read-write n 0x0 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 read-write SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 read-write CDS_MSP5 Channel Data Stride Memory Set Pattern (chid = 5) 0x1BC 32 read-write n 0x0 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 read-write SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 read-write CDS_MSP6 Channel Data Stride Memory Set Pattern (chid = 6) 0x1FC 32 read-write n 0x0 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 read-write SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 read-write CDS_MSP7 Channel Data Stride Memory Set Pattern (chid = 7) 0x23C 32 read-write n 0x0 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 read-write SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 read-write CDS_MSP8 Channel Data Stride Memory Set Pattern (chid = 8) 0x27C 32 read-write n 0x0 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 read-write SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 read-write CDS_MSP9 Channel Data Stride Memory Set Pattern (chid = 9) 0x2BC 32 read-write n 0x0 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 read-write SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 read-write CDUS0 Channel Destination Microblock Stride (chid = 0) 0x84 32 read-write n 0x0 0x0 DUBS Channel x Destination Microblock Stride 0 24 read-write CDUS1 Channel Destination Microblock Stride (chid = 1) 0xC4 32 read-write n 0x0 0x0 DUBS Channel x Destination Microblock Stride 0 24 read-write CDUS10 Channel Destination Microblock Stride (chid = 10) 0x304 32 read-write n 0x0 0x0 DUBS Channel x Destination Microblock Stride 0 24 read-write CDUS11 Channel Destination Microblock Stride (chid = 11) 0x344 32 read-write n 0x0 0x0 DUBS Channel x Destination Microblock Stride 0 24 read-write CDUS12 Channel Destination Microblock Stride (chid = 12) 0x384 32 read-write n 0x0 0x0 DUBS Channel x Destination Microblock Stride 0 24 read-write CDUS13 Channel Destination Microblock Stride (chid = 13) 0x3C4 32 read-write n 0x0 0x0 DUBS Channel x Destination Microblock Stride 0 24 read-write CDUS14 Channel Destination Microblock Stride (chid = 14) 0x404 32 read-write n 0x0 0x0 DUBS Channel x Destination Microblock Stride 0 24 read-write CDUS15 Channel Destination Microblock Stride (chid = 15) 0x444 32 read-write n 0x0 0x0 DUBS Channel x Destination Microblock Stride 0 24 read-write CDUS2 Channel Destination Microblock Stride (chid = 2) 0x104 32 read-write n 0x0 0x0 DUBS Channel x Destination Microblock Stride 0 24 read-write CDUS3 Channel Destination Microblock Stride (chid = 3) 0x144 32 read-write n 0x0 0x0 DUBS Channel x Destination Microblock Stride 0 24 read-write CDUS4 Channel Destination Microblock Stride (chid = 4) 0x184 32 read-write n 0x0 0x0 DUBS Channel x Destination Microblock Stride 0 24 read-write CDUS5 Channel Destination Microblock Stride (chid = 5) 0x1C4 32 read-write n 0x0 0x0 DUBS Channel x Destination Microblock Stride 0 24 read-write CDUS6 Channel Destination Microblock Stride (chid = 6) 0x204 32 read-write n 0x0 0x0 DUBS Channel x Destination Microblock Stride 0 24 read-write CDUS7 Channel Destination Microblock Stride (chid = 7) 0x244 32 read-write n 0x0 0x0 DUBS Channel x Destination Microblock Stride 0 24 read-write CDUS8 Channel Destination Microblock Stride (chid = 8) 0x284 32 read-write n 0x0 0x0 DUBS Channel x Destination Microblock Stride 0 24 read-write CDUS9 Channel Destination Microblock Stride (chid = 9) 0x2C4 32 read-write n 0x0 0x0 DUBS Channel x Destination Microblock Stride 0 24 read-write CID0 Channel Interrupt Disable Register (chid = 0) 0x54 32 write-only n 0x0 0x0 BID End of Block Interrupt Disable Bit 0 1 write-only DID End of Disable Interrupt Disable Bit 2 1 write-only FID End of Flush Interrupt Disable Bit 3 1 write-only LID End of Linked List Interrupt Disable Bit 1 1 write-only RBEID Read Bus Error Interrupt Disable Bit 4 1 write-only ROID Request Overflow Error Interrupt Disable Bit 6 1 write-only WBEID Write Bus Error Interrupt Disable Bit 5 1 write-only CID1 Channel Interrupt Disable Register (chid = 1) 0x94 32 write-only n 0x0 0x0 BID End of Block Interrupt Disable Bit 0 1 write-only DID End of Disable Interrupt Disable Bit 2 1 write-only FID End of Flush Interrupt Disable Bit 3 1 write-only LID End of Linked List Interrupt Disable Bit 1 1 write-only RBEID Read Bus Error Interrupt Disable Bit 4 1 write-only ROID Request Overflow Error Interrupt Disable Bit 6 1 write-only WBEID Write Bus Error Interrupt Disable Bit 5 1 write-only CID10 Channel Interrupt Disable Register (chid = 10) 0x2D4 32 write-only n 0x0 0x0 BID End of Block Interrupt Disable Bit 0 1 write-only DID End of Disable Interrupt Disable Bit 2 1 write-only FID End of Flush Interrupt Disable Bit 3 1 write-only LID End of Linked List Interrupt Disable Bit 1 1 write-only RBEID Read Bus Error Interrupt Disable Bit 4 1 write-only ROID Request Overflow Error Interrupt Disable Bit 6 1 write-only WBEID Write Bus Error Interrupt Disable Bit 5 1 write-only CID11 Channel Interrupt Disable Register (chid = 11) 0x314 32 write-only n 0x0 0x0 BID End of Block Interrupt Disable Bit 0 1 write-only DID End of Disable Interrupt Disable Bit 2 1 write-only FID End of Flush Interrupt Disable Bit 3 1 write-only LID End of Linked List Interrupt Disable Bit 1 1 write-only RBEID Read Bus Error Interrupt Disable Bit 4 1 write-only ROID Request Overflow Error Interrupt Disable Bit 6 1 write-only WBEID Write Bus Error Interrupt Disable Bit 5 1 write-only CID12 Channel Interrupt Disable Register (chid = 12) 0x354 32 write-only n 0x0 0x0 BID End of Block Interrupt Disable Bit 0 1 write-only DID End of Disable Interrupt Disable Bit 2 1 write-only FID End of Flush Interrupt Disable Bit 3 1 write-only LID End of Linked List Interrupt Disable Bit 1 1 write-only RBEID Read Bus Error Interrupt Disable Bit 4 1 write-only ROID Request Overflow Error Interrupt Disable Bit 6 1 write-only WBEID Write Bus Error Interrupt Disable Bit 5 1 write-only CID13 Channel Interrupt Disable Register (chid = 13) 0x394 32 write-only n 0x0 0x0 BID End of Block Interrupt Disable Bit 0 1 write-only DID End of Disable Interrupt Disable Bit 2 1 write-only FID End of Flush Interrupt Disable Bit 3 1 write-only LID End of Linked List Interrupt Disable Bit 1 1 write-only RBEID Read Bus Error Interrupt Disable Bit 4 1 write-only ROID Request Overflow Error Interrupt Disable Bit 6 1 write-only WBEID Write Bus Error Interrupt Disable Bit 5 1 write-only CID14 Channel Interrupt Disable Register (chid = 14) 0x3D4 32 write-only n 0x0 0x0 BID End of Block Interrupt Disable Bit 0 1 write-only DID End of Disable Interrupt Disable Bit 2 1 write-only FID End of Flush Interrupt Disable Bit 3 1 write-only LID End of Linked List Interrupt Disable Bit 1 1 write-only RBEID Read Bus Error Interrupt Disable Bit 4 1 write-only ROID Request Overflow Error Interrupt Disable Bit 6 1 write-only WBEID Write Bus Error Interrupt Disable Bit 5 1 write-only CID15 Channel Interrupt Disable Register (chid = 15) 0x414 32 write-only n 0x0 0x0 BID End of Block Interrupt Disable Bit 0 1 write-only DID End of Disable Interrupt Disable Bit 2 1 write-only FID End of Flush Interrupt Disable Bit 3 1 write-only LID End of Linked List Interrupt Disable Bit 1 1 write-only RBEID Read Bus Error Interrupt Disable Bit 4 1 write-only ROID Request Overflow Error Interrupt Disable Bit 6 1 write-only WBEID Write Bus Error Interrupt Disable Bit 5 1 write-only CID2 Channel Interrupt Disable Register (chid = 2) 0xD4 32 write-only n 0x0 0x0 BID End of Block Interrupt Disable Bit 0 1 write-only DID End of Disable Interrupt Disable Bit 2 1 write-only FID End of Flush Interrupt Disable Bit 3 1 write-only LID End of Linked List Interrupt Disable Bit 1 1 write-only RBEID Read Bus Error Interrupt Disable Bit 4 1 write-only ROID Request Overflow Error Interrupt Disable Bit 6 1 write-only WBEID Write Bus Error Interrupt Disable Bit 5 1 write-only CID3 Channel Interrupt Disable Register (chid = 3) 0x114 32 write-only n 0x0 0x0 BID End of Block Interrupt Disable Bit 0 1 write-only DID End of Disable Interrupt Disable Bit 2 1 write-only FID End of Flush Interrupt Disable Bit 3 1 write-only LID End of Linked List Interrupt Disable Bit 1 1 write-only RBEID Read Bus Error Interrupt Disable Bit 4 1 write-only ROID Request Overflow Error Interrupt Disable Bit 6 1 write-only WBEID Write Bus Error Interrupt Disable Bit 5 1 write-only CID4 Channel Interrupt Disable Register (chid = 4) 0x154 32 write-only n 0x0 0x0 BID End of Block Interrupt Disable Bit 0 1 write-only DID End of Disable Interrupt Disable Bit 2 1 write-only FID End of Flush Interrupt Disable Bit 3 1 write-only LID End of Linked List Interrupt Disable Bit 1 1 write-only RBEID Read Bus Error Interrupt Disable Bit 4 1 write-only ROID Request Overflow Error Interrupt Disable Bit 6 1 write-only WBEID Write Bus Error Interrupt Disable Bit 5 1 write-only CID5 Channel Interrupt Disable Register (chid = 5) 0x194 32 write-only n 0x0 0x0 BID End of Block Interrupt Disable Bit 0 1 write-only DID End of Disable Interrupt Disable Bit 2 1 write-only FID End of Flush Interrupt Disable Bit 3 1 write-only LID End of Linked List Interrupt Disable Bit 1 1 write-only RBEID Read Bus Error Interrupt Disable Bit 4 1 write-only ROID Request Overflow Error Interrupt Disable Bit 6 1 write-only WBEID Write Bus Error Interrupt Disable Bit 5 1 write-only CID6 Channel Interrupt Disable Register (chid = 6) 0x1D4 32 write-only n 0x0 0x0 BID End of Block Interrupt Disable Bit 0 1 write-only DID End of Disable Interrupt Disable Bit 2 1 write-only FID End of Flush Interrupt Disable Bit 3 1 write-only LID End of Linked List Interrupt Disable Bit 1 1 write-only RBEID Read Bus Error Interrupt Disable Bit 4 1 write-only ROID Request Overflow Error Interrupt Disable Bit 6 1 write-only WBEID Write Bus Error Interrupt Disable Bit 5 1 write-only CID7 Channel Interrupt Disable Register (chid = 7) 0x214 32 write-only n 0x0 0x0 BID End of Block Interrupt Disable Bit 0 1 write-only DID End of Disable Interrupt Disable Bit 2 1 write-only FID End of Flush Interrupt Disable Bit 3 1 write-only LID End of Linked List Interrupt Disable Bit 1 1 write-only RBEID Read Bus Error Interrupt Disable Bit 4 1 write-only ROID Request Overflow Error Interrupt Disable Bit 6 1 write-only WBEID Write Bus Error Interrupt Disable Bit 5 1 write-only CID8 Channel Interrupt Disable Register (chid = 8) 0x254 32 write-only n 0x0 0x0 BID End of Block Interrupt Disable Bit 0 1 write-only DID End of Disable Interrupt Disable Bit 2 1 write-only FID End of Flush Interrupt Disable Bit 3 1 write-only LID End of Linked List Interrupt Disable Bit 1 1 write-only RBEID Read Bus Error Interrupt Disable Bit 4 1 write-only ROID Request Overflow Error Interrupt Disable Bit 6 1 write-only WBEID Write Bus Error Interrupt Disable Bit 5 1 write-only CID9 Channel Interrupt Disable Register (chid = 9) 0x294 32 write-only n 0x0 0x0 BID End of Block Interrupt Disable Bit 0 1 write-only DID End of Disable Interrupt Disable Bit 2 1 write-only FID End of Flush Interrupt Disable Bit 3 1 write-only LID End of Linked List Interrupt Disable Bit 1 1 write-only RBEID Read Bus Error Interrupt Disable Bit 4 1 write-only ROID Request Overflow Error Interrupt Disable Bit 6 1 write-only WBEID Write Bus Error Interrupt Disable Bit 5 1 write-only CIE0 Channel Interrupt Enable Register (chid = 0) 0x50 32 write-only n 0x0 0x0 BIE End of Block Interrupt Enable Bit 0 1 write-only DIE End of Disable Interrupt Enable Bit 2 1 write-only FIE End of Flush Interrupt Enable Bit 3 1 write-only LIE End of Linked List Interrupt Enable Bit 1 1 write-only RBIE Read Bus Error Interrupt Enable Bit 4 1 write-only ROIE Request Overflow Error Interrupt Enable Bit 6 1 write-only WBIE Write Bus Error Interrupt Enable Bit 5 1 write-only CIE1 Channel Interrupt Enable Register (chid = 1) 0x90 32 write-only n 0x0 0x0 BIE End of Block Interrupt Enable Bit 0 1 write-only DIE End of Disable Interrupt Enable Bit 2 1 write-only FIE End of Flush Interrupt Enable Bit 3 1 write-only LIE End of Linked List Interrupt Enable Bit 1 1 write-only RBIE Read Bus Error Interrupt Enable Bit 4 1 write-only ROIE Request Overflow Error Interrupt Enable Bit 6 1 write-only WBIE Write Bus Error Interrupt Enable Bit 5 1 write-only CIE10 Channel Interrupt Enable Register (chid = 10) 0x2D0 32 write-only n 0x0 0x0 BIE End of Block Interrupt Enable Bit 0 1 write-only DIE End of Disable Interrupt Enable Bit 2 1 write-only FIE End of Flush Interrupt Enable Bit 3 1 write-only LIE End of Linked List Interrupt Enable Bit 1 1 write-only RBIE Read Bus Error Interrupt Enable Bit 4 1 write-only ROIE Request Overflow Error Interrupt Enable Bit 6 1 write-only WBIE Write Bus Error Interrupt Enable Bit 5 1 write-only CIE11 Channel Interrupt Enable Register (chid = 11) 0x310 32 write-only n 0x0 0x0 BIE End of Block Interrupt Enable Bit 0 1 write-only DIE End of Disable Interrupt Enable Bit 2 1 write-only FIE End of Flush Interrupt Enable Bit 3 1 write-only LIE End of Linked List Interrupt Enable Bit 1 1 write-only RBIE Read Bus Error Interrupt Enable Bit 4 1 write-only ROIE Request Overflow Error Interrupt Enable Bit 6 1 write-only WBIE Write Bus Error Interrupt Enable Bit 5 1 write-only CIE12 Channel Interrupt Enable Register (chid = 12) 0x350 32 write-only n 0x0 0x0 BIE End of Block Interrupt Enable Bit 0 1 write-only DIE End of Disable Interrupt Enable Bit 2 1 write-only FIE End of Flush Interrupt Enable Bit 3 1 write-only LIE End of Linked List Interrupt Enable Bit 1 1 write-only RBIE Read Bus Error Interrupt Enable Bit 4 1 write-only ROIE Request Overflow Error Interrupt Enable Bit 6 1 write-only WBIE Write Bus Error Interrupt Enable Bit 5 1 write-only CIE13 Channel Interrupt Enable Register (chid = 13) 0x390 32 write-only n 0x0 0x0 BIE End of Block Interrupt Enable Bit 0 1 write-only DIE End of Disable Interrupt Enable Bit 2 1 write-only FIE End of Flush Interrupt Enable Bit 3 1 write-only LIE End of Linked List Interrupt Enable Bit 1 1 write-only RBIE Read Bus Error Interrupt Enable Bit 4 1 write-only ROIE Request Overflow Error Interrupt Enable Bit 6 1 write-only WBIE Write Bus Error Interrupt Enable Bit 5 1 write-only CIE14 Channel Interrupt Enable Register (chid = 14) 0x3D0 32 write-only n 0x0 0x0 BIE End of Block Interrupt Enable Bit 0 1 write-only DIE End of Disable Interrupt Enable Bit 2 1 write-only FIE End of Flush Interrupt Enable Bit 3 1 write-only LIE End of Linked List Interrupt Enable Bit 1 1 write-only RBIE Read Bus Error Interrupt Enable Bit 4 1 write-only ROIE Request Overflow Error Interrupt Enable Bit 6 1 write-only WBIE Write Bus Error Interrupt Enable Bit 5 1 write-only CIE15 Channel Interrupt Enable Register (chid = 15) 0x410 32 write-only n 0x0 0x0 BIE End of Block Interrupt Enable Bit 0 1 write-only DIE End of Disable Interrupt Enable Bit 2 1 write-only FIE End of Flush Interrupt Enable Bit 3 1 write-only LIE End of Linked List Interrupt Enable Bit 1 1 write-only RBIE Read Bus Error Interrupt Enable Bit 4 1 write-only ROIE Request Overflow Error Interrupt Enable Bit 6 1 write-only WBIE Write Bus Error Interrupt Enable Bit 5 1 write-only CIE2 Channel Interrupt Enable Register (chid = 2) 0xD0 32 write-only n 0x0 0x0 BIE End of Block Interrupt Enable Bit 0 1 write-only DIE End of Disable Interrupt Enable Bit 2 1 write-only FIE End of Flush Interrupt Enable Bit 3 1 write-only LIE End of Linked List Interrupt Enable Bit 1 1 write-only RBIE Read Bus Error Interrupt Enable Bit 4 1 write-only ROIE Request Overflow Error Interrupt Enable Bit 6 1 write-only WBIE Write Bus Error Interrupt Enable Bit 5 1 write-only CIE3 Channel Interrupt Enable Register (chid = 3) 0x110 32 write-only n 0x0 0x0 BIE End of Block Interrupt Enable Bit 0 1 write-only DIE End of Disable Interrupt Enable Bit 2 1 write-only FIE End of Flush Interrupt Enable Bit 3 1 write-only LIE End of Linked List Interrupt Enable Bit 1 1 write-only RBIE Read Bus Error Interrupt Enable Bit 4 1 write-only ROIE Request Overflow Error Interrupt Enable Bit 6 1 write-only WBIE Write Bus Error Interrupt Enable Bit 5 1 write-only CIE4 Channel Interrupt Enable Register (chid = 4) 0x150 32 write-only n 0x0 0x0 BIE End of Block Interrupt Enable Bit 0 1 write-only DIE End of Disable Interrupt Enable Bit 2 1 write-only FIE End of Flush Interrupt Enable Bit 3 1 write-only LIE End of Linked List Interrupt Enable Bit 1 1 write-only RBIE Read Bus Error Interrupt Enable Bit 4 1 write-only ROIE Request Overflow Error Interrupt Enable Bit 6 1 write-only WBIE Write Bus Error Interrupt Enable Bit 5 1 write-only CIE5 Channel Interrupt Enable Register (chid = 5) 0x190 32 write-only n 0x0 0x0 BIE End of Block Interrupt Enable Bit 0 1 write-only DIE End of Disable Interrupt Enable Bit 2 1 write-only FIE End of Flush Interrupt Enable Bit 3 1 write-only LIE End of Linked List Interrupt Enable Bit 1 1 write-only RBIE Read Bus Error Interrupt Enable Bit 4 1 write-only ROIE Request Overflow Error Interrupt Enable Bit 6 1 write-only WBIE Write Bus Error Interrupt Enable Bit 5 1 write-only CIE6 Channel Interrupt Enable Register (chid = 6) 0x1D0 32 write-only n 0x0 0x0 BIE End of Block Interrupt Enable Bit 0 1 write-only DIE End of Disable Interrupt Enable Bit 2 1 write-only FIE End of Flush Interrupt Enable Bit 3 1 write-only LIE End of Linked List Interrupt Enable Bit 1 1 write-only RBIE Read Bus Error Interrupt Enable Bit 4 1 write-only ROIE Request Overflow Error Interrupt Enable Bit 6 1 write-only WBIE Write Bus Error Interrupt Enable Bit 5 1 write-only CIE7 Channel Interrupt Enable Register (chid = 7) 0x210 32 write-only n 0x0 0x0 BIE End of Block Interrupt Enable Bit 0 1 write-only DIE End of Disable Interrupt Enable Bit 2 1 write-only FIE End of Flush Interrupt Enable Bit 3 1 write-only LIE End of Linked List Interrupt Enable Bit 1 1 write-only RBIE Read Bus Error Interrupt Enable Bit 4 1 write-only ROIE Request Overflow Error Interrupt Enable Bit 6 1 write-only WBIE Write Bus Error Interrupt Enable Bit 5 1 write-only CIE8 Channel Interrupt Enable Register (chid = 8) 0x250 32 write-only n 0x0 0x0 BIE End of Block Interrupt Enable Bit 0 1 write-only DIE End of Disable Interrupt Enable Bit 2 1 write-only FIE End of Flush Interrupt Enable Bit 3 1 write-only LIE End of Linked List Interrupt Enable Bit 1 1 write-only RBIE Read Bus Error Interrupt Enable Bit 4 1 write-only ROIE Request Overflow Error Interrupt Enable Bit 6 1 write-only WBIE Write Bus Error Interrupt Enable Bit 5 1 write-only CIE9 Channel Interrupt Enable Register (chid = 9) 0x290 32 write-only n 0x0 0x0 BIE End of Block Interrupt Enable Bit 0 1 write-only DIE End of Disable Interrupt Enable Bit 2 1 write-only FIE End of Flush Interrupt Enable Bit 3 1 write-only LIE End of Linked List Interrupt Enable Bit 1 1 write-only RBIE Read Bus Error Interrupt Enable Bit 4 1 write-only ROIE Request Overflow Error Interrupt Enable Bit 6 1 write-only WBIE Write Bus Error Interrupt Enable Bit 5 1 write-only CIM0 Channel Interrupt Mask Register (chid = 0) 0x58 32 read-only n 0x0 0x0 BIM End of Block Interrupt Mask Bit 0 1 read-only DIM End of Disable Interrupt Mask Bit 2 1 read-only FIM End of Flush Interrupt Mask Bit 3 1 read-only LIM End of Linked List Interrupt Mask Bit 1 1 read-only RBEIM Read Bus Error Interrupt Mask Bit 4 1 read-only ROIM Request Overflow Error Interrupt Mask Bit 6 1 read-only WBEIM Write Bus Error Interrupt Mask Bit 5 1 read-only CIM1 Channel Interrupt Mask Register (chid = 1) 0x98 32 read-only n 0x0 0x0 BIM End of Block Interrupt Mask Bit 0 1 read-only DIM End of Disable Interrupt Mask Bit 2 1 read-only FIM End of Flush Interrupt Mask Bit 3 1 read-only LIM End of Linked List Interrupt Mask Bit 1 1 read-only RBEIM Read Bus Error Interrupt Mask Bit 4 1 read-only ROIM Request Overflow Error Interrupt Mask Bit 6 1 read-only WBEIM Write Bus Error Interrupt Mask Bit 5 1 read-only CIM10 Channel Interrupt Mask Register (chid = 10) 0x2D8 32 read-only n 0x0 0x0 BIM End of Block Interrupt Mask Bit 0 1 read-only DIM End of Disable Interrupt Mask Bit 2 1 read-only FIM End of Flush Interrupt Mask Bit 3 1 read-only LIM End of Linked List Interrupt Mask Bit 1 1 read-only RBEIM Read Bus Error Interrupt Mask Bit 4 1 read-only ROIM Request Overflow Error Interrupt Mask Bit 6 1 read-only WBEIM Write Bus Error Interrupt Mask Bit 5 1 read-only CIM11 Channel Interrupt Mask Register (chid = 11) 0x318 32 read-only n 0x0 0x0 BIM End of Block Interrupt Mask Bit 0 1 read-only DIM End of Disable Interrupt Mask Bit 2 1 read-only FIM End of Flush Interrupt Mask Bit 3 1 read-only LIM End of Linked List Interrupt Mask Bit 1 1 read-only RBEIM Read Bus Error Interrupt Mask Bit 4 1 read-only ROIM Request Overflow Error Interrupt Mask Bit 6 1 read-only WBEIM Write Bus Error Interrupt Mask Bit 5 1 read-only CIM12 Channel Interrupt Mask Register (chid = 12) 0x358 32 read-only n 0x0 0x0 BIM End of Block Interrupt Mask Bit 0 1 read-only DIM End of Disable Interrupt Mask Bit 2 1 read-only FIM End of Flush Interrupt Mask Bit 3 1 read-only LIM End of Linked List Interrupt Mask Bit 1 1 read-only RBEIM Read Bus Error Interrupt Mask Bit 4 1 read-only ROIM Request Overflow Error Interrupt Mask Bit 6 1 read-only WBEIM Write Bus Error Interrupt Mask Bit 5 1 read-only CIM13 Channel Interrupt Mask Register (chid = 13) 0x398 32 read-only n 0x0 0x0 BIM End of Block Interrupt Mask Bit 0 1 read-only DIM End of Disable Interrupt Mask Bit 2 1 read-only FIM End of Flush Interrupt Mask Bit 3 1 read-only LIM End of Linked List Interrupt Mask Bit 1 1 read-only RBEIM Read Bus Error Interrupt Mask Bit 4 1 read-only ROIM Request Overflow Error Interrupt Mask Bit 6 1 read-only WBEIM Write Bus Error Interrupt Mask Bit 5 1 read-only CIM14 Channel Interrupt Mask Register (chid = 14) 0x3D8 32 read-only n 0x0 0x0 BIM End of Block Interrupt Mask Bit 0 1 read-only DIM End of Disable Interrupt Mask Bit 2 1 read-only FIM End of Flush Interrupt Mask Bit 3 1 read-only LIM End of Linked List Interrupt Mask Bit 1 1 read-only RBEIM Read Bus Error Interrupt Mask Bit 4 1 read-only ROIM Request Overflow Error Interrupt Mask Bit 6 1 read-only WBEIM Write Bus Error Interrupt Mask Bit 5 1 read-only CIM15 Channel Interrupt Mask Register (chid = 15) 0x418 32 read-only n 0x0 0x0 BIM End of Block Interrupt Mask Bit 0 1 read-only DIM End of Disable Interrupt Mask Bit 2 1 read-only FIM End of Flush Interrupt Mask Bit 3 1 read-only LIM End of Linked List Interrupt Mask Bit 1 1 read-only RBEIM Read Bus Error Interrupt Mask Bit 4 1 read-only ROIM Request Overflow Error Interrupt Mask Bit 6 1 read-only WBEIM Write Bus Error Interrupt Mask Bit 5 1 read-only CIM2 Channel Interrupt Mask Register (chid = 2) 0xD8 32 read-only n 0x0 0x0 BIM End of Block Interrupt Mask Bit 0 1 read-only DIM End of Disable Interrupt Mask Bit 2 1 read-only FIM End of Flush Interrupt Mask Bit 3 1 read-only LIM End of Linked List Interrupt Mask Bit 1 1 read-only RBEIM Read Bus Error Interrupt Mask Bit 4 1 read-only ROIM Request Overflow Error Interrupt Mask Bit 6 1 read-only WBEIM Write Bus Error Interrupt Mask Bit 5 1 read-only CIM3 Channel Interrupt Mask Register (chid = 3) 0x118 32 read-only n 0x0 0x0 BIM End of Block Interrupt Mask Bit 0 1 read-only DIM End of Disable Interrupt Mask Bit 2 1 read-only FIM End of Flush Interrupt Mask Bit 3 1 read-only LIM End of Linked List Interrupt Mask Bit 1 1 read-only RBEIM Read Bus Error Interrupt Mask Bit 4 1 read-only ROIM Request Overflow Error Interrupt Mask Bit 6 1 read-only WBEIM Write Bus Error Interrupt Mask Bit 5 1 read-only CIM4 Channel Interrupt Mask Register (chid = 4) 0x158 32 read-only n 0x0 0x0 BIM End of Block Interrupt Mask Bit 0 1 read-only DIM End of Disable Interrupt Mask Bit 2 1 read-only FIM End of Flush Interrupt Mask Bit 3 1 read-only LIM End of Linked List Interrupt Mask Bit 1 1 read-only RBEIM Read Bus Error Interrupt Mask Bit 4 1 read-only ROIM Request Overflow Error Interrupt Mask Bit 6 1 read-only WBEIM Write Bus Error Interrupt Mask Bit 5 1 read-only CIM5 Channel Interrupt Mask Register (chid = 5) 0x198 32 read-only n 0x0 0x0 BIM End of Block Interrupt Mask Bit 0 1 read-only DIM End of Disable Interrupt Mask Bit 2 1 read-only FIM End of Flush Interrupt Mask Bit 3 1 read-only LIM End of Linked List Interrupt Mask Bit 1 1 read-only RBEIM Read Bus Error Interrupt Mask Bit 4 1 read-only ROIM Request Overflow Error Interrupt Mask Bit 6 1 read-only WBEIM Write Bus Error Interrupt Mask Bit 5 1 read-only CIM6 Channel Interrupt Mask Register (chid = 6) 0x1D8 32 read-only n 0x0 0x0 BIM End of Block Interrupt Mask Bit 0 1 read-only DIM End of Disable Interrupt Mask Bit 2 1 read-only FIM End of Flush Interrupt Mask Bit 3 1 read-only LIM End of Linked List Interrupt Mask Bit 1 1 read-only RBEIM Read Bus Error Interrupt Mask Bit 4 1 read-only ROIM Request Overflow Error Interrupt Mask Bit 6 1 read-only WBEIM Write Bus Error Interrupt Mask Bit 5 1 read-only CIM7 Channel Interrupt Mask Register (chid = 7) 0x218 32 read-only n 0x0 0x0 BIM End of Block Interrupt Mask Bit 0 1 read-only DIM End of Disable Interrupt Mask Bit 2 1 read-only FIM End of Flush Interrupt Mask Bit 3 1 read-only LIM End of Linked List Interrupt Mask Bit 1 1 read-only RBEIM Read Bus Error Interrupt Mask Bit 4 1 read-only ROIM Request Overflow Error Interrupt Mask Bit 6 1 read-only WBEIM Write Bus Error Interrupt Mask Bit 5 1 read-only CIM8 Channel Interrupt Mask Register (chid = 8) 0x258 32 read-only n 0x0 0x0 BIM End of Block Interrupt Mask Bit 0 1 read-only DIM End of Disable Interrupt Mask Bit 2 1 read-only FIM End of Flush Interrupt Mask Bit 3 1 read-only LIM End of Linked List Interrupt Mask Bit 1 1 read-only RBEIM Read Bus Error Interrupt Mask Bit 4 1 read-only ROIM Request Overflow Error Interrupt Mask Bit 6 1 read-only WBEIM Write Bus Error Interrupt Mask Bit 5 1 read-only CIM9 Channel Interrupt Mask Register (chid = 9) 0x298 32 read-only n 0x0 0x0 BIM End of Block Interrupt Mask Bit 0 1 read-only DIM End of Disable Interrupt Mask Bit 2 1 read-only FIM End of Flush Interrupt Mask Bit 3 1 read-only LIM End of Linked List Interrupt Mask Bit 1 1 read-only RBEIM Read Bus Error Interrupt Mask Bit 4 1 read-only ROIM Request Overflow Error Interrupt Mask Bit 6 1 read-only WBEIM Write Bus Error Interrupt Mask Bit 5 1 read-only CIS0 Channel Interrupt Status Register (chid = 0) 0x5C 32 read-only n 0x0 0x0 BIS End of Block Interrupt Status Bit 0 1 read-only DIS End of Disable Interrupt Status Bit 2 1 read-only FIS End of Flush Interrupt Status Bit 3 1 read-only LIS End of Linked List Interrupt Status Bit 1 1 read-only RBEIS Read Bus Error Interrupt Status Bit 4 1 read-only ROIS Request Overflow Error Interrupt Status Bit 6 1 read-only WBEIS Write Bus Error Interrupt Status Bit 5 1 read-only CIS1 Channel Interrupt Status Register (chid = 1) 0x9C 32 read-only n 0x0 0x0 BIS End of Block Interrupt Status Bit 0 1 read-only DIS End of Disable Interrupt Status Bit 2 1 read-only FIS End of Flush Interrupt Status Bit 3 1 read-only LIS End of Linked List Interrupt Status Bit 1 1 read-only RBEIS Read Bus Error Interrupt Status Bit 4 1 read-only ROIS Request Overflow Error Interrupt Status Bit 6 1 read-only WBEIS Write Bus Error Interrupt Status Bit 5 1 read-only CIS10 Channel Interrupt Status Register (chid = 10) 0x2DC 32 read-only n 0x0 0x0 BIS End of Block Interrupt Status Bit 0 1 read-only DIS End of Disable Interrupt Status Bit 2 1 read-only FIS End of Flush Interrupt Status Bit 3 1 read-only LIS End of Linked List Interrupt Status Bit 1 1 read-only RBEIS Read Bus Error Interrupt Status Bit 4 1 read-only ROIS Request Overflow Error Interrupt Status Bit 6 1 read-only WBEIS Write Bus Error Interrupt Status Bit 5 1 read-only CIS11 Channel Interrupt Status Register (chid = 11) 0x31C 32 read-only n 0x0 0x0 BIS End of Block Interrupt Status Bit 0 1 read-only DIS End of Disable Interrupt Status Bit 2 1 read-only FIS End of Flush Interrupt Status Bit 3 1 read-only LIS End of Linked List Interrupt Status Bit 1 1 read-only RBEIS Read Bus Error Interrupt Status Bit 4 1 read-only ROIS Request Overflow Error Interrupt Status Bit 6 1 read-only WBEIS Write Bus Error Interrupt Status Bit 5 1 read-only CIS12 Channel Interrupt Status Register (chid = 12) 0x35C 32 read-only n 0x0 0x0 BIS End of Block Interrupt Status Bit 0 1 read-only DIS End of Disable Interrupt Status Bit 2 1 read-only FIS End of Flush Interrupt Status Bit 3 1 read-only LIS End of Linked List Interrupt Status Bit 1 1 read-only RBEIS Read Bus Error Interrupt Status Bit 4 1 read-only ROIS Request Overflow Error Interrupt Status Bit 6 1 read-only WBEIS Write Bus Error Interrupt Status Bit 5 1 read-only CIS13 Channel Interrupt Status Register (chid = 13) 0x39C 32 read-only n 0x0 0x0 BIS End of Block Interrupt Status Bit 0 1 read-only DIS End of Disable Interrupt Status Bit 2 1 read-only FIS End of Flush Interrupt Status Bit 3 1 read-only LIS End of Linked List Interrupt Status Bit 1 1 read-only RBEIS Read Bus Error Interrupt Status Bit 4 1 read-only ROIS Request Overflow Error Interrupt Status Bit 6 1 read-only WBEIS Write Bus Error Interrupt Status Bit 5 1 read-only CIS14 Channel Interrupt Status Register (chid = 14) 0x3DC 32 read-only n 0x0 0x0 BIS End of Block Interrupt Status Bit 0 1 read-only DIS End of Disable Interrupt Status Bit 2 1 read-only FIS End of Flush Interrupt Status Bit 3 1 read-only LIS End of Linked List Interrupt Status Bit 1 1 read-only RBEIS Read Bus Error Interrupt Status Bit 4 1 read-only ROIS Request Overflow Error Interrupt Status Bit 6 1 read-only WBEIS Write Bus Error Interrupt Status Bit 5 1 read-only CIS15 Channel Interrupt Status Register (chid = 15) 0x41C 32 read-only n 0x0 0x0 BIS End of Block Interrupt Status Bit 0 1 read-only DIS End of Disable Interrupt Status Bit 2 1 read-only FIS End of Flush Interrupt Status Bit 3 1 read-only LIS End of Linked List Interrupt Status Bit 1 1 read-only RBEIS Read Bus Error Interrupt Status Bit 4 1 read-only ROIS Request Overflow Error Interrupt Status Bit 6 1 read-only WBEIS Write Bus Error Interrupt Status Bit 5 1 read-only CIS2 Channel Interrupt Status Register (chid = 2) 0xDC 32 read-only n 0x0 0x0 BIS End of Block Interrupt Status Bit 0 1 read-only DIS End of Disable Interrupt Status Bit 2 1 read-only FIS End of Flush Interrupt Status Bit 3 1 read-only LIS End of Linked List Interrupt Status Bit 1 1 read-only RBEIS Read Bus Error Interrupt Status Bit 4 1 read-only ROIS Request Overflow Error Interrupt Status Bit 6 1 read-only WBEIS Write Bus Error Interrupt Status Bit 5 1 read-only CIS3 Channel Interrupt Status Register (chid = 3) 0x11C 32 read-only n 0x0 0x0 BIS End of Block Interrupt Status Bit 0 1 read-only DIS End of Disable Interrupt Status Bit 2 1 read-only FIS End of Flush Interrupt Status Bit 3 1 read-only LIS End of Linked List Interrupt Status Bit 1 1 read-only RBEIS Read Bus Error Interrupt Status Bit 4 1 read-only ROIS Request Overflow Error Interrupt Status Bit 6 1 read-only WBEIS Write Bus Error Interrupt Status Bit 5 1 read-only CIS4 Channel Interrupt Status Register (chid = 4) 0x15C 32 read-only n 0x0 0x0 BIS End of Block Interrupt Status Bit 0 1 read-only DIS End of Disable Interrupt Status Bit 2 1 read-only FIS End of Flush Interrupt Status Bit 3 1 read-only LIS End of Linked List Interrupt Status Bit 1 1 read-only RBEIS Read Bus Error Interrupt Status Bit 4 1 read-only ROIS Request Overflow Error Interrupt Status Bit 6 1 read-only WBEIS Write Bus Error Interrupt Status Bit 5 1 read-only CIS5 Channel Interrupt Status Register (chid = 5) 0x19C 32 read-only n 0x0 0x0 BIS End of Block Interrupt Status Bit 0 1 read-only DIS End of Disable Interrupt Status Bit 2 1 read-only FIS End of Flush Interrupt Status Bit 3 1 read-only LIS End of Linked List Interrupt Status Bit 1 1 read-only RBEIS Read Bus Error Interrupt Status Bit 4 1 read-only ROIS Request Overflow Error Interrupt Status Bit 6 1 read-only WBEIS Write Bus Error Interrupt Status Bit 5 1 read-only CIS6 Channel Interrupt Status Register (chid = 6) 0x1DC 32 read-only n 0x0 0x0 BIS End of Block Interrupt Status Bit 0 1 read-only DIS End of Disable Interrupt Status Bit 2 1 read-only FIS End of Flush Interrupt Status Bit 3 1 read-only LIS End of Linked List Interrupt Status Bit 1 1 read-only RBEIS Read Bus Error Interrupt Status Bit 4 1 read-only ROIS Request Overflow Error Interrupt Status Bit 6 1 read-only WBEIS Write Bus Error Interrupt Status Bit 5 1 read-only CIS7 Channel Interrupt Status Register (chid = 7) 0x21C 32 read-only n 0x0 0x0 BIS End of Block Interrupt Status Bit 0 1 read-only DIS End of Disable Interrupt Status Bit 2 1 read-only FIS End of Flush Interrupt Status Bit 3 1 read-only LIS End of Linked List Interrupt Status Bit 1 1 read-only RBEIS Read Bus Error Interrupt Status Bit 4 1 read-only ROIS Request Overflow Error Interrupt Status Bit 6 1 read-only WBEIS Write Bus Error Interrupt Status Bit 5 1 read-only CIS8 Channel Interrupt Status Register (chid = 8) 0x25C 32 read-only n 0x0 0x0 BIS End of Block Interrupt Status Bit 0 1 read-only DIS End of Disable Interrupt Status Bit 2 1 read-only FIS End of Flush Interrupt Status Bit 3 1 read-only LIS End of Linked List Interrupt Status Bit 1 1 read-only RBEIS Read Bus Error Interrupt Status Bit 4 1 read-only ROIS Request Overflow Error Interrupt Status Bit 6 1 read-only WBEIS Write Bus Error Interrupt Status Bit 5 1 read-only CIS9 Channel Interrupt Status Register (chid = 9) 0x29C 32 read-only n 0x0 0x0 BIS End of Block Interrupt Status Bit 0 1 read-only DIS End of Disable Interrupt Status Bit 2 1 read-only FIS End of Flush Interrupt Status Bit 3 1 read-only LIS End of Linked List Interrupt Status Bit 1 1 read-only RBEIS Read Bus Error Interrupt Status Bit 4 1 read-only ROIS Request Overflow Error Interrupt Status Bit 6 1 read-only WBEIS Write Bus Error Interrupt Status Bit 5 1 read-only CNDA0 Channel Next Descriptor Address Register (chid = 0) 0x68 32 read-write n 0x0 0x0 NDA Channel x Next Descriptor Address 2 30 read-write NDAIF Channel x Next Descriptor Interface 0 1 read-write CNDA1 Channel Next Descriptor Address Register (chid = 1) 0xA8 32 read-write n 0x0 0x0 NDA Channel x Next Descriptor Address 2 30 read-write NDAIF Channel x Next Descriptor Interface 0 1 read-write CNDA10 Channel Next Descriptor Address Register (chid = 10) 0x2E8 32 read-write n 0x0 0x0 NDA Channel x Next Descriptor Address 2 30 read-write NDAIF Channel x Next Descriptor Interface 0 1 read-write CNDA11 Channel Next Descriptor Address Register (chid = 11) 0x328 32 read-write n 0x0 0x0 NDA Channel x Next Descriptor Address 2 30 read-write NDAIF Channel x Next Descriptor Interface 0 1 read-write CNDA12 Channel Next Descriptor Address Register (chid = 12) 0x368 32 read-write n 0x0 0x0 NDA Channel x Next Descriptor Address 2 30 read-write NDAIF Channel x Next Descriptor Interface 0 1 read-write CNDA13 Channel Next Descriptor Address Register (chid = 13) 0x3A8 32 read-write n 0x0 0x0 NDA Channel x Next Descriptor Address 2 30 read-write NDAIF Channel x Next Descriptor Interface 0 1 read-write CNDA14 Channel Next Descriptor Address Register (chid = 14) 0x3E8 32 read-write n 0x0 0x0 NDA Channel x Next Descriptor Address 2 30 read-write NDAIF Channel x Next Descriptor Interface 0 1 read-write CNDA15 Channel Next Descriptor Address Register (chid = 15) 0x428 32 read-write n 0x0 0x0 NDA Channel x Next Descriptor Address 2 30 read-write NDAIF Channel x Next Descriptor Interface 0 1 read-write CNDA2 Channel Next Descriptor Address Register (chid = 2) 0xE8 32 read-write n 0x0 0x0 NDA Channel x Next Descriptor Address 2 30 read-write NDAIF Channel x Next Descriptor Interface 0 1 read-write CNDA3 Channel Next Descriptor Address Register (chid = 3) 0x128 32 read-write n 0x0 0x0 NDA Channel x Next Descriptor Address 2 30 read-write NDAIF Channel x Next Descriptor Interface 0 1 read-write CNDA4 Channel Next Descriptor Address Register (chid = 4) 0x168 32 read-write n 0x0 0x0 NDA Channel x Next Descriptor Address 2 30 read-write NDAIF Channel x Next Descriptor Interface 0 1 read-write CNDA5 Channel Next Descriptor Address Register (chid = 5) 0x1A8 32 read-write n 0x0 0x0 NDA Channel x Next Descriptor Address 2 30 read-write NDAIF Channel x Next Descriptor Interface 0 1 read-write CNDA6 Channel Next Descriptor Address Register (chid = 6) 0x1E8 32 read-write n 0x0 0x0 NDA Channel x Next Descriptor Address 2 30 read-write NDAIF Channel x Next Descriptor Interface 0 1 read-write CNDA7 Channel Next Descriptor Address Register (chid = 7) 0x228 32 read-write n 0x0 0x0 NDA Channel x Next Descriptor Address 2 30 read-write NDAIF Channel x Next Descriptor Interface 0 1 read-write CNDA8 Channel Next Descriptor Address Register (chid = 8) 0x268 32 read-write n 0x0 0x0 NDA Channel x Next Descriptor Address 2 30 read-write NDAIF Channel x Next Descriptor Interface 0 1 read-write CNDA9 Channel Next Descriptor Address Register (chid = 9) 0x2A8 32 read-write n 0x0 0x0 NDA Channel x Next Descriptor Address 2 30 read-write NDAIF Channel x Next Descriptor Interface 0 1 read-write CNDC0 Channel Next Descriptor Control Register (chid = 0) 0x6C 32 read-write n 0x0 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 read-write DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 read-write DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 read-write SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 read-write NDV0 Next Descriptor View 0 0x0 NDV1 Next Descriptor View 1 0x1 NDV2 Next Descriptor View 2 0x2 NDV3 Next Descriptor View 3 0x3 CNDC1 Channel Next Descriptor Control Register (chid = 1) 0xAC 32 read-write n 0x0 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 read-write DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 read-write DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 read-write SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 read-write NDV0 Next Descriptor View 0 0x0 NDV1 Next Descriptor View 1 0x1 NDV2 Next Descriptor View 2 0x2 NDV3 Next Descriptor View 3 0x3 CNDC10 Channel Next Descriptor Control Register (chid = 10) 0x2EC 32 read-write n 0x0 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 read-write DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 read-write DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 read-write SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 read-write NDV0 Next Descriptor View 0 0x0 NDV1 Next Descriptor View 1 0x1 NDV2 Next Descriptor View 2 0x2 NDV3 Next Descriptor View 3 0x3 CNDC11 Channel Next Descriptor Control Register (chid = 11) 0x32C 32 read-write n 0x0 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 read-write DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 read-write DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 read-write SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 read-write NDV0 Next Descriptor View 0 0x0 NDV1 Next Descriptor View 1 0x1 NDV2 Next Descriptor View 2 0x2 NDV3 Next Descriptor View 3 0x3 CNDC12 Channel Next Descriptor Control Register (chid = 12) 0x36C 32 read-write n 0x0 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 read-write DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 read-write DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 read-write SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 read-write NDV0 Next Descriptor View 0 0x0 NDV1 Next Descriptor View 1 0x1 NDV2 Next Descriptor View 2 0x2 NDV3 Next Descriptor View 3 0x3 CNDC13 Channel Next Descriptor Control Register (chid = 13) 0x3AC 32 read-write n 0x0 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 read-write DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 read-write DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 read-write SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 read-write NDV0 Next Descriptor View 0 0x0 NDV1 Next Descriptor View 1 0x1 NDV2 Next Descriptor View 2 0x2 NDV3 Next Descriptor View 3 0x3 CNDC14 Channel Next Descriptor Control Register (chid = 14) 0x3EC 32 read-write n 0x0 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 read-write DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 read-write DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 read-write SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 read-write NDV0 Next Descriptor View 0 0x0 NDV1 Next Descriptor View 1 0x1 NDV2 Next Descriptor View 2 0x2 NDV3 Next Descriptor View 3 0x3 CNDC15 Channel Next Descriptor Control Register (chid = 15) 0x42C 32 read-write n 0x0 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 read-write DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 read-write DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 read-write SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 read-write NDV0 Next Descriptor View 0 0x0 NDV1 Next Descriptor View 1 0x1 NDV2 Next Descriptor View 2 0x2 NDV3 Next Descriptor View 3 0x3 CNDC2 Channel Next Descriptor Control Register (chid = 2) 0xEC 32 read-write n 0x0 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 read-write DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 read-write DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 read-write SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 read-write NDV0 Next Descriptor View 0 0x0 NDV1 Next Descriptor View 1 0x1 NDV2 Next Descriptor View 2 0x2 NDV3 Next Descriptor View 3 0x3 CNDC3 Channel Next Descriptor Control Register (chid = 3) 0x12C 32 read-write n 0x0 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 read-write DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 read-write DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 read-write SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 read-write NDV0 Next Descriptor View 0 0x0 NDV1 Next Descriptor View 1 0x1 NDV2 Next Descriptor View 2 0x2 NDV3 Next Descriptor View 3 0x3 CNDC4 Channel Next Descriptor Control Register (chid = 4) 0x16C 32 read-write n 0x0 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 read-write DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 read-write DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 read-write SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 read-write NDV0 Next Descriptor View 0 0x0 NDV1 Next Descriptor View 1 0x1 NDV2 Next Descriptor View 2 0x2 NDV3 Next Descriptor View 3 0x3 CNDC5 Channel Next Descriptor Control Register (chid = 5) 0x1AC 32 read-write n 0x0 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 read-write DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 read-write DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 read-write SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 read-write NDV0 Next Descriptor View 0 0x0 NDV1 Next Descriptor View 1 0x1 NDV2 Next Descriptor View 2 0x2 NDV3 Next Descriptor View 3 0x3 CNDC6 Channel Next Descriptor Control Register (chid = 6) 0x1EC 32 read-write n 0x0 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 read-write DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 read-write DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 read-write SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 read-write NDV0 Next Descriptor View 0 0x0 NDV1 Next Descriptor View 1 0x1 NDV2 Next Descriptor View 2 0x2 NDV3 Next Descriptor View 3 0x3 CNDC7 Channel Next Descriptor Control Register (chid = 7) 0x22C 32 read-write n 0x0 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 read-write DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 read-write DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 read-write SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 read-write NDV0 Next Descriptor View 0 0x0 NDV1 Next Descriptor View 1 0x1 NDV2 Next Descriptor View 2 0x2 NDV3 Next Descriptor View 3 0x3 CNDC8 Channel Next Descriptor Control Register (chid = 8) 0x26C 32 read-write n 0x0 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 read-write DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 read-write DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 read-write SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 read-write NDV0 Next Descriptor View 0 0x0 NDV1 Next Descriptor View 1 0x1 NDV2 Next Descriptor View 2 0x2 NDV3 Next Descriptor View 3 0x3 CNDC9 Channel Next Descriptor Control Register (chid = 9) 0x2AC 32 read-write n 0x0 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 read-write DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 read-write DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 read-write SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 read-write NDV0 Next Descriptor View 0 0x0 NDV1 Next Descriptor View 1 0x1 NDV2 Next Descriptor View 2 0x2 NDV3 Next Descriptor View 3 0x3 CSA0 Channel Source Address Register (chid = 0) 0x60 32 read-write n 0x0 0x0 SA Channel x Source Address 0 32 read-write CSA1 Channel Source Address Register (chid = 1) 0xA0 32 read-write n 0x0 0x0 SA Channel x Source Address 0 32 read-write CSA10 Channel Source Address Register (chid = 10) 0x2E0 32 read-write n 0x0 0x0 SA Channel x Source Address 0 32 read-write CSA11 Channel Source Address Register (chid = 11) 0x320 32 read-write n 0x0 0x0 SA Channel x Source Address 0 32 read-write CSA12 Channel Source Address Register (chid = 12) 0x360 32 read-write n 0x0 0x0 SA Channel x Source Address 0 32 read-write CSA13 Channel Source Address Register (chid = 13) 0x3A0 32 read-write n 0x0 0x0 SA Channel x Source Address 0 32 read-write CSA14 Channel Source Address Register (chid = 14) 0x3E0 32 read-write n 0x0 0x0 SA Channel x Source Address 0 32 read-write CSA15 Channel Source Address Register (chid = 15) 0x420 32 read-write n 0x0 0x0 SA Channel x Source Address 0 32 read-write CSA2 Channel Source Address Register (chid = 2) 0xE0 32 read-write n 0x0 0x0 SA Channel x Source Address 0 32 read-write CSA3 Channel Source Address Register (chid = 3) 0x120 32 read-write n 0x0 0x0 SA Channel x Source Address 0 32 read-write CSA4 Channel Source Address Register (chid = 4) 0x160 32 read-write n 0x0 0x0 SA Channel x Source Address 0 32 read-write CSA5 Channel Source Address Register (chid = 5) 0x1A0 32 read-write n 0x0 0x0 SA Channel x Source Address 0 32 read-write CSA6 Channel Source Address Register (chid = 6) 0x1E0 32 read-write n 0x0 0x0 SA Channel x Source Address 0 32 read-write CSA7 Channel Source Address Register (chid = 7) 0x220 32 read-write n 0x0 0x0 SA Channel x Source Address 0 32 read-write CSA8 Channel Source Address Register (chid = 8) 0x260 32 read-write n 0x0 0x0 SA Channel x Source Address 0 32 read-write CSA9 Channel Source Address Register (chid = 9) 0x2A0 32 read-write n 0x0 0x0 SA Channel x Source Address 0 32 read-write CSUS0 Channel Source Microblock Stride (chid = 0) 0x80 32 read-write n 0x0 0x0 SUBS Channel x Source Microblock Stride 0 24 read-write CSUS1 Channel Source Microblock Stride (chid = 1) 0xC0 32 read-write n 0x0 0x0 SUBS Channel x Source Microblock Stride 0 24 read-write CSUS10 Channel Source Microblock Stride (chid = 10) 0x300 32 read-write n 0x0 0x0 SUBS Channel x Source Microblock Stride 0 24 read-write CSUS11 Channel Source Microblock Stride (chid = 11) 0x340 32 read-write n 0x0 0x0 SUBS Channel x Source Microblock Stride 0 24 read-write CSUS12 Channel Source Microblock Stride (chid = 12) 0x380 32 read-write n 0x0 0x0 SUBS Channel x Source Microblock Stride 0 24 read-write CSUS13 Channel Source Microblock Stride (chid = 13) 0x3C0 32 read-write n 0x0 0x0 SUBS Channel x Source Microblock Stride 0 24 read-write CSUS14 Channel Source Microblock Stride (chid = 14) 0x400 32 read-write n 0x0 0x0 SUBS Channel x Source Microblock Stride 0 24 read-write CSUS15 Channel Source Microblock Stride (chid = 15) 0x440 32 read-write n 0x0 0x0 SUBS Channel x Source Microblock Stride 0 24 read-write CSUS2 Channel Source Microblock Stride (chid = 2) 0x100 32 read-write n 0x0 0x0 SUBS Channel x Source Microblock Stride 0 24 read-write CSUS3 Channel Source Microblock Stride (chid = 3) 0x140 32 read-write n 0x0 0x0 SUBS Channel x Source Microblock Stride 0 24 read-write CSUS4 Channel Source Microblock Stride (chid = 4) 0x180 32 read-write n 0x0 0x0 SUBS Channel x Source Microblock Stride 0 24 read-write CSUS5 Channel Source Microblock Stride (chid = 5) 0x1C0 32 read-write n 0x0 0x0 SUBS Channel x Source Microblock Stride 0 24 read-write CSUS6 Channel Source Microblock Stride (chid = 6) 0x200 32 read-write n 0x0 0x0 SUBS Channel x Source Microblock Stride 0 24 read-write CSUS7 Channel Source Microblock Stride (chid = 7) 0x240 32 read-write n 0x0 0x0 SUBS Channel x Source Microblock Stride 0 24 read-write CSUS8 Channel Source Microblock Stride (chid = 8) 0x280 32 read-write n 0x0 0x0 SUBS Channel x Source Microblock Stride 0 24 read-write CSUS9 Channel Source Microblock Stride (chid = 9) 0x2C0 32 read-write n 0x0 0x0 SUBS Channel x Source Microblock Stride 0 24 read-write CUBC0 Channel Microblock Control Register (chid = 0) 0x70 32 read-write n 0x0 0x0 UBLEN Channel x Microblock Length 0 24 read-write CUBC1 Channel Microblock Control Register (chid = 1) 0xB0 32 read-write n 0x0 0x0 UBLEN Channel x Microblock Length 0 24 read-write CUBC10 Channel Microblock Control Register (chid = 10) 0x2F0 32 read-write n 0x0 0x0 UBLEN Channel x Microblock Length 0 24 read-write CUBC11 Channel Microblock Control Register (chid = 11) 0x330 32 read-write n 0x0 0x0 UBLEN Channel x Microblock Length 0 24 read-write CUBC12 Channel Microblock Control Register (chid = 12) 0x370 32 read-write n 0x0 0x0 UBLEN Channel x Microblock Length 0 24 read-write CUBC13 Channel Microblock Control Register (chid = 13) 0x3B0 32 read-write n 0x0 0x0 UBLEN Channel x Microblock Length 0 24 read-write CUBC14 Channel Microblock Control Register (chid = 14) 0x3F0 32 read-write n 0x0 0x0 UBLEN Channel x Microblock Length 0 24 read-write CUBC15 Channel Microblock Control Register (chid = 15) 0x430 32 read-write n 0x0 0x0 UBLEN Channel x Microblock Length 0 24 read-write CUBC2 Channel Microblock Control Register (chid = 2) 0xF0 32 read-write n 0x0 0x0 UBLEN Channel x Microblock Length 0 24 read-write CUBC3 Channel Microblock Control Register (chid = 3) 0x130 32 read-write n 0x0 0x0 UBLEN Channel x Microblock Length 0 24 read-write CUBC4 Channel Microblock Control Register (chid = 4) 0x170 32 read-write n 0x0 0x0 UBLEN Channel x Microblock Length 0 24 read-write CUBC5 Channel Microblock Control Register (chid = 5) 0x1B0 32 read-write n 0x0 0x0 UBLEN Channel x Microblock Length 0 24 read-write CUBC6 Channel Microblock Control Register (chid = 6) 0x1F0 32 read-write n 0x0 0x0 UBLEN Channel x Microblock Length 0 24 read-write CUBC7 Channel Microblock Control Register (chid = 7) 0x230 32 read-write n 0x0 0x0 UBLEN Channel x Microblock Length 0 24 read-write CUBC8 Channel Microblock Control Register (chid = 8) 0x270 32 read-write n 0x0 0x0 UBLEN Channel x Microblock Length 0 24 read-write CUBC9 Channel Microblock Control Register (chid = 9) 0x2B0 32 read-write n 0x0 0x0 UBLEN Channel x Microblock Length 0 24 read-write GCFG Global Configuration Register 0x4 32 read-write n 0x0 0x0 BXKBEN Boundary X Kilobyte Enable 8 1 read-write CGDISFIFO FIFO Clock Gating Disable 2 1 read-write CGDISIF Bus Interface Clock Gating Disable 3 1 read-write CGDISPIPE Pipeline Clock Gating Disable 1 1 read-write CGDISREG Configuration Registers Clock Gating Disable 0 1 read-write GD Global Channel Disable Register 0x20 32 write-only n 0x0 0x0 DI0 XDMAC Channel 0 Disable Bit 0 1 write-only DI1 XDMAC Channel 1 Disable Bit 1 1 write-only DI10 XDMAC Channel 10 Disable Bit 10 1 write-only DI11 XDMAC Channel 11 Disable Bit 11 1 write-only DI12 XDMAC Channel 12 Disable Bit 12 1 write-only DI13 XDMAC Channel 13 Disable Bit 13 1 write-only DI14 XDMAC Channel 14 Disable Bit 14 1 write-only DI15 XDMAC Channel 15 Disable Bit 15 1 write-only DI2 XDMAC Channel 2 Disable Bit 2 1 write-only DI3 XDMAC Channel 3 Disable Bit 3 1 write-only DI4 XDMAC Channel 4 Disable Bit 4 1 write-only DI5 XDMAC Channel 5 Disable Bit 5 1 write-only DI6 XDMAC Channel 6 Disable Bit 6 1 write-only DI7 XDMAC Channel 7 Disable Bit 7 1 write-only DI8 XDMAC Channel 8 Disable Bit 8 1 write-only DI9 XDMAC Channel 9 Disable Bit 9 1 write-only GE Global Channel Enable Register 0x1C 32 write-only n 0x0 0x0 EN0 XDMAC Channel 0 Enable Bit 0 1 write-only EN1 XDMAC Channel 1 Enable Bit 1 1 write-only EN10 XDMAC Channel 10 Enable Bit 10 1 write-only EN11 XDMAC Channel 11 Enable Bit 11 1 write-only EN12 XDMAC Channel 12 Enable Bit 12 1 write-only EN13 XDMAC Channel 13 Enable Bit 13 1 write-only EN14 XDMAC Channel 14 Enable Bit 14 1 write-only EN15 XDMAC Channel 15 Enable Bit 15 1 write-only EN2 XDMAC Channel 2 Enable Bit 2 1 write-only EN3 XDMAC Channel 3 Enable Bit 3 1 write-only EN4 XDMAC Channel 4 Enable Bit 4 1 write-only EN5 XDMAC Channel 5 Enable Bit 5 1 write-only EN6 XDMAC Channel 6 Enable Bit 6 1 write-only EN7 XDMAC Channel 7 Enable Bit 7 1 write-only EN8 XDMAC Channel 8 Enable Bit 8 1 write-only EN9 XDMAC Channel 9 Enable Bit 9 1 write-only GID Global Interrupt Disable Register 0x10 32 write-only n 0x0 0x0 ID0 XDMAC Channel 0 Interrupt Disable Bit 0 1 write-only ID1 XDMAC Channel 1 Interrupt Disable Bit 1 1 write-only ID10 XDMAC Channel 10 Interrupt Disable Bit 10 1 write-only ID11 XDMAC Channel 11 Interrupt Disable Bit 11 1 write-only ID12 XDMAC Channel 12 Interrupt Disable Bit 12 1 write-only ID13 XDMAC Channel 13 Interrupt Disable Bit 13 1 write-only ID14 XDMAC Channel 14 Interrupt Disable Bit 14 1 write-only ID15 XDMAC Channel 15 Interrupt Disable Bit 15 1 write-only ID2 XDMAC Channel 2 Interrupt Disable Bit 2 1 write-only ID3 XDMAC Channel 3 Interrupt Disable Bit 3 1 write-only ID4 XDMAC Channel 4 Interrupt Disable Bit 4 1 write-only ID5 XDMAC Channel 5 Interrupt Disable Bit 5 1 write-only ID6 XDMAC Channel 6 Interrupt Disable Bit 6 1 write-only ID7 XDMAC Channel 7 Interrupt Disable Bit 7 1 write-only ID8 XDMAC Channel 8 Interrupt Disable Bit 8 1 write-only ID9 XDMAC Channel 9 Interrupt Disable Bit 9 1 write-only GIE Global Interrupt Enable Register 0xC 32 write-only n 0x0 0x0 IE0 XDMAC Channel 0 Interrupt Enable Bit 0 1 write-only IE1 XDMAC Channel 1 Interrupt Enable Bit 1 1 write-only IE10 XDMAC Channel 10 Interrupt Enable Bit 10 1 write-only IE11 XDMAC Channel 11 Interrupt Enable Bit 11 1 write-only IE12 XDMAC Channel 12 Interrupt Enable Bit 12 1 write-only IE13 XDMAC Channel 13 Interrupt Enable Bit 13 1 write-only IE14 XDMAC Channel 14 Interrupt Enable Bit 14 1 write-only IE15 XDMAC Channel 15 Interrupt Enable Bit 15 1 write-only IE2 XDMAC Channel 2 Interrupt Enable Bit 2 1 write-only IE3 XDMAC Channel 3 Interrupt Enable Bit 3 1 write-only IE4 XDMAC Channel 4 Interrupt Enable Bit 4 1 write-only IE5 XDMAC Channel 5 Interrupt Enable Bit 5 1 write-only IE6 XDMAC Channel 6 Interrupt Enable Bit 6 1 write-only IE7 XDMAC Channel 7 Interrupt Enable Bit 7 1 write-only IE8 XDMAC Channel 8 Interrupt Enable Bit 8 1 write-only IE9 XDMAC Channel 9 Interrupt Enable Bit 9 1 write-only GIM Global Interrupt Mask Register 0x14 32 read-only n 0x0 0x0 IM0 XDMAC Channel 0 Interrupt Mask Bit 0 1 read-only IM1 XDMAC Channel 1 Interrupt Mask Bit 1 1 read-only IM10 XDMAC Channel 10 Interrupt Mask Bit 10 1 read-only IM11 XDMAC Channel 11 Interrupt Mask Bit 11 1 read-only IM12 XDMAC Channel 12 Interrupt Mask Bit 12 1 read-only IM13 XDMAC Channel 13 Interrupt Mask Bit 13 1 read-only IM14 XDMAC Channel 14 Interrupt Mask Bit 14 1 read-only IM15 XDMAC Channel 15 Interrupt Mask Bit 15 1 read-only IM2 XDMAC Channel 2 Interrupt Mask Bit 2 1 read-only IM3 XDMAC Channel 3 Interrupt Mask Bit 3 1 read-only IM4 XDMAC Channel 4 Interrupt Mask Bit 4 1 read-only IM5 XDMAC Channel 5 Interrupt Mask Bit 5 1 read-only IM6 XDMAC Channel 6 Interrupt Mask Bit 6 1 read-only IM7 XDMAC Channel 7 Interrupt Mask Bit 7 1 read-only IM8 XDMAC Channel 8 Interrupt Mask Bit 8 1 read-only IM9 XDMAC Channel 9 Interrupt Mask Bit 9 1 read-only GIS Global Interrupt Status Register 0x18 32 read-only n 0x0 0x0 IS0 XDMAC Channel 0 Interrupt Status Bit 0 1 read-only IS1 XDMAC Channel 1 Interrupt Status Bit 1 1 read-only IS10 XDMAC Channel 10 Interrupt Status Bit 10 1 read-only IS11 XDMAC Channel 11 Interrupt Status Bit 11 1 read-only IS12 XDMAC Channel 12 Interrupt Status Bit 12 1 read-only IS13 XDMAC Channel 13 Interrupt Status Bit 13 1 read-only IS14 XDMAC Channel 14 Interrupt Status Bit 14 1 read-only IS15 XDMAC Channel 15 Interrupt Status Bit 15 1 read-only IS2 XDMAC Channel 2 Interrupt Status Bit 2 1 read-only IS3 XDMAC Channel 3 Interrupt Status Bit 3 1 read-only IS4 XDMAC Channel 4 Interrupt Status Bit 4 1 read-only IS5 XDMAC Channel 5 Interrupt Status Bit 5 1 read-only IS6 XDMAC Channel 6 Interrupt Status Bit 6 1 read-only IS7 XDMAC Channel 7 Interrupt Status Bit 7 1 read-only IS8 XDMAC Channel 8 Interrupt Status Bit 8 1 read-only IS9 XDMAC Channel 9 Interrupt Status Bit 9 1 read-only GRS Global Channel Read Suspend Register 0x28 32 read-write n 0x0 0x0 RS0 XDMAC Channel 0 Read Suspend Bit 0 1 read-write RS1 XDMAC Channel 1 Read Suspend Bit 1 1 read-write RS10 XDMAC Channel 10 Read Suspend Bit 10 1 read-write RS11 XDMAC Channel 11 Read Suspend Bit 11 1 read-write RS12 XDMAC Channel 12 Read Suspend Bit 12 1 read-write RS13 XDMAC Channel 13 Read Suspend Bit 13 1 read-write RS14 XDMAC Channel 14 Read Suspend Bit 14 1 read-write RS15 XDMAC Channel 15 Read Suspend Bit 15 1 read-write RS2 XDMAC Channel 2 Read Suspend Bit 2 1 read-write RS3 XDMAC Channel 3 Read Suspend Bit 3 1 read-write RS4 XDMAC Channel 4 Read Suspend Bit 4 1 read-write RS5 XDMAC Channel 5 Read Suspend Bit 5 1 read-write RS6 XDMAC Channel 6 Read Suspend Bit 6 1 read-write RS7 XDMAC Channel 7 Read Suspend Bit 7 1 read-write RS8 XDMAC Channel 8 Read Suspend Bit 8 1 read-write RS9 XDMAC Channel 9 Read Suspend Bit 9 1 read-write GRWR Global Channel Read Write Resume Register 0x34 32 write-only n 0x0 0x0 RWR0 XDMAC Channel 0 Read Write Resume Bit 0 1 write-only RWR1 XDMAC Channel 1 Read Write Resume Bit 1 1 write-only RWR10 XDMAC Channel 10 Read Write Resume Bit 10 1 write-only RWR11 XDMAC Channel 11 Read Write Resume Bit 11 1 write-only RWR12 XDMAC Channel 12 Read Write Resume Bit 12 1 write-only RWR13 XDMAC Channel 13 Read Write Resume Bit 13 1 write-only RWR14 XDMAC Channel 14 Read Write Resume Bit 14 1 write-only RWR15 XDMAC Channel 15 Read Write Resume Bit 15 1 write-only RWR2 XDMAC Channel 2 Read Write Resume Bit 2 1 write-only RWR3 XDMAC Channel 3 Read Write Resume Bit 3 1 write-only RWR4 XDMAC Channel 4 Read Write Resume Bit 4 1 write-only RWR5 XDMAC Channel 5 Read Write Resume Bit 5 1 write-only RWR6 XDMAC Channel 6 Read Write Resume Bit 6 1 write-only RWR7 XDMAC Channel 7 Read Write Resume Bit 7 1 write-only RWR8 XDMAC Channel 8 Read Write Resume Bit 8 1 write-only RWR9 XDMAC Channel 9 Read Write Resume Bit 9 1 write-only GRWS Global Channel Read Write Suspend Register 0x30 32 write-only n 0x0 0x0 RWS0 XDMAC Channel 0 Read Write Suspend Bit 0 1 write-only RWS1 XDMAC Channel 1 Read Write Suspend Bit 1 1 write-only RWS10 XDMAC Channel 10 Read Write Suspend Bit 10 1 write-only RWS11 XDMAC Channel 11 Read Write Suspend Bit 11 1 write-only RWS12 XDMAC Channel 12 Read Write Suspend Bit 12 1 write-only RWS13 XDMAC Channel 13 Read Write Suspend Bit 13 1 write-only RWS14 XDMAC Channel 14 Read Write Suspend Bit 14 1 write-only RWS15 XDMAC Channel 15 Read Write Suspend Bit 15 1 write-only RWS2 XDMAC Channel 2 Read Write Suspend Bit 2 1 write-only RWS3 XDMAC Channel 3 Read Write Suspend Bit 3 1 write-only RWS4 XDMAC Channel 4 Read Write Suspend Bit 4 1 write-only RWS5 XDMAC Channel 5 Read Write Suspend Bit 5 1 write-only RWS6 XDMAC Channel 6 Read Write Suspend Bit 6 1 write-only RWS7 XDMAC Channel 7 Read Write Suspend Bit 7 1 write-only RWS8 XDMAC Channel 8 Read Write Suspend Bit 8 1 write-only RWS9 XDMAC Channel 9 Read Write Suspend Bit 9 1 write-only GS Global Channel Status Register 0x24 32 read-only n 0x0 0x0 ST0 XDMAC Channel 0 Status Bit 0 1 read-only ST1 XDMAC Channel 1 Status Bit 1 1 read-only ST10 XDMAC Channel 10 Status Bit 10 1 read-only ST11 XDMAC Channel 11 Status Bit 11 1 read-only ST12 XDMAC Channel 12 Status Bit 12 1 read-only ST13 XDMAC Channel 13 Status Bit 13 1 read-only ST14 XDMAC Channel 14 Status Bit 14 1 read-only ST15 XDMAC Channel 15 Status Bit 15 1 read-only ST2 XDMAC Channel 2 Status Bit 2 1 read-only ST3 XDMAC Channel 3 Status Bit 3 1 read-only ST4 XDMAC Channel 4 Status Bit 4 1 read-only ST5 XDMAC Channel 5 Status Bit 5 1 read-only ST6 XDMAC Channel 6 Status Bit 6 1 read-only ST7 XDMAC Channel 7 Status Bit 7 1 read-only ST8 XDMAC Channel 8 Status Bit 8 1 read-only ST9 XDMAC Channel 9 Status Bit 9 1 read-only GSWF Global Channel Software Flush Request Register 0x40 32 write-only n 0x0 0x0 SWF0 XDMAC Channel 0 Software Flush Request Bit 0 1 write-only SWF1 XDMAC Channel 1 Software Flush Request Bit 1 1 write-only SWF10 XDMAC Channel 10 Software Flush Request Bit 10 1 write-only SWF11 XDMAC Channel 11 Software Flush Request Bit 11 1 write-only SWF12 XDMAC Channel 12 Software Flush Request Bit 12 1 write-only SWF13 XDMAC Channel 13 Software Flush Request Bit 13 1 write-only SWF14 XDMAC Channel 14 Software Flush Request Bit 14 1 write-only SWF15 XDMAC Channel 15 Software Flush Request Bit 15 1 write-only SWF2 XDMAC Channel 2 Software Flush Request Bit 2 1 write-only SWF3 XDMAC Channel 3 Software Flush Request Bit 3 1 write-only SWF4 XDMAC Channel 4 Software Flush Request Bit 4 1 write-only SWF5 XDMAC Channel 5 Software Flush Request Bit 5 1 write-only SWF6 XDMAC Channel 6 Software Flush Request Bit 6 1 write-only SWF7 XDMAC Channel 7 Software Flush Request Bit 7 1 write-only SWF8 XDMAC Channel 8 Software Flush Request Bit 8 1 write-only SWF9 XDMAC Channel 9 Software Flush Request Bit 9 1 write-only GSWR Global Channel Software Request Register 0x38 32 write-only n 0x0 0x0 SWREQ0 XDMAC Channel 0 Software Request Bit 0 1 write-only SWREQ1 XDMAC Channel 1 Software Request Bit 1 1 write-only SWREQ10 XDMAC Channel 10 Software Request Bit 10 1 write-only SWREQ11 XDMAC Channel 11 Software Request Bit 11 1 write-only SWREQ12 XDMAC Channel 12 Software Request Bit 12 1 write-only SWREQ13 XDMAC Channel 13 Software Request Bit 13 1 write-only SWREQ14 XDMAC Channel 14 Software Request Bit 14 1 write-only SWREQ15 XDMAC Channel 15 Software Request Bit 15 1 write-only SWREQ2 XDMAC Channel 2 Software Request Bit 2 1 write-only SWREQ3 XDMAC Channel 3 Software Request Bit 3 1 write-only SWREQ4 XDMAC Channel 4 Software Request Bit 4 1 write-only SWREQ5 XDMAC Channel 5 Software Request Bit 5 1 write-only SWREQ6 XDMAC Channel 6 Software Request Bit 6 1 write-only SWREQ7 XDMAC Channel 7 Software Request Bit 7 1 write-only SWREQ8 XDMAC Channel 8 Software Request Bit 8 1 write-only SWREQ9 XDMAC Channel 9 Software Request Bit 9 1 write-only GSWS Global Channel Software Request Status Register 0x3C 32 read-only n 0x0 0x0 SWRS0 XDMAC Channel 0 Software Request Status Bit 0 1 read-only SWRS1 XDMAC Channel 1 Software Request Status Bit 1 1 read-only SWRS10 XDMAC Channel 10 Software Request Status Bit 10 1 read-only SWRS11 XDMAC Channel 11 Software Request Status Bit 11 1 read-only SWRS12 XDMAC Channel 12 Software Request Status Bit 12 1 read-only SWRS13 XDMAC Channel 13 Software Request Status Bit 13 1 read-only SWRS14 XDMAC Channel 14 Software Request Status Bit 14 1 read-only SWRS15 XDMAC Channel 15 Software Request Status Bit 15 1 read-only SWRS2 XDMAC Channel 2 Software Request Status Bit 2 1 read-only SWRS3 XDMAC Channel 3 Software Request Status Bit 3 1 read-only SWRS4 XDMAC Channel 4 Software Request Status Bit 4 1 read-only SWRS5 XDMAC Channel 5 Software Request Status Bit 5 1 read-only SWRS6 XDMAC Channel 6 Software Request Status Bit 6 1 read-only SWRS7 XDMAC Channel 7 Software Request Status Bit 7 1 read-only SWRS8 XDMAC Channel 8 Software Request Status Bit 8 1 read-only SWRS9 XDMAC Channel 9 Software Request Status Bit 9 1 read-only GTYPE Global Type Register 0x0 32 read-only n 0x0 0x0 FIFO_SZ Number of Bytes 5 11 read-only NB_CH Number of Channels Minus One 0 5 read-only NB_REQ Number of Peripheral Requests Minus One 16 7 read-only GWAC Global Weighted Arbiter Configuration Register 0x8 32 read-write n 0x0 0x0 PW0 Pool Weight 0 0 4 read-write PW1 Pool Weight 1 4 4 read-write PW2 Pool Weight 2 8 4 read-write PW3 Pool Weight 3 12 4 read-write GWS Global Channel Write Suspend Register 0x2C 32 read-write n 0x0 0x0 WS0 XDMAC Channel 0 Write Suspend Bit 0 1 read-write WS1 XDMAC Channel 1 Write Suspend Bit 1 1 read-write WS10 XDMAC Channel 10 Write Suspend Bit 10 1 read-write WS11 XDMAC Channel 11 Write Suspend Bit 11 1 read-write WS12 XDMAC Channel 12 Write Suspend Bit 12 1 read-write WS13 XDMAC Channel 13 Write Suspend Bit 13 1 read-write WS14 XDMAC Channel 14 Write Suspend Bit 14 1 read-write WS15 XDMAC Channel 15 Write Suspend Bit 15 1 read-write WS2 XDMAC Channel 2 Write Suspend Bit 2 1 read-write WS3 XDMAC Channel 3 Write Suspend Bit 3 1 read-write WS4 XDMAC Channel 4 Write Suspend Bit 4 1 read-write WS5 XDMAC Channel 5 Write Suspend Bit 5 1 read-write WS6 XDMAC Channel 6 Write Suspend Bit 6 1 read-write WS7 XDMAC Channel 7 Write Suspend Bit 7 1 read-write WS8 XDMAC Channel 8 Write Suspend Bit 8 1 read-write WS9 XDMAC Channel 9 Write Suspend Bit 9 1 read-write XDMAC1 Extensible DMA Controller 1 XDMAC 0x0 0x0 0x50 registers n XDMAC1 50 CBC0 Channel Block Control Register (chid = 0) 0x74 32 read-write n 0x0 0x0 BLEN Channel x Block Length 0 12 read-write CBC1 Channel Block Control Register (chid = 1) 0xB4 32 read-write n 0x0 0x0 BLEN Channel x Block Length 0 12 read-write CBC10 Channel Block Control Register (chid = 10) 0x2F4 32 read-write n 0x0 0x0 BLEN Channel x Block Length 0 12 read-write CBC11 Channel Block Control Register (chid = 11) 0x334 32 read-write n 0x0 0x0 BLEN Channel x Block Length 0 12 read-write CBC12 Channel Block Control Register (chid = 12) 0x374 32 read-write n 0x0 0x0 BLEN Channel x Block Length 0 12 read-write CBC13 Channel Block Control Register (chid = 13) 0x3B4 32 read-write n 0x0 0x0 BLEN Channel x Block Length 0 12 read-write CBC14 Channel Block Control Register (chid = 14) 0x3F4 32 read-write n 0x0 0x0 BLEN Channel x Block Length 0 12 read-write CBC15 Channel Block Control Register (chid = 15) 0x434 32 read-write n 0x0 0x0 BLEN Channel x Block Length 0 12 read-write CBC2 Channel Block Control Register (chid = 2) 0xF4 32 read-write n 0x0 0x0 BLEN Channel x Block Length 0 12 read-write CBC3 Channel Block Control Register (chid = 3) 0x134 32 read-write n 0x0 0x0 BLEN Channel x Block Length 0 12 read-write CBC4 Channel Block Control Register (chid = 4) 0x174 32 read-write n 0x0 0x0 BLEN Channel x Block Length 0 12 read-write CBC5 Channel Block Control Register (chid = 5) 0x1B4 32 read-write n 0x0 0x0 BLEN Channel x Block Length 0 12 read-write CBC6 Channel Block Control Register (chid = 6) 0x1F4 32 read-write n 0x0 0x0 BLEN Channel x Block Length 0 12 read-write CBC7 Channel Block Control Register (chid = 7) 0x234 32 read-write n 0x0 0x0 BLEN Channel x Block Length 0 12 read-write CBC8 Channel Block Control Register (chid = 8) 0x274 32 read-write n 0x0 0x0 BLEN Channel x Block Length 0 12 read-write CBC9 Channel Block Control Register (chid = 9) 0x2B4 32 read-write n 0x0 0x0 BLEN Channel x Block Length 0 12 read-write CC0 Channel Configuration Register (chid = 0) 0x78 32 read-write n 0x0 0x0 CSIZE Channel x Chunk Size 8 3 read-write CHK_1 1 data transferred 0x0 CHK_2 2 data transferred 0x1 CHK_4 4 data transferred 0x2 CHK_8 8 data transferred 0x3 CHK_16 16 data transferred 0x4 DAM Channel x Destination Addressing Mode 18 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary; the data stride is added at the data boundary. 0x3 DIF Channel x Destination Interface Identifier 14 1 read-write AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 read-write PER2MEM Peripheral-to-memory transfer. 0 MEM2PER Memory-to-peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 read-write BYTE The data size is set to 8 bits 0x0 HALFWORD The data size is set to 16 bits 0x1 WORD The data size is set to 32 bits 0x2 DWORD The data size is set to 64 bits 0x3 INITD Channel Initialization Done (this bit is read-only) 21 1 read-write IN_PROGRESS Channel initialization is in progress. 0 TERMINATED Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 read-write SINGLE The memory burst size is set to one. 0x0 FOUR The memory burst size is set to four. 0x1 EIGHT The memory burst size is set to eight. 0x2 SIXTEEN The memory burst size is set to sixteen. 0x3 MEMSET Channel x Fill Block of Memory 7 1 read-write NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 read-write PROT Channel x Protection 5 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 RDIP Read in Progress (this bit is read-only) 22 1 read-write DONE No active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 SIF Channel x Source Interface Identifier 13 1 read-write AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 read-write MEM_TRAN Self-triggered mode (memory-to-memory transfer). 0 PER_TRAN Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 read-write DONE No active write transaction on the bus. 0 IN_PROGRESS A write transaction is in progress. 1 CC1 Channel Configuration Register (chid = 1) 0xB8 32 read-write n 0x0 0x0 CSIZE Channel x Chunk Size 8 3 read-write CHK_1 1 data transferred 0x0 CHK_2 2 data transferred 0x1 CHK_4 4 data transferred 0x2 CHK_8 8 data transferred 0x3 CHK_16 16 data transferred 0x4 DAM Channel x Destination Addressing Mode 18 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary; the data stride is added at the data boundary. 0x3 DIF Channel x Destination Interface Identifier 14 1 read-write AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 read-write PER2MEM Peripheral-to-memory transfer. 0 MEM2PER Memory-to-peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 read-write BYTE The data size is set to 8 bits 0x0 HALFWORD The data size is set to 16 bits 0x1 WORD The data size is set to 32 bits 0x2 DWORD The data size is set to 64 bits 0x3 INITD Channel Initialization Done (this bit is read-only) 21 1 read-write IN_PROGRESS Channel initialization is in progress. 0 TERMINATED Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 read-write SINGLE The memory burst size is set to one. 0x0 FOUR The memory burst size is set to four. 0x1 EIGHT The memory burst size is set to eight. 0x2 SIXTEEN The memory burst size is set to sixteen. 0x3 MEMSET Channel x Fill Block of Memory 7 1 read-write NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 read-write PROT Channel x Protection 5 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 RDIP Read in Progress (this bit is read-only) 22 1 read-write DONE No active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 SIF Channel x Source Interface Identifier 13 1 read-write AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 read-write MEM_TRAN Self-triggered mode (memory-to-memory transfer). 0 PER_TRAN Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 read-write DONE No active write transaction on the bus. 0 IN_PROGRESS A write transaction is in progress. 1 CC10 Channel Configuration Register (chid = 10) 0x2F8 32 read-write n 0x0 0x0 CSIZE Channel x Chunk Size 8 3 read-write CHK_1 1 data transferred 0x0 CHK_2 2 data transferred 0x1 CHK_4 4 data transferred 0x2 CHK_8 8 data transferred 0x3 CHK_16 16 data transferred 0x4 DAM Channel x Destination Addressing Mode 18 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary; the data stride is added at the data boundary. 0x3 DIF Channel x Destination Interface Identifier 14 1 read-write AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 read-write PER2MEM Peripheral-to-memory transfer. 0 MEM2PER Memory-to-peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 read-write BYTE The data size is set to 8 bits 0x0 HALFWORD The data size is set to 16 bits 0x1 WORD The data size is set to 32 bits 0x2 DWORD The data size is set to 64 bits 0x3 INITD Channel Initialization Done (this bit is read-only) 21 1 read-write IN_PROGRESS Channel initialization is in progress. 0 TERMINATED Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 read-write SINGLE The memory burst size is set to one. 0x0 FOUR The memory burst size is set to four. 0x1 EIGHT The memory burst size is set to eight. 0x2 SIXTEEN The memory burst size is set to sixteen. 0x3 MEMSET Channel x Fill Block of Memory 7 1 read-write NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 read-write PROT Channel x Protection 5 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 RDIP Read in Progress (this bit is read-only) 22 1 read-write DONE No active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 SIF Channel x Source Interface Identifier 13 1 read-write AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 read-write MEM_TRAN Self-triggered mode (memory-to-memory transfer). 0 PER_TRAN Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 read-write DONE No active write transaction on the bus. 0 IN_PROGRESS A write transaction is in progress. 1 CC11 Channel Configuration Register (chid = 11) 0x338 32 read-write n 0x0 0x0 CSIZE Channel x Chunk Size 8 3 read-write CHK_1 1 data transferred 0x0 CHK_2 2 data transferred 0x1 CHK_4 4 data transferred 0x2 CHK_8 8 data transferred 0x3 CHK_16 16 data transferred 0x4 DAM Channel x Destination Addressing Mode 18 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary; the data stride is added at the data boundary. 0x3 DIF Channel x Destination Interface Identifier 14 1 read-write AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 read-write PER2MEM Peripheral-to-memory transfer. 0 MEM2PER Memory-to-peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 read-write BYTE The data size is set to 8 bits 0x0 HALFWORD The data size is set to 16 bits 0x1 WORD The data size is set to 32 bits 0x2 DWORD The data size is set to 64 bits 0x3 INITD Channel Initialization Done (this bit is read-only) 21 1 read-write IN_PROGRESS Channel initialization is in progress. 0 TERMINATED Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 read-write SINGLE The memory burst size is set to one. 0x0 FOUR The memory burst size is set to four. 0x1 EIGHT The memory burst size is set to eight. 0x2 SIXTEEN The memory burst size is set to sixteen. 0x3 MEMSET Channel x Fill Block of Memory 7 1 read-write NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 read-write PROT Channel x Protection 5 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 RDIP Read in Progress (this bit is read-only) 22 1 read-write DONE No active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 SIF Channel x Source Interface Identifier 13 1 read-write AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 read-write MEM_TRAN Self-triggered mode (memory-to-memory transfer). 0 PER_TRAN Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 read-write DONE No active write transaction on the bus. 0 IN_PROGRESS A write transaction is in progress. 1 CC12 Channel Configuration Register (chid = 12) 0x378 32 read-write n 0x0 0x0 CSIZE Channel x Chunk Size 8 3 read-write CHK_1 1 data transferred 0x0 CHK_2 2 data transferred 0x1 CHK_4 4 data transferred 0x2 CHK_8 8 data transferred 0x3 CHK_16 16 data transferred 0x4 DAM Channel x Destination Addressing Mode 18 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary; the data stride is added at the data boundary. 0x3 DIF Channel x Destination Interface Identifier 14 1 read-write AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 read-write PER2MEM Peripheral-to-memory transfer. 0 MEM2PER Memory-to-peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 read-write BYTE The data size is set to 8 bits 0x0 HALFWORD The data size is set to 16 bits 0x1 WORD The data size is set to 32 bits 0x2 DWORD The data size is set to 64 bits 0x3 INITD Channel Initialization Done (this bit is read-only) 21 1 read-write IN_PROGRESS Channel initialization is in progress. 0 TERMINATED Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 read-write SINGLE The memory burst size is set to one. 0x0 FOUR The memory burst size is set to four. 0x1 EIGHT The memory burst size is set to eight. 0x2 SIXTEEN The memory burst size is set to sixteen. 0x3 MEMSET Channel x Fill Block of Memory 7 1 read-write NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 read-write PROT Channel x Protection 5 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 RDIP Read in Progress (this bit is read-only) 22 1 read-write DONE No active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 SIF Channel x Source Interface Identifier 13 1 read-write AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 read-write MEM_TRAN Self-triggered mode (memory-to-memory transfer). 0 PER_TRAN Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 read-write DONE No active write transaction on the bus. 0 IN_PROGRESS A write transaction is in progress. 1 CC13 Channel Configuration Register (chid = 13) 0x3B8 32 read-write n 0x0 0x0 CSIZE Channel x Chunk Size 8 3 read-write CHK_1 1 data transferred 0x0 CHK_2 2 data transferred 0x1 CHK_4 4 data transferred 0x2 CHK_8 8 data transferred 0x3 CHK_16 16 data transferred 0x4 DAM Channel x Destination Addressing Mode 18 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary; the data stride is added at the data boundary. 0x3 DIF Channel x Destination Interface Identifier 14 1 read-write AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 read-write PER2MEM Peripheral-to-memory transfer. 0 MEM2PER Memory-to-peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 read-write BYTE The data size is set to 8 bits 0x0 HALFWORD The data size is set to 16 bits 0x1 WORD The data size is set to 32 bits 0x2 DWORD The data size is set to 64 bits 0x3 INITD Channel Initialization Done (this bit is read-only) 21 1 read-write IN_PROGRESS Channel initialization is in progress. 0 TERMINATED Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 read-write SINGLE The memory burst size is set to one. 0x0 FOUR The memory burst size is set to four. 0x1 EIGHT The memory burst size is set to eight. 0x2 SIXTEEN The memory burst size is set to sixteen. 0x3 MEMSET Channel x Fill Block of Memory 7 1 read-write NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 read-write PROT Channel x Protection 5 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 RDIP Read in Progress (this bit is read-only) 22 1 read-write DONE No active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 SIF Channel x Source Interface Identifier 13 1 read-write AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 read-write MEM_TRAN Self-triggered mode (memory-to-memory transfer). 0 PER_TRAN Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 read-write DONE No active write transaction on the bus. 0 IN_PROGRESS A write transaction is in progress. 1 CC14 Channel Configuration Register (chid = 14) 0x3F8 32 read-write n 0x0 0x0 CSIZE Channel x Chunk Size 8 3 read-write CHK_1 1 data transferred 0x0 CHK_2 2 data transferred 0x1 CHK_4 4 data transferred 0x2 CHK_8 8 data transferred 0x3 CHK_16 16 data transferred 0x4 DAM Channel x Destination Addressing Mode 18 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary; the data stride is added at the data boundary. 0x3 DIF Channel x Destination Interface Identifier 14 1 read-write AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 read-write PER2MEM Peripheral-to-memory transfer. 0 MEM2PER Memory-to-peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 read-write BYTE The data size is set to 8 bits 0x0 HALFWORD The data size is set to 16 bits 0x1 WORD The data size is set to 32 bits 0x2 DWORD The data size is set to 64 bits 0x3 INITD Channel Initialization Done (this bit is read-only) 21 1 read-write IN_PROGRESS Channel initialization is in progress. 0 TERMINATED Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 read-write SINGLE The memory burst size is set to one. 0x0 FOUR The memory burst size is set to four. 0x1 EIGHT The memory burst size is set to eight. 0x2 SIXTEEN The memory burst size is set to sixteen. 0x3 MEMSET Channel x Fill Block of Memory 7 1 read-write NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 read-write PROT Channel x Protection 5 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 RDIP Read in Progress (this bit is read-only) 22 1 read-write DONE No active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 SIF Channel x Source Interface Identifier 13 1 read-write AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 read-write MEM_TRAN Self-triggered mode (memory-to-memory transfer). 0 PER_TRAN Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 read-write DONE No active write transaction on the bus. 0 IN_PROGRESS A write transaction is in progress. 1 CC15 Channel Configuration Register (chid = 15) 0x438 32 read-write n 0x0 0x0 CSIZE Channel x Chunk Size 8 3 read-write CHK_1 1 data transferred 0x0 CHK_2 2 data transferred 0x1 CHK_4 4 data transferred 0x2 CHK_8 8 data transferred 0x3 CHK_16 16 data transferred 0x4 DAM Channel x Destination Addressing Mode 18 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary; the data stride is added at the data boundary. 0x3 DIF Channel x Destination Interface Identifier 14 1 read-write AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 read-write PER2MEM Peripheral-to-memory transfer. 0 MEM2PER Memory-to-peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 read-write BYTE The data size is set to 8 bits 0x0 HALFWORD The data size is set to 16 bits 0x1 WORD The data size is set to 32 bits 0x2 DWORD The data size is set to 64 bits 0x3 INITD Channel Initialization Done (this bit is read-only) 21 1 read-write IN_PROGRESS Channel initialization is in progress. 0 TERMINATED Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 read-write SINGLE The memory burst size is set to one. 0x0 FOUR The memory burst size is set to four. 0x1 EIGHT The memory burst size is set to eight. 0x2 SIXTEEN The memory burst size is set to sixteen. 0x3 MEMSET Channel x Fill Block of Memory 7 1 read-write NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 read-write PROT Channel x Protection 5 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 RDIP Read in Progress (this bit is read-only) 22 1 read-write DONE No active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 SIF Channel x Source Interface Identifier 13 1 read-write AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 read-write MEM_TRAN Self-triggered mode (memory-to-memory transfer). 0 PER_TRAN Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 read-write DONE No active write transaction on the bus. 0 IN_PROGRESS A write transaction is in progress. 1 CC2 Channel Configuration Register (chid = 2) 0xF8 32 read-write n 0x0 0x0 CSIZE Channel x Chunk Size 8 3 read-write CHK_1 1 data transferred 0x0 CHK_2 2 data transferred 0x1 CHK_4 4 data transferred 0x2 CHK_8 8 data transferred 0x3 CHK_16 16 data transferred 0x4 DAM Channel x Destination Addressing Mode 18 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary; the data stride is added at the data boundary. 0x3 DIF Channel x Destination Interface Identifier 14 1 read-write AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 read-write PER2MEM Peripheral-to-memory transfer. 0 MEM2PER Memory-to-peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 read-write BYTE The data size is set to 8 bits 0x0 HALFWORD The data size is set to 16 bits 0x1 WORD The data size is set to 32 bits 0x2 DWORD The data size is set to 64 bits 0x3 INITD Channel Initialization Done (this bit is read-only) 21 1 read-write IN_PROGRESS Channel initialization is in progress. 0 TERMINATED Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 read-write SINGLE The memory burst size is set to one. 0x0 FOUR The memory burst size is set to four. 0x1 EIGHT The memory burst size is set to eight. 0x2 SIXTEEN The memory burst size is set to sixteen. 0x3 MEMSET Channel x Fill Block of Memory 7 1 read-write NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 read-write PROT Channel x Protection 5 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 RDIP Read in Progress (this bit is read-only) 22 1 read-write DONE No active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 SIF Channel x Source Interface Identifier 13 1 read-write AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 read-write MEM_TRAN Self-triggered mode (memory-to-memory transfer). 0 PER_TRAN Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 read-write DONE No active write transaction on the bus. 0 IN_PROGRESS A write transaction is in progress. 1 CC3 Channel Configuration Register (chid = 3) 0x138 32 read-write n 0x0 0x0 CSIZE Channel x Chunk Size 8 3 read-write CHK_1 1 data transferred 0x0 CHK_2 2 data transferred 0x1 CHK_4 4 data transferred 0x2 CHK_8 8 data transferred 0x3 CHK_16 16 data transferred 0x4 DAM Channel x Destination Addressing Mode 18 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary; the data stride is added at the data boundary. 0x3 DIF Channel x Destination Interface Identifier 14 1 read-write AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 read-write PER2MEM Peripheral-to-memory transfer. 0 MEM2PER Memory-to-peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 read-write BYTE The data size is set to 8 bits 0x0 HALFWORD The data size is set to 16 bits 0x1 WORD The data size is set to 32 bits 0x2 DWORD The data size is set to 64 bits 0x3 INITD Channel Initialization Done (this bit is read-only) 21 1 read-write IN_PROGRESS Channel initialization is in progress. 0 TERMINATED Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 read-write SINGLE The memory burst size is set to one. 0x0 FOUR The memory burst size is set to four. 0x1 EIGHT The memory burst size is set to eight. 0x2 SIXTEEN The memory burst size is set to sixteen. 0x3 MEMSET Channel x Fill Block of Memory 7 1 read-write NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 read-write PROT Channel x Protection 5 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 RDIP Read in Progress (this bit is read-only) 22 1 read-write DONE No active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 SIF Channel x Source Interface Identifier 13 1 read-write AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 read-write MEM_TRAN Self-triggered mode (memory-to-memory transfer). 0 PER_TRAN Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 read-write DONE No active write transaction on the bus. 0 IN_PROGRESS A write transaction is in progress. 1 CC4 Channel Configuration Register (chid = 4) 0x178 32 read-write n 0x0 0x0 CSIZE Channel x Chunk Size 8 3 read-write CHK_1 1 data transferred 0x0 CHK_2 2 data transferred 0x1 CHK_4 4 data transferred 0x2 CHK_8 8 data transferred 0x3 CHK_16 16 data transferred 0x4 DAM Channel x Destination Addressing Mode 18 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary; the data stride is added at the data boundary. 0x3 DIF Channel x Destination Interface Identifier 14 1 read-write AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 read-write PER2MEM Peripheral-to-memory transfer. 0 MEM2PER Memory-to-peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 read-write BYTE The data size is set to 8 bits 0x0 HALFWORD The data size is set to 16 bits 0x1 WORD The data size is set to 32 bits 0x2 DWORD The data size is set to 64 bits 0x3 INITD Channel Initialization Done (this bit is read-only) 21 1 read-write IN_PROGRESS Channel initialization is in progress. 0 TERMINATED Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 read-write SINGLE The memory burst size is set to one. 0x0 FOUR The memory burst size is set to four. 0x1 EIGHT The memory burst size is set to eight. 0x2 SIXTEEN The memory burst size is set to sixteen. 0x3 MEMSET Channel x Fill Block of Memory 7 1 read-write NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 read-write PROT Channel x Protection 5 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 RDIP Read in Progress (this bit is read-only) 22 1 read-write DONE No active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 SIF Channel x Source Interface Identifier 13 1 read-write AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 read-write MEM_TRAN Self-triggered mode (memory-to-memory transfer). 0 PER_TRAN Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 read-write DONE No active write transaction on the bus. 0 IN_PROGRESS A write transaction is in progress. 1 CC5 Channel Configuration Register (chid = 5) 0x1B8 32 read-write n 0x0 0x0 CSIZE Channel x Chunk Size 8 3 read-write CHK_1 1 data transferred 0x0 CHK_2 2 data transferred 0x1 CHK_4 4 data transferred 0x2 CHK_8 8 data transferred 0x3 CHK_16 16 data transferred 0x4 DAM Channel x Destination Addressing Mode 18 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary; the data stride is added at the data boundary. 0x3 DIF Channel x Destination Interface Identifier 14 1 read-write AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 read-write PER2MEM Peripheral-to-memory transfer. 0 MEM2PER Memory-to-peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 read-write BYTE The data size is set to 8 bits 0x0 HALFWORD The data size is set to 16 bits 0x1 WORD The data size is set to 32 bits 0x2 DWORD The data size is set to 64 bits 0x3 INITD Channel Initialization Done (this bit is read-only) 21 1 read-write IN_PROGRESS Channel initialization is in progress. 0 TERMINATED Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 read-write SINGLE The memory burst size is set to one. 0x0 FOUR The memory burst size is set to four. 0x1 EIGHT The memory burst size is set to eight. 0x2 SIXTEEN The memory burst size is set to sixteen. 0x3 MEMSET Channel x Fill Block of Memory 7 1 read-write NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 read-write PROT Channel x Protection 5 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 RDIP Read in Progress (this bit is read-only) 22 1 read-write DONE No active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 SIF Channel x Source Interface Identifier 13 1 read-write AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 read-write MEM_TRAN Self-triggered mode (memory-to-memory transfer). 0 PER_TRAN Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 read-write DONE No active write transaction on the bus. 0 IN_PROGRESS A write transaction is in progress. 1 CC6 Channel Configuration Register (chid = 6) 0x1F8 32 read-write n 0x0 0x0 CSIZE Channel x Chunk Size 8 3 read-write CHK_1 1 data transferred 0x0 CHK_2 2 data transferred 0x1 CHK_4 4 data transferred 0x2 CHK_8 8 data transferred 0x3 CHK_16 16 data transferred 0x4 DAM Channel x Destination Addressing Mode 18 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary; the data stride is added at the data boundary. 0x3 DIF Channel x Destination Interface Identifier 14 1 read-write AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 read-write PER2MEM Peripheral-to-memory transfer. 0 MEM2PER Memory-to-peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 read-write BYTE The data size is set to 8 bits 0x0 HALFWORD The data size is set to 16 bits 0x1 WORD The data size is set to 32 bits 0x2 DWORD The data size is set to 64 bits 0x3 INITD Channel Initialization Done (this bit is read-only) 21 1 read-write IN_PROGRESS Channel initialization is in progress. 0 TERMINATED Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 read-write SINGLE The memory burst size is set to one. 0x0 FOUR The memory burst size is set to four. 0x1 EIGHT The memory burst size is set to eight. 0x2 SIXTEEN The memory burst size is set to sixteen. 0x3 MEMSET Channel x Fill Block of Memory 7 1 read-write NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 read-write PROT Channel x Protection 5 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 RDIP Read in Progress (this bit is read-only) 22 1 read-write DONE No active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 SIF Channel x Source Interface Identifier 13 1 read-write AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 read-write MEM_TRAN Self-triggered mode (memory-to-memory transfer). 0 PER_TRAN Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 read-write DONE No active write transaction on the bus. 0 IN_PROGRESS A write transaction is in progress. 1 CC7 Channel Configuration Register (chid = 7) 0x238 32 read-write n 0x0 0x0 CSIZE Channel x Chunk Size 8 3 read-write CHK_1 1 data transferred 0x0 CHK_2 2 data transferred 0x1 CHK_4 4 data transferred 0x2 CHK_8 8 data transferred 0x3 CHK_16 16 data transferred 0x4 DAM Channel x Destination Addressing Mode 18 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary; the data stride is added at the data boundary. 0x3 DIF Channel x Destination Interface Identifier 14 1 read-write AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 read-write PER2MEM Peripheral-to-memory transfer. 0 MEM2PER Memory-to-peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 read-write BYTE The data size is set to 8 bits 0x0 HALFWORD The data size is set to 16 bits 0x1 WORD The data size is set to 32 bits 0x2 DWORD The data size is set to 64 bits 0x3 INITD Channel Initialization Done (this bit is read-only) 21 1 read-write IN_PROGRESS Channel initialization is in progress. 0 TERMINATED Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 read-write SINGLE The memory burst size is set to one. 0x0 FOUR The memory burst size is set to four. 0x1 EIGHT The memory burst size is set to eight. 0x2 SIXTEEN The memory burst size is set to sixteen. 0x3 MEMSET Channel x Fill Block of Memory 7 1 read-write NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 read-write PROT Channel x Protection 5 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 RDIP Read in Progress (this bit is read-only) 22 1 read-write DONE No active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 SIF Channel x Source Interface Identifier 13 1 read-write AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 read-write MEM_TRAN Self-triggered mode (memory-to-memory transfer). 0 PER_TRAN Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 read-write DONE No active write transaction on the bus. 0 IN_PROGRESS A write transaction is in progress. 1 CC8 Channel Configuration Register (chid = 8) 0x278 32 read-write n 0x0 0x0 CSIZE Channel x Chunk Size 8 3 read-write CHK_1 1 data transferred 0x0 CHK_2 2 data transferred 0x1 CHK_4 4 data transferred 0x2 CHK_8 8 data transferred 0x3 CHK_16 16 data transferred 0x4 DAM Channel x Destination Addressing Mode 18 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary; the data stride is added at the data boundary. 0x3 DIF Channel x Destination Interface Identifier 14 1 read-write AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 read-write PER2MEM Peripheral-to-memory transfer. 0 MEM2PER Memory-to-peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 read-write BYTE The data size is set to 8 bits 0x0 HALFWORD The data size is set to 16 bits 0x1 WORD The data size is set to 32 bits 0x2 DWORD The data size is set to 64 bits 0x3 INITD Channel Initialization Done (this bit is read-only) 21 1 read-write IN_PROGRESS Channel initialization is in progress. 0 TERMINATED Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 read-write SINGLE The memory burst size is set to one. 0x0 FOUR The memory burst size is set to four. 0x1 EIGHT The memory burst size is set to eight. 0x2 SIXTEEN The memory burst size is set to sixteen. 0x3 MEMSET Channel x Fill Block of Memory 7 1 read-write NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 read-write PROT Channel x Protection 5 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 RDIP Read in Progress (this bit is read-only) 22 1 read-write DONE No active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 SIF Channel x Source Interface Identifier 13 1 read-write AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 read-write MEM_TRAN Self-triggered mode (memory-to-memory transfer). 0 PER_TRAN Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 read-write DONE No active write transaction on the bus. 0 IN_PROGRESS A write transaction is in progress. 1 CC9 Channel Configuration Register (chid = 9) 0x2B8 32 read-write n 0x0 0x0 CSIZE Channel x Chunk Size 8 3 read-write CHK_1 1 data transferred 0x0 CHK_2 2 data transferred 0x1 CHK_4 4 data transferred 0x2 CHK_8 8 data transferred 0x3 CHK_16 16 data transferred 0x4 DAM Channel x Destination Addressing Mode 18 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary; the data stride is added at the data boundary. 0x3 DIF Channel x Destination Interface Identifier 14 1 read-write AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 read-write PER2MEM Peripheral-to-memory transfer. 0 MEM2PER Memory-to-peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 read-write BYTE The data size is set to 8 bits 0x0 HALFWORD The data size is set to 16 bits 0x1 WORD The data size is set to 32 bits 0x2 DWORD The data size is set to 64 bits 0x3 INITD Channel Initialization Done (this bit is read-only) 21 1 read-write IN_PROGRESS Channel initialization is in progress. 0 TERMINATED Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 read-write SINGLE The memory burst size is set to one. 0x0 FOUR The memory burst size is set to four. 0x1 EIGHT The memory burst size is set to eight. 0x2 SIXTEEN The memory burst size is set to sixteen. 0x3 MEMSET Channel x Fill Block of Memory 7 1 read-write NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 read-write PROT Channel x Protection 5 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 RDIP Read in Progress (this bit is read-only) 22 1 read-write DONE No active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 SIF Channel x Source Interface Identifier 13 1 read-write AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 read-write MEM_TRAN Self-triggered mode (memory-to-memory transfer). 0 PER_TRAN Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 read-write DONE No active write transaction on the bus. 0 IN_PROGRESS A write transaction is in progress. 1 CDA0 Channel Destination Address Register (chid = 0) 0x64 32 read-write n 0x0 0x0 DA Channel x Destination Address 0 32 read-write CDA1 Channel Destination Address Register (chid = 1) 0xA4 32 read-write n 0x0 0x0 DA Channel x Destination Address 0 32 read-write CDA10 Channel Destination Address Register (chid = 10) 0x2E4 32 read-write n 0x0 0x0 DA Channel x Destination Address 0 32 read-write CDA11 Channel Destination Address Register (chid = 11) 0x324 32 read-write n 0x0 0x0 DA Channel x Destination Address 0 32 read-write CDA12 Channel Destination Address Register (chid = 12) 0x364 32 read-write n 0x0 0x0 DA Channel x Destination Address 0 32 read-write CDA13 Channel Destination Address Register (chid = 13) 0x3A4 32 read-write n 0x0 0x0 DA Channel x Destination Address 0 32 read-write CDA14 Channel Destination Address Register (chid = 14) 0x3E4 32 read-write n 0x0 0x0 DA Channel x Destination Address 0 32 read-write CDA15 Channel Destination Address Register (chid = 15) 0x424 32 read-write n 0x0 0x0 DA Channel x Destination Address 0 32 read-write CDA2 Channel Destination Address Register (chid = 2) 0xE4 32 read-write n 0x0 0x0 DA Channel x Destination Address 0 32 read-write CDA3 Channel Destination Address Register (chid = 3) 0x124 32 read-write n 0x0 0x0 DA Channel x Destination Address 0 32 read-write CDA4 Channel Destination Address Register (chid = 4) 0x164 32 read-write n 0x0 0x0 DA Channel x Destination Address 0 32 read-write CDA5 Channel Destination Address Register (chid = 5) 0x1A4 32 read-write n 0x0 0x0 DA Channel x Destination Address 0 32 read-write CDA6 Channel Destination Address Register (chid = 6) 0x1E4 32 read-write n 0x0 0x0 DA Channel x Destination Address 0 32 read-write CDA7 Channel Destination Address Register (chid = 7) 0x224 32 read-write n 0x0 0x0 DA Channel x Destination Address 0 32 read-write CDA8 Channel Destination Address Register (chid = 8) 0x264 32 read-write n 0x0 0x0 DA Channel x Destination Address 0 32 read-write CDA9 Channel Destination Address Register (chid = 9) 0x2A4 32 read-write n 0x0 0x0 DA Channel x Destination Address 0 32 read-write CDS_MSP0 Channel Data Stride Memory Set Pattern (chid = 0) 0x7C 32 read-write n 0x0 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 read-write SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 read-write CDS_MSP1 Channel Data Stride Memory Set Pattern (chid = 1) 0xBC 32 read-write n 0x0 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 read-write SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 read-write CDS_MSP10 Channel Data Stride Memory Set Pattern (chid = 10) 0x2FC 32 read-write n 0x0 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 read-write SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 read-write CDS_MSP11 Channel Data Stride Memory Set Pattern (chid = 11) 0x33C 32 read-write n 0x0 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 read-write SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 read-write CDS_MSP12 Channel Data Stride Memory Set Pattern (chid = 12) 0x37C 32 read-write n 0x0 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 read-write SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 read-write CDS_MSP13 Channel Data Stride Memory Set Pattern (chid = 13) 0x3BC 32 read-write n 0x0 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 read-write SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 read-write CDS_MSP14 Channel Data Stride Memory Set Pattern (chid = 14) 0x3FC 32 read-write n 0x0 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 read-write SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 read-write CDS_MSP15 Channel Data Stride Memory Set Pattern (chid = 15) 0x43C 32 read-write n 0x0 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 read-write SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 read-write CDS_MSP2 Channel Data Stride Memory Set Pattern (chid = 2) 0xFC 32 read-write n 0x0 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 read-write SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 read-write CDS_MSP3 Channel Data Stride Memory Set Pattern (chid = 3) 0x13C 32 read-write n 0x0 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 read-write SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 read-write CDS_MSP4 Channel Data Stride Memory Set Pattern (chid = 4) 0x17C 32 read-write n 0x0 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 read-write SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 read-write CDS_MSP5 Channel Data Stride Memory Set Pattern (chid = 5) 0x1BC 32 read-write n 0x0 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 read-write SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 read-write CDS_MSP6 Channel Data Stride Memory Set Pattern (chid = 6) 0x1FC 32 read-write n 0x0 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 read-write SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 read-write CDS_MSP7 Channel Data Stride Memory Set Pattern (chid = 7) 0x23C 32 read-write n 0x0 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 read-write SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 read-write CDS_MSP8 Channel Data Stride Memory Set Pattern (chid = 8) 0x27C 32 read-write n 0x0 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 read-write SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 read-write CDS_MSP9 Channel Data Stride Memory Set Pattern (chid = 9) 0x2BC 32 read-write n 0x0 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 read-write SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 read-write CDUS0 Channel Destination Microblock Stride (chid = 0) 0x84 32 read-write n 0x0 0x0 DUBS Channel x Destination Microblock Stride 0 24 read-write CDUS1 Channel Destination Microblock Stride (chid = 1) 0xC4 32 read-write n 0x0 0x0 DUBS Channel x Destination Microblock Stride 0 24 read-write CDUS10 Channel Destination Microblock Stride (chid = 10) 0x304 32 read-write n 0x0 0x0 DUBS Channel x Destination Microblock Stride 0 24 read-write CDUS11 Channel Destination Microblock Stride (chid = 11) 0x344 32 read-write n 0x0 0x0 DUBS Channel x Destination Microblock Stride 0 24 read-write CDUS12 Channel Destination Microblock Stride (chid = 12) 0x384 32 read-write n 0x0 0x0 DUBS Channel x Destination Microblock Stride 0 24 read-write CDUS13 Channel Destination Microblock Stride (chid = 13) 0x3C4 32 read-write n 0x0 0x0 DUBS Channel x Destination Microblock Stride 0 24 read-write CDUS14 Channel Destination Microblock Stride (chid = 14) 0x404 32 read-write n 0x0 0x0 DUBS Channel x Destination Microblock Stride 0 24 read-write CDUS15 Channel Destination Microblock Stride (chid = 15) 0x444 32 read-write n 0x0 0x0 DUBS Channel x Destination Microblock Stride 0 24 read-write CDUS2 Channel Destination Microblock Stride (chid = 2) 0x104 32 read-write n 0x0 0x0 DUBS Channel x Destination Microblock Stride 0 24 read-write CDUS3 Channel Destination Microblock Stride (chid = 3) 0x144 32 read-write n 0x0 0x0 DUBS Channel x Destination Microblock Stride 0 24 read-write CDUS4 Channel Destination Microblock Stride (chid = 4) 0x184 32 read-write n 0x0 0x0 DUBS Channel x Destination Microblock Stride 0 24 read-write CDUS5 Channel Destination Microblock Stride (chid = 5) 0x1C4 32 read-write n 0x0 0x0 DUBS Channel x Destination Microblock Stride 0 24 read-write CDUS6 Channel Destination Microblock Stride (chid = 6) 0x204 32 read-write n 0x0 0x0 DUBS Channel x Destination Microblock Stride 0 24 read-write CDUS7 Channel Destination Microblock Stride (chid = 7) 0x244 32 read-write n 0x0 0x0 DUBS Channel x Destination Microblock Stride 0 24 read-write CDUS8 Channel Destination Microblock Stride (chid = 8) 0x284 32 read-write n 0x0 0x0 DUBS Channel x Destination Microblock Stride 0 24 read-write CDUS9 Channel Destination Microblock Stride (chid = 9) 0x2C4 32 read-write n 0x0 0x0 DUBS Channel x Destination Microblock Stride 0 24 read-write CID0 Channel Interrupt Disable Register (chid = 0) 0x54 32 write-only n 0x0 0x0 BID End of Block Interrupt Disable Bit 0 1 write-only DID End of Disable Interrupt Disable Bit 2 1 write-only FID End of Flush Interrupt Disable Bit 3 1 write-only LID End of Linked List Interrupt Disable Bit 1 1 write-only RBEID Read Bus Error Interrupt Disable Bit 4 1 write-only ROID Request Overflow Error Interrupt Disable Bit 6 1 write-only WBEID Write Bus Error Interrupt Disable Bit 5 1 write-only CID1 Channel Interrupt Disable Register (chid = 1) 0x94 32 write-only n 0x0 0x0 BID End of Block Interrupt Disable Bit 0 1 write-only DID End of Disable Interrupt Disable Bit 2 1 write-only FID End of Flush Interrupt Disable Bit 3 1 write-only LID End of Linked List Interrupt Disable Bit 1 1 write-only RBEID Read Bus Error Interrupt Disable Bit 4 1 write-only ROID Request Overflow Error Interrupt Disable Bit 6 1 write-only WBEID Write Bus Error Interrupt Disable Bit 5 1 write-only CID10 Channel Interrupt Disable Register (chid = 10) 0x2D4 32 write-only n 0x0 0x0 BID End of Block Interrupt Disable Bit 0 1 write-only DID End of Disable Interrupt Disable Bit 2 1 write-only FID End of Flush Interrupt Disable Bit 3 1 write-only LID End of Linked List Interrupt Disable Bit 1 1 write-only RBEID Read Bus Error Interrupt Disable Bit 4 1 write-only ROID Request Overflow Error Interrupt Disable Bit 6 1 write-only WBEID Write Bus Error Interrupt Disable Bit 5 1 write-only CID11 Channel Interrupt Disable Register (chid = 11) 0x314 32 write-only n 0x0 0x0 BID End of Block Interrupt Disable Bit 0 1 write-only DID End of Disable Interrupt Disable Bit 2 1 write-only FID End of Flush Interrupt Disable Bit 3 1 write-only LID End of Linked List Interrupt Disable Bit 1 1 write-only RBEID Read Bus Error Interrupt Disable Bit 4 1 write-only ROID Request Overflow Error Interrupt Disable Bit 6 1 write-only WBEID Write Bus Error Interrupt Disable Bit 5 1 write-only CID12 Channel Interrupt Disable Register (chid = 12) 0x354 32 write-only n 0x0 0x0 BID End of Block Interrupt Disable Bit 0 1 write-only DID End of Disable Interrupt Disable Bit 2 1 write-only FID End of Flush Interrupt Disable Bit 3 1 write-only LID End of Linked List Interrupt Disable Bit 1 1 write-only RBEID Read Bus Error Interrupt Disable Bit 4 1 write-only ROID Request Overflow Error Interrupt Disable Bit 6 1 write-only WBEID Write Bus Error Interrupt Disable Bit 5 1 write-only CID13 Channel Interrupt Disable Register (chid = 13) 0x394 32 write-only n 0x0 0x0 BID End of Block Interrupt Disable Bit 0 1 write-only DID End of Disable Interrupt Disable Bit 2 1 write-only FID End of Flush Interrupt Disable Bit 3 1 write-only LID End of Linked List Interrupt Disable Bit 1 1 write-only RBEID Read Bus Error Interrupt Disable Bit 4 1 write-only ROID Request Overflow Error Interrupt Disable Bit 6 1 write-only WBEID Write Bus Error Interrupt Disable Bit 5 1 write-only CID14 Channel Interrupt Disable Register (chid = 14) 0x3D4 32 write-only n 0x0 0x0 BID End of Block Interrupt Disable Bit 0 1 write-only DID End of Disable Interrupt Disable Bit 2 1 write-only FID End of Flush Interrupt Disable Bit 3 1 write-only LID End of Linked List Interrupt Disable Bit 1 1 write-only RBEID Read Bus Error Interrupt Disable Bit 4 1 write-only ROID Request Overflow Error Interrupt Disable Bit 6 1 write-only WBEID Write Bus Error Interrupt Disable Bit 5 1 write-only CID15 Channel Interrupt Disable Register (chid = 15) 0x414 32 write-only n 0x0 0x0 BID End of Block Interrupt Disable Bit 0 1 write-only DID End of Disable Interrupt Disable Bit 2 1 write-only FID End of Flush Interrupt Disable Bit 3 1 write-only LID End of Linked List Interrupt Disable Bit 1 1 write-only RBEID Read Bus Error Interrupt Disable Bit 4 1 write-only ROID Request Overflow Error Interrupt Disable Bit 6 1 write-only WBEID Write Bus Error Interrupt Disable Bit 5 1 write-only CID2 Channel Interrupt Disable Register (chid = 2) 0xD4 32 write-only n 0x0 0x0 BID End of Block Interrupt Disable Bit 0 1 write-only DID End of Disable Interrupt Disable Bit 2 1 write-only FID End of Flush Interrupt Disable Bit 3 1 write-only LID End of Linked List Interrupt Disable Bit 1 1 write-only RBEID Read Bus Error Interrupt Disable Bit 4 1 write-only ROID Request Overflow Error Interrupt Disable Bit 6 1 write-only WBEID Write Bus Error Interrupt Disable Bit 5 1 write-only CID3 Channel Interrupt Disable Register (chid = 3) 0x114 32 write-only n 0x0 0x0 BID End of Block Interrupt Disable Bit 0 1 write-only DID End of Disable Interrupt Disable Bit 2 1 write-only FID End of Flush Interrupt Disable Bit 3 1 write-only LID End of Linked List Interrupt Disable Bit 1 1 write-only RBEID Read Bus Error Interrupt Disable Bit 4 1 write-only ROID Request Overflow Error Interrupt Disable Bit 6 1 write-only WBEID Write Bus Error Interrupt Disable Bit 5 1 write-only CID4 Channel Interrupt Disable Register (chid = 4) 0x154 32 write-only n 0x0 0x0 BID End of Block Interrupt Disable Bit 0 1 write-only DID End of Disable Interrupt Disable Bit 2 1 write-only FID End of Flush Interrupt Disable Bit 3 1 write-only LID End of Linked List Interrupt Disable Bit 1 1 write-only RBEID Read Bus Error Interrupt Disable Bit 4 1 write-only ROID Request Overflow Error Interrupt Disable Bit 6 1 write-only WBEID Write Bus Error Interrupt Disable Bit 5 1 write-only CID5 Channel Interrupt Disable Register (chid = 5) 0x194 32 write-only n 0x0 0x0 BID End of Block Interrupt Disable Bit 0 1 write-only DID End of Disable Interrupt Disable Bit 2 1 write-only FID End of Flush Interrupt Disable Bit 3 1 write-only LID End of Linked List Interrupt Disable Bit 1 1 write-only RBEID Read Bus Error Interrupt Disable Bit 4 1 write-only ROID Request Overflow Error Interrupt Disable Bit 6 1 write-only WBEID Write Bus Error Interrupt Disable Bit 5 1 write-only CID6 Channel Interrupt Disable Register (chid = 6) 0x1D4 32 write-only n 0x0 0x0 BID End of Block Interrupt Disable Bit 0 1 write-only DID End of Disable Interrupt Disable Bit 2 1 write-only FID End of Flush Interrupt Disable Bit 3 1 write-only LID End of Linked List Interrupt Disable Bit 1 1 write-only RBEID Read Bus Error Interrupt Disable Bit 4 1 write-only ROID Request Overflow Error Interrupt Disable Bit 6 1 write-only WBEID Write Bus Error Interrupt Disable Bit 5 1 write-only CID7 Channel Interrupt Disable Register (chid = 7) 0x214 32 write-only n 0x0 0x0 BID End of Block Interrupt Disable Bit 0 1 write-only DID End of Disable Interrupt Disable Bit 2 1 write-only FID End of Flush Interrupt Disable Bit 3 1 write-only LID End of Linked List Interrupt Disable Bit 1 1 write-only RBEID Read Bus Error Interrupt Disable Bit 4 1 write-only ROID Request Overflow Error Interrupt Disable Bit 6 1 write-only WBEID Write Bus Error Interrupt Disable Bit 5 1 write-only CID8 Channel Interrupt Disable Register (chid = 8) 0x254 32 write-only n 0x0 0x0 BID End of Block Interrupt Disable Bit 0 1 write-only DID End of Disable Interrupt Disable Bit 2 1 write-only FID End of Flush Interrupt Disable Bit 3 1 write-only LID End of Linked List Interrupt Disable Bit 1 1 write-only RBEID Read Bus Error Interrupt Disable Bit 4 1 write-only ROID Request Overflow Error Interrupt Disable Bit 6 1 write-only WBEID Write Bus Error Interrupt Disable Bit 5 1 write-only CID9 Channel Interrupt Disable Register (chid = 9) 0x294 32 write-only n 0x0 0x0 BID End of Block Interrupt Disable Bit 0 1 write-only DID End of Disable Interrupt Disable Bit 2 1 write-only FID End of Flush Interrupt Disable Bit 3 1 write-only LID End of Linked List Interrupt Disable Bit 1 1 write-only RBEID Read Bus Error Interrupt Disable Bit 4 1 write-only ROID Request Overflow Error Interrupt Disable Bit 6 1 write-only WBEID Write Bus Error Interrupt Disable Bit 5 1 write-only CIE0 Channel Interrupt Enable Register (chid = 0) 0x50 32 write-only n 0x0 0x0 BIE End of Block Interrupt Enable Bit 0 1 write-only DIE End of Disable Interrupt Enable Bit 2 1 write-only FIE End of Flush Interrupt Enable Bit 3 1 write-only LIE End of Linked List Interrupt Enable Bit 1 1 write-only RBIE Read Bus Error Interrupt Enable Bit 4 1 write-only ROIE Request Overflow Error Interrupt Enable Bit 6 1 write-only WBIE Write Bus Error Interrupt Enable Bit 5 1 write-only CIE1 Channel Interrupt Enable Register (chid = 1) 0x90 32 write-only n 0x0 0x0 BIE End of Block Interrupt Enable Bit 0 1 write-only DIE End of Disable Interrupt Enable Bit 2 1 write-only FIE End of Flush Interrupt Enable Bit 3 1 write-only LIE End of Linked List Interrupt Enable Bit 1 1 write-only RBIE Read Bus Error Interrupt Enable Bit 4 1 write-only ROIE Request Overflow Error Interrupt Enable Bit 6 1 write-only WBIE Write Bus Error Interrupt Enable Bit 5 1 write-only CIE10 Channel Interrupt Enable Register (chid = 10) 0x2D0 32 write-only n 0x0 0x0 BIE End of Block Interrupt Enable Bit 0 1 write-only DIE End of Disable Interrupt Enable Bit 2 1 write-only FIE End of Flush Interrupt Enable Bit 3 1 write-only LIE End of Linked List Interrupt Enable Bit 1 1 write-only RBIE Read Bus Error Interrupt Enable Bit 4 1 write-only ROIE Request Overflow Error Interrupt Enable Bit 6 1 write-only WBIE Write Bus Error Interrupt Enable Bit 5 1 write-only CIE11 Channel Interrupt Enable Register (chid = 11) 0x310 32 write-only n 0x0 0x0 BIE End of Block Interrupt Enable Bit 0 1 write-only DIE End of Disable Interrupt Enable Bit 2 1 write-only FIE End of Flush Interrupt Enable Bit 3 1 write-only LIE End of Linked List Interrupt Enable Bit 1 1 write-only RBIE Read Bus Error Interrupt Enable Bit 4 1 write-only ROIE Request Overflow Error Interrupt Enable Bit 6 1 write-only WBIE Write Bus Error Interrupt Enable Bit 5 1 write-only CIE12 Channel Interrupt Enable Register (chid = 12) 0x350 32 write-only n 0x0 0x0 BIE End of Block Interrupt Enable Bit 0 1 write-only DIE End of Disable Interrupt Enable Bit 2 1 write-only FIE End of Flush Interrupt Enable Bit 3 1 write-only LIE End of Linked List Interrupt Enable Bit 1 1 write-only RBIE Read Bus Error Interrupt Enable Bit 4 1 write-only ROIE Request Overflow Error Interrupt Enable Bit 6 1 write-only WBIE Write Bus Error Interrupt Enable Bit 5 1 write-only CIE13 Channel Interrupt Enable Register (chid = 13) 0x390 32 write-only n 0x0 0x0 BIE End of Block Interrupt Enable Bit 0 1 write-only DIE End of Disable Interrupt Enable Bit 2 1 write-only FIE End of Flush Interrupt Enable Bit 3 1 write-only LIE End of Linked List Interrupt Enable Bit 1 1 write-only RBIE Read Bus Error Interrupt Enable Bit 4 1 write-only ROIE Request Overflow Error Interrupt Enable Bit 6 1 write-only WBIE Write Bus Error Interrupt Enable Bit 5 1 write-only CIE14 Channel Interrupt Enable Register (chid = 14) 0x3D0 32 write-only n 0x0 0x0 BIE End of Block Interrupt Enable Bit 0 1 write-only DIE End of Disable Interrupt Enable Bit 2 1 write-only FIE End of Flush Interrupt Enable Bit 3 1 write-only LIE End of Linked List Interrupt Enable Bit 1 1 write-only RBIE Read Bus Error Interrupt Enable Bit 4 1 write-only ROIE Request Overflow Error Interrupt Enable Bit 6 1 write-only WBIE Write Bus Error Interrupt Enable Bit 5 1 write-only CIE15 Channel Interrupt Enable Register (chid = 15) 0x410 32 write-only n 0x0 0x0 BIE End of Block Interrupt Enable Bit 0 1 write-only DIE End of Disable Interrupt Enable Bit 2 1 write-only FIE End of Flush Interrupt Enable Bit 3 1 write-only LIE End of Linked List Interrupt Enable Bit 1 1 write-only RBIE Read Bus Error Interrupt Enable Bit 4 1 write-only ROIE Request Overflow Error Interrupt Enable Bit 6 1 write-only WBIE Write Bus Error Interrupt Enable Bit 5 1 write-only CIE2 Channel Interrupt Enable Register (chid = 2) 0xD0 32 write-only n 0x0 0x0 BIE End of Block Interrupt Enable Bit 0 1 write-only DIE End of Disable Interrupt Enable Bit 2 1 write-only FIE End of Flush Interrupt Enable Bit 3 1 write-only LIE End of Linked List Interrupt Enable Bit 1 1 write-only RBIE Read Bus Error Interrupt Enable Bit 4 1 write-only ROIE Request Overflow Error Interrupt Enable Bit 6 1 write-only WBIE Write Bus Error Interrupt Enable Bit 5 1 write-only CIE3 Channel Interrupt Enable Register (chid = 3) 0x110 32 write-only n 0x0 0x0 BIE End of Block Interrupt Enable Bit 0 1 write-only DIE End of Disable Interrupt Enable Bit 2 1 write-only FIE End of Flush Interrupt Enable Bit 3 1 write-only LIE End of Linked List Interrupt Enable Bit 1 1 write-only RBIE Read Bus Error Interrupt Enable Bit 4 1 write-only ROIE Request Overflow Error Interrupt Enable Bit 6 1 write-only WBIE Write Bus Error Interrupt Enable Bit 5 1 write-only CIE4 Channel Interrupt Enable Register (chid = 4) 0x150 32 write-only n 0x0 0x0 BIE End of Block Interrupt Enable Bit 0 1 write-only DIE End of Disable Interrupt Enable Bit 2 1 write-only FIE End of Flush Interrupt Enable Bit 3 1 write-only LIE End of Linked List Interrupt Enable Bit 1 1 write-only RBIE Read Bus Error Interrupt Enable Bit 4 1 write-only ROIE Request Overflow Error Interrupt Enable Bit 6 1 write-only WBIE Write Bus Error Interrupt Enable Bit 5 1 write-only CIE5 Channel Interrupt Enable Register (chid = 5) 0x190 32 write-only n 0x0 0x0 BIE End of Block Interrupt Enable Bit 0 1 write-only DIE End of Disable Interrupt Enable Bit 2 1 write-only FIE End of Flush Interrupt Enable Bit 3 1 write-only LIE End of Linked List Interrupt Enable Bit 1 1 write-only RBIE Read Bus Error Interrupt Enable Bit 4 1 write-only ROIE Request Overflow Error Interrupt Enable Bit 6 1 write-only WBIE Write Bus Error Interrupt Enable Bit 5 1 write-only CIE6 Channel Interrupt Enable Register (chid = 6) 0x1D0 32 write-only n 0x0 0x0 BIE End of Block Interrupt Enable Bit 0 1 write-only DIE End of Disable Interrupt Enable Bit 2 1 write-only FIE End of Flush Interrupt Enable Bit 3 1 write-only LIE End of Linked List Interrupt Enable Bit 1 1 write-only RBIE Read Bus Error Interrupt Enable Bit 4 1 write-only ROIE Request Overflow Error Interrupt Enable Bit 6 1 write-only WBIE Write Bus Error Interrupt Enable Bit 5 1 write-only CIE7 Channel Interrupt Enable Register (chid = 7) 0x210 32 write-only n 0x0 0x0 BIE End of Block Interrupt Enable Bit 0 1 write-only DIE End of Disable Interrupt Enable Bit 2 1 write-only FIE End of Flush Interrupt Enable Bit 3 1 write-only LIE End of Linked List Interrupt Enable Bit 1 1 write-only RBIE Read Bus Error Interrupt Enable Bit 4 1 write-only ROIE Request Overflow Error Interrupt Enable Bit 6 1 write-only WBIE Write Bus Error Interrupt Enable Bit 5 1 write-only CIE8 Channel Interrupt Enable Register (chid = 8) 0x250 32 write-only n 0x0 0x0 BIE End of Block Interrupt Enable Bit 0 1 write-only DIE End of Disable Interrupt Enable Bit 2 1 write-only FIE End of Flush Interrupt Enable Bit 3 1 write-only LIE End of Linked List Interrupt Enable Bit 1 1 write-only RBIE Read Bus Error Interrupt Enable Bit 4 1 write-only ROIE Request Overflow Error Interrupt Enable Bit 6 1 write-only WBIE Write Bus Error Interrupt Enable Bit 5 1 write-only CIE9 Channel Interrupt Enable Register (chid = 9) 0x290 32 write-only n 0x0 0x0 BIE End of Block Interrupt Enable Bit 0 1 write-only DIE End of Disable Interrupt Enable Bit 2 1 write-only FIE End of Flush Interrupt Enable Bit 3 1 write-only LIE End of Linked List Interrupt Enable Bit 1 1 write-only RBIE Read Bus Error Interrupt Enable Bit 4 1 write-only ROIE Request Overflow Error Interrupt Enable Bit 6 1 write-only WBIE Write Bus Error Interrupt Enable Bit 5 1 write-only CIM0 Channel Interrupt Mask Register (chid = 0) 0x58 32 read-only n 0x0 0x0 BIM End of Block Interrupt Mask Bit 0 1 read-only DIM End of Disable Interrupt Mask Bit 2 1 read-only FIM End of Flush Interrupt Mask Bit 3 1 read-only LIM End of Linked List Interrupt Mask Bit 1 1 read-only RBEIM Read Bus Error Interrupt Mask Bit 4 1 read-only ROIM Request Overflow Error Interrupt Mask Bit 6 1 read-only WBEIM Write Bus Error Interrupt Mask Bit 5 1 read-only CIM1 Channel Interrupt Mask Register (chid = 1) 0x98 32 read-only n 0x0 0x0 BIM End of Block Interrupt Mask Bit 0 1 read-only DIM End of Disable Interrupt Mask Bit 2 1 read-only FIM End of Flush Interrupt Mask Bit 3 1 read-only LIM End of Linked List Interrupt Mask Bit 1 1 read-only RBEIM Read Bus Error Interrupt Mask Bit 4 1 read-only ROIM Request Overflow Error Interrupt Mask Bit 6 1 read-only WBEIM Write Bus Error Interrupt Mask Bit 5 1 read-only CIM10 Channel Interrupt Mask Register (chid = 10) 0x2D8 32 read-only n 0x0 0x0 BIM End of Block Interrupt Mask Bit 0 1 read-only DIM End of Disable Interrupt Mask Bit 2 1 read-only FIM End of Flush Interrupt Mask Bit 3 1 read-only LIM End of Linked List Interrupt Mask Bit 1 1 read-only RBEIM Read Bus Error Interrupt Mask Bit 4 1 read-only ROIM Request Overflow Error Interrupt Mask Bit 6 1 read-only WBEIM Write Bus Error Interrupt Mask Bit 5 1 read-only CIM11 Channel Interrupt Mask Register (chid = 11) 0x318 32 read-only n 0x0 0x0 BIM End of Block Interrupt Mask Bit 0 1 read-only DIM End of Disable Interrupt Mask Bit 2 1 read-only FIM End of Flush Interrupt Mask Bit 3 1 read-only LIM End of Linked List Interrupt Mask Bit 1 1 read-only RBEIM Read Bus Error Interrupt Mask Bit 4 1 read-only ROIM Request Overflow Error Interrupt Mask Bit 6 1 read-only WBEIM Write Bus Error Interrupt Mask Bit 5 1 read-only CIM12 Channel Interrupt Mask Register (chid = 12) 0x358 32 read-only n 0x0 0x0 BIM End of Block Interrupt Mask Bit 0 1 read-only DIM End of Disable Interrupt Mask Bit 2 1 read-only FIM End of Flush Interrupt Mask Bit 3 1 read-only LIM End of Linked List Interrupt Mask Bit 1 1 read-only RBEIM Read Bus Error Interrupt Mask Bit 4 1 read-only ROIM Request Overflow Error Interrupt Mask Bit 6 1 read-only WBEIM Write Bus Error Interrupt Mask Bit 5 1 read-only CIM13 Channel Interrupt Mask Register (chid = 13) 0x398 32 read-only n 0x0 0x0 BIM End of Block Interrupt Mask Bit 0 1 read-only DIM End of Disable Interrupt Mask Bit 2 1 read-only FIM End of Flush Interrupt Mask Bit 3 1 read-only LIM End of Linked List Interrupt Mask Bit 1 1 read-only RBEIM Read Bus Error Interrupt Mask Bit 4 1 read-only ROIM Request Overflow Error Interrupt Mask Bit 6 1 read-only WBEIM Write Bus Error Interrupt Mask Bit 5 1 read-only CIM14 Channel Interrupt Mask Register (chid = 14) 0x3D8 32 read-only n 0x0 0x0 BIM End of Block Interrupt Mask Bit 0 1 read-only DIM End of Disable Interrupt Mask Bit 2 1 read-only FIM End of Flush Interrupt Mask Bit 3 1 read-only LIM End of Linked List Interrupt Mask Bit 1 1 read-only RBEIM Read Bus Error Interrupt Mask Bit 4 1 read-only ROIM Request Overflow Error Interrupt Mask Bit 6 1 read-only WBEIM Write Bus Error Interrupt Mask Bit 5 1 read-only CIM15 Channel Interrupt Mask Register (chid = 15) 0x418 32 read-only n 0x0 0x0 BIM End of Block Interrupt Mask Bit 0 1 read-only DIM End of Disable Interrupt Mask Bit 2 1 read-only FIM End of Flush Interrupt Mask Bit 3 1 read-only LIM End of Linked List Interrupt Mask Bit 1 1 read-only RBEIM Read Bus Error Interrupt Mask Bit 4 1 read-only ROIM Request Overflow Error Interrupt Mask Bit 6 1 read-only WBEIM Write Bus Error Interrupt Mask Bit 5 1 read-only CIM2 Channel Interrupt Mask Register (chid = 2) 0xD8 32 read-only n 0x0 0x0 BIM End of Block Interrupt Mask Bit 0 1 read-only DIM End of Disable Interrupt Mask Bit 2 1 read-only FIM End of Flush Interrupt Mask Bit 3 1 read-only LIM End of Linked List Interrupt Mask Bit 1 1 read-only RBEIM Read Bus Error Interrupt Mask Bit 4 1 read-only ROIM Request Overflow Error Interrupt Mask Bit 6 1 read-only WBEIM Write Bus Error Interrupt Mask Bit 5 1 read-only CIM3 Channel Interrupt Mask Register (chid = 3) 0x118 32 read-only n 0x0 0x0 BIM End of Block Interrupt Mask Bit 0 1 read-only DIM End of Disable Interrupt Mask Bit 2 1 read-only FIM End of Flush Interrupt Mask Bit 3 1 read-only LIM End of Linked List Interrupt Mask Bit 1 1 read-only RBEIM Read Bus Error Interrupt Mask Bit 4 1 read-only ROIM Request Overflow Error Interrupt Mask Bit 6 1 read-only WBEIM Write Bus Error Interrupt Mask Bit 5 1 read-only CIM4 Channel Interrupt Mask Register (chid = 4) 0x158 32 read-only n 0x0 0x0 BIM End of Block Interrupt Mask Bit 0 1 read-only DIM End of Disable Interrupt Mask Bit 2 1 read-only FIM End of Flush Interrupt Mask Bit 3 1 read-only LIM End of Linked List Interrupt Mask Bit 1 1 read-only RBEIM Read Bus Error Interrupt Mask Bit 4 1 read-only ROIM Request Overflow Error Interrupt Mask Bit 6 1 read-only WBEIM Write Bus Error Interrupt Mask Bit 5 1 read-only CIM5 Channel Interrupt Mask Register (chid = 5) 0x198 32 read-only n 0x0 0x0 BIM End of Block Interrupt Mask Bit 0 1 read-only DIM End of Disable Interrupt Mask Bit 2 1 read-only FIM End of Flush Interrupt Mask Bit 3 1 read-only LIM End of Linked List Interrupt Mask Bit 1 1 read-only RBEIM Read Bus Error Interrupt Mask Bit 4 1 read-only ROIM Request Overflow Error Interrupt Mask Bit 6 1 read-only WBEIM Write Bus Error Interrupt Mask Bit 5 1 read-only CIM6 Channel Interrupt Mask Register (chid = 6) 0x1D8 32 read-only n 0x0 0x0 BIM End of Block Interrupt Mask Bit 0 1 read-only DIM End of Disable Interrupt Mask Bit 2 1 read-only FIM End of Flush Interrupt Mask Bit 3 1 read-only LIM End of Linked List Interrupt Mask Bit 1 1 read-only RBEIM Read Bus Error Interrupt Mask Bit 4 1 read-only ROIM Request Overflow Error Interrupt Mask Bit 6 1 read-only WBEIM Write Bus Error Interrupt Mask Bit 5 1 read-only CIM7 Channel Interrupt Mask Register (chid = 7) 0x218 32 read-only n 0x0 0x0 BIM End of Block Interrupt Mask Bit 0 1 read-only DIM End of Disable Interrupt Mask Bit 2 1 read-only FIM End of Flush Interrupt Mask Bit 3 1 read-only LIM End of Linked List Interrupt Mask Bit 1 1 read-only RBEIM Read Bus Error Interrupt Mask Bit 4 1 read-only ROIM Request Overflow Error Interrupt Mask Bit 6 1 read-only WBEIM Write Bus Error Interrupt Mask Bit 5 1 read-only CIM8 Channel Interrupt Mask Register (chid = 8) 0x258 32 read-only n 0x0 0x0 BIM End of Block Interrupt Mask Bit 0 1 read-only DIM End of Disable Interrupt Mask Bit 2 1 read-only FIM End of Flush Interrupt Mask Bit 3 1 read-only LIM End of Linked List Interrupt Mask Bit 1 1 read-only RBEIM Read Bus Error Interrupt Mask Bit 4 1 read-only ROIM Request Overflow Error Interrupt Mask Bit 6 1 read-only WBEIM Write Bus Error Interrupt Mask Bit 5 1 read-only CIM9 Channel Interrupt Mask Register (chid = 9) 0x298 32 read-only n 0x0 0x0 BIM End of Block Interrupt Mask Bit 0 1 read-only DIM End of Disable Interrupt Mask Bit 2 1 read-only FIM End of Flush Interrupt Mask Bit 3 1 read-only LIM End of Linked List Interrupt Mask Bit 1 1 read-only RBEIM Read Bus Error Interrupt Mask Bit 4 1 read-only ROIM Request Overflow Error Interrupt Mask Bit 6 1 read-only WBEIM Write Bus Error Interrupt Mask Bit 5 1 read-only CIS0 Channel Interrupt Status Register (chid = 0) 0x5C 32 read-only n 0x0 0x0 BIS End of Block Interrupt Status Bit 0 1 read-only DIS End of Disable Interrupt Status Bit 2 1 read-only FIS End of Flush Interrupt Status Bit 3 1 read-only LIS End of Linked List Interrupt Status Bit 1 1 read-only RBEIS Read Bus Error Interrupt Status Bit 4 1 read-only ROIS Request Overflow Error Interrupt Status Bit 6 1 read-only WBEIS Write Bus Error Interrupt Status Bit 5 1 read-only CIS1 Channel Interrupt Status Register (chid = 1) 0x9C 32 read-only n 0x0 0x0 BIS End of Block Interrupt Status Bit 0 1 read-only DIS End of Disable Interrupt Status Bit 2 1 read-only FIS End of Flush Interrupt Status Bit 3 1 read-only LIS End of Linked List Interrupt Status Bit 1 1 read-only RBEIS Read Bus Error Interrupt Status Bit 4 1 read-only ROIS Request Overflow Error Interrupt Status Bit 6 1 read-only WBEIS Write Bus Error Interrupt Status Bit 5 1 read-only CIS10 Channel Interrupt Status Register (chid = 10) 0x2DC 32 read-only n 0x0 0x0 BIS End of Block Interrupt Status Bit 0 1 read-only DIS End of Disable Interrupt Status Bit 2 1 read-only FIS End of Flush Interrupt Status Bit 3 1 read-only LIS End of Linked List Interrupt Status Bit 1 1 read-only RBEIS Read Bus Error Interrupt Status Bit 4 1 read-only ROIS Request Overflow Error Interrupt Status Bit 6 1 read-only WBEIS Write Bus Error Interrupt Status Bit 5 1 read-only CIS11 Channel Interrupt Status Register (chid = 11) 0x31C 32 read-only n 0x0 0x0 BIS End of Block Interrupt Status Bit 0 1 read-only DIS End of Disable Interrupt Status Bit 2 1 read-only FIS End of Flush Interrupt Status Bit 3 1 read-only LIS End of Linked List Interrupt Status Bit 1 1 read-only RBEIS Read Bus Error Interrupt Status Bit 4 1 read-only ROIS Request Overflow Error Interrupt Status Bit 6 1 read-only WBEIS Write Bus Error Interrupt Status Bit 5 1 read-only CIS12 Channel Interrupt Status Register (chid = 12) 0x35C 32 read-only n 0x0 0x0 BIS End of Block Interrupt Status Bit 0 1 read-only DIS End of Disable Interrupt Status Bit 2 1 read-only FIS End of Flush Interrupt Status Bit 3 1 read-only LIS End of Linked List Interrupt Status Bit 1 1 read-only RBEIS Read Bus Error Interrupt Status Bit 4 1 read-only ROIS Request Overflow Error Interrupt Status Bit 6 1 read-only WBEIS Write Bus Error Interrupt Status Bit 5 1 read-only CIS13 Channel Interrupt Status Register (chid = 13) 0x39C 32 read-only n 0x0 0x0 BIS End of Block Interrupt Status Bit 0 1 read-only DIS End of Disable Interrupt Status Bit 2 1 read-only FIS End of Flush Interrupt Status Bit 3 1 read-only LIS End of Linked List Interrupt Status Bit 1 1 read-only RBEIS Read Bus Error Interrupt Status Bit 4 1 read-only ROIS Request Overflow Error Interrupt Status Bit 6 1 read-only WBEIS Write Bus Error Interrupt Status Bit 5 1 read-only CIS14 Channel Interrupt Status Register (chid = 14) 0x3DC 32 read-only n 0x0 0x0 BIS End of Block Interrupt Status Bit 0 1 read-only DIS End of Disable Interrupt Status Bit 2 1 read-only FIS End of Flush Interrupt Status Bit 3 1 read-only LIS End of Linked List Interrupt Status Bit 1 1 read-only RBEIS Read Bus Error Interrupt Status Bit 4 1 read-only ROIS Request Overflow Error Interrupt Status Bit 6 1 read-only WBEIS Write Bus Error Interrupt Status Bit 5 1 read-only CIS15 Channel Interrupt Status Register (chid = 15) 0x41C 32 read-only n 0x0 0x0 BIS End of Block Interrupt Status Bit 0 1 read-only DIS End of Disable Interrupt Status Bit 2 1 read-only FIS End of Flush Interrupt Status Bit 3 1 read-only LIS End of Linked List Interrupt Status Bit 1 1 read-only RBEIS Read Bus Error Interrupt Status Bit 4 1 read-only ROIS Request Overflow Error Interrupt Status Bit 6 1 read-only WBEIS Write Bus Error Interrupt Status Bit 5 1 read-only CIS2 Channel Interrupt Status Register (chid = 2) 0xDC 32 read-only n 0x0 0x0 BIS End of Block Interrupt Status Bit 0 1 read-only DIS End of Disable Interrupt Status Bit 2 1 read-only FIS End of Flush Interrupt Status Bit 3 1 read-only LIS End of Linked List Interrupt Status Bit 1 1 read-only RBEIS Read Bus Error Interrupt Status Bit 4 1 read-only ROIS Request Overflow Error Interrupt Status Bit 6 1 read-only WBEIS Write Bus Error Interrupt Status Bit 5 1 read-only CIS3 Channel Interrupt Status Register (chid = 3) 0x11C 32 read-only n 0x0 0x0 BIS End of Block Interrupt Status Bit 0 1 read-only DIS End of Disable Interrupt Status Bit 2 1 read-only FIS End of Flush Interrupt Status Bit 3 1 read-only LIS End of Linked List Interrupt Status Bit 1 1 read-only RBEIS Read Bus Error Interrupt Status Bit 4 1 read-only ROIS Request Overflow Error Interrupt Status Bit 6 1 read-only WBEIS Write Bus Error Interrupt Status Bit 5 1 read-only CIS4 Channel Interrupt Status Register (chid = 4) 0x15C 32 read-only n 0x0 0x0 BIS End of Block Interrupt Status Bit 0 1 read-only DIS End of Disable Interrupt Status Bit 2 1 read-only FIS End of Flush Interrupt Status Bit 3 1 read-only LIS End of Linked List Interrupt Status Bit 1 1 read-only RBEIS Read Bus Error Interrupt Status Bit 4 1 read-only ROIS Request Overflow Error Interrupt Status Bit 6 1 read-only WBEIS Write Bus Error Interrupt Status Bit 5 1 read-only CIS5 Channel Interrupt Status Register (chid = 5) 0x19C 32 read-only n 0x0 0x0 BIS End of Block Interrupt Status Bit 0 1 read-only DIS End of Disable Interrupt Status Bit 2 1 read-only FIS End of Flush Interrupt Status Bit 3 1 read-only LIS End of Linked List Interrupt Status Bit 1 1 read-only RBEIS Read Bus Error Interrupt Status Bit 4 1 read-only ROIS Request Overflow Error Interrupt Status Bit 6 1 read-only WBEIS Write Bus Error Interrupt Status Bit 5 1 read-only CIS6 Channel Interrupt Status Register (chid = 6) 0x1DC 32 read-only n 0x0 0x0 BIS End of Block Interrupt Status Bit 0 1 read-only DIS End of Disable Interrupt Status Bit 2 1 read-only FIS End of Flush Interrupt Status Bit 3 1 read-only LIS End of Linked List Interrupt Status Bit 1 1 read-only RBEIS Read Bus Error Interrupt Status Bit 4 1 read-only ROIS Request Overflow Error Interrupt Status Bit 6 1 read-only WBEIS Write Bus Error Interrupt Status Bit 5 1 read-only CIS7 Channel Interrupt Status Register (chid = 7) 0x21C 32 read-only n 0x0 0x0 BIS End of Block Interrupt Status Bit 0 1 read-only DIS End of Disable Interrupt Status Bit 2 1 read-only FIS End of Flush Interrupt Status Bit 3 1 read-only LIS End of Linked List Interrupt Status Bit 1 1 read-only RBEIS Read Bus Error Interrupt Status Bit 4 1 read-only ROIS Request Overflow Error Interrupt Status Bit 6 1 read-only WBEIS Write Bus Error Interrupt Status Bit 5 1 read-only CIS8 Channel Interrupt Status Register (chid = 8) 0x25C 32 read-only n 0x0 0x0 BIS End of Block Interrupt Status Bit 0 1 read-only DIS End of Disable Interrupt Status Bit 2 1 read-only FIS End of Flush Interrupt Status Bit 3 1 read-only LIS End of Linked List Interrupt Status Bit 1 1 read-only RBEIS Read Bus Error Interrupt Status Bit 4 1 read-only ROIS Request Overflow Error Interrupt Status Bit 6 1 read-only WBEIS Write Bus Error Interrupt Status Bit 5 1 read-only CIS9 Channel Interrupt Status Register (chid = 9) 0x29C 32 read-only n 0x0 0x0 BIS End of Block Interrupt Status Bit 0 1 read-only DIS End of Disable Interrupt Status Bit 2 1 read-only FIS End of Flush Interrupt Status Bit 3 1 read-only LIS End of Linked List Interrupt Status Bit 1 1 read-only RBEIS Read Bus Error Interrupt Status Bit 4 1 read-only ROIS Request Overflow Error Interrupt Status Bit 6 1 read-only WBEIS Write Bus Error Interrupt Status Bit 5 1 read-only CNDA0 Channel Next Descriptor Address Register (chid = 0) 0x68 32 read-write n 0x0 0x0 NDA Channel x Next Descriptor Address 2 30 read-write NDAIF Channel x Next Descriptor Interface 0 1 read-write CNDA1 Channel Next Descriptor Address Register (chid = 1) 0xA8 32 read-write n 0x0 0x0 NDA Channel x Next Descriptor Address 2 30 read-write NDAIF Channel x Next Descriptor Interface 0 1 read-write CNDA10 Channel Next Descriptor Address Register (chid = 10) 0x2E8 32 read-write n 0x0 0x0 NDA Channel x Next Descriptor Address 2 30 read-write NDAIF Channel x Next Descriptor Interface 0 1 read-write CNDA11 Channel Next Descriptor Address Register (chid = 11) 0x328 32 read-write n 0x0 0x0 NDA Channel x Next Descriptor Address 2 30 read-write NDAIF Channel x Next Descriptor Interface 0 1 read-write CNDA12 Channel Next Descriptor Address Register (chid = 12) 0x368 32 read-write n 0x0 0x0 NDA Channel x Next Descriptor Address 2 30 read-write NDAIF Channel x Next Descriptor Interface 0 1 read-write CNDA13 Channel Next Descriptor Address Register (chid = 13) 0x3A8 32 read-write n 0x0 0x0 NDA Channel x Next Descriptor Address 2 30 read-write NDAIF Channel x Next Descriptor Interface 0 1 read-write CNDA14 Channel Next Descriptor Address Register (chid = 14) 0x3E8 32 read-write n 0x0 0x0 NDA Channel x Next Descriptor Address 2 30 read-write NDAIF Channel x Next Descriptor Interface 0 1 read-write CNDA15 Channel Next Descriptor Address Register (chid = 15) 0x428 32 read-write n 0x0 0x0 NDA Channel x Next Descriptor Address 2 30 read-write NDAIF Channel x Next Descriptor Interface 0 1 read-write CNDA2 Channel Next Descriptor Address Register (chid = 2) 0xE8 32 read-write n 0x0 0x0 NDA Channel x Next Descriptor Address 2 30 read-write NDAIF Channel x Next Descriptor Interface 0 1 read-write CNDA3 Channel Next Descriptor Address Register (chid = 3) 0x128 32 read-write n 0x0 0x0 NDA Channel x Next Descriptor Address 2 30 read-write NDAIF Channel x Next Descriptor Interface 0 1 read-write CNDA4 Channel Next Descriptor Address Register (chid = 4) 0x168 32 read-write n 0x0 0x0 NDA Channel x Next Descriptor Address 2 30 read-write NDAIF Channel x Next Descriptor Interface 0 1 read-write CNDA5 Channel Next Descriptor Address Register (chid = 5) 0x1A8 32 read-write n 0x0 0x0 NDA Channel x Next Descriptor Address 2 30 read-write NDAIF Channel x Next Descriptor Interface 0 1 read-write CNDA6 Channel Next Descriptor Address Register (chid = 6) 0x1E8 32 read-write n 0x0 0x0 NDA Channel x Next Descriptor Address 2 30 read-write NDAIF Channel x Next Descriptor Interface 0 1 read-write CNDA7 Channel Next Descriptor Address Register (chid = 7) 0x228 32 read-write n 0x0 0x0 NDA Channel x Next Descriptor Address 2 30 read-write NDAIF Channel x Next Descriptor Interface 0 1 read-write CNDA8 Channel Next Descriptor Address Register (chid = 8) 0x268 32 read-write n 0x0 0x0 NDA Channel x Next Descriptor Address 2 30 read-write NDAIF Channel x Next Descriptor Interface 0 1 read-write CNDA9 Channel Next Descriptor Address Register (chid = 9) 0x2A8 32 read-write n 0x0 0x0 NDA Channel x Next Descriptor Address 2 30 read-write NDAIF Channel x Next Descriptor Interface 0 1 read-write CNDC0 Channel Next Descriptor Control Register (chid = 0) 0x6C 32 read-write n 0x0 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 read-write DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 read-write DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 read-write SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 read-write NDV0 Next Descriptor View 0 0x0 NDV1 Next Descriptor View 1 0x1 NDV2 Next Descriptor View 2 0x2 NDV3 Next Descriptor View 3 0x3 CNDC1 Channel Next Descriptor Control Register (chid = 1) 0xAC 32 read-write n 0x0 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 read-write DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 read-write DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 read-write SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 read-write NDV0 Next Descriptor View 0 0x0 NDV1 Next Descriptor View 1 0x1 NDV2 Next Descriptor View 2 0x2 NDV3 Next Descriptor View 3 0x3 CNDC10 Channel Next Descriptor Control Register (chid = 10) 0x2EC 32 read-write n 0x0 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 read-write DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 read-write DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 read-write SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 read-write NDV0 Next Descriptor View 0 0x0 NDV1 Next Descriptor View 1 0x1 NDV2 Next Descriptor View 2 0x2 NDV3 Next Descriptor View 3 0x3 CNDC11 Channel Next Descriptor Control Register (chid = 11) 0x32C 32 read-write n 0x0 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 read-write DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 read-write DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 read-write SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 read-write NDV0 Next Descriptor View 0 0x0 NDV1 Next Descriptor View 1 0x1 NDV2 Next Descriptor View 2 0x2 NDV3 Next Descriptor View 3 0x3 CNDC12 Channel Next Descriptor Control Register (chid = 12) 0x36C 32 read-write n 0x0 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 read-write DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 read-write DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 read-write SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 read-write NDV0 Next Descriptor View 0 0x0 NDV1 Next Descriptor View 1 0x1 NDV2 Next Descriptor View 2 0x2 NDV3 Next Descriptor View 3 0x3 CNDC13 Channel Next Descriptor Control Register (chid = 13) 0x3AC 32 read-write n 0x0 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 read-write DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 read-write DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 read-write SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 read-write NDV0 Next Descriptor View 0 0x0 NDV1 Next Descriptor View 1 0x1 NDV2 Next Descriptor View 2 0x2 NDV3 Next Descriptor View 3 0x3 CNDC14 Channel Next Descriptor Control Register (chid = 14) 0x3EC 32 read-write n 0x0 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 read-write DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 read-write DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 read-write SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 read-write NDV0 Next Descriptor View 0 0x0 NDV1 Next Descriptor View 1 0x1 NDV2 Next Descriptor View 2 0x2 NDV3 Next Descriptor View 3 0x3 CNDC15 Channel Next Descriptor Control Register (chid = 15) 0x42C 32 read-write n 0x0 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 read-write DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 read-write DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 read-write SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 read-write NDV0 Next Descriptor View 0 0x0 NDV1 Next Descriptor View 1 0x1 NDV2 Next Descriptor View 2 0x2 NDV3 Next Descriptor View 3 0x3 CNDC2 Channel Next Descriptor Control Register (chid = 2) 0xEC 32 read-write n 0x0 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 read-write DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 read-write DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 read-write SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 read-write NDV0 Next Descriptor View 0 0x0 NDV1 Next Descriptor View 1 0x1 NDV2 Next Descriptor View 2 0x2 NDV3 Next Descriptor View 3 0x3 CNDC3 Channel Next Descriptor Control Register (chid = 3) 0x12C 32 read-write n 0x0 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 read-write DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 read-write DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 read-write SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 read-write NDV0 Next Descriptor View 0 0x0 NDV1 Next Descriptor View 1 0x1 NDV2 Next Descriptor View 2 0x2 NDV3 Next Descriptor View 3 0x3 CNDC4 Channel Next Descriptor Control Register (chid = 4) 0x16C 32 read-write n 0x0 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 read-write DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 read-write DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 read-write SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 read-write NDV0 Next Descriptor View 0 0x0 NDV1 Next Descriptor View 1 0x1 NDV2 Next Descriptor View 2 0x2 NDV3 Next Descriptor View 3 0x3 CNDC5 Channel Next Descriptor Control Register (chid = 5) 0x1AC 32 read-write n 0x0 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 read-write DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 read-write DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 read-write SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 read-write NDV0 Next Descriptor View 0 0x0 NDV1 Next Descriptor View 1 0x1 NDV2 Next Descriptor View 2 0x2 NDV3 Next Descriptor View 3 0x3 CNDC6 Channel Next Descriptor Control Register (chid = 6) 0x1EC 32 read-write n 0x0 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 read-write DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 read-write DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 read-write SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 read-write NDV0 Next Descriptor View 0 0x0 NDV1 Next Descriptor View 1 0x1 NDV2 Next Descriptor View 2 0x2 NDV3 Next Descriptor View 3 0x3 CNDC7 Channel Next Descriptor Control Register (chid = 7) 0x22C 32 read-write n 0x0 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 read-write DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 read-write DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 read-write SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 read-write NDV0 Next Descriptor View 0 0x0 NDV1 Next Descriptor View 1 0x1 NDV2 Next Descriptor View 2 0x2 NDV3 Next Descriptor View 3 0x3 CNDC8 Channel Next Descriptor Control Register (chid = 8) 0x26C 32 read-write n 0x0 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 read-write DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 read-write DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 read-write SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 read-write NDV0 Next Descriptor View 0 0x0 NDV1 Next Descriptor View 1 0x1 NDV2 Next Descriptor View 2 0x2 NDV3 Next Descriptor View 3 0x3 CNDC9 Channel Next Descriptor Control Register (chid = 9) 0x2AC 32 read-write n 0x0 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 read-write DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 read-write DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 read-write SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 read-write NDV0 Next Descriptor View 0 0x0 NDV1 Next Descriptor View 1 0x1 NDV2 Next Descriptor View 2 0x2 NDV3 Next Descriptor View 3 0x3 CSA0 Channel Source Address Register (chid = 0) 0x60 32 read-write n 0x0 0x0 SA Channel x Source Address 0 32 read-write CSA1 Channel Source Address Register (chid = 1) 0xA0 32 read-write n 0x0 0x0 SA Channel x Source Address 0 32 read-write CSA10 Channel Source Address Register (chid = 10) 0x2E0 32 read-write n 0x0 0x0 SA Channel x Source Address 0 32 read-write CSA11 Channel Source Address Register (chid = 11) 0x320 32 read-write n 0x0 0x0 SA Channel x Source Address 0 32 read-write CSA12 Channel Source Address Register (chid = 12) 0x360 32 read-write n 0x0 0x0 SA Channel x Source Address 0 32 read-write CSA13 Channel Source Address Register (chid = 13) 0x3A0 32 read-write n 0x0 0x0 SA Channel x Source Address 0 32 read-write CSA14 Channel Source Address Register (chid = 14) 0x3E0 32 read-write n 0x0 0x0 SA Channel x Source Address 0 32 read-write CSA15 Channel Source Address Register (chid = 15) 0x420 32 read-write n 0x0 0x0 SA Channel x Source Address 0 32 read-write CSA2 Channel Source Address Register (chid = 2) 0xE0 32 read-write n 0x0 0x0 SA Channel x Source Address 0 32 read-write CSA3 Channel Source Address Register (chid = 3) 0x120 32 read-write n 0x0 0x0 SA Channel x Source Address 0 32 read-write CSA4 Channel Source Address Register (chid = 4) 0x160 32 read-write n 0x0 0x0 SA Channel x Source Address 0 32 read-write CSA5 Channel Source Address Register (chid = 5) 0x1A0 32 read-write n 0x0 0x0 SA Channel x Source Address 0 32 read-write CSA6 Channel Source Address Register (chid = 6) 0x1E0 32 read-write n 0x0 0x0 SA Channel x Source Address 0 32 read-write CSA7 Channel Source Address Register (chid = 7) 0x220 32 read-write n 0x0 0x0 SA Channel x Source Address 0 32 read-write CSA8 Channel Source Address Register (chid = 8) 0x260 32 read-write n 0x0 0x0 SA Channel x Source Address 0 32 read-write CSA9 Channel Source Address Register (chid = 9) 0x2A0 32 read-write n 0x0 0x0 SA Channel x Source Address 0 32 read-write CSUS0 Channel Source Microblock Stride (chid = 0) 0x80 32 read-write n 0x0 0x0 SUBS Channel x Source Microblock Stride 0 24 read-write CSUS1 Channel Source Microblock Stride (chid = 1) 0xC0 32 read-write n 0x0 0x0 SUBS Channel x Source Microblock Stride 0 24 read-write CSUS10 Channel Source Microblock Stride (chid = 10) 0x300 32 read-write n 0x0 0x0 SUBS Channel x Source Microblock Stride 0 24 read-write CSUS11 Channel Source Microblock Stride (chid = 11) 0x340 32 read-write n 0x0 0x0 SUBS Channel x Source Microblock Stride 0 24 read-write CSUS12 Channel Source Microblock Stride (chid = 12) 0x380 32 read-write n 0x0 0x0 SUBS Channel x Source Microblock Stride 0 24 read-write CSUS13 Channel Source Microblock Stride (chid = 13) 0x3C0 32 read-write n 0x0 0x0 SUBS Channel x Source Microblock Stride 0 24 read-write CSUS14 Channel Source Microblock Stride (chid = 14) 0x400 32 read-write n 0x0 0x0 SUBS Channel x Source Microblock Stride 0 24 read-write CSUS15 Channel Source Microblock Stride (chid = 15) 0x440 32 read-write n 0x0 0x0 SUBS Channel x Source Microblock Stride 0 24 read-write CSUS2 Channel Source Microblock Stride (chid = 2) 0x100 32 read-write n 0x0 0x0 SUBS Channel x Source Microblock Stride 0 24 read-write CSUS3 Channel Source Microblock Stride (chid = 3) 0x140 32 read-write n 0x0 0x0 SUBS Channel x Source Microblock Stride 0 24 read-write CSUS4 Channel Source Microblock Stride (chid = 4) 0x180 32 read-write n 0x0 0x0 SUBS Channel x Source Microblock Stride 0 24 read-write CSUS5 Channel Source Microblock Stride (chid = 5) 0x1C0 32 read-write n 0x0 0x0 SUBS Channel x Source Microblock Stride 0 24 read-write CSUS6 Channel Source Microblock Stride (chid = 6) 0x200 32 read-write n 0x0 0x0 SUBS Channel x Source Microblock Stride 0 24 read-write CSUS7 Channel Source Microblock Stride (chid = 7) 0x240 32 read-write n 0x0 0x0 SUBS Channel x Source Microblock Stride 0 24 read-write CSUS8 Channel Source Microblock Stride (chid = 8) 0x280 32 read-write n 0x0 0x0 SUBS Channel x Source Microblock Stride 0 24 read-write CSUS9 Channel Source Microblock Stride (chid = 9) 0x2C0 32 read-write n 0x0 0x0 SUBS Channel x Source Microblock Stride 0 24 read-write CUBC0 Channel Microblock Control Register (chid = 0) 0x70 32 read-write n 0x0 0x0 UBLEN Channel x Microblock Length 0 24 read-write CUBC1 Channel Microblock Control Register (chid = 1) 0xB0 32 read-write n 0x0 0x0 UBLEN Channel x Microblock Length 0 24 read-write CUBC10 Channel Microblock Control Register (chid = 10) 0x2F0 32 read-write n 0x0 0x0 UBLEN Channel x Microblock Length 0 24 read-write CUBC11 Channel Microblock Control Register (chid = 11) 0x330 32 read-write n 0x0 0x0 UBLEN Channel x Microblock Length 0 24 read-write CUBC12 Channel Microblock Control Register (chid = 12) 0x370 32 read-write n 0x0 0x0 UBLEN Channel x Microblock Length 0 24 read-write CUBC13 Channel Microblock Control Register (chid = 13) 0x3B0 32 read-write n 0x0 0x0 UBLEN Channel x Microblock Length 0 24 read-write CUBC14 Channel Microblock Control Register (chid = 14) 0x3F0 32 read-write n 0x0 0x0 UBLEN Channel x Microblock Length 0 24 read-write CUBC15 Channel Microblock Control Register (chid = 15) 0x430 32 read-write n 0x0 0x0 UBLEN Channel x Microblock Length 0 24 read-write CUBC2 Channel Microblock Control Register (chid = 2) 0xF0 32 read-write n 0x0 0x0 UBLEN Channel x Microblock Length 0 24 read-write CUBC3 Channel Microblock Control Register (chid = 3) 0x130 32 read-write n 0x0 0x0 UBLEN Channel x Microblock Length 0 24 read-write CUBC4 Channel Microblock Control Register (chid = 4) 0x170 32 read-write n 0x0 0x0 UBLEN Channel x Microblock Length 0 24 read-write CUBC5 Channel Microblock Control Register (chid = 5) 0x1B0 32 read-write n 0x0 0x0 UBLEN Channel x Microblock Length 0 24 read-write CUBC6 Channel Microblock Control Register (chid = 6) 0x1F0 32 read-write n 0x0 0x0 UBLEN Channel x Microblock Length 0 24 read-write CUBC7 Channel Microblock Control Register (chid = 7) 0x230 32 read-write n 0x0 0x0 UBLEN Channel x Microblock Length 0 24 read-write CUBC8 Channel Microblock Control Register (chid = 8) 0x270 32 read-write n 0x0 0x0 UBLEN Channel x Microblock Length 0 24 read-write CUBC9 Channel Microblock Control Register (chid = 9) 0x2B0 32 read-write n 0x0 0x0 UBLEN Channel x Microblock Length 0 24 read-write GCFG Global Configuration Register 0x4 32 read-write n 0x0 0x0 BXKBEN Boundary X Kilobyte Enable 8 1 read-write CGDISFIFO FIFO Clock Gating Disable 2 1 read-write CGDISIF Bus Interface Clock Gating Disable 3 1 read-write CGDISPIPE Pipeline Clock Gating Disable 1 1 read-write CGDISREG Configuration Registers Clock Gating Disable 0 1 read-write GD Global Channel Disable Register 0x20 32 write-only n 0x0 0x0 DI0 XDMAC Channel 0 Disable Bit 0 1 write-only DI1 XDMAC Channel 1 Disable Bit 1 1 write-only DI10 XDMAC Channel 10 Disable Bit 10 1 write-only DI11 XDMAC Channel 11 Disable Bit 11 1 write-only DI12 XDMAC Channel 12 Disable Bit 12 1 write-only DI13 XDMAC Channel 13 Disable Bit 13 1 write-only DI14 XDMAC Channel 14 Disable Bit 14 1 write-only DI15 XDMAC Channel 15 Disable Bit 15 1 write-only DI2 XDMAC Channel 2 Disable Bit 2 1 write-only DI3 XDMAC Channel 3 Disable Bit 3 1 write-only DI4 XDMAC Channel 4 Disable Bit 4 1 write-only DI5 XDMAC Channel 5 Disable Bit 5 1 write-only DI6 XDMAC Channel 6 Disable Bit 6 1 write-only DI7 XDMAC Channel 7 Disable Bit 7 1 write-only DI8 XDMAC Channel 8 Disable Bit 8 1 write-only DI9 XDMAC Channel 9 Disable Bit 9 1 write-only GE Global Channel Enable Register 0x1C 32 write-only n 0x0 0x0 EN0 XDMAC Channel 0 Enable Bit 0 1 write-only EN1 XDMAC Channel 1 Enable Bit 1 1 write-only EN10 XDMAC Channel 10 Enable Bit 10 1 write-only EN11 XDMAC Channel 11 Enable Bit 11 1 write-only EN12 XDMAC Channel 12 Enable Bit 12 1 write-only EN13 XDMAC Channel 13 Enable Bit 13 1 write-only EN14 XDMAC Channel 14 Enable Bit 14 1 write-only EN15 XDMAC Channel 15 Enable Bit 15 1 write-only EN2 XDMAC Channel 2 Enable Bit 2 1 write-only EN3 XDMAC Channel 3 Enable Bit 3 1 write-only EN4 XDMAC Channel 4 Enable Bit 4 1 write-only EN5 XDMAC Channel 5 Enable Bit 5 1 write-only EN6 XDMAC Channel 6 Enable Bit 6 1 write-only EN7 XDMAC Channel 7 Enable Bit 7 1 write-only EN8 XDMAC Channel 8 Enable Bit 8 1 write-only EN9 XDMAC Channel 9 Enable Bit 9 1 write-only GID Global Interrupt Disable Register 0x10 32 write-only n 0x0 0x0 ID0 XDMAC Channel 0 Interrupt Disable Bit 0 1 write-only ID1 XDMAC Channel 1 Interrupt Disable Bit 1 1 write-only ID10 XDMAC Channel 10 Interrupt Disable Bit 10 1 write-only ID11 XDMAC Channel 11 Interrupt Disable Bit 11 1 write-only ID12 XDMAC Channel 12 Interrupt Disable Bit 12 1 write-only ID13 XDMAC Channel 13 Interrupt Disable Bit 13 1 write-only ID14 XDMAC Channel 14 Interrupt Disable Bit 14 1 write-only ID15 XDMAC Channel 15 Interrupt Disable Bit 15 1 write-only ID2 XDMAC Channel 2 Interrupt Disable Bit 2 1 write-only ID3 XDMAC Channel 3 Interrupt Disable Bit 3 1 write-only ID4 XDMAC Channel 4 Interrupt Disable Bit 4 1 write-only ID5 XDMAC Channel 5 Interrupt Disable Bit 5 1 write-only ID6 XDMAC Channel 6 Interrupt Disable Bit 6 1 write-only ID7 XDMAC Channel 7 Interrupt Disable Bit 7 1 write-only ID8 XDMAC Channel 8 Interrupt Disable Bit 8 1 write-only ID9 XDMAC Channel 9 Interrupt Disable Bit 9 1 write-only GIE Global Interrupt Enable Register 0xC 32 write-only n 0x0 0x0 IE0 XDMAC Channel 0 Interrupt Enable Bit 0 1 write-only IE1 XDMAC Channel 1 Interrupt Enable Bit 1 1 write-only IE10 XDMAC Channel 10 Interrupt Enable Bit 10 1 write-only IE11 XDMAC Channel 11 Interrupt Enable Bit 11 1 write-only IE12 XDMAC Channel 12 Interrupt Enable Bit 12 1 write-only IE13 XDMAC Channel 13 Interrupt Enable Bit 13 1 write-only IE14 XDMAC Channel 14 Interrupt Enable Bit 14 1 write-only IE15 XDMAC Channel 15 Interrupt Enable Bit 15 1 write-only IE2 XDMAC Channel 2 Interrupt Enable Bit 2 1 write-only IE3 XDMAC Channel 3 Interrupt Enable Bit 3 1 write-only IE4 XDMAC Channel 4 Interrupt Enable Bit 4 1 write-only IE5 XDMAC Channel 5 Interrupt Enable Bit 5 1 write-only IE6 XDMAC Channel 6 Interrupt Enable Bit 6 1 write-only IE7 XDMAC Channel 7 Interrupt Enable Bit 7 1 write-only IE8 XDMAC Channel 8 Interrupt Enable Bit 8 1 write-only IE9 XDMAC Channel 9 Interrupt Enable Bit 9 1 write-only GIM Global Interrupt Mask Register 0x14 32 read-only n 0x0 0x0 IM0 XDMAC Channel 0 Interrupt Mask Bit 0 1 read-only IM1 XDMAC Channel 1 Interrupt Mask Bit 1 1 read-only IM10 XDMAC Channel 10 Interrupt Mask Bit 10 1 read-only IM11 XDMAC Channel 11 Interrupt Mask Bit 11 1 read-only IM12 XDMAC Channel 12 Interrupt Mask Bit 12 1 read-only IM13 XDMAC Channel 13 Interrupt Mask Bit 13 1 read-only IM14 XDMAC Channel 14 Interrupt Mask Bit 14 1 read-only IM15 XDMAC Channel 15 Interrupt Mask Bit 15 1 read-only IM2 XDMAC Channel 2 Interrupt Mask Bit 2 1 read-only IM3 XDMAC Channel 3 Interrupt Mask Bit 3 1 read-only IM4 XDMAC Channel 4 Interrupt Mask Bit 4 1 read-only IM5 XDMAC Channel 5 Interrupt Mask Bit 5 1 read-only IM6 XDMAC Channel 6 Interrupt Mask Bit 6 1 read-only IM7 XDMAC Channel 7 Interrupt Mask Bit 7 1 read-only IM8 XDMAC Channel 8 Interrupt Mask Bit 8 1 read-only IM9 XDMAC Channel 9 Interrupt Mask Bit 9 1 read-only GIS Global Interrupt Status Register 0x18 32 read-only n 0x0 0x0 IS0 XDMAC Channel 0 Interrupt Status Bit 0 1 read-only IS1 XDMAC Channel 1 Interrupt Status Bit 1 1 read-only IS10 XDMAC Channel 10 Interrupt Status Bit 10 1 read-only IS11 XDMAC Channel 11 Interrupt Status Bit 11 1 read-only IS12 XDMAC Channel 12 Interrupt Status Bit 12 1 read-only IS13 XDMAC Channel 13 Interrupt Status Bit 13 1 read-only IS14 XDMAC Channel 14 Interrupt Status Bit 14 1 read-only IS15 XDMAC Channel 15 Interrupt Status Bit 15 1 read-only IS2 XDMAC Channel 2 Interrupt Status Bit 2 1 read-only IS3 XDMAC Channel 3 Interrupt Status Bit 3 1 read-only IS4 XDMAC Channel 4 Interrupt Status Bit 4 1 read-only IS5 XDMAC Channel 5 Interrupt Status Bit 5 1 read-only IS6 XDMAC Channel 6 Interrupt Status Bit 6 1 read-only IS7 XDMAC Channel 7 Interrupt Status Bit 7 1 read-only IS8 XDMAC Channel 8 Interrupt Status Bit 8 1 read-only IS9 XDMAC Channel 9 Interrupt Status Bit 9 1 read-only GRS Global Channel Read Suspend Register 0x28 32 read-write n 0x0 0x0 RS0 XDMAC Channel 0 Read Suspend Bit 0 1 read-write RS1 XDMAC Channel 1 Read Suspend Bit 1 1 read-write RS10 XDMAC Channel 10 Read Suspend Bit 10 1 read-write RS11 XDMAC Channel 11 Read Suspend Bit 11 1 read-write RS12 XDMAC Channel 12 Read Suspend Bit 12 1 read-write RS13 XDMAC Channel 13 Read Suspend Bit 13 1 read-write RS14 XDMAC Channel 14 Read Suspend Bit 14 1 read-write RS15 XDMAC Channel 15 Read Suspend Bit 15 1 read-write RS2 XDMAC Channel 2 Read Suspend Bit 2 1 read-write RS3 XDMAC Channel 3 Read Suspend Bit 3 1 read-write RS4 XDMAC Channel 4 Read Suspend Bit 4 1 read-write RS5 XDMAC Channel 5 Read Suspend Bit 5 1 read-write RS6 XDMAC Channel 6 Read Suspend Bit 6 1 read-write RS7 XDMAC Channel 7 Read Suspend Bit 7 1 read-write RS8 XDMAC Channel 8 Read Suspend Bit 8 1 read-write RS9 XDMAC Channel 9 Read Suspend Bit 9 1 read-write GRWR Global Channel Read Write Resume Register 0x34 32 write-only n 0x0 0x0 RWR0 XDMAC Channel 0 Read Write Resume Bit 0 1 write-only RWR1 XDMAC Channel 1 Read Write Resume Bit 1 1 write-only RWR10 XDMAC Channel 10 Read Write Resume Bit 10 1 write-only RWR11 XDMAC Channel 11 Read Write Resume Bit 11 1 write-only RWR12 XDMAC Channel 12 Read Write Resume Bit 12 1 write-only RWR13 XDMAC Channel 13 Read Write Resume Bit 13 1 write-only RWR14 XDMAC Channel 14 Read Write Resume Bit 14 1 write-only RWR15 XDMAC Channel 15 Read Write Resume Bit 15 1 write-only RWR2 XDMAC Channel 2 Read Write Resume Bit 2 1 write-only RWR3 XDMAC Channel 3 Read Write Resume Bit 3 1 write-only RWR4 XDMAC Channel 4 Read Write Resume Bit 4 1 write-only RWR5 XDMAC Channel 5 Read Write Resume Bit 5 1 write-only RWR6 XDMAC Channel 6 Read Write Resume Bit 6 1 write-only RWR7 XDMAC Channel 7 Read Write Resume Bit 7 1 write-only RWR8 XDMAC Channel 8 Read Write Resume Bit 8 1 write-only RWR9 XDMAC Channel 9 Read Write Resume Bit 9 1 write-only GRWS Global Channel Read Write Suspend Register 0x30 32 write-only n 0x0 0x0 RWS0 XDMAC Channel 0 Read Write Suspend Bit 0 1 write-only RWS1 XDMAC Channel 1 Read Write Suspend Bit 1 1 write-only RWS10 XDMAC Channel 10 Read Write Suspend Bit 10 1 write-only RWS11 XDMAC Channel 11 Read Write Suspend Bit 11 1 write-only RWS12 XDMAC Channel 12 Read Write Suspend Bit 12 1 write-only RWS13 XDMAC Channel 13 Read Write Suspend Bit 13 1 write-only RWS14 XDMAC Channel 14 Read Write Suspend Bit 14 1 write-only RWS15 XDMAC Channel 15 Read Write Suspend Bit 15 1 write-only RWS2 XDMAC Channel 2 Read Write Suspend Bit 2 1 write-only RWS3 XDMAC Channel 3 Read Write Suspend Bit 3 1 write-only RWS4 XDMAC Channel 4 Read Write Suspend Bit 4 1 write-only RWS5 XDMAC Channel 5 Read Write Suspend Bit 5 1 write-only RWS6 XDMAC Channel 6 Read Write Suspend Bit 6 1 write-only RWS7 XDMAC Channel 7 Read Write Suspend Bit 7 1 write-only RWS8 XDMAC Channel 8 Read Write Suspend Bit 8 1 write-only RWS9 XDMAC Channel 9 Read Write Suspend Bit 9 1 write-only GS Global Channel Status Register 0x24 32 read-only n 0x0 0x0 ST0 XDMAC Channel 0 Status Bit 0 1 read-only ST1 XDMAC Channel 1 Status Bit 1 1 read-only ST10 XDMAC Channel 10 Status Bit 10 1 read-only ST11 XDMAC Channel 11 Status Bit 11 1 read-only ST12 XDMAC Channel 12 Status Bit 12 1 read-only ST13 XDMAC Channel 13 Status Bit 13 1 read-only ST14 XDMAC Channel 14 Status Bit 14 1 read-only ST15 XDMAC Channel 15 Status Bit 15 1 read-only ST2 XDMAC Channel 2 Status Bit 2 1 read-only ST3 XDMAC Channel 3 Status Bit 3 1 read-only ST4 XDMAC Channel 4 Status Bit 4 1 read-only ST5 XDMAC Channel 5 Status Bit 5 1 read-only ST6 XDMAC Channel 6 Status Bit 6 1 read-only ST7 XDMAC Channel 7 Status Bit 7 1 read-only ST8 XDMAC Channel 8 Status Bit 8 1 read-only ST9 XDMAC Channel 9 Status Bit 9 1 read-only GSWF Global Channel Software Flush Request Register 0x40 32 write-only n 0x0 0x0 SWF0 XDMAC Channel 0 Software Flush Request Bit 0 1 write-only SWF1 XDMAC Channel 1 Software Flush Request Bit 1 1 write-only SWF10 XDMAC Channel 10 Software Flush Request Bit 10 1 write-only SWF11 XDMAC Channel 11 Software Flush Request Bit 11 1 write-only SWF12 XDMAC Channel 12 Software Flush Request Bit 12 1 write-only SWF13 XDMAC Channel 13 Software Flush Request Bit 13 1 write-only SWF14 XDMAC Channel 14 Software Flush Request Bit 14 1 write-only SWF15 XDMAC Channel 15 Software Flush Request Bit 15 1 write-only SWF2 XDMAC Channel 2 Software Flush Request Bit 2 1 write-only SWF3 XDMAC Channel 3 Software Flush Request Bit 3 1 write-only SWF4 XDMAC Channel 4 Software Flush Request Bit 4 1 write-only SWF5 XDMAC Channel 5 Software Flush Request Bit 5 1 write-only SWF6 XDMAC Channel 6 Software Flush Request Bit 6 1 write-only SWF7 XDMAC Channel 7 Software Flush Request Bit 7 1 write-only SWF8 XDMAC Channel 8 Software Flush Request Bit 8 1 write-only SWF9 XDMAC Channel 9 Software Flush Request Bit 9 1 write-only GSWR Global Channel Software Request Register 0x38 32 write-only n 0x0 0x0 SWREQ0 XDMAC Channel 0 Software Request Bit 0 1 write-only SWREQ1 XDMAC Channel 1 Software Request Bit 1 1 write-only SWREQ10 XDMAC Channel 10 Software Request Bit 10 1 write-only SWREQ11 XDMAC Channel 11 Software Request Bit 11 1 write-only SWREQ12 XDMAC Channel 12 Software Request Bit 12 1 write-only SWREQ13 XDMAC Channel 13 Software Request Bit 13 1 write-only SWREQ14 XDMAC Channel 14 Software Request Bit 14 1 write-only SWREQ15 XDMAC Channel 15 Software Request Bit 15 1 write-only SWREQ2 XDMAC Channel 2 Software Request Bit 2 1 write-only SWREQ3 XDMAC Channel 3 Software Request Bit 3 1 write-only SWREQ4 XDMAC Channel 4 Software Request Bit 4 1 write-only SWREQ5 XDMAC Channel 5 Software Request Bit 5 1 write-only SWREQ6 XDMAC Channel 6 Software Request Bit 6 1 write-only SWREQ7 XDMAC Channel 7 Software Request Bit 7 1 write-only SWREQ8 XDMAC Channel 8 Software Request Bit 8 1 write-only SWREQ9 XDMAC Channel 9 Software Request Bit 9 1 write-only GSWS Global Channel Software Request Status Register 0x3C 32 read-only n 0x0 0x0 SWRS0 XDMAC Channel 0 Software Request Status Bit 0 1 read-only SWRS1 XDMAC Channel 1 Software Request Status Bit 1 1 read-only SWRS10 XDMAC Channel 10 Software Request Status Bit 10 1 read-only SWRS11 XDMAC Channel 11 Software Request Status Bit 11 1 read-only SWRS12 XDMAC Channel 12 Software Request Status Bit 12 1 read-only SWRS13 XDMAC Channel 13 Software Request Status Bit 13 1 read-only SWRS14 XDMAC Channel 14 Software Request Status Bit 14 1 read-only SWRS15 XDMAC Channel 15 Software Request Status Bit 15 1 read-only SWRS2 XDMAC Channel 2 Software Request Status Bit 2 1 read-only SWRS3 XDMAC Channel 3 Software Request Status Bit 3 1 read-only SWRS4 XDMAC Channel 4 Software Request Status Bit 4 1 read-only SWRS5 XDMAC Channel 5 Software Request Status Bit 5 1 read-only SWRS6 XDMAC Channel 6 Software Request Status Bit 6 1 read-only SWRS7 XDMAC Channel 7 Software Request Status Bit 7 1 read-only SWRS8 XDMAC Channel 8 Software Request Status Bit 8 1 read-only SWRS9 XDMAC Channel 9 Software Request Status Bit 9 1 read-only GTYPE Global Type Register 0x0 32 read-only n 0x0 0x0 FIFO_SZ Number of Bytes 5 11 read-only NB_CH Number of Channels Minus One 0 5 read-only NB_REQ Number of Peripheral Requests Minus One 16 7 read-only GWAC Global Weighted Arbiter Configuration Register 0x8 32 read-write n 0x0 0x0 PW0 Pool Weight 0 0 4 read-write PW1 Pool Weight 1 4 4 read-write PW2 Pool Weight 2 8 4 read-write PW3 Pool Weight 3 12 4 read-write GWS Global Channel Write Suspend Register 0x2C 32 read-write n 0x0 0x0 WS0 XDMAC Channel 0 Write Suspend Bit 0 1 read-write WS1 XDMAC Channel 1 Write Suspend Bit 1 1 read-write WS10 XDMAC Channel 10 Write Suspend Bit 10 1 read-write WS11 XDMAC Channel 11 Write Suspend Bit 11 1 read-write WS12 XDMAC Channel 12 Write Suspend Bit 12 1 read-write WS13 XDMAC Channel 13 Write Suspend Bit 13 1 read-write WS14 XDMAC Channel 14 Write Suspend Bit 14 1 read-write WS15 XDMAC Channel 15 Write Suspend Bit 15 1 read-write WS2 XDMAC Channel 2 Write Suspend Bit 2 1 read-write WS3 XDMAC Channel 3 Write Suspend Bit 3 1 read-write WS4 XDMAC Channel 4 Write Suspend Bit 4 1 read-write WS5 XDMAC Channel 5 Write Suspend Bit 5 1 read-write WS6 XDMAC Channel 6 Write Suspend Bit 6 1 read-write WS7 XDMAC Channel 7 Write Suspend Bit 7 1 read-write WS8 XDMAC Channel 8 Write Suspend Bit 8 1 read-write WS9 XDMAC Channel 9 Write Suspend Bit 9 1 read-write